Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate includes: a base substrate, a first power line, and a circuit structure layer. The base substrate includes a display area and a peripheral area located outside the display area. The display area includes a first display area and a second display area at least partially surrounding the first display area. The first power line is located in the peripheral area. The circuit structure layer is located in the second display area and includes a plurality of power connection lines and at least one second power line. The second power line provides a second voltage signal that is greater than the first voltage signal provided by the first power line. The plurality of power connection lines extend along a first direction and are electrically connected to the first power line.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. Under-display camera technology is a new technology designed to increase the screen-to-body ratio of displays. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device.

[0005] On the one hand, an embodiment of the present disclosure provides a display substrate, comprising: a base substrate, a first power line, and a circuit structure layer. The base substrate includes a display area and a peripheral area located outside the display area, wherein the display area includes a first display area and a second display area at least partially surrounding the first display area. The first power line is located in the peripheral area. The circuit structure layer is located in the second display area and includes a plurality of power connection lines and at least one second power line. The second power line provides a second voltage signal that is greater than the first voltage signal provided by the first power line. The plurality of power connection lines extend along a first direction and are electrically connected to the first power line.

[0006] In some example embodiments, extension lines of the plurality of power connection lines along the first direction do not overlap with the first display area.

[0007] In some exemplary embodiments, the display substrate further includes: a plurality of first light-emitting elements located in the first display area; and a plurality of second light-emitting elements located in the second display area. The circuit structure layer further includes a plurality of first pixel circuits and a plurality of second pixel circuits, wherein the plurality of first pixel circuits include a plurality of effective pixel circuits and a plurality of ineffective pixel circuits; at least one effective pixel circuit in the second display area is electrically connected to at least one first light-emitting element in the first display area, and at least one second pixel circuit in the second display area is electrically connected to at least one second light-emitting element.

[0008] In some exemplary embodiments, the orthographic projection of at least one effective pixel circuit in the second display area on the substrate does not overlap with the orthographic projection of at least one first light-emitting element in the first display area on the substrate. The orthographic projection of at least one second pixel circuit in the second display area on the substrate at least partially overlaps with the orthographic projection of at least one second light-emitting element on the substrate.

[0009] In some exemplary embodiments, the circuit structure layer further includes: a plurality of second initial signal lines extending along the first direction and a plurality of third initial signal lines extending along the first direction. At least one second initial signal line is electrically connected to a plurality of second pixel circuits arranged along the first direction, or is electrically connected to a plurality of second pixel circuits and a plurality of inactive pixel circuits arranged along the first direction; the second initial signal line is configured to provide an anode reset signal to the second light-emitting element via the second pixel circuit. At least one third initial signal line is electrically connected to a plurality of active pixel circuits arranged along the first direction; the third initial signal line is configured to provide an anode reset signal to the first light-emitting element via the active pixel circuit.

[0010] In some exemplary embodiments, the circuit structure layer further includes: a plurality of first initial signal lines extending along the first direction. At least one first initial signal line is electrically connected to a plurality of first pixel circuits and a plurality of second pixel circuits arranged along the first direction, and the first initial signal line is configured to provide a first reset signal to gates of drive transistors of the first pixel circuits and the second pixel circuits.

[0011] In some exemplary embodiments, the first initial signal line, the second initial signal line, the third initial signal line, and the power connection line are in the same layer structure.

[0012] In some exemplary embodiments, the second power line extends along a second direction and is located on a side of the power connection line away from the base substrate, and the second direction intersects the first direction.

[0013] In some exemplary embodiments, the second display area includes at least one first sub-display area and at least one second sub-display area, wherein the first sub-display area is adjacent to the first display area in the first direction. The plurality of effective pixel circuits and the plurality of third initial signal lines are located in the first sub-display area. The plurality of power connection lines are located in the second sub-display area.

[0014] In some exemplary embodiments, in the first sub-display area, the orthographic projection of the third initial signal line on the base substrate is located between the orthographic projections of the first initial signal line and the second initial signal line on the base substrate. In the second sub-display area, the orthographic projection of the power connection line on the base substrate is located between the orthographic projections of the first initial signal line and the second initial signal line on the base substrate.

[0015] In some exemplary embodiments, the second pixel circuits and valid pixel circuits in the second display area are directly electrically connected to the second power line, and at least one invalid pixel circuit is electrically connected to the second power line through an adjacent second pixel circuit.

[0016] In some exemplary embodiments, at least one of the plurality of first pixel circuits and the plurality of second pixel circuits includes a first emission control transistor. A first electrode of the first emission control transistor of the second pixel circuit is electrically connected to the second power line. A first electrode of the first emission control transistor of the inactive pixel circuit is electrically connected to a first electrode of a first emission control transistor of an adjacent second pixel circuit.

[0017] In some exemplary embodiments, the first electrode of the first light emission control transistor of the inactive pixel circuit and the first electrode of the first light emission control transistor of the adjacent second pixel circuit are integrally structured.

[0018] In some exemplary embodiments, at least one of the plurality of first pixel circuits and the plurality of second pixel circuits includes a storage capacitor, and an overlapping area of ​​an orthographic projection of a first electrode and a second electrode of the storage capacitor of the effective pixel circuit or the second pixel circuit on the substrate is greater than an overlapping area of ​​an orthographic projection of a first electrode and a second electrode of the storage capacitor of the ineffective pixel circuit on the substrate.

[0019] In some exemplary embodiments, the first electrode of the storage capacitor and the gate of the driving transistor are integrated into one structure, and the second electrode of the storage capacitor is electrically connected to the second power line.

[0020] In some exemplary embodiments, the deactivated pixel circuit includes at least a driving transistor, a first emission control transistor, and a second emission control transistor. The gate of the first emission control transistor is electrically connected to the emission control line, the first electrode of the first emission control transistor is electrically connected to the second power line, and the second electrode of the first emission control transistor is electrically connected to the first electrode of the driving transistor. The gate of the second emission control transistor is electrically connected to the emission control line, and the first electrode of the second emission control transistor is electrically connected to the second electrode of the driving transistor. The active layers of the first emission control transistor, the second emission control transistor, and the driving transistor of the deactivated pixel circuit are independent of each other.

[0021] On the other hand, an embodiment of the present disclosure provides a display device including the display substrate as described above.

[0022] In another aspect, embodiments of the present disclosure provide a method for fabricating a display substrate, comprising: forming a first power line in a peripheral region of a base substrate, and forming a circuit structure layer in a second display area of ​​the display region of the base substrate; the second display area at least partially surrounds the first display area. The circuit structure layer includes: a plurality of power connection lines and at least one second power line; the second power line provides a second voltage signal greater than the first voltage signal provided by the first power line; and the plurality of power connection lines extend along a first direction and are electrically connected to the first power line.

[0023] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0025] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0026] Figure 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0027] Figure 3 for Figure 2 The working timing diagram of the pixel circuit provided;

[0028] Figure 4 A schematic diagram illustrating the arrangement of multiple pixel circuits in the second display area of ​​at least one embodiment of the present disclosure;

[0029] Figure 5A schematic diagram of the wiring arrangement of the second display area of ​​at least one embodiment of the present disclosure;

[0030] Figure 6 A partial plan view of the first sub-display area according to at least one embodiment of the present disclosure;

[0031] Figure 7A is a partial plan view of the first sub-display area after the semiconductor layer is formed in at least one embodiment of the present disclosure;

[0032] Figure 7B is a partial plan view of the first sub-display area after the first conductive layer is formed in at least one embodiment of the present disclosure;

[0033] Figure 7C is a partial plan view of the first sub-display area after the second conductive layer is formed in at least one embodiment of the present disclosure;

[0034] Figure 7D is a partial plan view of the first sub-display area after the third insulating layer is formed in at least one embodiment of the present disclosure;

[0035] Figure 8 A partial plan view of the second sub-display area according to at least one embodiment of the present disclosure;

[0036] Figure 9 is another partial plan view of the second sub-display area according to at least one embodiment of the present disclosure;

[0037] Figure 10A is a partial plan view of the second sub-display area after the semiconductor layer is formed in at least one embodiment of the present disclosure;

[0038] Figure 10B is a partial plan view of the second sub-display area after the first conductive layer is formed in at least one embodiment of the present disclosure;

[0039] Figure 10C is a partial plan view of the second sub-display area after the second conductive layer is formed in at least one embodiment of the present disclosure;

[0040] Figure 10D is a partial plan view of the second sub-display area after the third insulating layer is formed in at least one embodiment of the present disclosure;

[0041] Figure 10E is a partial plan view of the second sub-display area after the third conductive layer is formed in at least one embodiment of the present disclosure;

[0042] Figure 10F is a partial plan view of the second sub-display area after the fourth insulating layer is formed in at least one embodiment of the present disclosure;

[0043] Figure 11is another partial plan view of the second sub-display area after the semiconductor layer is formed in at least one embodiment of the present disclosure;

[0044] Figure 12 is another partial plan view of the second sub-display area according to at least one embodiment of the present disclosure;

[0045] Figure 13 A schematic diagram of heat generation of a second power line of a display substrate according to at least one embodiment of the present disclosure;

[0046] Figure 14 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0048] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0049] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0050] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0051] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0052] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0053] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0054] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0055] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0056] The term "light transmittance" in this disclosure refers to the ability of light to pass through a medium, and is the percentage of the luminous flux passing through a transparent or translucent body to the incident luminous flux.

[0057] In the present disclosure, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In the present disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0058] An embodiment of the present disclosure provides a display substrate, comprising: a base substrate, a first power line, and a circuit structure layer. The base substrate includes a display area and a peripheral area located outside the display area, wherein the display area includes a first display area and a second display area at least partially surrounding the first display area. The first power line is located in the peripheral area. The circuit structure layer is located in the second display area and includes a plurality of power connection lines and at least one second power line. The second power line provides a second voltage signal that is greater than the first voltage signal provided by the first power line. The plurality of power connection lines extend along a first direction and are electrically connected to the first power line.

[0059] The display substrate provided in this embodiment can optimize the resistance and capacitance load of the first power line, improve the stability of the first voltage signal, reduce the cross-voltage of the first voltage signal, and thus reduce the power consumption of the display substrate by setting multiple power connection lines connected to the first power line in the circuit structure layer of the second display area.

[0060] In some exemplary embodiments, the display substrate further includes: a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. The circuit structure layer further includes: a plurality of first pixel circuits and a plurality of second pixel circuits. The plurality of first pixel circuits may include a plurality of effective pixel circuits and a plurality of ineffective pixel circuits. At least one effective pixel circuit in the second display area is electrically connected to at least one first light-emitting element in the first display area, and at least one second pixel circuit in the second display area is electrically connected to at least one second light-emitting element. In this exemplary embodiment, by arranging the pixel circuits in the second display area, the light transmittance of the first display area can be improved.

[0061] In some exemplary embodiments, the circuit structure layer may further include: a plurality of second initial signal lines extending along the first direction and a plurality of third initial signal lines extending along the first direction. At least one second initial signal line is electrically connected to a plurality of second pixel circuits arranged along the first direction, or is electrically connected to a plurality of second pixel circuits and a plurality of invalid pixel circuits arranged along the first direction. The second initial signal line is configured to provide an anode reset signal to the second light-emitting element through the second pixel circuit. At least one third initial signal line is electrically connected to a plurality of effective pixel circuits arranged along the first direction. The third initial signal line is configured to provide an anode reset signal to the first light-emitting element through the effective pixel circuit. In this exemplary embodiment, by providing different anode reset signals to the first light-emitting element and the second light-emitting element through different initial signal lines, the reset ability of the first light-emitting element in the first display area can be improved, thereby improving the display effect of the first display area.

[0062] In some exemplary embodiments, the circuit structure layer may further include: a plurality of first initial signal lines extending along a first direction. At least one of the first initial signal lines is electrically connected to a plurality of pixel circuits arranged along the first direction. The first initial signal line is configured to provide a first reset signal to a gate of a driving transistor of the pixel circuit.

[0063] In some exemplary embodiments, the second pixel circuits and the valid pixel circuits in the second display area are directly electrically connected to the second power line, and at least one invalid pixel circuit is electrically connected to the second power line via an adjacent second pixel circuit. In this exemplary embodiment, there is no need to provide a second power line connected to the invalid pixel circuit, thereby reducing the resistance of the second power line.

[0064] In some exemplary embodiments, at least one pixel circuit among the plurality of first pixel circuits and the plurality of second pixel circuits includes: a storage capacitor. The overlapping area of ​​the orthographic projection of the first electrode and the second electrode of the storage capacitor of the effective pixel circuit or the second pixel circuit on the substrate is greater than the overlapping area of ​​the orthographic projection of the first electrode and the second electrode of the storage capacitor of the ineffective pixel circuit on the substrate. The first electrode of the storage capacitor is an integral structure with the gate of the driving transistor, and the second electrode of the storage capacitor is electrically connected to the second power line. In this exemplary embodiment, by reducing the overlapping area of ​​the orthographic projection of the first electrode and the second electrode of the storage capacitor of the ineffective pixel circuit on the substrate, the resistance and capacitance of the second power line can be reduced.

[0065] In some exemplary embodiments, the deactivated pixel circuit includes at least a driving transistor, a first light-emission control transistor, and a second light-emission control transistor. The gate of the first light-emission control transistor is electrically connected to a light-emission control line, the first electrode of the first light-emission control transistor is electrically connected to a second power supply line, and the second electrode of the first light-emission control transistor is electrically connected to the first electrode of the driving transistor. The gate of the second light-emission control transistor is electrically connected to the light-emission control line, and the first electrode of the second light-emission control transistor is electrically connected to the second electrode of the driving transistor. The active layers of the first light-emission control transistor, the second light-emission control transistor, and the driving transistor of the deactivated pixel circuit are independent of each other. In this exemplary embodiment, by disconnecting the active layers of the driving transistor, the first light-emission control transistor, and the second light-emission control transistor of the deactivated pixel circuit, the startup voltage across the driving transistor when it is turned on and off can be reduced, thereby reducing the power consumption of the display substrate.

[0066] The solution of this embodiment is illustrated below through some examples.

[0067] Figure 1 Schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 1As shown, the display substrate may include a display area AA and a peripheral area BB surrounding the display area AA. The display area AA of the display substrate may include a first display area A1 and a second display area A2 that at least partially surrounds the first display area A1. In this example, the second display area A2 surrounds the first display area A1.

[0068] In some exemplary embodiments, the first display area A1 is a light-transmitting display area, which may also be referred to as an under-display camera (UDC) area; the second display area A2 is a non-light-transmitting display area, which may also be referred to as a normal display area. For example, the orthographic projection of a light-sensitive sensor (such as a camera or other hardware) on the display substrate may be located within the first display area A1 of the display substrate. In some examples, such as Figure 1 As shown, the first display area A1 can be circular, and the size of the orthographic projection of the light sensor on the display substrate can be smaller than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 can be rectangular, and the size of the orthographic projection of the light sensor on the display substrate can be smaller than or equal to the size of the inscribed circle of the first display area A1.

[0069] In some exemplary embodiments, Figure 1 As shown, the first display area A1 can be located in the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 can be located in other locations such as the upper left corner or upper right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0070] In some exemplary embodiments, Figure 1 As shown, the display area AA can be a rectangle, such as a rounded rectangle. The first display area A1 can be circular or elliptical. However, this embodiment is not limited to this. For example, the first display area A1 can be a rectangle, a semicircle, a pentagon, or other shapes.

[0071] In some exemplary embodiments, the display area AA is provided with a plurality of sub-pixels. At least one sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit is configured to drive the connected light-emitting element. For example, the pixel circuit is configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may have a 3T1C (3 transistors and 1 capacitor) structure, a 7T1C (7 transistors and 1 capacitor) structure, or a 5T1C (5 transistors and 1 capacitor) structure. In some examples, the light-emitting element may be an organic light-emitting diode (OLED), which emits red, green, blue, or white light when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0072] In some exemplary embodiments, a pixel unit in the display area may include three sub-pixels, and the three sub-pixels may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0073] In some exemplary embodiments, the shape of the light-emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels may be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels may be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0074] Figure 2 FIG. 4 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Figure 3 for Figure 2 The working timing diagram of the pixel circuit is provided.

[0075] In some exemplary embodiments, Figure 2 As shown, the pixel circuit of this exemplary embodiment may include: six switching transistors (T1, T2, T4 to T7), a driving transistor T3, and a storage capacitor Cst. The six switching transistors are respectively a data writing transistor T4, a threshold compensation transistor T2, a first emission control transistor T5, a second emission control transistor T6, a first reset transistor T1, and a second reset transistor T7. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.

[0076] In some exemplary embodiments, the driving transistor and the six switching transistors may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the difficulty of display substrate processing, and improve product yield. In some possible implementations, the driving transistor and the six switching transistors may include P-type transistors and N-type transistors.

[0077] In some exemplary embodiments, the driving transistor and the six switching transistors may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0078] In some exemplary embodiments, Figure 2As shown, the pixel circuit is electrically connected to a scan line GL, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. In some examples, the first power line PL1 is configured to provide a constant first voltage signal VSS to the pixel circuit, and the second power line PL2 is configured to provide a constant second voltage signal VDD to the pixel circuit, where the first voltage signal VSS is less than the second voltage signal VDD. The scan line GL is configured to provide a scan signal SCAN to the pixel circuit, the data line DL is configured to provide a data signal DATA to the pixel circuit, the emission control line EML is configured to provide an emission control signal EM to the pixel circuit, the first reset control line RST1 is configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 is configured to provide a second reset signal RESET2 to the pixel circuit. In some examples, in a row of pixel circuits, the second reset control line RST2 can be connected to the scan line GL to receive the scan signal SCAN. That is, the second reset signal RESET2(n) received by the pixel circuit in the nth row is the scan signal SCAN(n) received by the pixel circuit in the nth row. However, this embodiment is not limited to this. For example, the second reset control signal line RST2 can be input with a second reset control signal RESET2 that is different from the scan signal SCAN. In some examples, in the pixel circuit in the nth row, the first reset control line RST1 can be connected to the scan line GL of the pixel circuit in the n-1th row to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). In this way, the signal lines of the display substrate can be reduced, and a narrow frame of the display substrate can be achieved.

[0079] In some exemplary embodiments, Figure 2As shown, the driving transistor T3 is electrically connected to the light-emitting element EL and outputs a driving current to drive the light-emitting element EL to emit light under the control of signals such as a scan signal SCAN, a data signal DATA, a first voltage signal VSS, and a second voltage signal VDD. The gate of the data writing transistor T4 is electrically connected to the scan line GL, the first electrode of the data writing transistor T4 is electrically connected to the data line DL, and the second electrode of the data writing transistor T4 is electrically connected to the first electrode of the driving transistor T3. The gate of the threshold compensation transistor T2 is electrically connected to the scan line GL, the first electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3. The gate of the first emission control transistor T5 is electrically connected to the emission control line EML, the first electrode of the first emission control transistor T5 is electrically connected to the second power line PL2, and the second electrode of the first emission control transistor T5 is electrically connected to the first electrode of the driving transistor T3. The gate of the second emission control transistor T6 is electrically connected to the emission control line EML. The first electrode of the second emission control transistor T6 is electrically connected to the second electrode of the drive transistor T3, and the second electrode of the second emission control transistor T6 is electrically connected to the anode of the light-emitting element EL. The first reset transistor T1 is electrically connected to the gate of the drive transistor T3 and is configured to reset the gate of the drive transistor T3. The second reset transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the anode of the light-emitting element EL. The gate of the first reset transistor T1 is electrically connected to the first reset control line RST1. The first electrode of the first reset transistor T1 is electrically connected to the first initial signal line INIT1. The second electrode of the first reset transistor T1 is electrically connected to the gate of the drive transistor T3. The gate of the second reset transistor T7 is electrically connected to the second reset control line RST2. The first electrode of the second reset transistor T7 is electrically connected to the second initial signal line INIT2. The second electrode of the second reset transistor T7 is electrically connected to the anode of the light-emitting element EL. The first electrode of the storage capacitor Cst is electrically connected to the gate of the drive transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the second power line PL2. The cathode of the light emitting element EL is electrically connected to the first power line PL1.

[0080] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the threshold compensation transistor T2, the second node N2 is the connection point of the first light-emitting control transistor T5, the data writing transistor T4 and the driving transistor T3, the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2 and the second light-emitting control transistor T6, and the fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7 and the light-emitting element EL.

[0081] Refer to the following Figure 3 right Figure 2The working process of the pixel circuit shown in FIG is described. Figure 2 The pixel circuit shown is described by taking as an example a case where all of the multiple transistors included are P-type transistors.

[0082] In some exemplary embodiments, Figure 2 and Figure 3 As shown, in a frame display period, the working process of the pixel circuit may include: a first stage S1, a second stage S2 and a third stage S3.

[0083] The first phase S1 is called the reset phase. The first reset control signal RESET1 provided by the first reset control line RST1 is low, turning on the first reset transistor T1. The first initial signal provided by the first initial signal line INIT1 is supplied to the first node N1, initializing the first node N1 and clearing the existing data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is high, and the emission control signal EM provided by the emission control line EML is high, turning off the data writing transistor T4, the threshold compensation transistor T2, the first emission control transistor T5, the second emission control transistor T6, and the second reset transistor T7. During this phase, the light-emitting element EL does not emit light.

[0084] The second phase S2 is called the data writing phase or the threshold compensation phase. The scan signal SCAN provided by the scan line GL is a low-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 and the emission control signal EM provided by the emission control line EML are both high-level signals, and the data line DL outputs the data signal DATA. During this phase, the second electrode of the storage capacitor Cst is at a low level, so the drive transistor T3 is turned on. The scan signal SCAN is a low-level signal, turning on the threshold compensation transistor T2, the data writing transistor T4, and the second reset transistor T7. The threshold compensation transistor T2 and the data writing transistor T4 are turned on, allowing the data voltage Vdata output by the data line DL to be provided to the first node N1 through the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst. The voltage at the second electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the driving transistor T3. The second reset transistor T7 is turned on, allowing the second initialization signal (i.e., the anode reset signal) provided by the second initialization signal line INIT2 to be provided to the anode of the light-emitting element EL, initializing (resetting) the anode of the light-emitting element EL and clearing the pre-stored voltage therein, completing the initialization and ensuring that the light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, turning off the first reset transistor T1. The light emitting control signal EM provided by the light emitting control signal line EML is a high level signal, which turns off the first light emitting control transistor T5 and the second light emitting control transistor T6.

[0085] The third phase S3 is called the light-emitting phase. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, while the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, turning on the first light-emitting control transistor T5 and the second light-emitting control transistor T6. The second voltage signal VDD output by the second power line PL2 then provides a driving voltage to the anode of the light-emitting element EL via the turned-on first light-emitting control transistor T5, the driving transistor T3, and the second light-emitting control transistor T6, thereby driving the light-emitting element EL to emit light.

[0086] During the driving process of the pixel circuit, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the driving transistor T3 is:

[0087] I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 ;

[0088] Wherein, I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the second voltage signal output by the second power line PL2.

[0089] It can be seen from the above formula that the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the driving transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the driving transistor T3.

[0090] In some exemplary embodiments, the first display area A1 is provided with a plurality of first light-emitting elements, and the second display area A2 is provided with a plurality of second light-emitting elements and a plurality of pixel circuits. The plurality of pixel circuits in the second display area A2 are configured to drive the first light-emitting elements in the first display area A1 and the second light-emitting elements in the second display area A2 to emit light. In this example, pixel circuits are provided only in the second display area A2, while pixel circuits are not provided in the first display area A1. This can improve the light transmittance of the first display area A1.

[0091] Figure 4 This is a schematic diagram illustrating the arrangement of multiple pixel circuits in the second display area of ​​at least one embodiment of the present disclosure. In this example, multiple pixel circuits arranged sequentially along the first direction F1 can be referred to as a row of pixel circuits, and multiple pixel circuits arranged sequentially along the second direction F2 can be referred to as a column of pixel circuits.

[0092] In some exemplary embodiments, Figure 4 As shown, the multiple pixel circuits of the second display area A2 may include: multiple first pixel circuits 11 and multiple second pixel circuits 12. The multiple first pixel circuits 11 may include multiple effective pixel circuits and multiple invalid (Dummy) pixel circuits. At least one effective pixel circuit of the second display area A2 may be electrically connected to at least one first light-emitting element of the first display area A1 through a transparent conductive line. For example, the effective pixel circuit and the first light-emitting element may be in a one-to-one or one-to-many relationship. At least one second pixel circuit of the second display area A2 is electrically connected to at least one second light-emitting element. For example, the second pixel circuit and the second light-emitting element may be in a one-to-one relationship. The invalid pixel circuit of the second display area A2 is not electrically connected to the first light-emitting element of the first display area A1 and the second light-emitting element of the second display area A2.

[0093] In some exemplary embodiments, Figure 4 As shown, at least one first pixel circuit 11 is provided between a plurality of second pixel circuits 12 arranged along the first direction F1. The first pixel circuit 11 can be arranged between a plurality of columns of second pixel circuits 12. For example, a column of first pixel circuits 11 is provided between every three columns of second pixel circuits 12. Compared to the second display area in which only second pixel circuits are provided, this exemplary embodiment compresses the original three columns of second pixel circuits along the first direction F1, thereby adding an arrangement space for a column of first pixel circuits 11, and the space occupied by the three columns of pixel circuits before compression and the four columns of pixel circuits after compression is the same. However, this embodiment is not limited to this.

[0094] In some exemplary embodiments, the circuit structures of the second pixel circuit and the invalid pixel circuit in the second display area may be as follows: Figure 2 The circuit structure of the effective pixel circuit in the second display area is the same as that of the 7T1C structure shown in FIG. Figure 2 The 7T1C structure shown is similar, in which the first electrode of the second reset transistor in the active pixel circuit is electrically connected to the third initial signal line INIT3. The first initial signal line INIT1 can provide a first reset signal to the pixel circuit in the second display area to reset the gate of the drive transistor. The second initial signal line INIT2 can provide a second initial signal to the second pixel circuit and the inactive pixel circuit in the second display area to reset the anode of the second light-emitting element electrically connected to the second pixel circuit. The third initial signal line INIT3 can provide a third initial signal to the active pixel circuit in the second display area to reset the anode of the first light-emitting element electrically connected to the active pixel circuit. In this example, the anode reset signal for the first light-emitting element is the third initial signal provided by the third initial signal line, and the anode reset signal for the second light-emitting element is the second initial signal provided by the second initial signal line. By providing different anode reset signals on the second and third initial signal lines, the dark and purple display effects in the first display area can be improved. By adjusting the anode reset signal provided by the third initial signal line, the anode reset capability of the first display area can be improved, thereby improving the display effect of the first display area.

[0095] Figure 5 FIG. 1 is a schematic diagram of the wiring arrangement of the second display area of ​​at least one embodiment of the present disclosure. In some exemplary embodiments, Figure 5As shown, the second display area A2 may include: at least one first sub-display area A21 and at least one second sub-display area A22. The first sub-display area A21 is located on at least one side of the first display area A1 along the first direction F1. The first sub-display area A21 is adjacent to the first display area A1 in the first direction F1. The effective pixel circuit is arranged in the first sub-display area A21 and is electrically connected to the first light-emitting element in the first display area A1 through a transparent conductive line. The first pixel circuits in the second sub-display area A22 are all invalid pixel circuits and are not electrically connected to the first light-emitting element in the first display area. Since the third initial signal line INIT3 is only electrically connected to the effective pixel circuit, the invalid pixel circuit does not need to be electrically connected to the third initial signal line INIT3. In this example, the third initial signal line INIT3 is only set in the first sub-display area A21, which can avoid occupying the arrangement space after the third initial signal line is set in the entire second display area, resulting in redundant routing design. As shown Figure 5 As shown, the third initial signal line INIT3 in the first sub-display area A21 may extend along the first direction F1 , and one end of the third initial signal line INIT3 extends to the peripheral area BB and is electrically connected to the initial signal connection line of the peripheral area BB.

[0096] In some exemplary embodiments, Figure 5 As shown, the peripheral area BB is provided with a first power line PL1. The first power line PL1 can surround the left, upper, and right sides of the display area AA. The second display area A2 is provided with multiple power connection lines 301 extending along a first direction F1. The multiple power connection lines 301 are arranged along a second direction F2 within the second sub-display area A22. The extensions of the multiple power connection lines 301 along the first direction F1 do not overlap with the first display area A1. The power connection lines 301 extend along the first direction F1 to the peripheral area BB and are electrically connected to the first power line PL1. For example, one end of a power connection line 301 can extend into the peripheral area BB on the left side of the display area and be electrically connected to the first power line PL1, and the other end can extend into the peripheral area BB on the right side of the display area and be electrically connected to the first power line PL1. In this example, both ends of the power connection line 301 are electrically connected to the first power line PL1. However, this embodiment is not limited to this. For example, one end of the power connection line can be electrically connected to the first power line. In this exemplary embodiment, connecting the first power line via a power connection line can optimize the resistance and capacitance loads of the first power line, improve the stability of the first voltage signal, and reduce the cross-voltage of the first power line, thereby reducing the power consumption of the display substrate. Furthermore, the location of the power connection line in the second sub-display area can refer to the redundant design location of the third initial signal line in the second sub-display area, thereby ensuring the uniformity of the routing arrangement of the second display area of ​​the display substrate. In other examples, power connection lines can be arranged in both the first sub-display area and the second sub-display area. However, this embodiment is not limited to this.

[0097] Figure 6 FIG. 1 is a partial plan view of the first sub-display area of ​​at least one embodiment of the present disclosure. In some exemplary embodiments, as Figure 6 As shown, the first sub-display area may include: a first circuit area 101 and a second circuit area 102 arranged at intervals in a first direction F1. The first circuit area 101 is provided with multiple columns of second pixel circuits (for example, three columns of second pixel circuits), and the second circuit area 102 is provided with one column of first pixel circuits (for example, including multiple valid pixel circuits, or including at least one valid pixel circuit and multiple invalid pixel circuits, or including multiple invalid pixel circuits). Figure 6 In the figure, one effective pixel circuit provided in the second circuit area 102 and three second pixel circuits provided in the first circuit area 101 are taken as an example for illustration.

[0098] In some exemplary embodiments, Figure 6 As shown, the second pixel circuit of the first circuit area 101 may include: a driving transistor 23, a data writing transistor 24, a threshold compensation transistor 22, a first light emission control transistor 25, a second light emission control transistor 26, a first reset transistor 21, a second reset transistor and a storage capacitor 28. Figure 6 The second reset transistor 27 in FIG is the second reset transistor of the second pixel circuit in the previous row. The effective pixel circuit of the second circuit area 102 may include: a driving transistor 13, a data writing transistor 14, a threshold compensation transistor 12, a first emission control transistor 15, a second emission control transistor 16, a first reset transistor 11, a second reset transistor, and a storage capacitor 18. Figure 6 The second reset transistor 17 in FIG. 1 is the second reset transistor of the effective pixel circuit of the previous row.

[0099] Figure 7A FIG. 4 is a partial plan view of the first sub-display region after the semiconductor layer is formed in at least one embodiment of the present disclosure. Figure 7B FIG. 4 is a partial plan view of the first sub-display area after the first conductive layer is formed in at least one embodiment of the present disclosure. Figure 7C FIG. 4 is a partial plan view of the first sub-display area after the second conductive layer is formed in at least one embodiment of the present disclosure. Figure 7D FIG. 4 is a partial plan view of the first sub-display area after the third insulating layer is formed in at least one embodiment of the present disclosure.

[0100] In some exemplary embodiments, in a direction perpendicular to the display substrate, the circuit structure layer of the second display area may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially arranged on the base substrate. A first insulating layer is arranged between the semiconductor layer and the first conductive layer, a second insulating layer is arranged between the first conductive layer and the second conductive layer, a third insulating layer is arranged between the second conductive layer and the third conductive layer, and a fourth insulating layer is arranged between the third conductive layer and the fourth conductive layer. In some examples, the first to fourth insulating layers may all be inorganic insulating layers. The first conductive layer may also be referred to as a first gate metal layer, the second conductive layer may also be referred to as a second gate metal layer, the third conductive layer may also be referred to as a first source-drain metal layer, and the fourth conductive layer may also be referred to as a second source-drain metal layer. However, this embodiment is not limited to this.

[0101] In some exemplary embodiments, Figure 7A As shown, the semiconductor layer of the first sub-display area may include at least: active layers of multiple transistors of the second pixel circuit (for example, the active layer 210 of the first reset transistor 21, the active layer 220 of the threshold compensation transistor 22, the active layer 230 of the driving transistor 23, the active layer 240 of the data writing transistor 24, the active layer 250 of the first light-emitting control transistor 25, the active layer 260 of the second light-emitting control transistor 26, and the active layer 270 of the second reset transistor 27), and active layers of multiple transistors of the effective pixel circuit (for example, the active layer 110 of the first reset transistor 11, the active layer 120 of the threshold compensation transistor 12, the active layer 130 of the driving transistor 13, the active layer 140 of the data writing transistor 14, the active layer 150 of the first light-emitting control transistor 15, the active layer 160 of the second light-emitting control transistor 16, and the active layer 170 of the second reset transistor 17).

[0102] In some exemplary embodiments, Figure 7BAs shown, the first conductive layer of the first sub-display area includes at least: the gates of multiple transistors in the second pixel circuit and the first electrode 281 of the storage capacitor, the gates of multiple transistors in the effective pixel circuit and the first electrode 181 of the storage capacitor, a scan line GL, an emission control line EML, and a first reset control line RST1. The scan line GL, the emission control line EML, and the first reset control line RST1 all extend along a first direction F1. The first reset control line RST1 can be integrated with the gate of the first reset transistor 21 of the second pixel circuit in the current row, the gate of the second reset transistor 27 of the second pixel circuit in the previous row, the gate of the first reset transistor 11 of the effective pixel circuit in the current row, and the gate of the second reset transistor 17 of the effective pixel circuit in the previous row. The scan line GL can be integrated with the gates of the data write transistor 24 and the threshold compensation transistor 22 of the second pixel circuit in the current row, and the gates of the data write transistor 14 and the threshold compensation transistor 12 of the effective pixel circuit in the current row. The emission control line EML may be integrated with the gates of the first emission control transistor 25 and the second emission control transistor 26 of the second pixel circuit of this row and the gates of the first emission control transistor 15 and the second emission control transistor 16 of the effective pixel circuit of this row.

[0103] In some exemplary embodiments, Figure 7C As shown, the second conductive layer of the first sub-display area includes at least: a second electrode 282 of the storage capacitor of the second pixel circuit, a second electrode 182 of the storage capacitor of the effective pixel circuit, a first initial signal line INIT1, a second initial signal line INIT2, and a third initial signal line INIT3. The first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3 all extend along a first direction F1. The orthographic projection of the third initial signal line INIT3 on the base substrate is located between the orthographic projections of the first initial signal line INIT1 and the second initial signal line INIT2 on the base substrate.

[0104] In some exemplary embodiments, Figure 7D As shown, the third insulating layer of the first sub-display area is provided with a plurality of via holes, including, for example, via holes 1 through 20 K20. The third insulating layer, second insulating layer, and first insulating layer within via holes 1 through 6 K6 and via holes 11 through 16 K16 are removed, exposing the surface of the semiconductor layer. The third insulating layer and second insulating layer within via holes 7 through 17 K17 are removed, exposing the surface of the first conductive layer. The third insulating layer within via holes 8 through 10 K10 and via holes 18 through 20 K20 is removed, exposing the surface of the second conductive layer.

[0105] In some exemplary embodiments, Figure 6 As shown, the third conductive layer of the first sub-display area includes at least: the first electrodes and the second electrodes of multiple transistors of the second pixel circuit (for example, the first electrode 211 of the first reset transistor 21, the first electrode 221 of the threshold compensation transistor 22, the first electrode 241 of the data write transistor 24, the first electrode 251 of the first light-emitting control transistor 25, the second electrode 262 of the second light-emitting control transistor 26, and the first electrode 271 of the second reset transistor 27), and the first electrodes and the second electrodes of multiple transistors of the effective pixel circuit (for example, the first electrode 111 of the first reset transistor 11, the first electrode 121 of the threshold compensation transistor 12, the first electrode 141 of the data write transistor 14, the first electrode 151 of the first light-emitting control transistor 15, the second electrode 162 of the second light-emitting control transistor 16, and the first electrode 171 of the second reset transistor 17).

[0106] In some examples, the first electrode 111 of the first reset transistor 11 of the effective pixel circuit can be electrically connected to the first doped region of the active layer 110 through the first via K1, and can also be electrically connected to the first initial signal line INIT1 through the ninth via K9. The first electrode 121 of the threshold compensation transistor 12 can be electrically connected to the first doped region of the active layer 120 through the second via K2, and can also be electrically connected to the gate of the drive transistor 13 through the seventh via K7. The first electrode 141 of the data write transistor 14 can be electrically connected to the first doped region of the active layer 140 through the third via K3. The first electrode 151 of the first emission control transistor 15 can be electrically connected to the first doped region of the active layer 150 through the fourth via K4, and can also be electrically connected to the second electrode 182 of the storage capacitor 18 through the tenth via K10. The second electrode 162 of the second emission control transistor 16 can be electrically connected to the second doped region of the active layer 160 through the fifth via K5. The first electrode 171 of the second reset transistor 17 can be electrically connected to the first doping region of the active layer 170 through the sixth via hole K6 , and can also be electrically connected to the third initial signal line INIT3 through the eighth via hole K8 .

[0107] In some examples, the first electrode 211 of the first reset transistor 21 of the second pixel circuit can be electrically connected to the first doped region of the active layer 210 through the eleventh via K11, and can also be electrically connected to the first initial signal line INIT1 through the nineteenth via K19. The first electrode 221 of the threshold compensation transistor 22 can be electrically connected to the first doped region of the active layer 220 through the twelfth via K12, and can also be electrically connected to the gate of the drive transistor 23 through the seventeenth via K17. The first electrode 241 of the data write transistor 24 can be electrically connected to the first doped region of the active layer 240 through the thirteenth via K13. The first electrode 251 of the first emission control transistor 25 can be electrically connected to the first doped region of the active layer 250 through the fourteenth via K14, and can also be electrically connected to the second electrode 282 of the storage capacitor 28 through the twentieth via K20. The second electrode 262 of the second emission control transistor 26 can be electrically connected to the second doped region of the active layer 260 through the fifteenth via K15. The first electrode 271 of the second reset transistor 27 can be electrically connected to the first doping region of the active layer 270 through the sixteenth via hole K16 , and can also be electrically connected to the second initial signal line INIT2 through the eighteenth via hole K18 .

[0108] In some exemplary embodiments, the fourth conductive layer of the first sub-display area may include: a plurality of connection electrodes (e.g., a first connection electrode and a second connection electrode), a plurality of data lines, and a second power line. The first electrode 151 of the first emission control transistor 15 of the effective pixel circuit may be electrically connected to the second power line via a via hole defined in the fourth insulating layer. The second electrode 162 of the second emission control transistor 16 may be electrically connected to the first connection electrode via a via hole defined in the fourth insulating layer, and the first connection electrode may be electrically connected to the anode of the first light-emitting element in the first display area via a transparent conductive line. The first electrode 141 of the data write transistor 14 may be electrically connected to a data line via a via hole defined in the fourth insulating layer. The first electrode 251 of the first emission control transistor 25 of the second pixel circuit may be electrically connected to the second power line via a via hole defined in the fourth insulating layer. The first electrode 241 of the data write transistor 24 may be electrically connected to a data line via a via hole defined in the fourth insulating layer. The second electrode 262 of the second emission control transistor 26 may be electrically connected to the second connection electrode via a via hole defined in the fourth insulating layer, and the second connection electrode may be electrically connected to the anode of the second light-emitting element.

[0109] Figure 8 FIG. 1 is a partial plan view of the second sub-display area of ​​at least one embodiment of the present disclosure. In some exemplary embodiments, as Figure 8As shown, the second sub-display area may include: a third circuit area 103 and a fourth circuit area 104 arranged alternately in the first direction F1. The third circuit area 103 is provided with multiple columns of second pixel circuits (for example, three columns of second pixel circuits), and the fourth circuit area 104 is provided with one column of first pixel circuits (for example, including multiple invalid pixel circuits). Figure 8 In the figure, an invalid pixel circuit provided in the fourth circuit area 104 and three second pixel circuits provided in the third circuit area 103 are taken as an example for illustration.

[0110] In some exemplary embodiments, Figure 8 As shown, the invalid pixel circuit of the fourth circuit area 104 may include: a driving transistor 33, a data writing transistor 34, a threshold compensation transistor 32, a first light emission control transistor 35, a second light emission control transistor 36, a first reset transistor 31, a second reset transistor and a storage capacitor 38. Figure 8 The second reset transistor 37 is the second reset transistor of the invalid pixel circuit in the previous row. The structure of the second pixel circuit in the third circuit area 103 is the same as that of the second pixel circuit in the first circuit area 101, so it will not be repeated here.

[0111] In some exemplary embodiments, Figure 8 As shown, the first electrode 371 of the second reset transistor 37 of the invalid pixel circuit of the fourth circuit area 104 can be electrically connected to the second initial signal line INIT2. The second sub-display area does not have a third initial signal line INIT3, and a power connection line 301 can be provided. The power connection line 301 extends along the first direction F1. The power connection line 301 is located in the second conductive layer and has the same layer structure as the first initial signal line INIT1 and the second initial signal line INIT2. The orthographic projection of the power connection line 301 on the base substrate is located between the orthographic projection of the first initial signal line INIT1 and the second initial signal line INIT2 on the base substrate. The remaining film layer structure of the second sub-display area can refer to the film layer structure of the first sub-display area, so it will not be repeated here.

[0112] The display substrate provided in this exemplary embodiment can improve the stability of the first voltage signal and reduce the cross-voltage of the first power line by providing multiple power connection lines connected to the first power line in the circuit structure layer, thereby reducing the power consumption of the display substrate.

[0113] Figure 9 FIG. 4 is another partial plan view of the second sub-display area according to at least one embodiment of the present disclosure. Figure 10A FIG. 4 is a partial plan view of the second sub-display area after the semiconductor layer is formed in at least one embodiment of the present disclosure. Figure 10B FIG. 4 is a partial plan view of the second sub-display area after the first conductive layer is formed in at least one embodiment of the present disclosure. Figure 10CFIG. 4 is a partial plan view of the second sub-display area after the second conductive layer is formed in at least one embodiment of the present disclosure. Figure 10D FIG. 4 is a partial plan view of the second sub-display area after the third insulating layer is formed in at least one embodiment of the present disclosure. Figure 10E FIG. 4 is a partial plan view of the second sub-display area after the third conductive layer is formed in at least one embodiment of the present disclosure. Figure 10F FIG. 4 is a partial plan view of the second sub-display area after the fourth insulating layer is formed in at least one embodiment of the present disclosure. Figures 9 to 10F In the figure, two rows and one column of invalid pixel circuits provided in the fourth circuit area 104 and two rows and three columns of second pixel circuits provided in the third circuit area 103 are taken as an example for illustration.

[0114] In some exemplary embodiments, Figure 10A As shown, the semiconductor layer of the second sub-display area includes at least: active layers of multiple transistors of the second pixel circuit (for example, the active layer 210 of the first reset transistor 21, the active layer 220 of the threshold compensation transistor 22, the active layer 230 of the driving transistor 23, the active layer 240 of the data writing transistor 24, the active layer 250 of the first light-emitting control transistor 25, the active layer 260 of the second light-emitting control transistor 26, and the active layer 270 of the second reset transistor 27), and active layers of multiple transistors of the invalid pixel circuit (for example, the active layer 310 of the first reset transistor 31, the active layer 320 of the threshold compensation transistor 32, the active layer 330 of the driving transistor 33, the active layer 340 of the data writing transistor 34, the active layer 350 of the first light-emitting control transistor 35, the active layer 360 of the second light-emitting control transistor 36, and the active layer 370 of the second reset transistor 37).

[0115] In some exemplary embodiments, Figure 10BAs shown, the first conductive layer of the second sub-display area includes at least: the gates of multiple transistors of the second pixel circuit and the first electrode 281 of the storage capacitor, the gates of multiple transistors of the invalid pixel circuit and the first electrode 381 of the storage capacitor, multiple scan lines (for example, scan lines GL(i) and GL(i+1)), multiple light-emitting control lines (for example, EML(i) and EML(i+1)), and a first reset control line (for example, RST1(i) and RST1(i+1)). The first reset control line RST1(i+1) is an integrated structure with the gate of the first reset transistor of the second pixel circuit of this row, the gate of the second reset transistor of the second pixel circuit of the previous row, the gate of the first reset transistor of the invalid pixel circuit of this row, and the gate of the second reset transistor of the invalid pixel circuit of the previous row. The scan line GL(i) can be an integrated structure with the gate of the data write transistor and the gate of the threshold compensation transistor of the second pixel circuit of this row, and the gate of the data write transistor 34 and the gate of the threshold compensation transistor 32 of the invalid pixel circuit of this row. The light-emitting control line EML(i) can be an integrated structure with the gates of the first light-emitting control transistor 25 and the second light-emitting control transistor 26 of the second pixel circuit of this row, and the gates of the first light-emitting control transistor 35 and the second light-emitting control transistor 36 of the invalid pixel circuit of this row.

[0116] In some exemplary embodiments, Figure 10C As shown, the second conductive layer of the second sub-display area includes at least: a second electrode 282 of the storage capacitor of the second pixel circuit, a second electrode 382 of the storage capacitor of the invalid pixel circuit, a plurality of first initial signal lines (e.g., INIT1(i) and INIT1(i+1)), a second initial signal line (e.g., INIT2(i) and INIT2(i+1)), and a power connection line 301. The first initial signal line, the second initial signal line, and the power connection line 301 all extend along a first direction F1. The orthographic projection of the second initial signal line on the base substrate is located between the orthographic projections of the first initial signal line and the power connection line 301 on the base substrate.

[0117] In some exemplary embodiments, Figure 10D As shown, the third insulating layer of the second sub-display area is provided with a plurality of via holes, including, for example, the 21st through 30th via holes K21 to K30. The third insulating layer, the second insulating layer, and the first insulating layer within the 21st through 26th via holes K21 to K26 are removed, exposing the surface of the semiconductor layer. The third insulating layer and the second insulating layer within the 27th through 27th via holes K27 are removed, exposing the surface of the first conductive layer. The third insulating layer within the 28th through 30th via holes K28 to K30 is removed, exposing the surface of the second conductive layer.

[0118] In some exemplary embodiments, Figure 10EAs shown, the third conductive layer of the second sub-display area includes at least: the first and second electrodes of multiple transistors of the second pixel circuit, and the first and second electrodes of multiple transistors of the invalid pixel circuit (for example, the first electrode 311 of the first reset transistor 31, the first electrode 321 of the threshold compensation transistor 32, the first electrode 341 of the data write transistor 34, the first electrode 351 of the first light-emitting control transistor 35, the second electrode 362 of the second light-emitting control transistor 36, and the first electrode 371 of the second reset transistor 37). The first electrode 311 of the first reset transistor 31 of the invalid pixel circuit in the i-th row is electrically connected to the first doped region of the active layer 310 through the twenty-first via K21, and is also electrically connected to the first initial signal line INIT1(i) through the twenty-ninth via K29. The first electrode 321 of the threshold compensation transistor 32 can be electrically connected to the first doped region of the active layer 320 through the twenty-second via K22, and is also electrically connected to the gate of the driving transistor 33 through the twenty-seventh via K27. The first electrode 341 of the data write transistor 34 can be electrically connected to the first doped region of the active layer 340 through the twenty-third via K23. The first electrode 351 of the first emission control transistor 35 can be electrically connected to the first doped region of the active layer 350 through the twenty-fourth via K24, and can also be electrically connected to the second electrode 382 of the storage capacitor 38 through the thirtieth via K30. The second electrode 362 of the second emission control transistor 36 can be electrically connected to the second doped region of the active layer 360 through the twenty-fifth via K25. The first electrode 371 of the second reset transistor 37 can be electrically connected to the first doped region of the active layer 370 through the twenty-sixth via K26, and can also be electrically connected to the second initial signal line INIT2(i+1) through the twenty-eighth via K28.

[0119] In some exemplary embodiments, Figure 10E As shown, the first electrode 351 of the first emission control transistor 35 of the inactive pixel circuit and the first electrode 251 of the first emission control transistor 25 of the second pixel circuit adjacent to the same row can be an integral structure. For example, the first electrode 351 of the first emission control transistor 35 of the inactive pixel circuit can be an integral structure with the first electrode 251 of the first emission control transistor 25 of the second pixel circuit adjacent to the left in the same row, or can be an integral structure with the first electrode 251 of the first emission control transistor 25 of the second pixel circuit adjacent to the right in the same row. However, this embodiment is not limited to this.

[0120] In some exemplary embodiments, Figure 10F As shown, the fourth insulating layer of the second sub-display area may include a plurality of via holes, such as the 31st to 35th via holes K31 to K35. The fourth insulating layer within the 31st to 35th via holes K31 to K35 is removed to expose the surface of the third conductive layer.

[0121] In some exemplary embodiments, Figure 9 As shown, the fourth conductive layer of the second sub-display area may include: a plurality of connection electrodes (for example, a second connection electrode 402 and a third connection electrode 403), a plurality of data lines (for example, data lines DL(j) to DL(j+7)), and a plurality of second power lines (for example, second power lines PL2(j) to PL2(j+5)). Among them, the third connection electrode 403 can be electrically connected to the second electrode 362 of the second light-emitting control transistor 36 of the invalid pixel circuit through the thirty-first via K31. The second connection electrode 402 can be electrically connected to the second electrode 262 of the second light-emitting control transistor of the second pixel circuit through the thirty-third via K33. The first electrode 341 of the data write transistor 34 of the invalid pixel circuit can be electrically connected to the data line (for example, data line DL(j+2)) through the thirty-fourth via K34. The first electrode of the data write transistor 24 of the second pixel circuit can be electrically connected to the data line (for example, data line DL(j+3)) through the thirty-fifth via K35. The second power line PL2(j+3) can be electrically connected to the first electrode 251 of the first light emission control transistor 25 of the second pixel circuit through the 32nd via K32. In this example, the inactive pixel circuit is not directly electrically connected to the second power line, but is electrically connected to the second power line through an adjacent second pixel circuit. This reduces the resistance of the second power line, thereby reducing the load on the second power line.

[0122] In some exemplary embodiments, Figures 9 to 10F As shown, the gate of the driving transistor 33 of the inactive pixel circuit is integrally structured with the first electrode 381 of the storage capacitor 38. The second electrode 382 of the storage capacitor 38 is electrically connected to the second power line via the first electrode 351 of the first light-emitting control transistor 35 and the adjacent second pixel circuit. The orthogonal projection area of ​​the second electrode 382 of the storage capacitor 38 of the inactive pixel circuit on the substrate can be less than or equal to the orthogonal projection area of ​​the second electrode 282 of the storage capacitor 28 of the second pixel circuit on the substrate. The orthogonal projection area of ​​the first electrode 381 of the storage capacitor 38 of the inactive pixel circuit on the substrate can be substantially the same as the orthogonal projection area of ​​the first electrode 281 of the storage capacitor 28 of the second pixel circuit on the substrate. The overlapping area of ​​the orthogonal projections of the second electrode 382 and the first electrode 381 of the storage capacitor 38 of the inactive pixel circuit on the substrate can be substantially the same as the overlapping area of ​​the orthogonal projections of the second electrode 282 and the first electrode 281 of the storage capacitor 28 of the second pixel circuit on the substrate.

[0123] Refer to the following Figures 9 to 10FThe preparation process of the display substrate is exemplified. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0124] In some exemplary embodiments, a process of preparing a display substrate may include the following operations.

[0125] (1) Forming a semiconductor layer.

[0126] In some exemplary embodiments, forming the semiconductor layer may include: depositing a semiconductor thin film on a substrate, patterning the semiconductor thin film through a patterning process, and forming a semiconductor layer in the second display area, such as Figure 10A The active layers of the seven transistors of a pixel circuit can be an integrated structure connected to each other.

[0127] In some exemplary embodiments, the material of the semiconductor layer may include, for example, polysilicon. The active layer may include at least one channel region and multiple doped regions. The channel region may not be doped with impurities and have semiconductor properties. Multiple doped regions may be on both sides of the channel region and are doped with impurities, thereby having conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. Portions of the active layer between transistors may be interpreted as impurity-doped wiring that can be used to electrically connect the transistors.

[0128] In some exemplary embodiments, the base substrate may be a rigid substrate, such as a glass substrate. However, this embodiment is not limited thereto. For example, the base substrate may be a flexible substrate.

[0129] (2) Forming a first conductive layer.

[0130] In some exemplary embodiments, a first insulating film and a first conductive film are sequentially deposited on the substrate substrate forming the aforementioned structure, and the first conductive film is patterned by a patterning process to form a first insulating layer covering the semiconductor layer and a first conductive layer disposed on the first insulating layer. Figure 10B shown.

[0131] (3) Forming a second conductive layer.

[0132] In some exemplary embodiments, a second insulating film and a second conductive film are sequentially deposited on the base substrate forming the aforementioned structure, and the second conductive film is patterned by a patterning process to form a second insulating layer covering the first conductive layer, and a second conductive layer provided on the second insulating layer, such as Figure 10C shown.

[0133] (4) Forming a third insulating layer.

[0134] In some exemplary embodiments, a third insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the third insulating film is patterned by a patterning process to form a third insulating layer, such as Figure 10D shown.

[0135] (5) Forming a third conductive layer.

[0136] In some exemplary embodiments, a third conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the third conductive film is patterned by a patterning process to form a third conductive layer on the third insulating layer. Figure 10E shown.

[0137] (6) Forming a fourth insulating layer.

[0138] In some exemplary embodiments, a fourth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer, such as Figure 10F shown.

[0139] (7) Forming a fourth conductive layer.

[0140] In some exemplary embodiments, a fourth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fourth insulating layer. Figure 9 shown.

[0141] At this point, the circuit structure layer of the second display area A2 is prepared. The first display area A1 may include a base substrate and a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer stacked on the base substrate.

[0142] (8) A first flat layer, a transparent conductive layer, a second flat layer, an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer are formed in sequence.

[0143] In some exemplary embodiments, a first flattening film is coated on the substrate having the aforementioned pattern formed thereon, and the first flattening film is patterned through a patterning process to form a first flattening layer. The first flattening layer may have a plurality of first transfer holes and a plurality of second transfer holes. The first flattening layer within the first transfer hole is removed to expose the first connection electrode of the effective pixel circuit, and the first flattening layer within the second transfer hole is removed to expose the second connection electrode of the second pixel circuit. Subsequently, a transparent conductive film is deposited on the substrate having the aforementioned pattern formed thereon, and the transparent conductive film is patterned through a patterning process to form a transparent conductive layer. The transparent conductive layer may include transparent conductive lines electrically connecting the effective pixel circuit and the first light-emitting element. Subsequently, a second flattening film is coated on the substrate having the aforementioned pattern formed thereon, and the second flattening film is patterned through a patterning process to form a second flattening layer. Subsequently, an anode film is deposited on the substrate having the aforementioned pattern formed thereon, and the anode film is patterned through a patterning process to form an anode layer. Subsequently, a pixel definition film is coated on the substrate having the aforementioned pattern formed thereon, and the pixel definition layer is formed through masking, exposure, and development processes. The pixel definition layer is formed with a plurality of pixel openings that expose the anode layer. An organic light-emitting layer is then formed within the aforementioned pixel openings, and the organic light-emitting layer is connected to the anode. A cathode film is then deposited and patterned using a patterning process to form a cathode layer, which is electrically connected to the organic light-emitting layer and the second power line. In some examples, an encapsulation layer is formed on the cathode layer, and the encapsulation layer may include a laminated structure of inorganic material / organic material / inorganic material.

[0144] In some exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer and the second insulating layer may be referred to as gate insulating (GI) layers, and the third insulating layer and the fourth insulating layer may be referred to as interlayer insulating (ILD) layers. The first planarizing layer and the second planarizing layer may be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer may be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate. The anode layer may be made of a reflective material such as metal, and the cathode layer may be made of a transparent conductive material. However, this embodiment is not limited thereto.

[0145] The structure of the display substrate and its preparation process in this embodiment are merely exemplary. In some exemplary implementations, the corresponding structure may be changed and patterning processes may be added or reduced according to actual needs.

[0146] The preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment and is well compatible with existing preparation processes. The process is simple to realize, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0147] Figure 11 FIG. 1 is another partial plan view of the second sub-display area after forming the semiconductor layer in at least one embodiment of the present disclosure. In some exemplary embodiments, as Figure 11 As shown, the active layer 310 of the first reset transistor, the active layer 320 of the threshold compensation transistor, the active layer 340 of the data write transistor, and the active layer 330 of the drive transistor in the invalid pixel circuit of the second display area can be an integrated structure. The active layer 360 of the second light-emitting control transistor and the active layer 370 of the second reset transistor can be an integrated structure. The active layer 350 of the first light-emitting control transistor is disconnected from the active layer 330 of the drive transistor, and the active layer 360 of the second light-emitting control transistor is disconnected from the active layer 330 of the drive transistor. The active layer 330 of the drive transistor, the active layer 350 of the first light-emitting control transistor, and the active layer 360 of the second light-emitting control transistor are independent of each other. In this way, the power consumption of charging and discharging the load capacitor when the drive transistor is turned on and off can be reduced.

[0148] In some exemplary embodiments, Figure 11 As shown, the active layers 310 to 370 of the seven transistors of the second pixel circuit of the second display area may be an integrated structure. The active layers of the seven transistors of the effective pixel circuit of the second display area may be an integrated structure.

[0149] The remaining film layer structures of the display substrate of this embodiment can refer to the description of the aforementioned embodiment, and thus will not be described again here.

[0150] Figure 12 FIG. 1 is another partial plan view of the second sub-display area of ​​at least one embodiment of the present disclosure. In some exemplary embodiments, as Figure 12 As shown, the gate of the driving transistor 33 of the inactive pixel circuit is integrally structured with the first electrode 381 of the storage capacitor 38, and the second electrode 382 of the storage capacitor 38 is electrically connected to the second power line via the first electrode 351 of the first light-emitting control transistor 35 and the adjacent second pixel circuit. The orthographic projection area of ​​the second electrode 382 of the storage capacitor 38 of the inactive pixel circuit on the substrate is smaller than the orthographic projection area of ​​the second electrode 282 of the storage capacitor 28 of the second pixel circuit on the substrate. The orthographic projection area of ​​the first electrode 381 of the storage capacitor 38 of the inactive pixel circuit on the substrate is substantially the same as the orthographic projection area of ​​the first electrode 281 of the storage capacitor 28 of the second pixel circuit on the substrate. The overlapping area of ​​the orthographic projections of the second electrode 382 and the first electrode 381 of the storage capacitor 38 of the inactive pixel circuit on the substrate is smaller than the overlapping area of ​​the orthographic projections of the second electrode 282 and the first electrode 281 of the storage capacitor 28 of the second pixel circuit on the substrate. In this exemplary embodiment, by reducing the area of ​​the second electrode of the storage capacitor of the invalid pixel circuit, the overlapping area of ​​the first electrode and the second electrode of the storage capacitor of the invalid pixel circuit can be reduced, thereby reducing the resistance and capacitance of the second power line.

[0151] The remaining film layer structures of the display substrate of this embodiment can refer to the description of the aforementioned embodiment, and thus will not be described again here.

[0152] Figure 13 This is a schematic diagram of heat generation of a second power line of a display substrate according to at least one embodiment of the present disclosure. Figure 13 (a) Figure 6 A schematic diagram of the heat generation of the second power supply line of the display substrate in the embodiment shown, Figure 13 (b) Figure 9 A schematic diagram of the heat generation of the second power supply line of the display substrate in the embodiment shown, Figure 13 (c) Figure 12 A schematic diagram of heat generation of a second power line of a display substrate in the embodiment shown is shown. Figure 6The display substrate of the embodiment shown is provided with a second power line connected to the invalid pixel circuit. The capacitance of the second power line of the display substrate may be approximately 2.648 pf, and the resistance may be approximately 841 ohms. Figure 9 The display substrate of the embodiment shown is not provided with a second power line connected to the invalid pixel circuit. The capacitance of the second power line of the display substrate may be approximately 2.557 pf and the resistance may be approximately 633 ohms. Figure 12 The display substrate of the embodiment shown is not provided with a second power line connected to the invalid pixel circuit, and the overlapping area of ​​the second electrode and the first electrode of the storage capacitor of the invalid pixel circuit is reduced. The capacitance of the second power line of the display substrate can be about 2.296 pf and the resistance is about 644 ohms. Figure 13 As shown, the heat generation of the second power line of the display substrate in the three embodiments is roughly the same. In this exemplary embodiment, by eliminating the second power line connected to the inactive pixel circuit or reducing the overlapping area between the second electrode and the first electrode of the storage capacitor of the inactive pixel circuit, the resistance and capacitance of the second power line can be reduced without increasing the heat generation of the second power line, thereby reducing the power consumption of the display substrate.

[0153] The present disclosure also provides a method for preparing a display substrate, comprising: forming a first power line in a peripheral region of a base substrate, and forming a circuit structure layer in a second display area of ​​the display region of the base substrate; wherein the second display area at least partially surrounds the first display area. The circuit structure layer includes: a plurality of power connection lines and at least one second power line. The second power line provides a second voltage signal that is greater than the first voltage signal provided by the first power line. The plurality of power connection lines extend along a first direction and are electrically connected to the first power line.

[0154] The method for preparing the display substrate of this embodiment can be referred to the description of the aforementioned embodiment, and thus will not be described in detail here.

[0155] At least one embodiment of the present disclosure further provides a display device including the display substrate as described above.

[0156] Figure 14 FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 14 As shown, this embodiment provides a display device, including: a display substrate 91 and a light sensor 92 located on the light-emitting side of the display structure layer away from the display substrate 91. The orthographic projection of the light sensor 92 on the display substrate 91 overlaps with the first display area A1.

[0157] In some exemplary embodiments, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be any product or component with a display function, such as an OLED display, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system, although the embodiments of the present disclosure are not limited thereto.

[0158] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to general designs. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, may be combined with each other to obtain new embodiments.

[0159] It should be understood by those skilled in the art that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising: a display area and a peripheral area located outside the display area; the display area comprising: a first display area and a second display area at least partially surrounding the first display area; the first display area being provided with a plurality of first light-emitting elements, the second display area being provided with a plurality of second light-emitting elements and a plurality of pixel circuits, the plurality of pixel circuits in the second display area being configured to drive the first light-emitting elements in the first display area and the second light-emitting elements in the second display area to emit light; the plurality of pixel circuits in the second display area comprising a plurality of first pixel circuits and a plurality of second pixel circuits, the first pixel circuits being arranged between a plurality of columns of the second pixel circuits; the plurality of first pixel circuits comprising a plurality of valid pixel circuits and a plurality of invalid pixel circuits, the valid pixel circuits being electrically connected to the first light-emitting elements, the invalid pixel circuits being not electrically connected to either the first light-emitting elements or the second light-emitting elements, and the second pixel circuits being electrically connected to the second light-emitting elements; The second display area includes at least one first sub-display area and at least one second sub-display area, the first sub-display area being adjacent to the first display area in a first direction; the effective pixel circuits are arranged in the first sub-display area, and the first pixel circuits in the second sub-display area are all ineffective pixel circuits and are not electrically connected to the first light-emitting element; a first power line, located in the peripheral area; a circuit structure layer, located in the second display area, comprising a plurality of power connection lines and at least one second power line; a second voltage signal provided by the second power line is greater than a first voltage signal provided by the first power line; The plurality of power connection lines extend along a first direction and are electrically connected to the first power lines. The plurality of power connection lines are located in the second sub-display area.

2. The display substrate according to claim 1, wherein: Extension lines of the plurality of power connection lines along the first direction do not overlap with the first display area.

3. The display substrate according to claim 2, wherein: The orthographic projection of at least one effective pixel circuit in the second display area on the base substrate does not overlap with the orthographic projection of at least one first light-emitting element in the first display area on the base substrate; An orthographic projection of at least one second pixel circuit in the second display area on the base substrate at least partially overlaps with an orthographic projection of at least one second light-emitting element on the base substrate.

4. The display substrate according to claim 3, wherein: The circuit structure layer further includes: a plurality of second initial signal lines extending along the first direction and a plurality of third initial signal lines extending along the first direction; At least one second initial signal line is electrically connected to a plurality of second pixel circuits arranged along the first direction, or is electrically connected to a plurality of second pixel circuits and a plurality of invalid pixel circuits arranged along the first direction; the second initial signal line is configured to provide an anode reset signal to the second light-emitting element through the second pixel circuit; At least one third initial signal line is electrically connected to a plurality of effective pixel circuits arranged along the first direction; the third initial signal line is configured to provide an anode reset signal to the first light-emitting element through the effective pixel circuit.

5. The display substrate according to claim 4, wherein: The circuit structure layer further includes: a plurality of first initial signal lines extending along the first direction; At least one first initial signal line is electrically connected to a plurality of first pixel circuits and a plurality of second pixel circuits arranged along the first direction, and the first initial signal line is configured to provide a first reset signal to the gates of the driving transistors of the first pixel circuits and the second pixel circuits.

6. The display substrate according to claim 5, wherein: The first initial signal line, the second initial signal line, the third initial signal line, and the power connection line are in the same layer structure.

7. The display substrate according to claim 6, wherein: The second power line extends along a second direction and is located on a side of the power connection line away from the base substrate. The second direction intersects the first direction.

8. The display substrate according to claim 5, wherein: The plurality of effective pixel circuits and the plurality of third initial signal lines are located in the first sub-display area.

9. The display substrate according to claim 8, wherein: In the first sub-display area, the orthographic projection of the third initial signal line on the base substrate is located between the orthographic projections of the first initial signal line and the second initial signal line on the base substrate; In the second sub-display area, an orthographic projection of the power connection line on the base substrate is located between an orthographic projection of the first initial signal line and an orthographic projection of the second initial signal line on the base substrate.

10. The display substrate according to any one of claims 2 to 9, characterized in that: The second pixel circuits and the effective pixel circuits in the second display area are directly electrically connected to the second power line, and at least one ineffective pixel circuit is electrically connected to the second power line through an adjacent second pixel circuit.

11. The display substrate according to claim 10, wherein: At least one pixel circuit among the plurality of first pixel circuits and the plurality of second pixel circuits includes: a first light emission control transistor; A first electrode of the first light emitting control transistor of the second pixel circuit is electrically connected to the second power line; A first electrode of the first light emission control transistor of the invalid pixel circuit is electrically connected to a first electrode of the first light emission control transistor of the adjacent second pixel circuit.

12. The display substrate according to claim 11, wherein: The first electrode of the first light emission control transistor of the invalid pixel circuit and the first electrode of the first light emission control transistor of the adjacent second pixel circuit are integrated into one structure.

13. The display substrate according to any one of claims 2 to 9, characterized in that: At least one pixel circuit among the plurality of first pixel circuits and the plurality of second pixel circuits comprises: a storage capacitor; The overlapping area of ​​the orthographic projection of the first electrode and the second electrode of the storage capacitor of the effective pixel circuit or the second pixel circuit on the substrate is greater than the overlapping area of ​​the orthographic projection of the first electrode and the second electrode of the storage capacitor of the invalid pixel circuit on the substrate.

14. The display substrate according to claim 13, wherein: The first electrode of the storage capacitor and the gate of the driving transistor are integrated into one structure, and the second electrode of the storage capacitor is electrically connected to the second power line.

15. The display substrate according to any one of claims 2 to 9, characterized in that: The invalid pixel circuit at least includes: a driving transistor, a first light emitting control transistor and a second light emitting control transistor; The gate of the first light emitting control transistor is electrically connected to the light emitting control line, the first electrode of the first light emitting control transistor is electrically connected to the second power line, and the second electrode of the first light emitting control transistor is electrically connected to the first electrode of the driving transistor; The gate of the second light emitting control transistor is electrically connected to the light emitting control line, and the first electrode of the second light emitting control transistor is electrically connected to the second electrode of the driving transistor; Active layers of the first light emission control transistor, the second light emission control transistor and the driving transistor of the inactive pixel circuit are independent of each other.

16. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 15.

17. A method for preparing a display substrate, characterized in that: include: forming a first power supply line in a peripheral area of ​​the base substrate, and forming a circuit structure layer in a second display area of ​​the display area of ​​the base substrate; The second display area at least partially surrounds the first display area; The first display area is provided with a plurality of first light-emitting elements, and the second display area is provided with a plurality of second light-emitting elements and a plurality of pixel circuits, the plurality of pixel circuits in the second display area being configured to drive the first light-emitting elements in the first display area and the second light-emitting elements in the second display area to emit light; the plurality of pixel circuits in the second display area include a plurality of first pixel circuits and a plurality of second pixel circuits, the first pixel circuits being arranged between a plurality of columns of the second pixel circuits; the plurality of first pixel circuits include a plurality of valid pixel circuits and a plurality of invalid pixel circuits, the valid pixel circuits being electrically connected to the first light-emitting elements, the invalid pixel circuits being not electrically connected to either the first light-emitting elements or the second light-emitting elements, and the second pixel circuits being electrically connected to the second light-emitting elements; The second display area includes at least one first sub-display area and at least one second sub-display area, the first sub-display area being adjacent to the first display area in a first direction; the effective pixel circuits are arranged in the first sub-display area, and the first pixel circuits in the second sub-display area are all ineffective pixel circuits and are not electrically connected to the first light-emitting element; In which, the circuit structure layer includes: multiple power connection lines and at least one second power line; the second voltage signal provided by the second power line is greater than the first voltage signal provided by the first power line; the multiple power connection lines extend along the first direction and are electrically connected to the first power line, and the multiple power connection lines are located in the second sub-display area.

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