Capacitance-to-digital converter, method and system

Abstract

Capacitance-to-digital converters, methods, and systems are provided. Apparatuses and methods of capacitance-to-digital code conversion are described. An apparatus includes a bridge circuit and a modulator front-end circuit. The bridge circuit includes a first terminal coupled to a reference cell and a second terminal coupled to a sensor cell. The modulator front-end circuit includes a comparator coupled to the bridge circuit, a first modulation capacitor coupled to a first input of the comparator, and a second modulation capacitor coupled to a second input of the comparator. The modulator front-end circuit provides a digital bit stream. A duty cycle of the digital bit stream is representative of a ratio between a capacitance of the sensor cell and a reference capacitance of the reference cell.

Description

[0001] Cross-references to related applications

[0002] This patent application claims the benefit of U.S. Provisional Patent Application No. 63 / 072,329, filed on August 31, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to sensing systems, and more specifically to capacitive sensing systems configurable to measure capacitance or convert capacitance into digital values ​​representing capacitance. Background Technology

[0004] Capacitive sensing systems sense electrical signals generated on electrodes that reflect changes in capacitance. These changes in capacitance indicate touch events (i.e., an object approaching a specific electrode). Capacitive sensing elements can replace mechanical buttons, knobs, and other similar mechanical user interface controls. The use of capacitive sensing elements eliminates the need for complex mechanical switches and buttons, providing reliable operation even under harsh conditions. Furthermore, capacitive sensing elements are widely used in modern customer applications, offering new user interface options in existing products. The range of capacitive sensing elements can vary from single buttons to large arrays of elements arranged as capacitive sensors on a touch-sensing surface.

[0005] An array of capacitive sensing elements works by measuring the capacitance of the sensing elements and looking for capacitance increments (changes) that indicate the touch or presence of a conductive object. When a conductive object (e.g., a finger, hand, or other object) comes into contact with or is very close to a capacitive sensing element, the capacitance changes and the conductive object is detected. The capacitance change of the capacitive touch sensing element can be measured by electrical circuitry. The electrical circuitry converts the measured capacitance of the capacitive sensing element into a digital value.

[0006] There are two typical types of capacitance: 1) mutual capacitance, where the capacitance sensing circuit is coupled to two electrodes and a drive / receive configuration to measure the capacitance between the electrodes; and 2) self-capacitance, where the capacitance sensing circuit is coupled to a single electrode of a capacitor, with the second electrode connected to a direct current (DC) voltage level or parasiticly coupled to ground. Touch panels have loads of both types of distributed capacitance, and some touch solutions uniquely or in a hybrid manner sense both types of capacitance through their various sensing modes. Summary of the Invention

[0007] This invention provides a capacitor-to-digital converter, comprising:

[0008] A bridge circuit includes a first terminal coupled to a reference unit and a second terminal coupled to a sensor unit; and

[0009] a modulator front-end circuit comprising a comparator coupled to the bridge circuit, a first modulation capacitor coupled to a first input of the comparator, and a second modulation capacitor coupled to a second input of the comparator, wherein the modulator front-end circuit is configured to provide a digital bit stream, wherein a duty cycle of the digital bit stream is representative of a ratio between a capacitance of the sensor cell and a reference capacitance of the reference cell.

[0010] The present invention also provides a method comprising:

[0011] in a first phase, applying a supply voltage to charge a sensor electrode of a sensor cell to a first voltage level;

[0012] in a second phase, coupling the sensor electrode to a first modulation capacitor to charge the first modulation capacitor, the first modulation capacitor being coupled to a first input of a comparator;

[0013] in a third phase, coupling the sensor electrode to a ground potential to ground the sensor electrode; and

[0014] in a fourth phase, coupling the sensor electrode to a second modulation capacitor to discharge the second modulation capacitor, the second modulation capacitor being coupled to a second input of the comparator, wherein a modulator front-end circuit comprises the first modulation capacitor, the second modulation capacitor, and the comparator, the modulator front-end circuit being configured to provide a digital bit stream, and wherein a duty cycle of the digital bit stream is representative of a ratio between a capacitance of the sensor cell and a reference capacitance of a reference cell.

[0015] The present invention also provides a system comprising:

[0016] a reference cell;

[0017] a sensor cell; and

[0018] a capacitance-to-digital converter comprising:

[0019] a bridge circuit comprising a first terminal coupled to a reference cell and a second terminal coupled to a sensor cell; and

[0020] a modulator front-end circuit comprising a comparator coupled to the bridge circuit, a first modulation capacitor coupled to a first input of the comparator, and a second modulation capacitor coupled to a second input of the comparator, wherein the modulator front-end circuit is configured to provide a digital bit stream, wherein a duty cycle of the digital bit stream is representative of a ratio between a capacitance of the sensor cell and a reference capacitance of the reference cell. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1A capacitance-to-digital converter (CDC) configured for ratio metric self-capacitance-to-code conversion is shown, in accordance with an embodiment.

[0022] Figure 2 A CDC configured for ratio metric self-capacitance-to-code conversion is shown, in accordance with an embodiment. Figure 1 Voltage waveforms at various nodes of the CDC of

[0023] Figure 3A A CDC configured for ratio metric self-capacitance-to-code conversion including a compensation branch is shown, in accordance with an embodiment.

[0024] Figure 3B A CDC configured for ratio metric self-capacitance-to-code conversion including a compensation branch is shown, in accordance with another embodiment.

[0025] Figure 3C A CDC configured for ratio metric self-capacitance-to-code conversion including a compensation branch is shown, in accordance with another embodiment.

[0026] Figure 3D A CDC configured for ratio metric self-capacitance-to-code conversion including a feedback switch for a reference unit is shown, in accordance with another embodiment.

[0027] Figure 4 A CDC configured for ratio metric self-capacitance-to-code conversion is shown, in accordance with an embodiment. Figure 3D Voltage waveforms at various nodes of the CDC of

[0028] Figure 5 A CDC configured for ratio metric self-capacitance-to-code conversion having a mutual capacitance reference unit is shown, in accordance with an embodiment.

[0029] Figures 6A-6D An effective representation of the CDC of Figure 5 in each of a first phase, a second phase, a third phase, and a fourth phase, in accordance with an embodiment.

[0030] Figures 6E-6H An effective representation of the CDC of Figure 1 in each of a first phase, a second phase, a third phase, and a fourth phase, in accordance with an embodiment.

[0031] Figure 7 A CDC configured for ratio metric self-capacitance-to-code conversion having a single-ended analog front end (AFE) is shown, in accordance with an embodiment.

[0032] Figure 8 Voltage waveforms at various nodes of the CDC of Figure 7

[0033] Figure 9 ​CDC with active shield driver is shown in accordance with an embodiment.

[0034] Figure 10 CDC configured for ratio metric self-capacitance to code conversion with single ended AFE is shown in accordance with an embodiment.

[0035] Figure 11A CDC configured for ratio metric self-capacitance to code conversion with compensation branch is shown in accordance with an embodiment.

[0036] Figure 11B CDC configured for ratio metric self-capacitance to code conversion with increased resolution is shown in accordance with an embodiment.

[0037] Figure 12 CDC configured for ratio metric mutual-capacitance to code conversion with single ended AFE is shown in accordance with an embodiment.

[0038] Figure 13 CDC in accordance with an embodiment. Figure 12 Voltage waveforms at nodes of the CDC.

[0039] Figure 14 CDC configured for ratio metric mutual-capacitance to code conversion with single ended AFE is shown in accordance with an embodiment.

[0040] Figure 15 Flowchart of one embodiment of a method of capacitance to digital code conversion in accordance with one embodiment. DETAILED DESCRIPTION

[0041] Sensing devices must be robust and high performance while still being relatively inexpensive and consuming relatively low power. Sensing devices such as multi-sense transducers can include capacitance sensing, inductance sensing, resistance sensing, and voltage sensing devices and can convert sensing signals, which appear as currents, into digital codes. However, variations in supply voltage, clock frequency, reference voltage, and current digital-to-analog converters (IDACs) can present problems for high sensitivity applications. For example, for high sensitivity and fast scan applications, noise effects from the sources listed above can result in a decrease in signal-to-noise ratio (SNR). Low SNR can limit performance for various applications.

[0042] Various embodiments of apparatuses and methods for ratio metric capacitance-to-digital conversion are described herein. Ratio metric measurements depend on a ratio of known values (e.g., a ratio of capacitance values), rather than on a direct current (DC) voltage source value, among other things. Ratio metric capacitance-to-digital conversion can eliminate the above and other issues. Ratio metric capacitance-to-digital conversion can be insensitive to clock frequency, current source, and power supply and reference voltage variations that support capacitance, inductance, resistance, voltage, and current measurements. Aspects of the present disclosure provide a fast, simple, high performance, and low cost solution for capacitance-to-digital conversion. Aspects of the present disclosure can be implemented in various configurations, including with (pseudo) differential analog front end (AFE) or single-ended AFE.

[0043] A ratio metric capacitance-to-digital converter (CDC) can include a sensor cell having a sensor capacitance and a reference cell having a reference capacitance. The sensor cell can include a sensor electrode, and the reference cell can include a reference electrode. The sensor electrode and the reference electrode can be charged and discharged in certain phases, and can alternately charge and discharge a first modulator capacitor and a second modulator capacitor to generate a bit stream having a duty cycle representative of a ratio between the sensor capacitance and the reference capacitance, thus allowing common mode noise between the sensor cell and the reference cell to be eliminated.

[0044] Figure 1 A capacitance-to-digital converter (CDC) 100 configured for ratio metric self-capacitance-to-code conversion is shown in accordance with an embodiment. The CDC 100 can be a four-phase CDC, and can include a bridge circuit 120 and a modulator front-end circuit 130. The CDC 100 can also include a sensor cell 105 having a sensor capacitance 112 (Cs) and a reference cell 115 having a reference capacitance 122 (Cref).

[0045] The modulator front-end circuit 130 can be a differential analog front end (AFE), and can include a comparator 142, a modulator capacitor 141.1, and a modulator capacitor 141.2. In one embodiment, the modulator capacitor 141.1 and the modulator capacitor 141.2 have the same capacitance. In other embodiments, the modulator capacitors 141.1 and 141.2 can have different capacitance values. The modulator capacitors can also be referred to as summing capacitors. The modulator front-end circuit 130 can also include a voltage detector, AND gates 148.2 and 148.4, and a clock signal divider.

[0046] The modulating capacitors 141.1 can be coupled to a first input of the comparator 142, and the modulating capacitors 141.2 can be coupled to a second input of the comparator 142. The comparator 142 can also be coupled to the bridge circuit 120. The bridge circuit 120 can have a first terminal coupled to the reference unit 115 and a second terminal coupled to the sensor unit 105. The bridge circuit 120 can include switches that can be closed to couple the sensor unit 105 and / or the reference unit 115 to the modulator front-end circuit 130 when the corresponding phase is enabled. The signals switching the phases (PhO, Phl, Ph2, and Ph3) can be clocked by the sensor clock frequency Fs.

[0047] The modulator front-end circuit 130 can include or be coupled to digitization circuitry to provide a digital bit stream (e.g., one or more digital values) to the processing unit 160. The digital bit stream can represent the sensor capacitance CS of the sensor unit 105, which can be less than the reference capacitance Cref of the reference unit 115. The duty cycle of the digital bit stream can represent the ratio between the sensor capacitance CS and the reference capacitance Cref of the reference unit 115. In particular, the duty cycle is given by:

[0048]

[0049] where 0 < DC < 1. Equation 1 is satisfied when the following condition is true:

[0050] and

[0051] The modulator front-end circuit 130 can include a sequencer 146 to generate various phases (e.g., PhO, Phl, Ph2, Ph3) that can be sequenced at the frequency of Fs (also referred to as the sensor excitation frequency) to generate a bit stream that can include low values (0) and high values (1). The illustrated phases can correspond to the labeled switches. In particular, for a CDC (e.g., CDC 100) configured for a ratio metric self-capacitance-to-code conversion, the duty cycle of the bit stream can represent the ratio between the sensor capacitance CS of the sensor unit 105 and the reference capacitance Cref of the reference unit 115. The phases are designed such that each of the modulating capacitors 141.1 and 141.2 can be alternately charged and discharged by the sensor unit and the reference unit. The reference capacitance of the reference unit 115 can be set by a single capacitor or can be a variable capacitance, e.g., using a capacitance digital-to-analog converter (DAC).

[0052] In the first phase PhO, the supply voltage VDDA can be applied to the sensor electrode of the sensor unit 105 to charge the sensor electrode to the supply voltage level VDDA, and the supply voltage VDDA can be applied to the reference electrode of the reference unit 115 to charge the sensor electrode to the supply voltage level VDDA.

[0053] In the second phase Phl, the sensor electrode of the sensor unit 105 can be coupled to the modulation capacitor 141.1 to charge the modulation capacitor 141.1. In case the bitstream is low (0), the output of the first AND gate for generating the second feedback phase Phl_fb is low, and thus the reference unit is not coupled to the bridge circuit 120. In case the bitstream is high (1), the output of the first AND gate for generating the second feedback phase Phl_fb is high, and the reference electrode of the reference unit 115 is coupled to the modulation capacitor 141.2 to charge the modulation capacitor 141.2.

[0054] In the third phase Ph2, the sensor electrode of the sensor unit 105 is disconnected from the modulation capacitor 141.1 and coupled to the ground potential to ground the sensor electrode. The reference electrode of the reference unit 115 is disconnected from the modulation capacitor 141.2 and coupled to the ground potential to ground the reference electrode.

[0055] In the fourth phase Ph3, the sensor electrode of the sensor unit 105 can be coupled to the modulation capacitor 141.2 to discharge the modulation capacitor 141.2. In case the bitstream is low (0), the output of the second AND gate for generating the fourth feedback phase Ph3_fb is low, and thus the reference unit is not coupled to the bridge circuit 120. In case the bitstream is high (1), the output of the second AND gate for generating the fourth feedback phase Ph3_fb is high, and the reference electrode of the reference unit 115 is coupled to the modulation capacitor 141.1 to discharge the modulation capacitor 141.1. In other words, in the second and fourth phases, the sensor unit 105 and the reference unit 115 alternate between charging and discharging different capacitors (modulation capacitors 141.1 and 141.2).

[0056] At any given point in time, the first input of comparator 142 has a voltage Vm1 and the second input of comparator 142 has a voltage Vm2, which vary as a function of time. When the second feedback phase Phl_fb and the fourth feedback phase Ph3_fb are enabled (e.g., when the bitstream is high), the difference AV between Vm2 and Vm1 (AV = Vm2 - Vm1) can decrease as Cref is greater than Cs. In other words, modulating capacitor 141.1 discharges more than modulating capacitor 141.2. On the other hand, as the difference AV changes polarity, the feedback phases Phl_fb and Ph3_fb can be disabled as the reference unit 115 becomes disconnected (in other words, decoupled from the bridge circuit 120). This can be considered as two processes occurring in parallel. The first process switches the sensor unit 105 with the capacitance Cs, which allows the charging of modulating capacitor 141.1 and the discharging of modulating capacitor 141.2, and is uninterrupted during the conversion time. The second process switches the reference unit 115 with the capacitance Cref, which allows the charging of modulating capacitor 141.2 and the discharging of modulating capacitor 141.1. If the difference AV between Vm2 and Vm1 is positive and Cref is greater than Cs, the process is interrupted. Therefore, no precise common-mode direct current (DC) voltage is needed. Over several Fs clock cycles, AV can reach half of the supply voltage VDDA due to the symmetric switching process. The first phase PhO and the third phase Ph2 are designed to excite the sensor unit 105 and the reference unit 115.

[0057] In other implementations, the processes can be reversed. In this case, the first process that switches the sensor unit 105 allows the charging of modulating capacitor 141.2 and the discharging of modulating capacitor 141.1, while the second process that switches the reference unit 115 allows the charging of modulating capacitor 141.1 and the discharging of modulating capacitor 141.2. In view of this reversal, the output of comparator 142 should also be reversed.

[0058] It is worth noting that although CDC 100 is described as having four phases (PhO, Phl, Ph2, and Ph3) and two feedback phases (Phl_fb and Ph3_fb), in other implementations, there can be fewer or more phases, and the number of feedback phases can be less than or equal to the number of phases. In some implementations, there can be more feedback phases than the number of phases, e.g., when some feedback phases require positive feedback from only one phase and other feedback phases require positive feedback from a combination of phases.

[0059] As Figure 1As depicted, the CDC 100 shows a case where the sensor excitation frequency Fs is equal to the clock frequency Fmod of the modulator front-end circuit 130. The CDC 100 can operate as a combination of charge transfer and modulator front-end circuit. The modulator front-end circuit can be a differential sigma-delta modulator or other type of modulator. The CDC 100 and the method of converting capacitance to digital values are completely independent of voltage, current, and time parameter variations.

[0060] Figure 2 Voltage waveforms at various nodes of the CDC 100 are shown in accordance with an embodiment. Figure 1 The sequencer 146 generates the first phase PhO, the second phase Phl, the third phase Ph2, and the fourth phase Ph3 in sequence. The second feedback phase Phl_fb and the fourth feedback phase Ph3_fb are at the same time as the second phase Phl and the fourth phase Ph3, respectively, but are only enabled when the bitstream is high (1). When the bitstream is low, the second feedback phase Phl_fb and the fourth feedback phase Ph3_fb are not enabled even when the first phase Phl and the fourth phase Ph3 are enabled.

[0061] In Figure 2 VC represents the voltage of the sensor cell 105. During the first phase (PhO is high and Phl, Ph2, and Ph3 are low), the sensor cell 105 can be coupled to the supply voltage source and the sensor electrode of the sensor cell 105 can be charged to the supply voltage VDDA. During the second phase (Phl is high and PhO, Ph2, and Ph3 are low), the sensor electrode can be coupled to the modulating capacitor 141.1 to charge the modulating capacitor 141.1 and thus the voltage at the sensor electrode decreases. During the third phase (Ph2 is high and PhO, Phl, and Ph3 are low), the sensor electrode can be coupled to the ground potential to ground the sensor electrode and thus the voltage at the sensor electrode decreases to the ground potential. During the fourth phase (Ph3 is high and PhO, Phl, and Ph2 are low), the sensor electrode can be coupled to the modulating capacitor 141.2 to discharge the modulating capacitor 141.2 (if the bitstream is high, the modulating capacitor 141.2 can be charged by the reference electrode of the reference cell 115 during the second phase) and thus the voltage at the sensor electrode increases.

[0062] The described method of CDC conversion can be independent of voltage, current, and time parameter variations. It is evident from Equation 1 that the output duty cycle of the bitstream depends only on the relationship between the sensor capacitance and the reference capacitance.

[0063] It should be noted that a CDC such as CDC 100 can include more than one sensor unit having a sensor capacitance. Each sensor unit can be used as a sensor. The sensor units can also be combined or coupled together and used simultaneously. The number of charge transfer cycles can define the resolution of the CDC. The digital time can be used to count the number of charge transfer cycles, and the measurement process can be terminated when the desired number of charge transfer cycles is reached. Thus, the result output by the CDC is not dependent on the clock frequency (Fclk), but rather on the number of clock cycles (Nres). This allows the CDC to use different types of sequencers with a fixed number of clock cycles, including spread spectrum clock sequencers, random clock sequencers, pseudo-random clock sequencers, fixed frequency clock sequencers, and the like. The raw count of the digital bit stream for a CDC with a first order decimator is

[0064] RawCount = N res · DC, where N res = T mea · F mod (3)

[0065] Figures 3A-3D Various CDC configurations including compensation circuits are shown. Figures 3A-3C The compensation branch can improve the resolution of the capacitance-to-digital conversion by eliminating parasitic capacitance from the conversion. Figure 3D The resolution is improved by including an additional feedback phase.

[0066] Figure 3A A CDC 300a including a compensation branch 340a configured for ratio metric self-capacitance-to-code conversion according to an embodiment is shown. The CDC 300a is the same or similar to the CDC 100 of Figure 1 except that the CDC 300a includes the compensation branch 340a. The CDC 300a can be a four-phase CDC with a four-phase compensation branch 340a. The compensation branch 340a can include a compensation unit 325a having a compensation capacitance, which is a self-capacitance. The compensation capacitance can be provided by a capacitor Ccomp 322, which can be a variable capacitance (e.g., provided by a capacitor stack) or can be an inherent capacitance. In some embodiments, the compensation unit 322 can include at least a portion of the bridge circuit 320a. In addition to the portion of the bridge circuit 320a that can be a portion of the compensation branch 340a, the bridge circuit 320a can be similar to the bridge circuit 320 of Figure 1The bridge circuit 320a can include a third terminal coupled to the compensation unit 325a (in addition to the first terminal coupled to the sensor unit 105 and the second terminal coupled to the reference unit 115). A portion of the bridge circuit 320a can be coupled to or decoupled from the modulator front-end circuit 130 by a switch 350a that is synchronized to the phases (PhO, Phl, Ph2, and Ph3) generated by the sequencer 146. In other words, the compensation branch 340a can be a four-phase controlled compensation branch, meaning that the compensation branch 340a can have a different operation in each of the four phases (PhO, Phl, Ph2, and Ph3) generated by the sequencer 146.

[0067] In addition to the phase operations described with reference to Figure 1 In addition to the phase operations described with reference to

[0068] Inclusion of a compensation branch (e.g., the compensation branch 340a) can increase the CDC resolution by affecting the duty cycle of the bitstream. For example, in addition to the sensor and reference capacitances, the duty cycle can depend on the compensation capacitance. As described above (without a compensation branch), the duty cycle can be determined by the ratio of the sensor capacitance to the reference capacitance. When the compensation branch 340a is included, this ratio can be based on the reference capacitance, the sensor capacitance, and the compensation capacitance. In particular, for the CDC 300a, the duty cycle can be given by:

[0069]

[0070] where 0 < DC < 1 and C s - C s_comp + AC s ≤ C ref , and AC s represents the variation in the compensation capacitance due to the compensation capacitor 322 being a variable capacitor. In other words, when the value of C ref is defined, there can be a maximum sensor capacitance C s_max = C s + AC s and a minimum compensation capacitance value C s_comp_min . In some implementations, the sensor capacitance Cs C can be defined as C ref ≥ 1.3 (C s - C s_comp_min + ΔC s_max ). In some implementations, the coefficient (e.g., 1.3 in the previous sentence) can be other values such as, but not limited to, 1, 1.2, 1.5, 2, etc.

[0071] Figure 3B CDC 300b configured for ratio metric self-capacitance to code conversion including a compensation branch 340b is shown in accordance with another implementation. As indicated by like reference numbers, CDC 300b is the same or similar to CDC 100 described with reference to Figure 1 except that CDC 300b includes a compensation branch 340b. CDC 300b can be a four-phase CDC with a two-phase compensation branch 340b. The compensation branch 340b can include a compensation capacitor (Ccomp) 332 that can have a compensation capacitance that is a mutual capacitance. The compensation capacitor 332 can be a variable capacitor or a fixed capacitor. The compensation branch 340b can be a two-phase controlled compensation branch, meaning that in a first compensation branch phase (e.g., Ph0 and / or Phl), the compensation branch 340b can have a certain operation, and in a second compensation branch phase (e.g., Ph2 and / or Ph3), the compensation branch 340b can have another operation.

[0072] The bridge circuit 320b can be similar to the bridge circuit 120 described with reference to Figure 1 except that a portion of the bridge circuit 320b can be a portion of the compensation branch 340b. The bridge circuit 320b can include a third terminal coupled to the compensation capacitor 332. The compensation capacitor 332 can be coupled to or decoupled from the modulator front-end circuit 130 by switches that are phased in synchronization with the phases (Ph0, Phl, Ph2, and Ph3) generated by the sequencer 146.

[0073] In addition to the phase operations described with reference to Figure 1 , in the first phase (Ph0) and the second phase (Phl), a first compensation electrode of the compensation capacitor 332 can be coupled to a ground potential. Specifically, in the first phase, a second compensation electrode of the compensation capacitor 332 can be coupled to a power supply voltage and a sensor electrode of the sensor unit 105, such that the sensor electrode can be charged to a voltage less than the power supply voltage level VDDA. Specifically, in the second phase, the second electrode of the compensation capacitor 332 can be coupled to the modulator capacitor 141.1 as well as the sensor electrode of the sensor unit 105.

[0074] In the third phase (Ph2) and the fourth phase (Ph3), the first compensation electrode of the compensation capacitor 332 can be coupled to the supply voltage. Specifically, in the third phase, the second compensation electrode of the compensation capacitor 332 can be coupled to the ground potential and the sensor electrode of the sensor unit 105, such that the sensor electrode is not fully discharged to the ground potential. Specifically, in the fourth phase, the second compensation electrode of the compensation capacitor 332 can be coupled to the sensor electrode and the modulation capacitor 141.2, such that the modulation capacitor 141.2 can be partially discharged onto both the sensor electrode and the second compensation electrode.

[0075] Similar to adding the compensation branch 340a, Figure 3A the compensation branch 340b can increase the CDC resolution by affecting the duty cycle of the bitstream. For example, in addition to the sensor capacitance and the reference capacitance, the duty cycle can depend on the compensation capacitance. As described above (in the absence of a compensation branch), the duty cycle can be determined by the ratio of the sensor capacitance to the reference capacitance. When including the compensation branch 340a, the ratio can be based on the reference capacitance, the sensor capacitance, and the compensation capacitance. In particular, for the CDC 300b, the duty cycle can be given by:

[0076]

[0077] where 0 < DC < 1 and C s - C s_comp + AC s ≤ C ref , and AC s represents a potential variation or change in the compensation capacitance due to the compensation capacitor 322 being a variable capacitor.

[0078] Figure 3C A CDC 300c configured for ratio metric self-capacitance-to-code including a compensation branch 340c according to another embodiment is shown. The CDC 300c is the same as or similar to the CDC 100 of Figure 1 except that the CDC 300c includes the compensation branch 340c. The CDC 300c can be a four-phase CDC with a two-phase compensation branch 340c. The compensation branch 340c can include a compensation capacitor (Ccomp) 342 that can have a compensation capacitance that is a mutual capacitance. The compensation capacitor 342 can be a variable capacitor or a fixed capacitor. The compensation branch 340c can be a two-phase controlled compensation branch, meaning that in a first compensation branch phase (e.g., PhO and / or Phl), the compensation branch 340b can have a certain operation, and in a second compensation branch phase (e.g., Ph2 and / or Ph3), the compensation branch 340b can have another operation.

[0079] The bridge circuit 320c can be similar to the bridge circuit 120 of Figure 1 except that a portion of the bridge circuit 320b can be a portion of the compensation branch 340b. The bridge circuit 320b can include a third terminal coupled to a compensation capacitor 332c. The compensation capacitor 342 can be coupled to or decoupled from the modulator front-end circuit 130 by switches phased in synchronization with the phases (PhO, Phl, Ph2, and Ph3) generated by the sequencer 146.

[0080] Depending on whether the output bitstream is high (1) or low (0), the compensation unit 342 can be coupled to the reference unit 115 in certain phases.

[0081] When the output bitstream is low, the second feedback phase (Phl_fb) and the fourth feedback phase (Ph3_fb) can remain low (not enabled) even when the second phase and / or the third phase are enabled. Thus, in addition to the phase operations described with reference to Figure 1 in the first phase (PhO) and the second phase (Phl), a supply voltage can be applied to a first compensation electrode of the compensation unit 342. Further, in the first phase and the second phase, a second compensation electrode of the compensation unit 342 can be coupled to the modulation capacitor 141.2 and can charge the modulation capacitor 141.2. In the third phase (Ph2) and the fourth phase (Ph3), the first compensation electrode can be coupled to a ground potential and the second compensation electrode can be coupled to the modulation capacitor 141.1 to partially discharge the modulation capacitor 141.1.

[0082] When the output bitstream is high, during the second phase, the second compensation electrode can also be coupled to the reference unit 115 and both the reference electrode and the second compensation electrode can be coupled to the modulation capacitor 141.2 to charge the modulation capacitor 141.2. During the fourth phase, the second compensation electrode can be coupled to the reference unit 115 and both the reference electrode and the second compensation electrode can be coupled to the modulation capacitor 141.1 to discharge the modulation capacitor 141.1. Further, similar to the CDC 300b of Figure 3B the duty cycle of the output bitstream can be given by Equation 4.

[0083] As shown in Figures 3A-3B adding a compensation branch can improve the CDC resolution. The reference capacitance value Crefmay be reduced along with the reference compensation value Cref_comp. Thus, the new Crefvalue used here can be lower than the C refThe sensitivity of the sensor remains unchanged. This means that the relationship ACs / Cref increases and the converter resolution increases. For example, if Cs_comp is the mutual capacitance of the sensor, the converter mode becomes hybrid and the conversion result reflects changes in both self- and mutual capacitance. In other words, there can be a two-electrode sensor with self- and mutual capacitance properties, and mutual capacitance changes can affect the sensing result.

[0084] A second method for increasing resolution uses a modulation frequency Fmod higher than the sensor clock frequency Fs. Figure 3D A converter schematic is shown when Fmod is K = 2, 3, 4... times higher than Fs. Figure 4 Voltage waveforms in key nodes are shown for K = 4.

[0085] Figure 3D A CDC 300d configured for ratio metric self-capacitance to code conversion according to another embodiment is shown including feedback switches for the reference cells. As indicated by like reference numerals, the CDC 300d is the same or similar to the CDC 100 of Figure 1 but with an improved bridge circuit 320d and an improved modulator front-end circuit 330d. The CDC 300d can be a four-phase CDC. In the depicted embodiment, when the bitstream is high, the reference cell 115 can be coupled to the modulator front-end circuit 330d only because each corresponding feedback phase (PhO_fb, Phl_fb, Ph2_fb, and Ph3_fb) is enabled by one or more feedback signals. A frequency divider 347.2 receives a clock signal and, like before, divides the frequency of the signal in half, and a second frequency divider 347.1 receives the divided frequency from the frequency divider 347.2 and also divides the signal by four to switch the phases PhO, Phl, Ph2, and Ph3.

[0086] The phases are designed such that each of the modulation capacitors 141.1 and 141.2 can be charged and discharged alternately by the sensor cell and the reference cell. The reference capacitance of the reference cell 115 can be set by a single capacitor or can be a variable capacitance, for example, using a capacitance digital-to-analog converter (DAC). The phases can be generated by a sequencer 346 and the feedback phases can be generated by a sequencer 345. The feedback phases can depend on the bitstream being high and the corresponding phases are enabled via AND gates 348.1-348.4.

[0087] In the first phase PhO, the supply voltage VDDA can be applied to the sensor electrode of the sensor unit 105 to charge the sensor electrode to the supply voltage level VDDA, and the supply voltage VDDA can be applied to the reference electrode of the reference unit 115 to charge the sensor electrode to the supply voltage level VDDA. In case the bitstream is high (1), the output of the AND gate 348.1 for generating the first feedback phase PhO_fb is high, and the reference unit can be coupled to the supply voltage and charged to the supply voltage level. In case the bitstream is low (0), the output of the AND gate 348.1 for generating the first feedback phase PhO_fb is low, and thus the reference unit is not coupled to the supply voltage and not charged to the supply voltage level.

[0088] In the second phase Phl, the sensor electrode of the sensor unit 105 can be coupled to the modulation capacitor 141.1 to charge the modulation capacitor 141.1. In case the bitstream is high (1), the output of the AND gate 348.2 for generating the second feedback phase Phl_fb is high, and the reference electrode of the reference unit 115 can be coupled to the modulation capacitor 141.2 to charge the modulation capacitor 141.2. In case the bitstream is low (0), the output of the AND gate 348.2 for generating the second feedback phase Phl_fb is low, and thus the reference unit can not be coupled to the bridge circuit 320d.

[0089] In the third phase Ph2, the sensor electrode of the sensor unit 105 can be disconnected from the modulation capacitor 141.1 and coupled to the ground potential to ground the sensor electrode. In case the bitstream is high, the output of the AND gate 348.3 for generating the third feedback phase Ph2_fb can be high, and the reference electrode of the reference unit 115 can be disconnected from the modulation capacitor 141.2 and coupled to the ground potential to ground the reference electrode. In case the bitstream is low, the output of the AND gate 348.3 can be low, and the reference electrode of the reference unit can be disconnected from the modulation capacitor 141.2, but not coupled to the ground potential.

[0090] In the fourth phase Ph3, the sensor electrode of the sensor unit 105 can be coupled to the modulation capacitor 141.2 to discharge the modulation capacitor 141.2. In case the bitstream is high (1), the output of the AND gate 348.4 for generating the fourth feedback phase Ph3_fb is high, and the reference electrode of the reference unit 115 can be coupled to the modulation capacitor 141.1 to discharge the modulation capacitor 141.1. In case the bitstream is low (0), the output of the AND gate 348.4 for generating the fourth feedback phase Ph3_fb is low, and thus the reference unit can not be coupled to the bridge circuit 320d.

[0091] Figure 4 voltage waveforms at various nodes of the CDC 300d are shown. A case where the ratio of the reference capacitance to the sensor capacitance is 3 / 2 (Cref / Cs = 3 / 2) and the ratio of the modulation frequency (e.g., modulator front-end circuit clock frequency) to the sensor excitation frequency is 4 (Fmod / Fs = 4) is depicted. It should be noted that Fmod / Fs is also denoted as K herein. Figure 3D

[0092] The duty cycle of the output bitstream is calculated as follows:

[0093] where 0 < DC < 1 (6)

[0094] Equation 6 indicates that a K times lower reference capacitance Cref value can be used, which can be beneficial for chip-integrated reference capacitors (or reference cells).

[0095] Returning to Equation 3, the increase in resolution can be obtained by increasing Fmod by K times while keeping the measurement time Tmea.

[0096] The two methods of improving resolution described can be combined. Figures 3A-3C CDCs 300a-c are shown that include a compensation branch that can be controlled by four-phase or two-phase, which can be sequenced by a digital sequencer at a compensation frequency Fcomp. Generally, Fcomp can be less than or greater than the sensor clock frequency Fs, and their relationship can be characterized by a factor Kcomp (which can also be referred to as a compensation coefficient) (e.g., Fcomp = Kcomp · Fs). In some embodiments, Fcomp can be the same as the sensor clock frequency Fs, in which case Kcomp = 1. In such a case, the modulation frequency Fmod, the sensor clock frequency Fs, and the compensation frequency Fcomp are equal. In other embodiments, Fcomp can be greater than or less than the sensor clock frequency Fs. In this general case, the transfer function can be represented as

[0097] In another aspect, Figure 3D CDC 300d is shown that has a configuration that sequences a sensor cell 105 having a sensor capacitance Cs and a reference cell 115 having a reference capacitance Cref using different clock frequencies. Thus, Fmod > Fs. CDC 300d can additionally include any of the compensation branches 340a, 340b, and / or 340c. When CDC 300d includes any of the compensation branches 340a-c, the transfer function can be represented as

[0098] ​CDC 100 and 300a-d each use a grounded reference unit (e.g., the reference capacitance Cref is a self-capacitance). In other embodiments, as described with reference to Figure 5 the reference unit can be configured to operate with a mutual reference capacitance.

[0099] Figure 5 CDC 500 with mutual capacitance reference units 515 configured for ratio metric self-capacitance to code conversion is shown in accordance with an embodiment. CDC 500 can be a four-phase CDC and can include a bridge circuit 520 and a modulator front-end circuit (not explicitly shown in Figure 5 ). The modulator front-end circuit can be the same as or similar to the modulator front-end circuit of Figure 1 and Figures 3A-3D . The modulation circuit can include a four-phase sequencer and two or more feedback loops. The four-phase sequencer can generate first, second, third, and fourth phases and first and third modulation phases (PhO mod and Ph2 mod) to couple the sensor units 505 and / or the reference units 515 to one of the bridge circuit 520, the power supply voltage VDDA, or the ground potential.

[0100] The sensor units 505 can include sensor electrodes and have sensor capacitances Cs 512 that are self-capacitances. The reference units 515 can include reference capacitors 522 with first and second reference electrodes. The reference capacitances Cref can have first and second reference electrodes and reference capacitances 522 that are mutual capacitances. The first reference electrodes can be coupled to the bridge circuit 520 through switches enabled by the second feedback phase (Phl_fb) or the fourth feedback phase (Ph3_fb).

[0101] The phases are designed such that each of the modulation capacitors 141.1 and 141.2 can be alternately charged and discharged by the sensor units and the reference units. In the first phase PhO, the sensor electrodes of the sensor units 505 can be coupled to the power supply voltage VDDA. In other words, the power supply voltage can be applied to charge the sensor electrodes. During the first phase, the second reference electrodes can be coupled to the power supply voltage and uncoupled from the power supply voltage at the modulation frequency (through the PhO mod switch). For example, the phases (PhO, Phl, Ph2, and Ph3) can be modulated at a frequency of Fs, while the first modulation phase PhO mod can be modulated at the modulation frequency during the first phase PhO. The modulation frequency is K times greater than Fs.

[0102] In the second phase Phl, the sensor electrode of the sensor unit 505 can be coupled to the modulating capacitor 141.1 to charge the modulating capacitor 141.1. In case of a low bitstream (0), the reference unit 515 is not coupled to the bridge circuit 520, however, in case of a high bitstream (1), the second electrode of the reference unit 515 can be coupled (through Phl_fb switch) to the modulating capacitor 141.2 to charge the modulating capacitor 141.2.

[0103] In the third phase Ph2, the sensor electrode of the sensor unit 505 can be coupled to ground potential to ground the sensor electrode. The second reference electrode of the reference unit 515 can be uncoupled from the modulating capacitor 141.2. During the third phase, the first electrode of the reference unit 515 can be coupled (through Ph2_mod switch) to the ground frequency and uncoupled from the ground frequency at the modulating frequency.

[0104] In the fourth phase Ph3, the sensor electrode of the sensor unit 515 can be coupled to the modulating capacitor 141.2 to discharge the modulating capacitor 141.2. In case of a low bitstream, the reference unit 515 is not coupled to the bridge circuit 520, however, in case of a high bitstream (1), the second electrode of the reference unit 515 can be coupled (through Ph3_fb switch) to the modulating 141.1 to discharge the modulating capacitor 141.1.

[0105] The duty cycle of the bitstream output by the modulator front-end circuit can be expressed as

[0106] where 0 < DC < 1 (7)

[0107] Implementing a mutual reference capacitor for a reference capacitor can provide the benefit of reducing the parasitic capacitance associated with the reference unit. Such parasitic capacitance can affect sensing. High sensitivity applications of capacitive sensing can benefit from lower mutual reference capacitor values. Lower mutual reference capacitor values can be achieved by replacing the reference capacitor with a T-bridge of capacitors. For example, Cref can be replaced with a T-bridge of capacitors that can include a first capacitor, a second capacitor, and a third capacitor (C1, C2, and C3, respectively). The equivalent capacitance of the T-bridge of capacitors (representing the mutual reference capacitor) can be expressed as

[0108]

[0109] Figures 6A-6D is the effective representation of the CDC 500 in each of the first phase, the second phase, the third phase, and the fourth phase according to an embodiment. Figures 6A-6DModulation capacitors 141.1 and 141.2, capacitor Cs, which represents an effective sensor capacitor cell 505 with self-capacitance, and capacitor Cmref, which represents an effective reference cell 515 with mutual capacitance, are shown. First, second, third, and fourth phases are generated (e.g., enabled) by a sequencer of the modulator front-end circuit. When a given phase is enabled, one or more switches corresponding to that phase can be closed, and when the phase changes (e.g., a different phase is enabled and the given phase is disabled), one or more switches can be opened, and another set of one or more switches can be closed. Whether or not a reference cell (represented by capacitor Cmref) is coupled into the CDC 500 can depend on whether the bitstream is high (1) or low (0). On the other hand, whether or not a sensor cell (represented by capacitor Cs) is coupled into the CDC 500 does not depend on whether the bitstream is high or low.

[0110] In the first phase Pho, the CDC 500 can be configured to apply a supply voltage VDDA to the sensor electrode of the sensor cell to charge the sensor electrode to a first voltage level. When the bitstream is high, the CDC 500 can also be configured to apply the supply voltage to the first reference electrode of the reference cell to charge the first reference electrode to the first voltage level.

[0111] In the second phase Phl, the CDC 500 can be configured to couple the sensor electrode to the first modulation capacitor Cmodl to charge the first modulation capacitor Cmodl. When the bitstream is high, the CDC 500 can also be configured to couple the second reference electrode to the second modulation capacitor Cmod2 to charge the second modulation capacitor Cmod2.

[0112] In the third phase Ph2, the CDC 500 can be configured to couple the sensor electrode to a ground potential to ground the sensor electrode. When the bitstream is high, the CDC 500 can also be configured to couple the first reference electrode to the ground potential to ground the first reference electrode.

[0113] In the fourth phase Ph3, the CDC 500 can be configured to couple the sensor electrode to the second modulation capacitor Cmod2 to discharge the second modulation capacitor Cmod2. When the bitstream is high, the CDC 500 can also be configured to couple the second reference electrode to the first modulation capacitor Cmodl to discharge the first modulation capacitor Cmodl.

[0114] When the bitstream is low, in the second and fourth phases, the sensor unit can alternately charge the first modulation capacitor Cmodi and discharge the second modulation capacitor Cmod2 (if the second modulation capacitor Cmod2 is charged), while the reference unit is not coupled to the bridge circuit, and thus not coupled to the first or second modulation capacitor. Only when the bitstream is high, the reference unit can be coupled to the bridge circuit. In particular, in the second and fourth phases, the reference unit can alternately charge the second modulation capacitor Cmod2 and discharge the first modulation capacitor Cmodi.

[0115] In a similar manner as described above with respect to the CDCs 300a-d, Figures 3A-3D In a similar manner as described above with respect to the CDCs 300a-d, s comp s_comp Ref

[0116] Figures 6E-6H is an effective representation of the CDC 100 in each of the first, second, third, and fourth phases according to an embodiment. Figures 6E-6H The modulation capacitors 141.1 and 141.2, the capacitor Cs representing the effective sensor capacitor unit 105 with self-capacitance, and the capacitor Csref representing the effective reference unit 115 with self-capacitance are shown. The first, second, third, and fourth phases are generated (e.g., enabled) by a sequencer of the modulator front-end circuit. When a given phase is enabled, one or more switches corresponding to that phase can be closed, and when the phase changes (e.g., a different phase is enabled, and the given phase is disabled), one or more switches can be opened, and another set of one or more switches can be closed. Whether the reference unit (represented by capacitor Csref) is coupled into the CDC 100 can depend on whether the bitstream is high (1) or low (0). On the other hand, whether the sensor unit (represented by capacitor Cs) is coupled into the CDC 100 does not depend on whether the bitstream is high or low.

[0117] In the first phase Pho, the CDC 100 can be configured to apply a supply voltage VDDA to the sensor electrode of the sensor unit to charge the sensor electrode to a first voltage level. When the bitstream is high, the CDC 100 can also be configured to apply the supply voltage to the reference electrode of the reference unit to charge the reference electrode to the first voltage level.

[0118] ​​​​In the second phase Phl, the CDC 100 can be configured to couple the sensor electrode to the first modulator capacitor Cmodl to charge the first modulator capacitor Cmodl. When the bitstream is high, the CDC 100 can also be configured to couple the reference electrode to the second modulator capacitor Cmod2 to charge the second modulator capacitor Cmod2.

[0119] In the third phase Ph2, the CDC 100 can also be configured to couple the sensor electrode to ground potential to ground the sensor electrode. When the bitstream is high, the CDC 100 can also be configured to couple the reference electrode to ground potential to ground the reference electrode.

[0120] In the fourth phase Ph3, the CDC 100 can be configured to couple the sensor electrode to the second modulator capacitor Cmod2 to discharge the second modulator capacitor Cmod2. When the bitstream is high, the CDC 100 can also be configured to couple the reference electrode to the first modulator capacitor Cmodl to discharge the first modulator capacitor Cmodl.

[0121] When the bitstream is low, in the second and fourth phases, the sensor cell can alternately charge the first modulator capacitor Cmodl and discharge the second modulator capacitor Cmod2 (if the second modulator capacitor Cmod2 is charged), while the reference cell is not coupled to the bridge circuit, and thus not coupled to the first or second modulator capacitors. Only when the bitstream is high, the reference cell can be coupled to the bridge circuit. In particular, in the second and fourth phases, the reference cell can alternately charge the second modulator capacitor Cmod2 and discharge the first modulator capacitor Cmodl.

[0122] Figure 7 A CDC 700 with single-ended AFE configured for ratio metric self- capacitance to code conversion according to an embodiment is shown. In particular, Figure 7 An AFE for ratio metric self-capacitance to code sigma-delta converter is shown. Capacitive sensing technology can provide some applications that are less demanding and can be implemented with lower power cost. In such cases, a single-ended architecture for the modulator front-end circuit can be used. Generally, the ratio metric CDCs described herein are ratio metric in nature and do not require specific hardware, which means that a differential ratio metric architecture can have all the required elements for building a single-ended CDC, such as the CDC 700. In particular, a CDC such as the CDC 700 can be implemented for ratio metric applications without requiring specific hardware. For example, a modulator front-end circuit with a single-ended architecture can be used.

[0123] While the measurement method is a ratiometric measurement, the single-ended modulator front-end circuit can be different than the differential modulator front-end circuit used for conventional capacitive sensing architectures, as the single-ended modulator front-end circuit does not need to include a reference voltage source, and the method for initialization can not require an analog buffer.

[0124] The CDC 700 can include a modulator front-end circuit 730. The modulator front-end circuit 730 can include a modulation capacitor 741 (also referred to as a summation capacitor) coupled to a first input of a comparator 742. A second input of the comparator 742 can be coupled to a ground potential. The modulator front-end circuit 730 can include or be coupled to digitization circuitry to provide a digital bitstream (e.g., one or more digital values) to the processing unit 160.

[0125] The signals can be used to control the phases and can be clocked by the sensor clock frequency (e.g., Fs frequency). Each active capacitor with a capacitance (e.g., sensor capacitance 712 of the sensor unit 705, reference capacitance 722 of the reference unit 715, modulation capacitor 741, etc.) can form a charge transfer circuit that can generate a source current (referred to herein as Isen).

[0126] The first and second phases (enabled by Ph0 and Ph1 switches, respectively) can be enabled / disabled by non-overlapping signals that can be clocked by the sensor clock frequency (Fs) and the bitstream. The first and second modulation signals (enabled by Ph0 mod and Ph1 mod switches, respectively) can be non-overlapping signals that are modulated by the bitstream. The modulation signals can be modulated by the bitstream signal. In other words, they can be alternately enabled and disabled only when the bitstream is high. The modulation signals can be modulated at a modulation frequency F s . The modulation frequency can be greater than the sensor clock frequency. For example, the modulation frequency can be K mod times greater than the modulation frequency: ref

[0127] F mod = K ref · F s , where K ref = 1, 2,... (9)

[0128] The reference capacitance C ref , the modulation capacitance C mod , the modulation switches Ph0 mod and Ph1 mod can form a charge transfer circuit that generates a sink current I bal . Similarly, the sensor capacitance C s , the modulation capacitance C mod , and the switches Ph0 and Ph1 can form a charge transfer circuit that generates a sense current I sen ​charge transfer circuit. The sink current and the sense current can be expressed as:

[0129] I bal = F s · V DDA · C s (10)

[0130] I sen = F mod · V DDA · DC (11)

[0131] As a result of the sigma-delta modulation as a sigma-delta modulator, the sink current can be designed to be equal to the sense current:

[0132] I bal = I sen (12)

[0133] and as a result, the average current I avg over the branches of the modulator front-end circuit 730 vanishes (e.g., is zero). For similar reasons, the modulating voltage V mod at the first input of the comparator 742 fluctuates around a zero value. These conditions can be satisfied when the following two conditions are met:

[0134] C mod < 100 C s (13)

[0135] C s < K ref · C ref (14)

[0136] For the configuration of the CDC 700, the capacitance-to-code transfer function (e.g., the duty cycle of the bitstream signal) can be expressed as:

[0137]

[0138] In particular, equation (15) indicates that the capacitance-to-code conversion (e.g., capacitance-to-digital code conversion (CDC)) does not depend on the supply voltage V DDA nor on the clock frequency. Thus, the conversion is a ratio metric, and the reference source for the measurement is the reference capacitance C ref . Notably, since there is no reference source voltage (e.g., the reference source voltage is zero), the CDC 700 can provide a simple initialization scheme as well as the feature of simple waterproof capacitance scanning with active shielding, as will be further described with reference to Figure 9 .

[0139] Figure 8 is shown in accordance with an embodiment Figure 7voltage waveforms at the individual nodes of the CDC 700. The modulation frequency F mod is depicted at the top. As described with respect to Figure 7 the first switch Pho and the second switch Phl can be controlled with non-overlapping signals. The modulation switches Pho mod and Phl mod can be controlled with non-overlapping signals, which are modulated at the modulation frequency only when the bitstream signal is high. When the second switch Phl is enabled, the sense current can reach a peak value, while the sink current can reach a peak value when the second modulation switch Phl mod is enabled, which in the described example occurs three times when the bitstream is high, and thus the sink current can reach a peak value three times. The sense current and the sink current have opposite polarity, and the amplitude of each sink current peak can be one third smaller than the amplitude of the sense current, which results in an average current of zero. Thus, during the balancing process, the fluctuations of V mod can be kept at values of less than a few tens of millivolts, which means that the sensor excitation signals (e.g., VCs) have a rectangular waveform that fluctuates between the supply voltage VDDA and the ground potential.

[0140] Figure 9 A CDC 900 with an active shield driver 902 is shown, according to an embodiment. The CDC 900 is identical to the CDC 700, except that the CDC 900 comprises an active shield driver 902 and except that the sensor unit 905 comprises a mutual capacitance 912 and is affected by two parasitic capacitances C PS . The CDC 900 is a CDC that is capable of water-proof capacitive scanning with an active shield.

[0141] The above-described current balancing (e.g., I sen = I bal ) keeps the modulation voltage V mod fluctuating around zero. As described above, during the balancing process, the fluctuations of V mod can be kept at values of less than a few tens of millivolts, which means that the sensor excitation signals (e.g., VCs) have a rectangular waveform that fluctuates between the supply voltage VDDA and the ground potential, as shown in Figure 8 .

[0142] To create water-proofness for the CDC 900, the active shield driver 902 can generate an active shield signal with a shield waveform that repeats the sensor excitation signal. The active shield signal can be designed by pull-up and pull-down switches on a general purpose input / output (GPIO) driver pin. In other words, the sensor unit 905 comprising the sensor capacitance 912 can be coupled (but via the active shield driver 902) to the same supply voltage as in Figure 7 .

[0143] Figure 10CDC 1000 with single-ended AFE configured for ratio metric self-capacitance to code conversion is shown according to an embodiment. CDC 1000 is identical to CDC 700 except that the sense current I sen and the sink current I bal are reversed in polarity by switching the terminals coupled by the supply voltage and ground potential. The duty cycle of CDC 1000 is described and given by equations (9) to (15).

[0144] In general, the initialization scheme has a buffer voltage source connected to the modulator capacitor 1041 during the initialization period. CDC 1000 does not require a buffer voltage source, and furthermore, the initialization scheme can be designed to have only a single pull-down switch (S init). The initialization of CDC 1000 can reduce the overall power consumption of CDC 1000. In particular, the current used to charge the modulator capacitor 1041 is approximately zero, and an analog buffer is not required.

[0145] CDC 1000 can include a voltage comparator 1042 to allow for a minimum input voltage between 0 V and 0.1 V. Such a minimum input is a typical requirement for rail-to-rail input comparators, such as those that include positive and negative supply voltages as well as an intermediate supply voltage for common mode. CDC 1000 can also be used when the comparator only supports a VDDA rail voltage. In such a case, the Vmod balancing voltage can fluctuate around VDDA instead of around zero. The sense capacitance switching can generate a sink current I sen while the reference capacitance switching generates a source current. As described with respect to Figures 11A-11B there can be two methods for increasing the scan resolution of CDC 1000.

[0146] Figure 11A CDC 1100a with compensation branch 1132 configured for ratio metric self-capacitance to code conversion is shown according to an embodiment. The resolution of the CDC can be increased in various ways. First, the ratio of the modulator clock frequency to the sensor clock frequency can be increased while the reference capacitance C ref is decreased. In this case, the same architecture as CDC 1000 can be used. Second, and as described above, a compensation branch with a compensation capacitance 1132 (C scomp ) can be added. Adding a compensation branch requires the addition of switched capacitors as part of the compensation branch, as shown by CDC 1100a. It is noted that the compensation branch shown by CDC 1100a is a self-capacitance compensation branch.

[0147] The compensation switches PhOcompand Phlcompmay be driven by a compensation branch clock frequency F compThe clock source is switched. In some embodiments, switches Ph0comp and Ph1comp can switch synchronously with Ph0 and Ph1. In the above embodiments, when the switching of Ph0comp and Ph1comp is synchronized with the switching of Ph0 and Ph1, they are typically based on the sensor clock frequency F. s Switch, then F comp It can be equal to F s In other implementations, a compensation factor K can be defined when Ph0comp and Ph1comp are switched via separate clock signals. comp This characterizes the ratio of the compensation branch's compensation frequency to the sensor clock frequency, and the capacitor-to-code transfer function (duty cycle) can be expressed as...

[0148] in,

[0149] Figure 11B A CDC 1100b with increased resolution, configured for ratio measurement from capacitance to code conversion, is shown according to an embodiment. The compensation branch is equipped with mutual capacitance 1120 (C). comp In addition to the mutual compensation branch, CDC1100b and Figure 11A The CDC 1100a is the same as or similar. In both cases, the current I... comp It can be switched to the compensation branch via the Ph0comp and Ph1comp switch.

[0150] Figure 12 A CDC 1200 with a single-ended AFE, configured for ratio measurement mutual capacitance to code conversion, is shown according to an embodiment. In addition to including mutual capacitance 1212 (C... M In addition to the self-capacitive sensor unit, the CDC 1200 and Figure 10 The CDC 1000 is the same as or similar. Mutual capacitance may also be affected by parasitic capacitance C. PS The impact. Similar to the CDC 1000, switches Ph0, Ph1, and at least one feedback switch Ph... 1_fb The switching generates a balanced sensing current I sen absorption current I bal And a zero average current is generated at the first input of comparator 1242.

[0151] The architecture of the CDC 1200 can be improved by eliminating C ps to I sen The impact will simultaneously affect VC s Mutual capacitance measurements are performed by maintaining a voltage level near zero, thereby eliminating parasitic capacitance C. psImpact on CDC1200 performance. The capacitor-to-code transfer function of the CDC1200 can be expressed as:

[0152] If C m <K ref ·C ref ,but

[0153] Figure 13 An embodiment is shown. Figure 12 Voltage waveforms at various nodes of the CDC 1200. Modulation frequency F mod Depicted at the top. Similar to... Figure 7 CDC 700 and Figure 8 The corresponding waveforms described herein indicate that the first switch Ph0 and the second switch Ph1 can be controlled by non-overlapping signals. The modulation switches Ph0_mod and Ph1_mod can be controlled by non-overlapping signals, modulated only at the modulation frequency when the bitstream signal is high. When the second switch Ph1 is enabled, the sense current can reach its peak value, while when the second modulation switch Ph1_mod is enabled, the absorb current can reach its peak value, which occurs three times in the described example when the bitstream is high, and therefore the absorb current can reach its peak value three times. The sense current and absorb current have opposite polarities, and the amplitude of each absorb current peak can be one-third smaller than the amplitude of the sense current, causing the average current to disappear. Therefore, during the balancing process, V mod The fluctuations can be kept below tens of millivolts, which means that the sensor excitation signal (e.g., VCs) has a rectangular waveform that fluctuates between the power supply voltage VDDA and the ground potential.

[0154] Figure 14 A CDC 1400 with a single-ended AFE, configured for ratio measurement mutual capacitance to code conversion according to an embodiment, is shown. The sensing current I is reversed by switching the terminals coupled to the supply voltage and ground potential. sen and absorption current I bal Apart from their polarity, CDC 1400 and CDC 1200 are the same.

[0155] To increase the resolution of CDC 1200 and CDC1400, a compensation branch can be added, for example... Figure 11A and Figure 11B The compensation branch. Such a compensation branch can generate a compensation branch that corresponds to the sensed current I. sen The opposite DC current can be controlled by switching one or more modulation switches, similar to Ph0_mod and Ph1_mod. In this case, the modulated balance voltage V... mod It can be near the power supply voltage VDDA.

[0156] Figure 15 is a flowchart of one embodiment of a method 1500 of capacitive-to-digital code conversion according to one embodiment. In some embodiments, the method 1500 can be performed using processing logic. The processing logic can include hardware, software, or any combination of hardware and software. In one embodiment, the method 1500 is performed by the CDC 100 of FIG. 1, Figure 1 FIG. 3, Figure 5 Figure 7 Figures 9-12 Figure 14 The processing device 160 of FIG. 1, FIG. 2, Figure 1 FIG. 3, Figure 5 FIG. 6, Figures 9-12 Figure 14 The CDC of FIG. 1, FIG. 2, or FIG. 3 can perform the method 1500. Alternatively, some or all operations of the method 1500 can be performed using other components.

[0157] At block 1502, the processing logic can apply a supply voltage in a first phase to charge a sensor electrode of a sensor cell to a first voltage level. At block 1504, the processing logic can couple the sensor electrode to a first modulation capacitor in a second phase to charge the first modulation capacitor. The first modulation capacitor can be coupled to a first input of a comparator. At block 1506, the processing logic can couple the sensor electrode to a ground potential in a third phase to ground the sensor electrode. At block 1508, the processing logic can couple the sensor electrode to a second modulation capacitor in a fourth phase to discharge the second modulation capacitor. The second modulation capacitor can be coupled to a second input of the comparator. The modulator front-end circuit includes the first modulation capacitor, the second modulation capacitor, and the comparator, and provides a digital bit stream. A duty cycle of the digital bit stream represents a ratio between a capacitance of the sensor cell and a reference capacitance of a reference cell. In some embodiments, the reference cell includes a reference electrode, and the reference capacitance is a self-capacitance. In other embodiments, the reference cell includes a reference electrode and a second reference electrode, and the reference capacitance is a mutual-capacitance.

[0158] In further embodiments, the processing logic can apply a supply voltage in a first phase to charge a reference electrode of a reference cell to a first voltage level. The processing can couple the reference electrode to a second modulation capacitor in a second phase to charge the second modulation capacitor. The processing logic can couple the reference electrode to a ground potential in a third phase to ground the reference electrode. The processing logic can couple the reference electrode to a first modulation capacitor in a fourth phase to discharge the first modulation capacitor.

[0159] ​​​​In another implementation, the processing logic may apply a power supply voltage to the compensation electrode of the compensation unit having a compensation capacitor in a first phase. In a second phase, the processing logic may couple the compensation electrode to a second modulation capacitor to charge the second modulation capacitor. In a third phase, the processing logic may couple the compensation electrode to ground potential to ground the compensation electrode. In a fourth phase, the processing logic may couple the compensation electrode to a first modulation capacitor to discharge the first modulation capacitor. The duty cycle of the digital bitstream is the ratio between the capacitance of the reference unit and the difference between the capacitance of the sensor unit and the capacitance of the compensation unit.

[0160] The embodiments described herein can be used in various designs of mutual capacitance sensing arrays in capacitive sensing systems, or in self-capacitance sensing arrays. In one embodiment, the capacitive sensing system detects multiple activated sensing elements in the array and can analyze signal patterns on adjacent sensing elements to separate noise from the actual signal. As will be understood by those skilled in the art who benefit from this disclosure, the embodiments described herein are not dependent on a specific capacitive sensing solution and can also be used with other sensing solutions, including optical sensing solutions.

[0161] Numerous details have been set forth in the foregoing description. However, it will be apparent to those skilled in the art who benefit from this disclosure that embodiments of the disclosure can be practiced without these specific details. In some instances, to avoid obscuring the description, well-known structures and apparatuses are shown in block diagram form rather than in detail.

[0162] Certain parts of the specific implementation are presented according to algorithms and symbolic representations for manipulating data bits in computer memory. These algorithmic descriptions and representations are means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Here, an algorithm is generally considered to be a self-consistent sequence of steps leading to a desired result. These steps are steps required to physically manipulate physical quantities. Typically, although not essential, these quantities are in the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise processed. It has proven convenient to sometimes refer to these signals primarily for general purposes as bits, values, elements, symbols, characters, items, numbers, etc.

[0163] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as "applying," "coupling," "communicating," or the like, refer to the action and processes of a computing system, or similar electronic computing device, that manipulates and transforms data represented as physical (e.g., electronic) quantities within the computing system's registers and memories into other data similarly represented as physical quantities within the computing system memories or registers or other such information storage, transmission or display devices.

[0164] The word "example" or "exemplary" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, the use of the words "example" or "exemplary" is intended to present concepts in a concrete manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or as is clear from the context, the statement "X includes A or B" is intended to mean any of the natural inclusive permutations. That is, if X includes A, X includes B, or X includes both A and B, then "X includes A or B" is satisfied under any of the foregoing instances. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term "an implementation" or "one implementation" or "an implementation" or "one implementation" throughout is not intended to mean the same implementation or implementation unless so described.

[0165] The implementations described herein can also relate to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, or it can comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a non-transitory computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, flash memories, or any type of media suitable for storing electronic instructions. The term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store the one or more sets of instructions. The term "computer-readable medium" should also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methodologies of the present implementations. The term "computer-readable medium" should accordingly be taken to include, but not be limited to, solid-state memories, optical media, magnetic media, any medium that is capable of storing a set of instructions for execution by a machine, and any medium that is capable of carrying or encoding a set of instructions for execution by a machine.

[0166] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the description below. In addition, the present implementations are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the implementations as described herein.

[0167] The above description sets forth numerous specific details, such as examples of specific systems, components, methods and so forth, in order to provide a good understanding of several embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that at least some embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simple block diagram format in order to avoid unnecessarily obscuring the present disclosure. Thus, the specific details set forth above are merely exemplary. Particular implementations can vary from these exemplary details and still be contemplated to be within the scope of the present disclosure.

[0168] It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the application should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A capacitance-to-digital converter, comprising: a bridge circuit comprising a first terminal coupled to a reference cell and a second terminal coupled to a sensor cell; and a modulator front-end circuit comprising a comparator coupled to the bridge circuit, a first modulation capacitor coupled to a first input of the comparator, and a second modulation capacitor coupled to a second input of the comparator, wherein the modulator front-end circuit is to provide a digital bit stream, wherein a duty cycle of the digital bit stream is representative of a ratio between a capacitance of the sensor cell and a reference capacitance of the reference cell; wherein the sensor cell comprises a sensor electrode, wherein the modulator front-end circuit further comprises a sequencer to generate a first phase, a second phase, a third phase, and a fourth phase, wherein the capacitance-to-digital converter is configured to: in the first phase, apply a supply voltage to charge the sensor electrode to a first voltage level; in the second phase, couple the sensor electrode to the first modulation capacitor to charge the first modulation capacitor; in the third phase, couple the sensor electrode to a ground potential to ground the sensor electrode; and in the fourth phase, couple the sensor electrode to the second modulation capacitor to discharge the second modulation capacitor. the reference cell comprises a reference electrode, wherein the capacitance-to-digital converter is further to:

2. The capacitance-to-digital converter of claim 1, wherein, in the first phase, apply the supply voltage to charge the reference electrode to the first voltage level; in the second phase, couple the reference electrode to the second modulation capacitor to charge the second modulation capacitor; in the third phase, couple the reference electrode to the ground potential to ground the reference electrode; and in the fourth phase, couple the reference electrode to the first modulation capacitor to discharge the first modulation capacitor. the reference cell comprises a reference electrode, wherein the reference capacitance is a self-capacitance.

3. The capacitance-to-digital converter of claim 1, wherein, the reference cell comprises a first electrode and a second electrode, wherein the reference capacitance is a mutual capacitance.

4. The capacitance-to-digital converter of claim 1, wherein, the bridge circuit further comprises a third terminal coupled to a compensation cell having a compensation capacitance, wherein the ratio is based on the reference capacitance, the capacitance of the sensor cell, and the compensation capacitance.

5. The capacitance-to-digital converter of claim 1, wherein, the compensation cell comprises a compensation electrode, and wherein the capacitance-to-digital converter is further to:

6. The capacitance-to-digital converter of claim 5, wherein, in the first phase, apply the supply voltage to charge the compensation electrode to the first voltage level; in the second phase, couple the compensation electrode to the second modulation capacitor to charge the second modulation capacitor; in the third phase, couple the compensation electrode to the ground potential to ground the compensation electrode; and in the fourth phase, couple the compensation electrode to the first modulation capacitor to discharge the first modulation capacitor. the duty cycle of the digital bit stream is a ratio between a capacitance of the reference capacitance and a difference between the capacitance of the sensor cell and a capacitance of the compensation cell.

7. The capacitance-to-digital converter of claim 5, wherein, the capacitance of the sensor cell is a self-capacitance.

8. The capacitance-to-digital converter of claim 1, wherein, ​ 9. A method for a capacitance-to-digital converter, comprising: in a first phase, applying a supply voltage to charge a sensor electrode of a sensor cell to a first voltage level; in a second phase, coupling the sensor electrode to a first modulation capacitor to charge the first modulation capacitor, the first modulation capacitor coupled to a first input of a comparator; in a third phase, coupling the sensor electrode to a ground potential to ground the sensor electrode; and in a fourth phase, coupling the sensor electrode to a second modulation capacitor to discharge the second modulation capacitor, the second modulation capacitor coupled to a second input of the comparator, wherein a modulator front-end circuit comprises the first modulation capacitor, the second modulation capacitor, and the comparator, the modulator front-end circuit for providing a digital bit stream, and wherein a duty cycle of the digital bit stream represents a ratio between a capacitance of the sensor cell and a reference capacitance of a reference cell.

10. The method of claim 9, further comprising: in the first phase, applying the supply voltage to charge a reference electrode of the reference cell to the first voltage level; in the second phase, coupling the reference electrode to the second modulation capacitor to charge the second modulation capacitor; in the third phase, coupling the reference electrode to the ground potential to ground the reference electrode; and in the fourth phase, coupling the reference electrode to the first modulation capacitor to discharge the first modulation capacitor.

11. The method of claim 10, wherein, the reference cell comprises the reference electrode, wherein the reference capacitance is a self-capacitance.

12. The method of claim 10, wherein, the reference cell further comprises the reference electrode and a second reference electrode, wherein the reference capacitance is a mutual capacitance.

13. The method of claim 10, further comprising: in the first phase, applying the supply voltage to a compensation electrode of a compensation cell having a compensation capacitance; in the second phase, coupling the compensation electrode to the second modulation capacitor to charge the second modulation capacitor; in the third phase, coupling the compensation electrode to the ground potential to ground the compensation electrode; and in the fourth phase, coupling the compensation electrode to the first modulation capacitor to discharge the first modulation capacitor.

14. The method of claim 13, wherein, a duty cycle of the digital bit stream is a ratio between a capacitance of the reference cell and a difference between a capacitance of the sensor cell and a capacitance of the compensation cell.

15. A system for a capacitance-to-digital converter, comprising: a reference cell; a sensor cell; and a capacitance-to-digital converter comprising: a bridge circuit comprising a first terminal coupled to the reference cell and a second terminal coupled to the sensor cell; and a modulator front-end circuit coupled to the bridge circuit. a modulator front-end circuit comprising a comparator coupled to the bridge circuit, a first modulation capacitor coupled to a first input of the comparator, and a second modulation capacitor coupled to a second input of the comparator, wherein the modulator front-end circuit is configured to provide a digital bit stream, wherein a duty cycle of the digital bit stream represents a ratio between a capacitance of the sensor cell and a reference capacitance of the reference cell, wherein the sensor cell comprises a sensor electrode, wherein the modulator front-end circuit further comprises a sequencer configured to generate a first phase, a second phase, a third phase, and a fourth phase, wherein the capacitance-to-digital converter is configured to: in the first phase, apply a supply voltage to charge the sensor electrode to a first voltage level; in the second phase, couple the sensor electrode to the first modulation capacitor to charge the first modulation capacitor; in the third phase, couple the sensor electrode to a ground potential to ground the sensor electrode; and in the fourth phase, couple the sensor electrode to the second modulation capacitor to discharge the second modulation capacitor.

16. The system of claim 15, wherein, the reference cell comprises a reference electrode, wherein the reference capacitance is a self-capacitance.

17. The system of claim 15, wherein, the reference cell comprises a first electrode and a second electrode, wherein the reference capacitance is a mutual capacitance.

18. The system of claim 15, further comprising a compensation unit having a compensation capacitance, wherein, the ratio is based on the reference capacitance, a capacitance of the sensor cell, and the compensation capacitance.

19. The system of claim 15, wherein, the capacitance of the sensor cell is a self-capacitance. the reference cell comprises a reference electrode, wherein the reference capacitance is a self-capacitance. the reference cell comprises a first electrode and a second electrode, wherein the reference capacitance is a mutual capacitance. the ratio is based on the reference capacitance, a capacitance of the sensor cell, and the compensation capacitance. the capacitance of the sensor cell is a self-capacitance.

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