Classifying patterns in electronic circuit layouts using machine learning-based coding

Abstract

The system performs distributed or parallel pattern extraction and clustering to classify patterns for large electronic circuit layouts. The system uses a layout representation to identify circuit patterns. The system encodes circuit patterns using a neural network-based autoencoder to generate encoded circuit patterns that can be efficiently stored. The system clusters the encoded circuit patterns into any number of clusters based on high similarity. The clusters of circuit patterns can be used to train and evaluate machine learning-based models.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. patent application serial number 62 / 850,026, filed on May 20, 2019, the contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to the field of electronic design automation, and more particularly to distributed pattern extraction and clustering for pattern classification of large layouts of electronic circuits using machine learning based pattern encoding. Background Art

[0004] Electronic design automation of large electronic circuits typically handles large designs containing billions of unique patterns. Some applications such as lithography model fitting and machine learning (ML) model training require understanding of the pattern types within the design so that the model can be well extrapolated to these patterns. Certain processes performed during the electronic design automation of circuits group the patterns of the electronic circuits into subgroups or clusters, where each subgroup or cluster contains similar patterns so that the clusters can be represented using one representative pattern from each cluster. Due to the large size of current electronic circuits, it is impractical to perform pattern collection and subsequent clustering of billions (or more) of patterns on a single computing system because a single computing system typically does not have enough memory and computing power to load and process such large electronic circuits. As a result, conventional techniques that cannot be distributed across a large number of computer processors can only handle small electronic circuits. Summary of the invention

[0005] A configuration (e.g., a system, a method, a non-transitory computer-readable storage medium including stored instructions executable by a processor) for classifying a layout of an electronic circuit is disclosed. A representation of a circuit layout is received. The layout representation includes a geometric shape. A set of circuit patterns is extracted from the layout representation of the circuit design. The set of circuit patterns is encoded to generate a set of encoded circuit patterns. Encoding of the circuit pattern is performed by providing the circuit pattern as an input to a machine learning-based encoder, the encoder being configured to receive the input circuit pattern and generate an encoded circuit pattern. The encoded circuit pattern is represented using less data than the input circuit pattern. The encoder is executed to generate an encoded circuit pattern corresponding to the input circuit pattern. The set of encoded circuit patterns is clustered into clusters.

[0006] In one embodiment, the machine learning based encoder is a neural network based autoencoder that performs (1) encoding and (2) decoding. A collection of functions / steps may be used to perform encoding / decoding.

[0007] The clusters can be used to train or evaluate machine learning based models. For example, a machine learning model can be trained by selecting a subset of circuit patterns from each cluster to train a machine learning based model. Similarly, a machine learning model can be evaluated by selecting a subset of circuit patterns from each cluster to evaluate a machine learning based model.

[0008] According to one embodiment, a machine learning based encoder is trained using distributed training. Therefore, a training data set is determined. Each training data set includes a circuit pattern. A computer processor is used to train the machine learning based encoder in parallel. Each computer processor uses one of the training data sets to determine a parameter set for the machine learning based encoder. The parameter represents the weight of the machine learning based encoder. For example, a machine learning based model can be a neural network including nodes, wherein each node represents a linear combination of the inputs of the node, wherein the input is weighted according to the parameter. The weight of the machine learning based encoder is an adjustable parameter of the model, which is adjusted during the training of the machine learning based encoder, for example, via a back propagation process. The parameters of the trained machine learning based model are applied to new inputs to make predictions using the model. The parameter sets generated in parallel are aggregated to obtain a combined parameter set for the machine learning based encoder. This process can be repeated multiple times.

[0009] In one embodiment, the machine learning based encoder is a neural network comprising a convolution component comprising a set of layers that receive an input circuit pattern to generate an encoded circuit pattern and a deconvolution component comprising a set of layers that receive the encoded circuit pattern as input and generate an output representation of the circuit pattern. Each of the convolution component and the deconvolution component comprises a set of layers of a neural network, each layer receiving a set of values, processing the set of values, and providing a result to the next layer. Alternatively, each of the convolution component and the deconvolution component can be viewed as a sequence of execution steps, each step receiving an input, processing the input, and providing a result to the next step.

[0010] According to one embodiment, clustering of encoded circuit patterns is performed using a hierarchical clustering technique. The hierarchical clustering technique is performed using a distributed system that repeatedly divides each cluster into sub-clusters in parallel.

[0011] According to one embodiment, for each cluster, hierarchical clustering determines whether the cluster should be further subdivided into subclusters. For each cluster, a similarity measure of circuit patterns within the cluster is determined. The system determines whether the similarity measure of the circuit patterns indicates less than a threshold similarity between the circuit patterns of the cluster. If the similarity measure of the circuit patterns of the cluster indicates less than a threshold similarity between the circuit patterns of the cluster, the cluster is further subdivided into subclusters. As further described herein, other embodiments may use other rules to determine whether to continue to subdivide a cluster into subclusters. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present disclosure will be more fully understood according to the specific embodiments given below and the drawings according to the embodiments of the present disclosure. The drawings are used to provide knowledge and understanding of the embodiments of the present disclosure and do not limit the scope of the present disclosure to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.

[0013] Figure 1 Flowcharts depicting various processes used during the design and fabrication of integrated circuits according to some embodiments of the present disclosure.

[0014] Figure 2 A block diagram illustrating a system architecture of a layout classification system according to one embodiment.

[0015] Figure 3 A flow chart illustrating the overall process of layout classification according to one embodiment is shown.

[0016] Figure 4 The overall process flow using an example layout according to one embodiment is illustrated.

[0017] Figure 5 An autoencoder model according to one embodiment is depicted.

[0018] Figure 6 Depicted is an original rasterized circuit pattern and its encoded representation according to one embodiment.

[0019] Figure 7 Depicted is an example of top-down hierarchical clustering of layouts of circuits according to one embodiment.

[0020] Figure 8 Depicted is an example of cluster items after they have been decoded back into rasterized polygon space, according to one embodiment.

[0021] Fig. 9 An abstract diagram of an example computer system is depicted in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0022] Large circuits often have multiple repeating circuit patterns. For example, a circuit layout may have a repeating pattern of geometric shapes. Similar circuit patterns store similar information. Therefore, if a large number of similar circuit patterns are provided as a training dataset for training a machine learning model, the model may not be able to handle other types of circuit patterns that are not provided as training data.

[0023] A layout classification system according to an embodiment classifies circuit patterns of a circuit to generate clusters of similar circuit patterns. For example, the clusters of circuit patterns can be used to generate a training data set for training a machine learning model, the training data set including different types of circuit patterns instead of a large number of similar circuit patterns. As a result, the machine learning model trained using the generated training data set can handle a wider range of circuit patterns than a model trained using a training data set including a large number of similar circuit patterns.

[0024] The layout of large electronic circuits can include billions of circuit patterns. Loading and processing such large amounts of data consumes a large amount of computing and input / output resources. Conventional techniques for clustering the layout of such large circuits are slow and inefficient, or require expensive computing resources.

[0025] An embodiment performs clustering by performing steps including: (1) receiving a circuit design and using distributed processing (DP) to find all unique patterns in the circuit. (2) using distributed training to train a machine learning based encoder model. The encoder compresses the circuit pattern to a smaller size so that the encoded representation of the circuit pattern uses significantly less data than the unencoded representation of the circuit pattern. (3) clustering the compressed data patterns into clusters, for example using a distributed hierarchical clustering method.

[0026] Encoding the circuit patterns to use less data allows computing resources to load and process a much larger number of circuit patterns. This reduces computing time and input / output overhead for processing circuits. In addition, the layout classification system performs distributed processing of various steps, such as steps for training the machine learning-based encoder and steps for clustering the encoded circuit patterns. Distributed processing allows the various steps of the clustering process to be performed in parallel using a large number of computing processes, thereby speeding up the process and allowing much larger circuits to be processed in a reasonable time.

[0027] Electronic Design Automation Process

[0028] Figure 1An example set 100 of processes used during the design, verification, and manufacture of an article of manufacture such as an integrated circuit is illustrated, which is used to transform and verify design data and instructions representing the integrated circuit. Each of these processes can be structured and implemented as multiple modules or operations. The term 'EDA' represents the term 'electronic design automation'. These processes begin with the creation of a product concept 110 using information provided by a designer, which is transformed to produce an article of manufacture using a set of EDA processes 112. When the design is completed, the design is taped out 134, which is when the artwork (e.g., geometric pattern) of the integrated circuit is sent to a manufacturing plant to manufacture a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor die are manufactured 136, and packaging and assembly processes 138 are performed to produce a finished integrated circuit 140.

[0029] The specification of a circuit or electronic structure may range from low-level transistor material layout to high-level description languages. Circuits and systems can be designed using a high level of abstraction by using a hardware description language ('HDL') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL or OpenVera. The HDL description can be converted into a register transfer level ('RTL') description at the logic level, a gate level description, a layout level description or a mask level description. Each lower level of abstraction (i.e. less abstract description) adds more useful detail to the design description, for example, more detail for the modules that comprise the description. The lower level of abstraction (i.e. less abstract description) may be computer generated, derived from a design library or created by another design automation process. An example of a specification language for a lower level of abstraction language that specifies more detailed descriptions is SPICE, which is used for detailed descriptions of circuits with many analog components. The description at each level of abstraction is implemented for use by the corresponding tools for that layer (e.g. formal verification tools). The design process may use Figure 1 The sequence described in . The described process is implemented by an EDA product (or tool).

[0030] During system design 114, the functionality of the integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design may be divided into different types of modules or components.

[0031] During logic design and functional verification 116, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of the specification is checked. For example, components of a circuit can be verified to generate outputs that match the requirements of the specification of the circuit or system being designed. Functional verification can use simulators and other programs such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, special systems of components called "emulators" or "prototyping systems" are used to speed up functional verification.

[0032] During synthesis and design for testing 118, the HDL code is converted into a netlist. In some embodiments, the netlist can be a graph structure, where the edges of the graph structure represent components of the circuit, and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical artifacts that can be used by EDA products to verify that the integrated circuit operates according to the specified design when manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. In addition, the completed integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0033] During netlist verification 120, the netlist is checked for consistency with timing constraints and correspondence with HDL code. During design planning 122, a general floorplan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0034] During layout or physical implementation 124, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connecting circuit components through multiple conductors) are performed, and selection of cells from a library to implement a specific logic function may be performed. As used herein, the term "cell" may specify a group of transistors, other components, and interconnections that provide a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (such as a flip-flop or latch). As used herein, a circuit "block" may refer to two or more cells. Both cells and circuit blocks may be referred to as modules or components and implemented as physical structures and implemented in simulation. Parameters, such as size, are specified for the selected cell (based on a "standard cell"), and the parameters are made accessible in a database for use by EDA products.

[0035] During analysis and extraction 126, circuit functionality is verified at the layout level, which allows refinement of the layout design. During physical verification 128, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, lithography constraints, and that the circuit functionality matches the HDL design specifications. During resolution enhancement 130, the geometry of the layout is transformed to improve the way the circuit design is manufactured.

[0036] During tape-out, data is created for the production of lithographic masks (after applying lithographic enhancements where appropriate).During mask data preparation 132, the "tape-out" data is used to produce lithographic masks, which are used to produce finished integrated circuits.

[0037] Computer systems (such as Fig. 9 Computer system 900 or Figure 8 The storage subsystem of the host system 807) can be used to store programs and data structures used by some or all of the EDA products described herein, as well as units for developing libraries and products for physical and logical designs that use the libraries.

[0038] Embodiments may be used to process circuit designs during various stages of an electronic design automation process that stores circuit layouts, for example, during layout or physical implementation 124, analysis and extraction 126, mask data preparation 132, and the like.

[0039] Laying out the architecture of the classification system

[0040] Figure 2 A block diagram of a system architecture of a layout classification system according to one embodiment is shown. Layout classification system 210 includes circuit pattern generation component 220, autoencoder 230, model training component 240, and clustering component 250. Other embodiments may include more or fewer components than indicated herein. Functions indicated herein as being performed by a particular component may be performed by other components than those indicated herein.

[0041] The circuit pattern generation component 220 extracts a set of circuit patterns from the representation of the circuit layout. The circuit pattern is also referred to as a clip in this article. In one embodiment, the circuit pattern generation component 220 divides the layout into smaller fragments and calculates a unique identifier such as a geometric hash key for each fragment. The calculation of the unique identifier is completed so that the system can have a compact identifier for each clip, which can be compared with other compact identifiers of other clips to see if the clips are the same. The hash key is a mathematical function of the vertex position of a geometric shape. For example, a mathematical function can aggregate the vertex position and use a predetermined value as a divisor to determine the modulus (or remainder) value. Various embodiments can use other geometric hash functions. The circuit pattern generation component 220 stores the hash key for each clip together with the position of the clip in a database so that the hash key can be accessed later. The database allows identification of which circuit patterns are present in different positions of the circuit, thereby identifying a unique set of circuit patterns, which generally represents all different geometric shapes in the circuit.

[0042] The autoencoder 240 is a machine learning based model that receives as input a representation of a circuit partition and outputs a representation of the circuit partition. The autoencoder 240 generates an intermediate representation of the circuit partition that is an encoded representation of the input representation and can be stored using fewer bits than the input representation.

[0043] Model training component 230 trains an autoencoder using the circuit partitions obtained from the circuit. Model training component 230 trains autoencoder 240 to output a circuit partition representation that matches the input representation of the circuit partition.

[0044] Clustering component 250 performs clustering of circuit partitions represented by the input layout of the circuit. Clustering component 250 stores clusters. In one embodiment, the generated clusters are used for training or evaluation of a machine learning model. For example, a machine learning model can be trained by selecting a subset of circuit patterns from each cluster for use as a training data set. Using circuit patterns from each cluster ensures that training is performed using circuit patterns that are different from each other. This improves the computational efficiency of the training process because computational resources are not wasted on training models with repeated training data. Training models with repeated training data wastes resources.

[0045] Similarly, machine learning models can be evaluated by selecting a subset of circuit patterns from each cluster to evaluate machine learning based models. Using circuit patterns from different clusters to evaluate machine learning based models improves the quality of evaluation of machine learning based models and ensures that there is sufficient coverage for evaluation across all different types of circuit patterns. In addition, the evaluation process using circuit patterns from different clusters improves the computational efficiency of conventional model evaluation techniques because computational resources are not wasted in evaluating machine learning based models using similar circuit patterns.

[0046] Layout Classification Process

[0047] Figure 3 A flow chart illustrating the overall process of layout classification according to one embodiment is shown. Figure 3 The steps shown in the flowchart of can be performed in an order different from the order indicated in the flowchart. For example, some steps can be performed in parallel with other steps. In addition, the various steps shown in the flowchart can be performed using a parallel or distributed system.

[0048] The layout classification system 210 receives 310 a layout representation of a circuit, the layout representation including a geometric shape. The circuit pattern generation component 220 identifies 320 a unique circuit pattern from the layout representation of the circuit. The circuit pattern generation component 220 stores the unique pattern in a database.

[0049] The layout classification system 210 encodes the circuit pattern to generate a set of encoded circuit patterns by repeating steps 330 and 340 for each circuit pattern identified. The layout classification system 210 provides the circuit pattern as input to an encoder, such as an autoencoder 230. The encoder is executed to generate an encoded circuit pattern for each circuit pattern. The encoded circuit pattern is represented using less data than the input circuit pattern.

[0050] The clustering component 250 performs clustering of the set of encoded circuit patterns to generate a plurality of clusters of circuit patterns. The generated clusters are stored in a database. Figure 3 The process of identifying a unique circuit pattern 320 is described in detail below. Figure 4 The steps 330 and 340 of encoding the circuit pattern are shown in FIG. Figure 5 is shown in the figure. Figure 6 Examples of coded circuit patterns and uncoded circuit patterns are shown. Step 350 of clustering coded circuit patterns is Figure 7 is shown in the figure.

[0051] Figure 4 The overall process flow using an example layout according to one embodiment is illustrated.

[0052] Step 1: Identify all unique patterns in your layout.

[0053] In one embodiment, the distributed system divides the design into circuit patterns and then processes each of the circuit patterns in parallel to find all unique windows. For each circuit pattern, the layout classification system 210 obtains its hash key. In one embodiment, the layout classification system 210 calculates an integer hash key from a geometric layout clip. The hash key can be generated using a geometric hashing technique that generates a key based on features (e.g., a geometric pattern) of an input image corresponding to a geometric layout clip. The hash key is used to build a global database of all circuit patterns encountered in a circuit. In some embodiments, if the circuit patterns can be obtained from each other by mirroring, translating, or rotating, the layout classification system 210 treats the circuit patterns as the same. Therefore, two circuit patterns that can be obtained from each other by performing one or more of mirroring, translating, or rotating are mapped to the same hash key. The layout classification system 210 stores the geometric clips in a global database D that maps hash keys to circuit patterns, for example, as D[hash key]=geometry_polygons. In one embodiment, the layout classification system 210 uses cloud storage to allow a large number of key value pairs to be generated.

[0054] Step 2: Build an autoencoder model to reduce the data size.

[0055] In one embodiment, the model training component 240 uses a distributed machine learning training process to train the autoencoder model 230, which has a small data size at the midpoint of its representation of the encoded data. In one embodiment, the layout classification system 210 converts the polygon data of the circuit layout into a rasterized pixel grid, and in a subsequent step uses a convolutional neural network to process the rasterized pixel grid.

[0056] Figure 5 An autoencoder model is shown that receives an input circuit pattern and regenerates the circuit pattern as an output. The autoencoder converts the input circuit pattern into a low-dimensional encoded representation generated by a hidden layer of the model, which is then converted into an output circuit pattern that matches the input circuit pattern. As a result, the encoded representation generated by the hidden layer of the autoencoder includes all the information of the circuit pattern required to regenerate the circuit pattern as an output. The hidden layers are also referred to as the inner layers of the autoencoder model.

[0057] like Figure 5 As shown in , the autoencoder receives a layout representation of a circuit pattern. The autoencoder may include the following components: (1) One or more convolutional layers for performing downsampling on the input circuit pattern. The convolutional layer scans the input circuit pattern to identify features of the circuit pattern. The convolutional layer may use one or more filters, each filter configured to recognize specific features in the circuit pattern. (2) Dense connections to the encoding layer. The encoding layer is a hidden layer (or internal layer). The dense layer connects the output of the convolutional layer to the input of the encoding layer. The layer is dense because it has a large number of connections, for example, each output of the convolutional layer can be connected to each input of the encoding layer. (3) The encoding layer uses an encoded representation to represent the input circuit pattern, and the encoded representation uses fewer data values ​​than the input representation. An example of an encoded circuit pattern corresponding to an input circuit pattern is shown in Figure 6 (4) A densely connected layer connects the output of the encoding layer to one or more deconvolution layers. This layer is also dense because it has a large number of connections, for example, each output of the encoding layer is connected to each input of the deconvolution layer. (5) One or more deconvolution layers are used to upsample the encoded circuit pattern to generate a decoded representation of the circuit pattern that matches the input circuit pattern. Deconvolution reverses the convolution process performed by the convolution layer later and represents the inverse process of the convolution operation.

[0058] In one embodiment, the model training component 240 performs distributed training of the autoencoder using random weight averaging, which may include the following steps. (1) The model training module 240 splits the training data into blocks. (2) The model training module 240 partially fits the model on each block in parallel. (3) The model training module 240 averages the weights from each partial fit to create a combined model. (3) The model training module 240 repeats the steps starting from step 2, and continues to train the model in step 3 according to its latest weight value found.

[0059] This allows the model to fit larger data sets than can be contained in memory on a single computing system.

[0060] After the autoencoder is trained, the encoded version of each data point is stored, which results in a 1024x1024 image being reduced to an 8x8 encoded representation. This is done using distributed machine learning based model inference. Figure 6 An example of an original rasterized pattern 610 and its encoded representation 620 is shown.

[0061] In some embodiments, the layout classification system 210 uses geometric density over different pattern areas. Thus, the layout classification system 210 uses geometric density to construct the encoding of the circuit pattern. In one embodiment, the layout classification system 210 performs sampling of geometric polarity (polygons / empty space) within an area of ​​a given size and adds the sampled values ​​to obtain a density value used in encoding the circuit pattern. In another embodiment, the layout classification system 210 rasterizes the polygons and convolves the result with an indicator function to generate a pixel value that has a value of 1 within a particular area and a value of 0 outside the area. The layout classification system 210 adds the pixel values ​​to obtain a density value used in encoding the circuit pattern.

[0062] In some embodiments, the layout classification system 210 samples different convolutions of the rasterized pattern. Therefore, the layout classification system 210 uses the convolved rasterized pattern. This is done by rasterizing the pattern and then convolving it with a set of convolution kernels to obtain a set of convolved images. The layout classification system 210 adds the pixel values ​​to obtain a convolution and representation similar to the density calculation described above.

[0063] In some embodiments, the layout classification system 210 performs local sampling of the rasterized pattern or convolution above. Thus, the layout classification system 210 determines a set of local sampling points that are geometrically specified (e.g., near the center of the circuit pattern). Then, a pixelated image (which can be calculated from the rasterized pattern, convolution, lithographic image, etc.) is sampled at these points, and the layout classification system 210 uses the sampled values ​​directly, or calculates a mathematical function of the sampled values, such as a sum or aggregate value, for use in encoding the circuit pattern.

[0064] It should be noted that, depending on the application, other methods for creating encoded data sets may be used, such as using lithography simulation of polygons and extracting geometry / pixel information from the lithography simulation. The encoder for encoding circuit patterns satisfies the following properties. If the encoder is applied to two different circuit patterns C1 and C2 that are similar according to a certain similarity measure, then according to the similarity measure, the output encoded circuit patterns (e.g., E1 and E2, respectively) are also similar. Therefore, clusters of input circuit patterns will generate corresponding clusters in the encoded circuit pattern. An encoder that does not satisfy the above properties is a hash function that generates keys that are not necessarily similar for similar inputs. Such an encoder that does not generate similar encoded circuit patterns for similar circuits is not used in the embodiments.

[0065] In some embodiments, the layout classification system 210 performs local sampling of lithography simulation of the pattern. The layout classification system 210 takes the clip polygons and uses them as mask representations and feeds them into the lithography simulation system to obtain simulated wafer images, which are then processed by sampling, convolution, etc. as described above.

[0066] Step 3: Distributed Clustering

[0067] Figure 7 A top-down hierarchical clustering of a layout of a circuit is shown according to one embodiment.

[0068] In this step, the encoding circuit patterns are clustered by clustering component 250. In one embodiment, clustering component 250 uses distributed hierarchical clustering because the usual clustering algorithm has a computational complexity of O(kNd), where k is the number of clusters, N is the number of patterns to be clustered, and d is the size of the pattern.

[0069] The clustering component 250 performs clustering in the following manner. The clustering component 250 initially includes all input circuit patterns as large clusters. The clustering component 250 divides the cluster into smaller clusters. For each cluster, the clustering component 250 determines the similarity measure of the coding circuit pattern within the cluster. The clustering component 250 determines whether the similarity measure of the coding circuit pattern meets the threshold condition based on the similarity between the coding circuit patterns of the cluster. If the similarity measure of the coding circuit pattern indicates a threshold similarity between the coding circuit patterns of the cluster that is less than (or equal to) the cluster, the clustering component 250 further subdivides the cluster into sub-clusters. If the similarity measure of the coding circuit pattern indicates a threshold similarity between the coding circuit patterns of the cluster that is greater than the cluster, the clustering component 250 stops subdividing the cluster.

[0070] Thus, hierarchical clustering makes the clustering process computationally efficient by reducing k and N (and therefore reducing the turnaround time at each level) as the data of the set 710 including circuit patterns from the circuits is successively split into subclusters 720 which can be subdivided in parallel. Thus, the complexity of clustering is not O(kNd), but rather the system can distribute the work (e.g., 2 subclusters per branch of the tree) and obtain a complexity of O(Ndlog(k)). This is a significant savings when k is large. Furthermore, conventional techniques require extremely large amounts of memory to execute clustering algorithms with large k. In contrast, the disclosed embodiments improve memory usage by using encoded circuit patterns that take up significantly less storage than conventional representations of circuit patterns.

[0071] Other clustering methods, such as k-means clustering, spectral clustering, agglomerative clustering, etc., running on a single machine or distributed machines, may also be used by clustering module 250. This will depend on the amount of data and other data characteristics as to which clustering method is best suited for the problem at hand.

[0072] In one embodiment, the clustering component 250 uses k-means clustering at each hierarchical branch of the cluster tree. The clustering component 250 can use different methods to determine which cluster leaf 730 to split at any given level based on each leaf cluster indicator such as cluster inertia. Various embodiments can use other clustering methods instead of k-means at each hierarchical branch.

[0073] The encoding of the circuit patterns separates the circuit patterns well enough so that the resulting clusters have patterns that satisfy a similarity metric, such as a degree of match based on the geometry of the patterns. Figure 8 8 shows sample cluster entries 810 after they have been decoded back into rasterized polygon space. Figure 8 As shown in , the various circuit patterns have significant similarities, although there may be subtle differences in the circuit patterns across clusters.

[0074] After the cluster tree is completed, the leaves of the tree are used as the final clusters. For hierarchical clustering, the clustering component 250 can use the intermediate cluster branches on the tree to determine whether the "optimal number of clusters" (i.e., not excessive clustering based on various indicators) is less than the total number of leaves of the tree. Then, different clustering results are generated without performing additional work.

[0075] In some embodiments, clustering component 250 uses application-specific indicators to help distinguish when a cluster should be further divided. For example, clustering component 250 determines whether the similarity measure of the encoded circuit patterns meets a threshold condition corresponding to the similarity between the encoded circuit patterns of the clusters. If the threshold condition is met, clustering component 250 further subdivides the cluster. As an example, when greater than or equal to a threshold percentage of the compared circuit patterns are different, the threshold condition is met, and if less than a threshold percentage of the circuit patterns are different, the threshold condition is not met. The comparison of circuit patterns can be performed using any of the following techniques.

[0076] Clustering component 250 can use the similarity of the polygons closest to the center of the circuit pattern, for example, by comparing only a subset of the circuit pattern that covers the area of ​​the circuit pattern center. Thus, clustering component 250 identifies the polygons closest to the center of the circuit pattern and compares them across different circuit patterns in a cluster. Limiting the comparison to the polygons closest to the center of the polygon makes the process computationally efficient compared to the process of comparing the entire circuit pattern.

[0077] Clustering component 250 can determine the polygon density in the circuit pattern to compare the circuit patterns in the clusters. Therefore, clustering component 250 determines a measure of the polygon density of the circuit patterns of the clusters, for example, by counting the number of polygons in each cluster. Clustering component 250 determines a measure of similarity of the circuit patterns in the clusters by comparing their polygon densities.

[0078] In some embodiments, clustering component 250 performs sampling of simulated lithography images of polygons in the circuit pattern for comparing the circuit pattern of the cluster to determine whether to further subdivide the cluster. Thus, clustering component 250 samples the circuit pattern to select a subset or region within the circuit pattern and compares it with a corresponding subset or region of another circuit pattern.

[0079] In some embodiments, clustering component 250 weights different parts of the coded circuit pattern in different ways. For example, if each coded circuit pattern has 16 values ​​(digits), clustering component 250 places more emphasis on some of the digits and less emphasis on other digits. For example, the value closer to the center of the geometric pattern can be weighted differently compared to the value closer to the border of the circuit pattern. For example, the value closer to the center of the geometric pattern can be weighted more highly than the value closer to the border of the circuit pattern. Therefore, clustering component 250 weights some of the values ​​more highly than other values. The determination of these weights is application-specific because each coded entry has a relative importance that the user will determine. Therefore, the weight can be received from the user and is configurable.

[0080] In some embodiments, clustering component 250 performs clustering using encoded circuit patterns, but uses uncompressed (original) circuit patterns corresponding to the encoded circuit patterns to determine whether to further subdivide a cluster. Thus, clustering component 250 performs what is essentially a hybrid clustering, which utilizes compressed data (encoded circuit patterns) to perform the actual clustering process, but makes decisions about which clusters to split based on metrics about the corresponding original data set (unencoded circuit patterns). For example, even if clustering is performed using encoded circuit patterns, unencoded circuit patterns can be used to determine a similarity measure between two circuit patterns.

[0081] Computer architecture

[0082] Fig. 9 An example machine of computer system 900 is shown within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0083] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Furthermore, while a single machine is shown, the term "machine" should also be construed to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0084] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 918, which communicate with each other via a bus 930.

[0085] Processing device 902 represents one or more processors, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 902 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 902 can be configured to execute instructions 926 for performing the operations and steps described herein.

[0086] The computer system 900 may also include a network interface device 908 to communicate over a network 920. The computer system 900 may also include a video display unit 910 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), a graphics processing unit 922, a signal generating device 916 (e.g., a speaker), a graphics processing unit 922, a video processing unit 928, and an audio processing unit 932.

[0087] The data storage device 918 may include a machine-readable storage medium 924 (also referred to as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 926 or software embodying any one or more of the methodologies or functions described herein. The instructions 926 may also reside completely or at least partially within the main memory 904 and / or within the processing device 902 during execution by the computer system 900, the main memory 904 and the processing device 902 also constituting machine-readable storage media.

[0088] In some implementations, the instructions 926 include instructions for implementing functions corresponding to the present disclosure. Although the machine-readable storage medium 924 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine and processing device 902 to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0089] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. These operations are operations requiring physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0090] It should be remembered, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise stated, as will be apparent from this disclosure, it should be understood that throughout the specification certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0091] The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purpose, or the apparatus may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including a floppy disk, an optical disk, a CD-ROM, and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic card or an optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0092] The algorithm and display proposed herein are not intrinsically related to any particular computer or other device. Various other systems can be used together with the program according to the teachings herein, or it can be proved that it is convenient to construct a more specialized device to perform the method. In addition, the present disclosure is not described with reference to any specific programming language. It will be understood that various programming languages ​​can be used to implement the teachings of the present disclosure as described herein.

[0093] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0094] In the foregoing disclosure, the implementation of the present disclosure has been described with reference to its specific example implementation. It is obvious that various modifications can be made to these implementations without departing from the scope and broad spirit of the embodiments of the present disclosure as set forth in the appended claims. Where the present disclosure refers to some elements in the singular, more than one element may be depicted in the accompanying drawings, and the same elements are marked with the same numerals. Therefore, the present disclosure and the accompanying drawings should be considered to be illustrative rather than restrictive.

Claims

1. A method for performing classification on a physical layout of a circuit, the method comprising: receiving a representation of the physical layout of the circuit; identifying a set of circuit patterns from the representation of the physical layout of the circuit; encoding, by a processor, the set of circuit patterns into a set of encoded circuit patterns, the set of encoded circuit patterns including one encoded circuit pattern corresponding to each circuit pattern in the set of circuit patterns, wherein the encoding is performed by a machine learning based autoencoder, the autoencoder receiving the circuit pattern as input and regenerating a circuit pattern as output, the autoencoder converting the input circuit pattern into a low-dimensional encoded representation generated by a hidden layer of the autoencoder and then converting it into an output circuit pattern that matches the input circuit pattern, the encoded circuit pattern being represented using less data than the input circuit pattern; and The set of encoded circuit patterns is clustered into a plurality of clusters.

2. The method of claim 1 , wherein the machine learning based autoencoder is a neural network based autoencoder, the neural network based autoencoder being trained to: receive the circuit pattern as input and generate an output representation of the circuit pattern that matches the input circuit pattern, wherein an internal layer of the neural network based autoencoder generates the encoded circuit pattern.

3. The method of claim 2, wherein the neural network-based autoencoder comprises: A convolutional layer receives the input circuit pattern to generate the encoded circuit pattern.

4. The method of claim 3, wherein the neural network-based autoencoder further comprises: A deconvolution layer receives the encoded circuit pattern as input and generates the output representation of the circuit pattern.

5. The method according to claim 1, further comprising: Distributed training of the machine learning based autoencoder is performed using a subset of the circuit patterns of the circuit design.

6. The method according to claim 5, wherein the distributed training comprises: determining a plurality of training data sets, each training data set comprising a plurality of circuit patterns; Training the machine learning based autoencoder in parallel using a plurality of computer processors, wherein each computer processor uses one of the plurality of training data sets to determine a set of parameters for the machine learning based autoencoder; as well as The parameter sets generated in parallel are aggregated to obtain a combined parameter set for the machine learning based autoencoder.

7. The method according to claim 1, further comprising: A machine learning based model is trained using the plurality of clusters of the encoded circuit patterns, the training comprising: selecting a subset of circuit patterns from each cluster to train the machine learning based model.

8. The method according to claim 1, further comprising: The trained machine learning-based model is evaluated using the plurality of clusters of the encoded circuit patterns, the evaluating comprising selecting a subset of circuit patterns from each cluster to evaluate the machine learning-based model.

9. The method of claim 1, wherein clustering the encoded circuit patterns is performed using a hierarchical clustering technique.

10. The method of claim 9, wherein the hierarchical clustering technique is performed using a distributed system that divides each cluster into sub-clusters in parallel.

11. The method according to claim 10, further comprising: For each cluster, determining whether the cluster should be further subdivided into subclusters comprises: For each cluster, determining a similarity measure of the encoded circuit patterns within the cluster; determining whether the similarity measure of the encoded circuit patterns satisfies a threshold condition, the threshold condition corresponding to the similarity between the encoded circuit patterns of the clusters; and In response to determining that the similarity measure of encoded circuit patterns satisfies the threshold condition, the cluster is further subdivided into sub-clusters.

12. The method of claim 11, wherein the similarity measure of circuit patterns is determined for a pair of circuit patterns by comparing corresponding portions of each circuit pattern from the pair of circuit patterns.

13. The method of claim 11, wherein the similarity measure of the encoded circuit pattern assigns different weights to different portions of the encoded circuit pattern.

14. The method of claim 11, wherein the similarity measure of circuit patterns is determined by comparing polygon densities of circuit patterns.

15. The method of claim 11, wherein the similarity measure of circuit patterns is determined using circuit patterns input to the autoencoder, and the partitioning of the clusters into subclusters is performed using encoded circuit patterns.

16. A non-transitory computer readable medium comprising stored instructions which, when executed by a processor, cause the processor to perform steps comprising: a representation of the physical layout of the receiving circuit; identifying a set of circuit patterns from the representation of the physical layout of the circuit; encoding, by a processor, the set of circuit patterns into a set of encoded circuit patterns, the set of encoded circuit patterns including one encoded circuit pattern corresponding to each circuit pattern in the set of circuit patterns, wherein the encoding is based on executing a machine learning-based autoencoder that receives the circuit pattern as input and regenerates a circuit pattern as output, the autoencoder converting the input circuit pattern into a low-dimensional encoded representation generated by a hidden layer of the autoencoder and then converting it into an output circuit pattern that matches the input circuit pattern, the encoded circuit pattern being represented using less data than the input circuit pattern; and The set of encoded circuit patterns is clustered into a plurality of clusters.

17. The non-transitory computer-readable medium of claim 16, wherein the machine learning based autoencoder is a neural network based autoencoder trained to receive the circuit pattern as input and generate an output representation of the circuit pattern that matches the input circuit pattern, wherein an internal layer of the neural network based autoencoder generates the encoded circuit pattern.

18. The non-transitory computer readable medium of claim 16, the steps further comprising performing distributed training by: determining a plurality of training data sets, each training data set comprising a plurality of circuit patterns; Training the machine learning based autoencoder in parallel using a plurality of computer processors, wherein each computer processor uses one of the plurality of training data sets to determine a set of parameters for the machine learning based autoencoder; as well as The parameter sets generated in parallel are aggregated to obtain a combined parameter set for the machine learning based autoencoder.

19. The non-transitory computer readable medium of claim 16, the steps further comprising: For each cluster, determining whether the cluster should be further subdivided into subclusters comprises: For each cluster, determining a similarity measure of circuit patterns within the cluster; determining whether the similarity measure of the encoded circuit patterns satisfies a threshold condition, the threshold condition corresponding to the similarity between the encoded circuit patterns of the clusters; and In response to determining that the similarity measure of circuit patterns satisfies the threshold condition, the cluster is further subdivided into sub-clusters.

20. A system comprising: Memory, which stores instructions; as well as A processor coupled to the memory and configured to execute the instructions, which when executed cause the processor to perform steps comprising: a representation of the physical layout of the receiving circuit; identifying a set of circuit patterns from the representation of the physical layout of the circuit; encoding the set of circuit patterns into a set of encoded circuit patterns, the set of encoded circuit patterns including one encoded circuit pattern corresponding to each circuit pattern in the set of circuit patterns, wherein the encoding is based on executing a machine learning based autoencoder, the autoencoder receiving the circuit pattern as input and regenerating a circuit pattern as output, the autoencoder converting the input circuit pattern into a low-dimensional encoded representation generated by a hidden layer of the autoencoder and then converting it into an output circuit pattern that matches the input circuit pattern, the encoded circuit pattern being represented using less data than the input circuit pattern; and The set of encoded circuit patterns is clustered into a plurality of clusters.

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