Dynamic refresh rate control

Abstract

In one embodiment, a memory controller in an integrated circuit can generate refreshes to one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit can include one or more temperature sensors. A rate of change of temperature can be determined according to the temperature sensors. If the rate is greater than a threshold, the memory controller can generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller can generate refreshes at a reduced refresh rate.

Description

Technical Field

[0001] The implementation described in this article relates to refresh operations in dynamic random access memory (DRAM). Background Technology

[0002] DRAM is commonly used as the main memory system in a wide variety of computing systems, from desktop or server computers to laptops, personal digital assistants, smartphones, and other portable devices. In many cases, the power consumed in DRAM constitutes a significant portion of the total power. In portable systems that often operate on limited power sources such as batteries, reducing the power consumption of components in the system is crucial to extending the time the system can operate on limited power. Additionally, power consumption leads to heat generation, which must be dissipated in all types of systems.

[0003] DRAM memory cells store data as charge on capacitors and are subject to the risk of charge leakage over time. That is, the stored charge may leak, and the value read from the memory cell after a leak will differ from the value written, leading to erroneous operations. To prevent data loss / corruption in DRAM due to charge loss on capacitors, memory cells are periodically refreshed (reading values ​​from the cell and writing them back). The power consumed by performing refreshes can be a significant portion of the total power consumed in DRAM.

[0004] The refresh rate required to prevent data loss / corruption is specified for a given DRAM and varies with temperature. As temperature increases, leakage increases, thus requiring a higher refresh rate (e.g., more frequent refreshes are needed). Many DRAMs are equipped with temperature sensors, and the DRAM determines the required refresh rate based on the temperature sensed by the sensor. DRAM includes registers that can be read to determine the required refresh rate. However, the temperature sensors implemented in most DRAMs are fairly coarse-grained (e.g., a range of 10-20 degrees Celsius is often assigned the same refresh rate). The refresh rate for a given range is the refresh rate required at the higher temperatures within that range. If the temperature is near the lower end of the given refresh rate range, the refresh rate is higher than actually needed. Additionally, many DRAMs implement a single temperature sensor. Considering potential hotspots not close to the temperature sensor location on the DRAM, the DRAM can impose a significant margin on the temperature measurement results. If no hotspots are present, the refresh rate is higher than actually needed. In some cases, the margin can be as high as 10 degrees Celsius or higher. Summary of the Invention

[0005] In one embodiment, one or more DRAMs are adjacent to an integrated circuit package, which includes a memory controller to control the DRAMs. The memory controller can generate refreshes for the DRAMs based on a refresh rate. In one embodiment, the integrated circuit includes multiple temperature sensors. A thermal controller can read the sensors and determine the rate of temperature change (“temperature change rate”). If the rate is greater than a threshold, the memory controller can generate a refresh based on the refresh rate specified by the DRAM. If the rate is less than the threshold, the memory controller can generate a refresh at a reduced refresh rate. A reduced refresh rate can be used because if the rate is less than the threshold, hot spots may not be generated in the DRAM, and margins in the DRAM temperature measurements may be unnecessary. Additionally, the temperature read from the temperature sensors on the integrated circuit can be finer-grained than the temperature range mapped from the DRAM to the corresponding refresh rate, so a reduced rate may be sufficient for the actual temperature. Refreshes can be performed less frequently compared to using a refresh rate specified by the DRAM, thus reducing power consumption. Attached Figure Description

[0006] The following detailed description refers to the accompanying drawings, which will now be briefly described.

[0007] Figure 1 This is a side view of one implementation of a DRAM that encapsulates an integrated circuit (System-on-a-Chip (SOC) in this example).

[0008] Figure 2 This is a top view of one implementation of a DRAM packaged with integrated circuits.

[0009] Figure 3 It is an implementation scheme of an integrated circuit (SOC) and includes Figure 1 and Figure 2 The diagram shows a block diagram of a DRAM memory.

[0010] Figure 4 This is a block diagram of an implementation scheme for DRAM, including a memory controller and a thermal controller.

[0011] Figure 5 This is a flowchart illustrating one implementation of an integrated circuit that controls the refresh operation of DRAM.

[0012] Figure 6 It is a block diagram of one implementation of a system including an integrated circuit (SOC) and a memory with DRAM.

[0013] While the embodiments described herein may be subject to various modifications and alternatives, specific embodiments thereof are illustrated by way of example in the accompanying drawings and will be described in detail herein. However, it should be understood that the drawings and specific embodiments thereof are not intended to limit the embodiments to the particular forms disclosed, but rather, the invention is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the appended claims. The headings used herein are for organizational purposes only and are not intended to limit the scope of the specification. As used throughout this application, the word “may” is used in an permissive sense (i.e., meaning possible) rather than a mandatory sense (i.e., meaning must). Similarly, the words “comprising” and “including” mean “including, but not limited to”. As used herein, the terms “first,” “second,” etc., serve as labels for the nouns that follow them and do not imply any kind of ordering (e.g., spatial, temporal, logical, etc.) unless expressly indicated.

[0014] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or claimed to be “configured to” perform one or more tasks or operations. This expression—an [entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing, such as an electronic circuit). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be described as “configured to” perform a task even if the structure is not currently being operated. “A clock circuit configured to generate an output clock signal” is intended to cover, for example, a circuit that performs this function during operation, even if the circuit in question is not currently being used (e.g., the circuit is not connected to a power source). Therefore, an entity described or stated as “configured to” perform a task refers to a physical thing, such as a device, circuit, memory storing program instructions executable to perform that task, etc. This phrase is not used herein to refer to intangible things. Typically, the circuit forming the structure corresponding to “configured to” may include hardware circuitry. Hardware circuitry may include any combination of the following: combinational logic circuits, clock storage devices (such as flip-flops, registers, latches, etc.), finite state machines, memories (such as static random access memory or embedded dynamic random access memory), custom-designed circuits, analog circuits, programmable logic arrays, etc. Similarly, for ease of description, various units / circuits / components may be described as performing one or more tasks. Such descriptions should be interpreted as including the phrase "configured to".

[0015] The term "configured as" is not intended to mean "able to be configured as". For example, an unprogrammed FPGA is not considered "configured as" to perform a particular function, although it may be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform that function.

[0016] In one implementation, the hardware circuit according to this disclosure can be implemented by encoding a description of the circuit in a hardware description language (HDL) such as Verilog or VHDL. The HDL description can be synthesized against a cell library designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain a final design database that can be transferred to a factory to generate a mask and ultimately produce an integrated circuit. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit can include transistors and may also include other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete elements may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a field-programmable gate array (FPGA) and implemented in the FPGA.

[0017] As used herein, the terms “based on” or “depending on” are used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors may influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase “A is determined based on B.” This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on another factor such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase “based on” is synonymous with the phrase “at least partially based on.”

[0018] This specification includes references to various embodiments to indicate that this disclosure is not intended to refer to a particular specific embodiment, but rather to a range of embodiments falling within the spirit of this disclosure, including the appended claims. Specific features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0019] This specification may use the words “an” or “a kind” to refer to an element, or the word “the” to refer to an element. These words are not intended to mean that only one instance of the element exists. More than one may exist in various embodiments. Therefore, unless explicitly described as only one, “an,” “a kind,” and “the” should be interpreted as meaning “one or more.”

[0020] This specification may describe various components, units, circuits, etc., as coupled. In some embodiments, components, units, circuits, etc., may be coupled if they are electrically coupled (e.g., directly connected or indirectly connected through one or more other circuits) and / or communicatively coupled. Detailed Implementation

[0021] Figure 1 This is a side view of one embodiment of integrated circuit 10 (in this case, a system-on-a-chip or SOC, although any integrated circuit can be used in other embodiments) and one or more DRAMs such as DRAMs 30A-30B. Each DRAM 30A-30B may also be an integrated circuit and may be coupled immediately adjacent to SOC 10. More specifically, DRAMs 30A-30B may be in contact with or packaged with SOC 10. For example, DRAMs 30A-30B may be in a package stack (POP) configuration with SOC 10. In another specific embodiment, DRAMs 30A-30B may be in a chip stack (COC) configuration with SOC 10.

[0022] Figure 2 This is a top view of SOC 10, with DRAM 30A-30D arranged on top of SOC 10, including... Figure 1 The DRAMs shown are 30A-30B. That is to say, Figure 2 The top view shown is taken from the top down, where... Figure 1 The side view shown in Figure 2 At the top edge. DRAM 30A-30D is available... Figure 2 On top of the SOC 10 in the view. Each DRAM 30A-30D may include a temperature sensor, which is shown as... Figure 2 The plus sign "+" in the diagram (e.g., for reference numerals 32A-32D). Temperature sensors 32A-32D can be located approximately at the center of each DRAM 30A-30D, such as... Figure 2 As shown. It should be noted that, although Figure 2 Four DRAM 30A-30Ds are shown, but more or fewer DRAM 30A-30Ds may be used in other embodiments. Additionally, one or more DRAM 30A-30Ds may be stacked on top of each other and mounted as a stack on the SOC 10, allowing more DRAM 30A-30Ds to be included in the area defined by the size of the SOC 10.

[0023] The SOC 10 may also have one or more temperature sensors (e.g., in various embodiments, it may have at least one temperature sensor or multiple temperature sensors), in Figure 2 This is indicated by "x". For example, reference numerals 34A-34C show temperature sensors, for example, located in an area of ​​SOC 10 covered by DRAM 30A. Other temperature sensors 34D-34M may be located in other areas of SOC 10, such as... Figure 2 As shown. Typically, a System-on-a-Chip (SOC) 10 may implement one or more temperature sensors in a region of the SOC 10, which may generate significant heat during operation (e.g., the temperature sensors may be located near potential hot spots in the SOC). For example, the SOC 10 may include one or more processors that execute operating system software and various application software on the SOC 10. The processor may generate significant heat under certain operating conditions, and therefore one or more temperature sensors may be present near the processor. Implementations of the SOC 10 may include one or more graphics processing units (GPUs), which may generate significant heat in certain operating modes, and therefore one or more temperature sensors may be present near the GPU. Other video processing peripherals may similarly have temperature sensors (e.g., image signal processors (ISPs), encoders / decoders, etc.). Other types of peripherals may also have temperature sensors. In other implementations, additional temperature sensors may be distributed across a region of the SOC 10, allowing for reasonable accuracy in measuring the surface temperature of the SOC 10. The number and location of the temperature sensors may vary depending on the implementation.

[0024] Temperature sensors can include any circuitry that can be implemented on an integrated circuit and respond to temperature in a predictable manner. In one embodiment, a temperature sensor may include an analog-to-digital converter that converts a voltage or current representing the sensed temperature into a digital value that can be transmitted using other parts of the integrated circuit. This digital value may be a direct mapping to temperature, or it may be adjusted to represent the sensed temperature by calibration results. Other embodiments may measure temperature in other ways (e.g., using the frequency of a temperature-varying ring oscillator, etc.).

[0025] Due to the close proximity of DRAM 30A-30D and SOC 10, significant thermal coupling may exist between them. When SOC 10 develops a "hot spot" due to significant activity in one area of ​​SOC 10, the generated heat can be transferred to DRAM 30A-30D, which is located in a higher area of ​​SOC 10, thus forming a hot spot in the DRAM. A hot spot can be a localized area with a temperature higher than the surrounding integrated circuit. While heat tends to diffuse and dissipate over time, rapid heat generation can temporarily create a hot spot with an elevated temperature, potentially tens of degrees Celsius hotter than the surrounding integrated circuit area.

[0026] Because heat is transferred to DRAM 30A-30D, DRAM 30A-30D can develop hot spots that are physically far from the temperature sensor 32A-32D within DRAM 30A-30D. Due to this effect, DRAM 30A-30D can apply a margin to the temperature sensed by temperature sensor 32A-32D when determining the desired refresh rate. This margin ensures that refreshes are frequent enough to maintain data integrity, even if hot spots exist within DRAM 30A-30D, but these hot spots are far from the temperature sensor 32A-32D and therefore not directly sensed by it. In experiments with SOC 10 and DRAM 30A-30D, it was determined that DRAM 30A-30D does not generate hot spots due to "self-heating" (e.g., due to the operation of DRAM 30A-30D itself), but may have hot spots due to heating from SOC 10. Therefore, the margin does not need to be as large as designed. The temperature sensor 34A-34M in SOC 10 can be used to detect hot spots and apply refresh margin when needed, and apply smaller margin at other times.

[0027] More specifically, hot spots can form in an SOC 10 when the temperature changes rapidly. Therefore, when the temperature changes rapidly, the SOC 10 can implement a refresh control mechanism that uses a more conservative (higher) refresh rate. When the temperature is in a more stable state, i.e., changing slowly, a less conservative (lower) refresh rate can be used. During periods of slow temperature change, the temperature variation on the DRAM has been experimentally determined to be low. Generally, the refresh rate can refer to the frequency at which refreshes are generated for the DRAM. A higher refresh rate means more frequent refreshes, and a lower refresh rate means less frequent refreshes. The refresh rate can be specified based on how frequently each cell must be refreshed, and refreshes can be generated to ensure that each memory cell receives a refresh within a specified time. A given refresh command (also called a refresh request) can refresh a row of memory cells in a group of DRAM ("per group" refresh) or a row of memory cells in each group of DRAM ("full group" refresh). Based on the number of memory cells refreshed by each command and the total number of memory cells in DRAM 30A-30D, the number of refresh commands required to ensure the correct refresh of all memory cells within a given time period can be calculated, and the memory controller can generate refresh commands accordingly.

[0028] By reducing the refresh rate when the temperature change rate is low, the SOC 10 can reduce the power consumed in performing refreshes compared to the refresh rate requested by the DRAM 30A-30D. Since the margin implemented by the DRAM 30A-30D is known to be unnecessary when the temperature change rate is low, data integrity is still protected even at the reduced refresh rate. On the other hand, when the temperature change rate is high, the SOC 10 can use the more conservative refresh rate requested by the DRAM 30A-30D to ensure data integrity. In one embodiment, a programmable threshold for the temperature change rate can be used to determine whether the temperature change rate is high enough to use the refresh rate specified by the DRAM or low enough to use a reduced refresh rate.

[0029] In one implementation, since temperature measurements from the temperature sensors 34A-34M implemented within the SOC 10 are available within the SOC 10, a finer-grained refresh rate can be generated. For example, as described above, the same refresh rate can be requested from the DRAMs 30A-30D for any temperature within a relatively wide range (e.g., 10-20 degrees Celsius). The SOC 10 can scale the refresh rate at a finer granular level, allowing the refresh rate to be closer to the actual required refresh rate for the current temperature. Further reductions in power consumption can be achieved due to this finer granularity.

[0030] In one implementation, the typical operating temperature of the SOC 10 can be close to the boundary temperature between the two refresh rates supported by the DRAM 30A-30D. Utilizing the margin imposed by the DRAM 30A-30D, a higher refresh rate can typically be selected during this typical operating condition. The higher refresh rate can be twice that of the lower refresh rate, and therefore the power consumption impact of using the higher refresh rate is significant. If the rate of temperature change is low, the margin is unnecessary, and a refresh rate closer to the lower refresh rate may suffice. Choosing a lower refresh rate can allow for reduced power consumption in these cases.

[0031] Figure 3 This is a block diagram of an implementation of SOC 10 and a memory 12 formed by DRAM 30A-30D. Figure 3 The implementation scheme is a logic view of SOC 10 and DRAM 30A-30D, which can be described as above regarding... Figure 1 and Figure 2 The physical arrangement is as discussed. Temperature sensors 32A-32D and 34A-34M are not included. Figure 3 As shown, but included. For example, CPU cluster 14 may have one or more temperature sensors 34A-34M, as well as various peripheral devices 16A-16B that can generate significant heat (e.g., GPUs may be peripheral).

[0032] As the name suggests, the components of SOC 10 can be integrated onto a single semiconductor substrate, which serves as an integrated circuit "chip". Other implementations can be used that have an integrated circuit with a memory controller 18 to control memory 12 (including generating refresh commands to memory 12). However, SOC 10 will be used as an example herein. In the illustrated implementation, the components of SOC 10 include a processor cluster 14. In one implementation, the processor can be a central processing unit (CPU), so the processor cluster 14 can be a CPU cluster 14. In the illustrated implementation, the components of SOC 10 also include peripheral components 16A-16B (more simply, "peripheral devices" 16), a memory controller 18, a SOC power manager (PMGR) 20, and a communication structure 22. Components 14, 16, 18, and 20 can all be coupled to the communication structure 22, and therefore to each other for communication between components. The memory controller 18 can be coupled to memory 12 during use.

[0033] The memory controller 18 may include refresh control circuitry 36, which generates refresh commands for each DRAM 30A-30D based on the refresh rate of the DRAMs 30A-30D. That is, in the illustrated embodiment, each DRAM 30A-30D may have an independent refresh rate, and the memory controller 18 may independently generate refresh commands for each DRAM 30A-30D. In one embodiment, each DRAM 30A-30D may be on a different channel between the memory controller 18 and the memory 12, and therefore may be accessed independently of other DRAMs 30A-30D. For example, each DRAM 30A-30D may have its own set of open pages and may be read or written using commands on its channel, independent of reads / writes to other channels of other DRAMs 30A-30D.

[0034] The refresh control circuit 36 ​​includes refresh rate registers 38A-38D and reduced refresh rate registers 40A-40D. In this embodiment, there may be different refresh rate registers 38A-38D for each DRAM 30A-30D, and different reduced refresh rate registers 40A-40D for each DRAM 30A-30D, allowing independent control of the refresh rate for each DRAM 30A-30D. The refresh rate registers 38A-38D can be programmed individually with the refresh rate requested by each DRAM 30A-30D. The reduced refresh rate registers 40A-40D can be programmed with a reduced refresh rate lower than the corresponding refresh rate requested by each DRAM 30A-30D.

[0035] In one implementation, in response to a temperature change rate exceeding a threshold, refresh control circuitry 36 can select a refresh rate from refresh rate registers 38A-38D to control the rate at which refresh commands are generated for each DRAM 30A-30D. In response to a temperature change rate not exceeding the threshold, refresh control circuitry 36 can select a reduced refresh rate from reduced refresh rate registers 40A-40D to control the rate at which refresh commands are generated for each DRAM 30A-30D. In other implementations, a position-aware mechanism can be used. That is, temperature sensors 34A-34M can be grouped according to physically proximate DRAMs 30A-30D, and the temperature change rate of each group can be used to select the refresh rate of the corresponding DRAM 30A-30D.

[0036] In other implementations, there may be more than one set of reduced refresh rate registers similar to registers 40A-40D. There may be more than one threshold for the rate of temperature change, and the corresponding refresh rate from the reduced refresh rate register set can be selected based on which thresholds have been exceeded or not exceeded. The reduced refresh rate can be programmed in any desired manner (e.g., instructions executed in SOC 10 can program registers 40A-40D via SOC PMGR 20, or can be directly programmed into the refresh control circuitry 36).

[0037] The SOC PMGR 20 can be configured to control the amount of supply voltage requested from the power management unit (PMU) in the system. Multiple supply voltages may be generated by the PMU for the SOC 10. For example, a voltage may be generated for the processor cores in CPU cluster 14, and another voltage may be generated for other components in the SOC 10. In one embodiment, the other voltages may be used for the memory controller 18, peripheral devices 16, the SOC PMGR 20, and other components of the SOC 10, and power gating may be employed based on power domains. In some embodiments, multiple supply voltages may be present for the remainder of the SOC 10. In some embodiments, memory supply voltages may also be present for the CPU cluster 14 and / or the various memory arrays in the SOC 10. The memory supply voltages may be used in conjunction with the voltages supplied to logic circuitry, and may have a lower voltage value than that required to ensure robust memory operation. The SOC PMGR 20 can be under direct software control (e.g., the software can directly request the power-on and / or power-off of components) and / or can be configured to monitor the SOC 10 and determine when to power on or off individual components. For the CPU cluster 14, a voltage request can be provided to the SOC PMGR 20, which can then forward the request to the PMU to implement changes in the supply voltage magnitude.

[0038] Additionally, the SOC PMGR 20 may include one or more temperature registers 42, which can record the temperatures measured by the respective temperature sensors 34A-34M. The temperature can be read periodically at a rate programmable into the SOC PMGR 20. Alternatively, software executing on the CPU cluster 14 can read the temperature and record it in the temperature register 42, directly included in the memory controller 18 / refresh control circuitry 36. Figure 3 (Not shown in the image) A similar temperature register is located in, and / or in, memory 12. The rate of temperature change can be calculated based on continuous temperature readings from each sensor.

[0039] CPU cluster 14 may include one or more processor cores that serve as CPUs for the SOC 10. CPUs typically execute software that controls the overall operation of the system (e.g., operating system software) and various application software that provides the desired functionality within the system. In some embodiments, there may be more than one CPU cluster 14. In some embodiments, in addition to local caches for each processor, CPU cluster 14 may also include one or more shared caches.

[0040] In addition to refresh control circuitry 36, memory controller 18 typically includes circuitry for receiving memory operations from other components of SOC 10 and for accessing memory 12 to complete the memory operations. Memory controller 18 can be configured to access any type of DRAM memory, such as synchronous DRAM (SDRAM), including double data rate (DDR, DDR2, DDR3, DDR4, etc.) DRAM. Low-power / mobile versions of DDR DRAM (e.g., LPDDR, mDDR, etc.) may be supported. Memory controller 18 may include a memory operation queue for ordering (and possibly reordering) these operations and presenting them to memory 12. Memory controller 18 may also include data buffers for storing write data awaiting to be written to memory and read data awaiting return to the source of the memory operation. In some embodiments, memory controller 18 may include a memory cache for storing recently accessed memory data. For example, in a specific SOC implementation, a memory cache can reduce power consumption in the SOC by preventing data from being re-accessed from memory 12 if it is expected to be accessed again soon. In some cases, the memory cache may also be referred to as the system cache, which differs from private caches such as shared caches or processor caches that serve only certain components. Furthermore, in some implementations, the system cache does not need to reside within the memory controller 18.

[0041] Peripheral devices 16A-16B can be any set of additional hardware functions included in the SOC 10. For example, peripheral devices 16A-16B may include video peripherals such as image signal processors configured to process image capture data from cameras or other image sensors, display controllers configured to display video data on one or more display devices, graphics processing units (GPUs), video encoders / decoders, scalers, rotators, mixers, etc. Peripheral devices may include audio peripherals such as microphones, speakers, interfaces to microphones and speakers, audio processors, digital signal processors, mixers, etc. Peripheral devices may include interface controllers (such as peripheral device 16B) for various interfaces external to the SOC 10, including interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI) (including PCI High Speed ​​(PCIe)), serial ports, and parallel ports, etc. Peripheral devices may include networking peripherals such as Media Access Controllers (MACs). Any set of hardware may be included.

[0042] Communication structure 22 can be any communication interconnect and protocol used for communication between components of SOC 10. Communication structure 22 can be bus-based, including shared bus configuration, crossbar configuration, and hierarchical bus with bridges. Communication structure 22 can also be packet-based and can be hierarchical, crossbar, point-to-point, or other interconnects with bridges.

[0043] It should be noted that the number of components in SOC 10 can vary depending on the implementation. There may be a difference between... Figure 3 The number of each component shown is either more or less.

[0044] Figure 4This is a block diagram illustrating one embodiment of DRAM 30A coupled to memory controller 18 and a thermal controller 50 coupled to memory controller 18. Memory controller 18 may be similarly coupled to other DRAMs 30B-30D and may also perform similar operations as described below with respect to each of the other DRAMs 30B-30D. Thermal controller 50 includes a temperature register 42 from SOC PMGR 20 or has access to it. In one embodiment, thermal controller 50 may include hardware in SOC PMGR 20 and / or software stored in memory 12 and executable on another processor or cluster in CPU cluster 14 or SOC 10 (e.g., a processor in SOC PMGR 20 (not shown)). Any combination of hardware and / or software may be used in various embodiments. Memory controller 18 includes refresh control circuitry 36 and a refresh rate register 38A corresponding to DRAM 30A and a reduced refresh rate register 40A are shown. DRAM 30A includes a memory refresh (MR) register 52.

[0045] MR register 52 can be defined by the specifications of DRAM 30A to store an indication of the refresh rate requested by DRAM 30A. That is, SOC 10 (and more specifically, refresh control circuitry 36 in memory controller 18) can read MR register 52 to determine the refresh rate. This indication can be a divisor of the DRAM's base refresh rate. For example, a refresh rate of 85 degrees Celsius can be the base refresh rate. In the range of 65 to 85 degrees, the divisor can be 1. In the range of 45 to 65 degrees, the divisor can be 2, and in the range of 25 to 45 degrees, the divisor can be 4. In the range of 85 to 105 degrees, the divisor can be 1 / 2. Alternatively, a multiplier can be used, and the reciprocal of the above can be reported from MR register 52. In yet another alternative, the MR register can report the actual refresh rate instead of a multiplier or divisor. Any representation of the refresh rate can be used.

[0046] As mentioned above, the refresh rate indicated by MR register 52 can be based on the temperature measured by DRAM 30A (using... Figure 2 The temperature sensor 32A shown applies a design margin to the DRAM 30A (e.g., approximately 10 degrees Celsius in one embodiment). The memory controller 18 can periodically read the MR register 52 to obtain the refresh rate and can store an indication of the refresh rate in the refresh rate register 38A. This indication can be the multiplier / divisor described above, or it can be a value representing the actual refresh rate (e.g., based on clock cycles or time) based on the base refresh rate and that multiplier or divisor.

[0047] As previously described, the reduced refresh rate register 40A can be programmed with a lower refresh rate compared to the refresh rate in refresh rate register 38A. The reduced refresh rate can be obtained by scaling the refresh rate based on the current temperature in the SOC 10. The current temperature can be the maximum temperature measured by any of the temperature sensors 34A-34M provided by the thermal controller 50. Alternatively, the thermal controller 50 can program the reduced refresh rate register 40A based on the maximum measured temperature. Furthermore, the thermal controller 50 can determine the rate of temperature change based on previous and current temperature measurements and can provide the rate to the refresh control circuit 36. Alternatively, the thermal controller 50 can compare the rate of temperature change with a threshold used to select between the refresh rate and the reduced refresh rate and can provide an indication to the memory controller 18 whether the threshold has been exceeded to select between the refresh rate and the reduced refresh rate.

[0048] Figure 5 This is a flowchart illustrating the operation of selecting the refresh rate of DRAM 30A-30D in one implementation of SOC 10. However, for ease of understanding, the block diagram is shown in a specific order, but other orders may be used. The blocks implemented in the hardware can be executed in parallel within the combinational logic that forms the hardware. The blocks, combinations of blocks, and / or flowcharts as a whole can be pipelined over multiple clock cycles.

[0049] Figure 5 The operations shown can be performed periodically in the SOC 10. The frequency of the operations can be related to the rate of temperature change in the SOC 10. For example, in one embodiment, Figure 5 The operations can be performed at a frequency of approximately once per millisecond. In another embodiment, the operations can be performed more frequently than once per millisecond (e.g., multiple operations per millisecond, or once every 100 microseconds, more than once every 10 microseconds, etc.). In yet another embodiment, the operations can be performed less frequently than once per millisecond (e.g., once every 2 milliseconds, once every 5 milliseconds, once every 10 milliseconds, etc.). Any desired rate can be used.

[0050] Thermal controller 50 or PMGR 20 can read the temperature sensor and capture the current temperature in register 42 (box 60). Thermal controller 50 can determine the maximum temperature in the current temperature range (box 62) and can also determine the maximum rate of change of temperature (box 64). The rate of change of temperature for each temperature sensor can be determined based on the previous temperature and the current temperature measured by the sensor (and the amount of time between reading the two temperatures). Alternatively, the history of two or more temperatures from each sensor can be used with the current temperature to determine the rate of change of temperature. The maximum rate of change can be associated with a temperature other than the maximum temperature (e.g., a lower temperature may change faster than the maximum temperature).

[0051] The memory controller 18 can read the MR register of each DRAM 30A-30D and can set the corresponding unmodified refresh rate in the refresh rate registers 38A-38D (box 66). The thermal controller 50 can generate a reduced refresh rate for each DRAM 30A-30D based on the maximum measured temperature (box 68). For example, based on the maximum temperature measured by the SOC 10, the thermal controller 50 can scale the unmodified refresh rate and the margin implemented by the DRAM 30A-30D, which is associated with the maximum temperature range associated with the unmodified refresh rate. Alternatively, a reduced refresh rate can be generated based on the specifications of the DRAM 30A-30D (e.g., if the temperature is the temperature of the DRAM, then it is a refresh corresponding to the maximum temperature measurement result, without applying a margin).

[0052] The thermal controller 50 can compare a maximum rate of temperature change with a threshold rate programmed into the thermal controller (decision box 70). If the rate is greater than the threshold (decision box 70, "Yes" branch), the thermal controller 50 can communicate with the memory controller 18 to select an unmodified refresh rate from registers 38A-38D to control the refresh rate (box 72). If the rate is less than the threshold (decision box 70, "No" branch), the thermal controller 50 can communicate with the memory controller 18 to select a reduced refresh rate from registers 40A-40D to control the refresh rate (box 74). In another embodiment, the memory controller 18 can be programmed to have a threshold and can perform a comparison with the maximum rate of change provided by the thermal controller 50.

[0053] Figure 6 This is a block diagram of one embodiment of system 150. In the illustrated embodiment, system 150 includes at least one instance of a System-on-Chip (SOC) 10 coupled to external memory 12 and one or more peripheral devices 154. A Power Supply Unit (PMU) 156 is provided to supply power voltage to the SOC 10 and to supply one or more power voltages to the memory 12 and / or peripheral devices 154. In some embodiments, more than one instance of SOC 10 may be included (and more than one memory 12 may also be included). As previously described, external memory 12 may include DRAMs 30A-30D.

[0054] PMU 156 may generally include circuitry for generating supply voltages and providing those supply voltages to other components of the system, such as SOC 10, memory 12, and various off-chip peripheral devices 154, such as display devices, image sensors, user interface devices, etc. PMU 156 may therefore include programmable voltage regulators, logic components for interfacing with SOC 10, and more specifically with SOC PMGR 20, to receive voltage requests, etc.

[0055] Depending on the type of system 150, peripheral device 154 may include any desired circuitry. For example, in one embodiment, system 150 may be a mobile device (e.g., a personal digital assistant (PDA), smartphone, etc.), and peripheral device 154 may include devices for various types of wireless communications, such as WiFi, Bluetooth, cellular, GPS, etc. Peripheral device 154 may also include additional storage devices, including RAM storage devices, solid-state storage devices, or disk storage devices. Peripheral device 154 may include user interface devices, such as displays, including touch displays or multi-touch displays, keyboards or other input devices, microphones, speakers, etc. In other embodiments, system 150 may be any type of computing system (e.g., a desktop PC, laptop, workstation, network set-top box, etc.).

[0056] Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. This disclosure is intended to make the following claims interpretable as encompassing all such variations and modifications.

Claims

1. A system for refresh rate control, comprising: Dynamic random access memory (DRAM), the DRAM being configured to provide a first refresh rate; An integrated circuit, coupled to the DRAM, wherein the integrated circuit includes: At least one temperature sensor; A memory controller configured to determine a refresh rate for refreshing the DRAM in response to a rate of temperature change sensed by the at least one temperature sensor, wherein determining the refresh rate includes selecting the refresh rate between a first refresh rate and a second refresh rate, the second refresh rate being lower than the first refresh rate and determined based on one or more temperature measurements from the at least one temperature sensor, wherein a second rate of change for selecting the second refresh rate is lower than a first rate of change for selecting the first refresh rate.

2. The system of claim 1, wherein the DRAM is configured to provide a first refresh rate, and wherein the memory controller is configured to select the first refresh rate in response to the rate of change exceeding a threshold.

3. The system of claim 2, wherein the DRAM further comprises a second temperature sensor, wherein the DRAM is configured to generate the first refresh rate in response to a temperature sensed by the second temperature sensor.

4. The system of claim 2, wherein the memory controller is configured to select a second refresh rate in response to the rate of change not exceeding the threshold.

5. The system according to claim 4, wherein, The second refresh rate is obtained by scaling the first refresh rate in response to the temperature sensed by the at least one temperature sensor.

6. The system of claim 3, wherein the temperature sensed by the second temperature sensor is mapped to the first refresh rate with a first granularity, and wherein the temperature sensed by the at least one temperature sensor is mapped to the second refresh rate with a second granularity finer than the first granularity.

7. The system of claim 1, wherein the integrated circuit includes a thermal controller configured to detect a rate of temperature change in the integrated circuit in response to a temperature sensed by the at least one temperature sensor in the integrated circuit.

8. The system of claim 7, wherein the at least one temperature sensor in the integrated circuit comprises a plurality of temperature sensors, and wherein the temperature is the maximum temperature sensed by the plurality of temperature sensors.

9. The system of claim 1, wherein the DRAM is one of a plurality of DRAMs coupled to the memory controller, and wherein the memory controller is configured to independently control a plurality of the refresh rates of the plurality of DRAMs.

10. The system of claim 9, wherein a given DRAM of the plurality of DRAMs is configured to generate a first refresh rate for the given DRAM, and the memory controller is configured to refresh the given DRAM based on the refresh rate of the given DRAM.

11. A method for refresh rate control, comprising: Determine the rate of temperature change in an integrated circuit, which includes a memory controller; as well as The memory controller refreshes the refresh rate of the dynamic random access memory (DRAM) in response to the temperature change rate, wherein determining the refresh rate includes selecting the refresh rate from a first refresh rate provided by the DRAM and a second refresh rate determined based on one or more temperature measurements from a temperature sensor in the integrated circuit and lower than the first refresh rate, wherein the second change rate for selecting the second refresh rate is lower than the first change rate for selecting the first refresh rate.

12. The method of claim 11, wherein selecting the refresh rate includes selecting the first refresh rate in response to the rate of change exceeding a threshold.

13. The method of claim 12, wherein selecting the refresh rate includes selecting the second refresh rate in response to the rate of change not exceeding the threshold.

14. The method of claim 11, further comprising scaling the first refresh rate in response to the one or more temperature measurements to determine the second refresh rate.

15. The method of claim 11, wherein the DRAM is one of a plurality of DRAMs controlled by the memory controller, and the method further comprises independently determining the refresh rate of the plurality of DRAMs.

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