Semiconductor device

Abstract

Provided is a semiconductor device including a semiconductor substrate having a transistor portion and a diode portion, an injection suppression region that suppresses injection of second-conductivity-type carriers at an end portion of the diode portion when viewed from above the semiconductor substrate, and a lifetime control region that includes a lifetime inhibitor. Both the transistor portion and the diode portion have a base region of the second conductivity type on a surface of the semiconductor substrate. The transistor portion further has an emitter region of the first conductivity type and an extraction region of the second conductivity type having a higher doping concentration than the base region on the surface of the semiconductor substrate. The injection suppression region is free of the emitter region and the extraction region.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device. BACKGROUND

[0002] Conventionally, a technique is known in which, in a semiconductor device in which a transistor portion and a diode portion are formed on the same substrate, a particle beam such as a helium ion is irradiated to a predetermined depth position of the semiconductor substrate, and a lifetime control region containing a lifetime inhibitor is provided (for example, Patent Document 1 and Patent Document 2).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2017-135339

[0004] Patent Document 2: Japanese Patent Application Publication No. 2014-175517 SUMMARY

[0005] PROBLEMS TO BE SOLVED BY THE INVENTION

[0006] In such a semiconductor device, there is a problem in that a region of the transistor portion adjacent to the diode portion is damaged by the lifetime inhibitor, and a decrease and inconsistency in threshold voltage occur.

[0007] TECHNICAL SOLUTION

[0008] In a first aspect of the present application, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a transistor portion and a diode portion, an injection inhibition region that inhibits injection of a second-conductivity-type carrier at an end portion of the diode portion when viewed from the surface of the semiconductor substrate, and a lifetime control region containing a lifetime inhibitor in the diode portion.

[0009] The transistor portion and the diode portion both have a base region of the second-conductivity-type at the surface of the semiconductor substrate, the transistor portion further has an emitter region of the first-conductivity-type at the surface of the semiconductor substrate, and an extraction region of the second-conductivity-type having a higher doping concentration than the base region, and the injection inhibition region can not have the emitter region and the extraction region.

[0010] The lifetime control region can be provided from the diode portion to at least a portion of the injection inhibition region.

[0011] When viewed from the surface of the semiconductor substrate, a width of the lifetime control region in the arrangement direction of the transistor portion and the diode portion in the injection inhibition region can be 20 μm or more and 1500 μm or less.

[0012] When viewed from the surface of the semiconductor substrate, a width of the injection inhibition region in the arrangement direction of the transistor portion and the diode portion can be 20 μm or more and 900 μm or less.

[0013] When viewed from above, the injection suppression region may also be disposed between the end of the diode portion in the extending direction and the outer periphery of the active region.

[0014] When viewed from above the semiconductor substrate, the area of ​​the diode section can be more than 10% of the combined area of ​​the diode section and the injection suppression region.

[0015] When viewed from above the semiconductor substrate, the total area of ​​the diode section can be more than 1.4% and less than 22% of the area of ​​the semiconductor device.

[0016] The doping concentration of the base region in the implantation suppression region can be lower than or equal to the doping concentration of the base region in the diode section.

[0017] The doping concentration of the base region in the implantation suppression region can be 1E+16cm. -3 Above and 5E+19cm -3 the following.

[0018] The doping concentration of the base region of the diode can be 1E+16cm. -3 Above and 1E+18cm -3 the following.

[0019] The doping concentration in the extracted region can be 5E+18cm. -3 Above and 5E+20cm -3 the following.

[0020] Both the transistor section and the diode section have a base region of a second conductivity type on the surface of the semiconductor substrate. The transistor section and the implantation suppression region also have an emitter region of a first conductivity type and an extract region of a second conductivity type with a doping concentration higher than that of the base region on the surface of the semiconductor substrate. The ratio of the extract region in the implantation suppression region can be lower than the ratio of the extract region in the transistor section.

[0021] The end of the lifetime control region on the injection suppression region side can be located at a distance of more than 1 μm and less than 100 μm from the end of the injection suppression region side of the diode section into the diode section.

[0022] The transistor section and the injection suppression region have multiple mesa sections. The multiple mesa sections extend along the extension direction between multiple trench sections that extend along the extension direction of the transistor section and the diode section and are arranged along the arrangement direction of the transistor section and the diode section. In the mesa section of the injection suppression region, either the emitter region or the extraction region can be configured to be adjacent to the emitter region disposed on the mesa section adjacent to the transistor section side.

[0023] The emission region of the injection suppression region can be adjacent to the extraction region in the extension direction.

[0024] The mesa adjacent to the diode section in the injection suppression region may not have an emitter region configured.

[0025] When viewed from above, the length of the extracted region in the extending direction of the transistor and diode sections can be 0.5 μm or more.

[0026] When viewed from above, the length of the extracted region can be 0.3 μm or more in the arrangement direction of the transistor and diode sections.

[0027] In the implantation suppression region, a base region may be provided in the portion of the semiconductor substrate that is not configured with an emitter region and an extractor region when viewed from above.

[0028] The semiconductor substrate also has an accumulation region of the first conductivity type inside.

[0029] It should be noted that the above description of the invention does not list all the essential features of the invention. Furthermore, sub-combinations of these feature groups can also constitute an invention. Attached Figure Description

[0030] Figure 1A This is a partial top view of the semiconductor device 100 of Embodiment 1 of this invention.

[0031] Figure 1B It means Figure 1A The diagram of section a-a' in the figure.

[0032] Figure 2A This is a diagram showing an example of the front view of the comparative example semiconductor device 1100.

[0033] Figure 2B It means Figure 2A The diagram of section a-a' in the figure.

[0034] Figure 3A This is a top view of the semiconductor device 100 of Embodiment 1 of this invention.

[0035] Figure 3B yes Figure 3A A magnified view of part A.

[0036] Figure 3C yes Figure 3A A magnified view of part A.

[0037] Figure 4 This is a partial cross-sectional view of the semiconductor device 200 of Embodiment 2 of this invention.

[0038] Figure 5A This is a partial top view of the semiconductor device 300 of Embodiment 3 of this invention.

[0039] Figure 5B yes Figure 5A A magnified view of part B.

[0040] Figure 5C It means Figure 5A A diagram of the b-b' section.

[0041] Figure 5D This is a partially enlarged top view of the semiconductor device 300.

[0042] Figure 6A This is a partial top view of the semiconductor device 400 of Embodiment 4 of this implementation.

[0043] Figure 6B It means Figure 6A A diagram of the a-a' section.

[0044] Symbol Explanation

[0045] 10…Substrate, 11…Well region, 12…Emitter region, 14…Base region, 15…Ejection region, 16…Accumulation region, 17…Plug region, 18…Drift region, 20…Buffer zone, 21…Front side, 22…Collector region, 23…Back side, 24…Collector, 25…Connection portion, 29…Linear portion, 30…Dummy trench portion, 31…Front end portion, 32…Dummy insulating film, 34…Dummy conductive portion, 38…Interlayer insulating film, 39…Linear portion, 40…Gate trench portion, 41…Front end portion, 42…Gate insulating film, 44…Gate conductive portion, 48…Gate channel, 49…Contact hole, 50…Gate metal Layer, 52…Emitter, 54…Contact Hole, 56…Contact Hole, 58…Contact Hole, 60…Gateway, 60a…First Gateway, 60b…Second Gateway, 60c…Third Gateway, 60d…Fourth Gateway, 61…Gateway, 70…Transistor Section, 80…Diode Section, 82…Cathode Region, 85…Lifetime Control Region, 90…Implement Suppression Region, 94…Base Region, 100…Semiconductor Device, 102…Edge, 160…Active Region, 190…Edge Termination Structure Section, 200…Semiconductor Device, 300…Semiconductor Device, 400…Semiconductor Device, 1100…Semiconductor Device. Detailed Implementation

[0046] The present invention will now be described through embodiments thereof, but these embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are essential to the technical solution of the invention.

[0047] In this specification, one side parallel to the depth direction of the semiconductor substrate is referred to as "upper" and the other side as "lower". One of the two main surfaces of the substrate, layer, or other component is referred to as the front surface and the other as the back surface. The directions "upper" and "lower" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0048] In this specification, orthogonal coordinate axes of X, Y, and Z are sometimes used to illustrate technical matters. Orthogonal coordinate axes merely determine the relative positions of constituent elements and do not limit specific directions. For example, the Z-axis does not necessarily represent the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions. When a direction is referred to as the Z-axis without specifying positive or negative, it refers to a direction parallel to both the +Z-axis and the Z-axis.

[0049] In this specification, orthogonal axes parallel to the front and back surfaces of the semiconductor substrate are designated as the X-axis and Y-axis. An axis perpendicular to the front and back surfaces of the semiconductor substrate is designated as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Additionally, in this specification, the direction including the X-axis and Y-axis and parallel to the front and back surfaces of the semiconductor substrate is sometimes referred to as the horizontal direction.

[0050] In this specification, the terms "same" or "equal" may also include cases with errors caused by manufacturing deviations, etc. Such errors are, for example, within 10%.

[0051] In this specification, the conductivity type of a doped region containing impurities is described as P-type or N-type. In this specification, impurities sometimes specifically refer to either an N-type donor or a P-type acceptor, and are sometimes referred to as dopant. In this specification, doping refers to the introduction of donors or acceptors into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity type or a P-type conductivity type.

[0052] In this specification, doping concentration refers to the concentration of donors or acceptors at thermal equilibrium. In this specification, net doping concentration refers to the concentration obtained by adding the concentrations, including charge polarity, together with the donor concentration set to the concentration of positive ions and the acceptor concentration set to the concentration of negative ions. As an example, if the donor concentration is set to N... D Set the acceptor concentration to N A Then the net doping concentration at any position is N. D -N A .

[0053] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of receiving electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) in semiconductors, function as electron donors.

[0054] In this specification, when referred to as P+ or N+, it means that the doping concentration is higher than that of P- or N-type doping concentrations; when referred to as P- or N-, it means that the doping concentration is lower than that of P- or N-type doping concentrations. Furthermore, when referred to as P++ or N++, it means that the doping concentration is higher than that of P+ or N+ type doping concentrations.

[0055] In this specification, chemical concentration refers to the concentration of impurities measured independently of the electroactivated state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration mentioned above can be determined by voltage-capacitance measurement (CV method). Alternatively, the carrier concentration measured by extended resistance measurement (SR method) can be used as the net doping concentration. The carrier concentration measured by CV or SR methods can be set to the value under thermal equilibrium conditions. Furthermore, in the N-type region, since the donor concentration is significantly greater than the acceptor concentration, the carrier concentration in this region can also be set as the donor concentration. Similarly, in the P-type region, the carrier concentration in this region can also be set as the acceptor concentration.

[0056] Furthermore, when the concentration distribution of donor, acceptor, or net dopant has a peak, the peak value can be set as the concentration of donor, acceptor, or net dopant in that region. When the concentration of donor, acceptor, or net dopant is approximately uniform, the average concentration of donor, acceptor, or net dopant in that region can be set as the concentration of donor, acceptor, or net dopant.

[0057] The carrier concentration measured by the SR method can be lower than the donor or acceptor concentration. During the measurement of extended resistance, within the current flow range, the carrier mobility of the semiconductor substrate is sometimes lower than that in the crystalline state. This decrease in carrier mobility is caused by the dispersion of carriers due to crystal structure disorder caused by lattice defects, etc.

[0058] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method can be lower than the chemical concentration of the element representing the donor or acceptor. For example, in silicon semiconductors, the donor concentration of phosphorus or arsenic (which acts as a donor) or the acceptor concentration of boron (which acts as an acceptor) is approximately 99% of their chemical concentration. On the other hand, in silicon semiconductors, the donor concentration of hydrogen (which acts as a donor) is on the order of 0.1% to 10% of the chemical concentration of hydrogen.

[0059] [Example 1]

[0060] Figure 1AThis is a partial top view of the semiconductor device 100 according to Embodiment 1 of this invention. The semiconductor device 100 includes a semiconductor substrate having a transistor section 70 including transistor elements such as IGBTs and a diode section 80 including diode elements such as freewheeling diodes (FWDs).

[0061] It should be noted that, in this specification, "top view" refers to viewing from the front side of the semiconductor substrate. In this example, the arrangement direction of the transistor section 70 and the diode section 80 when viewed from above is called the X-axis, the direction perpendicular to the X-axis on the front side of the semiconductor substrate is called the Y-axis, and the direction perpendicular to the front side of the semiconductor substrate is called the Z-axis.

[0062] The transistor section 70 and the diode section 80 may each have a length in the extending direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extending directions of the transistor section 70 and the diode section 80 may be the same as the length directions of the trench sections described later.

[0063] The diode section 80 has an N+ type cathode region in the area that contacts the back side of the semiconductor substrate. In this specification, the area where the cathode region is provided is referred to as the diode section 80. That is, the diode section 80 is the area that overlaps with the cathode region when viewed from above. On the other hand, the transistor section 70 has a P+ type collector region in the area that contacts the back side of the semiconductor substrate.

[0064] The semiconductor device 100 in this example includes a gate trench 40, a dummy trench 30, a well region 11, an emitter region 12, a base region 14, and an extract region 15 disposed inside the front side of a semiconductor substrate. The gate trench 40 and the dummy trench 30 are examples of trench portions.

[0065] Furthermore, the semiconductor device 100 in this example includes a gate metal layer 50 and an emitter 52 disposed on the upper surface of the front side of a semiconductor substrate. The gate metal layer 50 and the emitter 52 are disposed separately from each other.

[0066] An interlayer insulating film is disposed between the emitter 52 and the gate metal layer 50 and the front side of the semiconductor substrate, but... Figure 1A (The text is omitted.) In this example, contact holes 49, 54, 56, and 58 are formed through the interlayer insulating film. Figure 1A In the middle, the shading of the diagonal lines marked on each contact hole is shown.

[0067] The emitter 52 is disposed above the gate trench 40, the dummy trench 30, the well region 11, the emitter region 12, the base region 14, and the extraction region 15. The emitter 52 contacts the emitter region 12, the base region 14, and the extraction region 15 on the front side of the semiconductor substrate through the contact hole 54.

[0068] Furthermore, the emitter 52 is connected to the dummy conductive portion within the dummy trench portion 30 via contact hole 56 or contact hole 58. A connection portion 25, formed of a conductive material such as polycrystalline silicon doped with impurities, can be provided between the emitter 52 and the dummy conductive portion. The connection portions 25 are respectively disposed on the front side of the semiconductor substrate through an insulating film.

[0069] The gate metal layer 50 contacts the gate flow channel 48 through the contact hole 49. The gate flow channel 48 may be formed of polysilicon or the like, which is doped with impurities. The gate flow channel 48 is connected to the gate conductive portion within the gate trench portion 40 on the front side of the semiconductor substrate. The gate flow channel 48 is not electrically connected to the dummy conductive portion within the dummy trench portion 30 or to the emitter 52.

[0070] The gate channel 48 and the emitter 52 can be electrically separated by insulating materials such as interlayer insulating films and oxide films. In this example, the gate channel 48 is disposed from below the contact hole 49 to the front end of the gate trench portion 40. At the front end of the gate trench portion 40, the gate conductive portion is exposed on the front side of the semiconductor substrate and contacts the gate channel 48.

[0071] The emitter 52 and the gate metal layer 50 are formed of a conductive material containing metal. For example, they are formed of polysilicon, aluminum, or an aluminum-silicon alloy. Each electrode may have a barrier metal formed of titanium and / or titanium compounds in a layer beneath the region formed of aluminum or the like.

[0072] Each electrode may also have a plug made of tungsten or the like within the contact hole. The plug may have a blocking metal on the side that contacts the semiconductor substrate, and tungsten may be embedded in the plug in a manner that contacts the blocking metal, and formed on the tungsten by aluminum or the like.

[0073] It should be noted that the plug is disposed in a contact hole that contacts the extraction region 15 or the base region 14. Furthermore, a P++ type plug region 17 with a higher doping concentration than the extraction region 15 is formed below the contact hole of the plug. This improves the contact resistance between the barrier metal and the extraction region 15. Additionally, the depth of the plug region 17 is approximately 0.1 μm or less, having a region that is less than 10% smaller than the depth of the extraction region 15.

[0074] The plug region 17 has the following characteristics. During the operation of the transistor section 70, the latch-up resistance is improved by increasing the contact resistance. On the other hand, during the operation of the diode section 80, although the contact resistance between the blocking metal and the base region 14 is high and the conduction loss and switching loss increase when there is no plug region, the increase in conduction loss and switching loss can be suppressed by providing the plug region 17.

[0075] The well region 11 is disposed overlapping the gate channel 48. The well region 11 is also disposed with a predetermined width within a range that does not overlap with the gate channel 48. In this example, the well region 11 is disposed such that it is separated from the end of the contact hole 54 in the Y-axis direction towards the gate channel 48 side. The well region 11 is a region of the second conductivity type with a higher doping concentration than the base region 14.

[0076] In this example, the base region 14 is P-type and the well region 11 is P+ type. In addition, the well region 11 is formed from the front side of the semiconductor substrate to a depth deeper than the lower end of the base region 14.

[0077] The transistor section 70 and the diode section 80 each have a plurality of trench sections arranged along the arrangement direction. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately arranged along the arrangement direction. In this example, the diode section 80 has a plurality of dummy trench sections 30 arranged along the arrangement direction. In this example, the diode section 80 does not have a gate trench section 40.

[0078] In this example, the gate trench portion 40 may have two straight portions 39 (the trench portion that is straight along the extension direction) extending in an extension direction perpendicular to the arrangement direction and a front end portion 41 connecting the two straight portions 39.

[0079] At least a portion of the front end portion 41 can be curved when viewed from above. The ends of the two straight portions 39 in the Y-axis direction are connected to each other via the front end portion 41 to the gate channel 48, thereby functioning as a gate electrode to the gate trench portion 40. On the other hand, by making the front end portion 41 curved, the electric field concentration at the end can be mitigated compared to ending with straight portions 39.

[0080] In the transistor section 70, dummy trench sections 30 are provided between each straight section 39 of the gate trench section 40. One dummy trench section 30 may be provided between each straight section 39, or multiple dummy trench sections 30 may be provided.

[0081] Furthermore, between each straight section 39, either a dummy trench portion 30 can be omitted, or a gate trench portion 40 can be provided. With this configuration, the electron current from the emitter region 12 can be increased, thereby reducing the on-state voltage.

[0082] The dummy trench portion 30 may have a straight shape extending in the extension direction, or it may have a straight portion 29 and a front end portion 31, similar to the gate trench portion 40. Figure 1A The semiconductor device 100 shown includes both a dummy trench portion 30 with a straight shape and a front end portion 31.

[0083] The diffusion depth of the well region 11 can be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are located within the well region 11 when viewed from above. That is, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This mitigates the electric field concentration at the bottom of each trench portion.

[0084] A mesa is provided between each trench portion in the alignment direction. A mesa refers to the area within the semiconductor substrate that is sandwiched between the trench portions. As an example, the depth of the mesa extends from the front side of the semiconductor substrate to the lower end of the trench portion.

[0085] In this example, the mesa is sandwiched between adjacent trenches in the X-axis direction and is disposed on the front side of the semiconductor substrate, extending along the trenches in the extension direction (Y-axis direction). For example, in Figure 1B As will be described later, in this example, a mesa 60 is provided in the transistor section 70, and a mesa 61 is provided in the diode section 80. In this specification, when referred to simply as mesa, it refers to mesa 60 and mesa 61 respectively.

[0086] A base region 14 is provided on each facet of the transistor section 70. In each facet of the transistor section 70, at least one of a first conductivity type emitter region 12 and a second conductivity type extractor region 15 may be provided in the area sandwiched between the base regions 14 when viewed from above. In this example, the emitter region 12 is N+ type, and the extractor region 15 is P+ type. The emitter region 12 and the extractor region 15 may be disposed in the depth direction between the base region 14 and the front surface of the semiconductor substrate.

[0087] The mesa portion of the transistor section 70 has an emitter region 12 exposed on the front side of the semiconductor substrate. The emitter region 12 is disposed in contact with the gate trench portion 40. An extractor region 15 exposed on the front side of the semiconductor substrate is disposed on the mesa portion in contact with the gate trench portion 40.

[0088] The extraction area 15 and the emission area 12 on the platform are respectively provided from one groove portion to another in the X-axis direction. As an example, the extraction area 15 and the emission area 12 on the platform are alternately arranged along the extension direction of the groove portion (Y-axis direction).

[0089] In another example, the extraction area 15 and the emission area 12 of the platform can be set in a stripe shape along the extension direction (Y-axis direction) of the groove. For example, the emission area 12 is set in the area that contacts the groove, and the extraction area 15 is set in the area that is held by the emission area 12.

[0090] However, in the transistor section 70, the emitter region 12 is not provided on the mesa adjacent to the injection suppression region 90 described later, but is provided on the front exposed part of the semiconductor substrate as the extractor region 15. The extractor region 15 can be provided in contact with the dummy trench section 30 in the area held by the base region 14 when viewed from above.

[0091] The emitter region 12 is not provided on the mesa of the diode section 80. A base region 14 may be provided on the upper surface of the mesa of the diode section 80. The base region 14 may be disposed on the entire mesa of the diode section 80.

[0092] A contact hole 54 is provided above each stage surface. The contact hole 54 is disposed in the region sandwiched by the base region 14 in its extending direction (Y-axis direction). In this example, the contact hole 54 is disposed above each region of the extraction region 15, the base region 14, and the emission region 12. The contact hole 54 may be disposed at the center in the arrangement direction (X-axis direction) of the stage surface.

[0093] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the back side of the semiconductor substrate. On the back side of the semiconductor substrate, in a region where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. Figure 1A In the diagram, the boundary between the cathode region 82 and the collector region 22 is represented by a dashed line.

[0094] The cathode region 82 is positioned away from the well region 11 in the Y-axis direction. Therefore, by ensuring a sufficient distance between the cathode region 82 and the P-type region (well region 11) with a relatively high doping concentration and deep formation, hole injection from the well region 11 can be suppressed, thus reducing reverse recovery loss. In this example, the end of the cathode region 82 in the Y-axis direction is positioned further away from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be positioned between the well region 11 and the contact hole 54.

[0095] When viewed from above the semiconductor substrate, the transistor section 70 has an injection suppression region 90 at the end on the diode section 80 side to suppress the injection of second conductivity type charge carriers.

[0096] In the implantation suppression region 90, a P+ type collector region 22 is provided on the back side of the semiconductor substrate. That is to say, the implantation suppression region 90 is part of the transistor section 70, but in this specification, the transistor section 70 and the implantation suppression region 90 will be described separately.

[0097] Unlike the transistor section 70, the upper surface of the injection suppression region 90 does not have an emitter region 12 and an extraction region 15, but instead has a base region 14. Furthermore, unlike the transistor section 70, the injection suppression region 90 does not have a gate trench section 40, but instead has a dummy trench section 30. It should be noted that in... Figure 1AIn this diagram, although the injection suppression region 90 is shown as two mesa-shaped surfaces adjacent to the dummy trench portion 30, it is not limited thereto. The injection suppression region 90 may have more than two mesa-shaped surfaces.

[0098] When the diode section 80 is turned on, an electron current flows from the cathode region 82 to the base region 14, which operates as the anode layer. If the electron current reaches the base region 14, conductivity modulation occurs, and a hole current flows from the anode layer. However, since the base region 14 is also provided in the transistor section 70, an electron current diffuses from the cathode region 82 to the base region 14 of the transistor section 70 and the injection suppression region 90.

[0099] The electron current diffused toward the transistor section 70 promotes hole injection from the base region 14 and the extraction region 15 of the transistor section 70. The boron concentration in the extraction region 15 is two orders of magnitude higher than that in the base region 14, thus increasing the hole density of the substrate 10. As a result, time is spent until the holes disappear when the diode section 80 is turned off, thus increasing the reverse recovery peak current and the reverse recovery loss.

[0100] In this example, the semiconductor device 100 provides an injection suppression region 90 on the diode section 80 side of the transistor section 70, thereby increasing the distance between the cathode region 82 and the base region 14 and extraction region 15 of the transistor section 70. As a result, when the diode section 80 is turned on, the proportion of the extraction region 15 of the transistor section 70 within the diffusion range of the electron current decreases, thus suppressing hole injection.

[0101] Figure 1B It means Figure 1A The diagram shows the a-a' section. The a-a' section is the XZ plane passing through the emitter region 12, the base region 14, the gate trench portion 40, and the dummy trench portion 30. In this example, the semiconductor device 100 has a substrate 10, an interlayer insulating film 38, an emitter 52, and a collector 24 in the a-a' section.

[0102] An interlayer insulating film 38 is disposed on the front side 21 of the substrate 10. The interlayer insulating film 38 is an insulating film such as silicate glass with added impurities such as boron or phosphorus. The interlayer insulating film 38 may be in contact with the front side 21, or an oxide film or other film may be disposed between the interlayer insulating film 38 and the front side 21. The interlayer insulating film 38 has... Figure 1A Contact hole 54 as described in the text.

[0103] An emitter 52 is disposed on the front side 21 of the substrate 10 and the upper surface of the interlayer insulating film 38. The emitter 52 is electrically contacted with the front side 21 through a contact hole 54 in the interlayer insulating film 38. A tungsten (W) or similar contact plug may also be disposed inside the contact hole 54. A collector 24 is disposed on the back side 23 of the substrate 10. The emitter 52 and the collector 24 are formed of a material containing metal.

[0104] The substrate 10 can be a silicon substrate, a silicon carbide substrate, or a gallium nitride or other nitride semiconductor substrate. In this example, the substrate 10 is a silicon substrate.

[0105] The substrate 10 has a drift region 18 of a first conductivity type. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining in the substrate 10 where no other doped regions are formed.

[0106] Above the drift region 18, one or more accumulation regions 16 can be provided along the Z-axis. The accumulation region 16 is a region formed by accumulating the same dopant as the drift region 18 at a higher concentration than the drift region 18. The doping concentration of the accumulation region 16 is higher than that of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be improved, and the turn-on voltage can be reduced.

[0107] In the transistor section 70, an emitter region 12 is disposed above the base region 14 in contact with the front surface 21. The emitter region 12 is disposed in contact with the gate trench section 40. The doping concentration of the emitter region 12 is higher than that of the drift region 18. As an example, the dopant of the emitter region 12 is arsenic (As), phosphorus (P), antimony (Sb), etc.

[0108] The arrangement direction of the injection inhibition region 90 ( Figure 1B The width A in the X-axis direction is 20 μm or more and 900 μm or less. In addition, the following formula (1) holds between the width A of the implantation suppression region 90 and the substrate thickness W of the semiconductor device 100.

[0109] A≤6W…[Equation(1)]

[0110] It should be noted that the substrate thickness W represents the thickness from the upper surface of the base region 14 of the diode section 80 to the lower surface of the cathode region 82. By increasing the substrate thickness W, the electron diffusion region of the cathode region 82 of the diode section 80 is increased, and therefore, according to equation (1), the reverse recovery and conduction losses are reduced.

[0111] Furthermore, in the transistor section 70, an extraction region 15 is provided on the mesa 60 on the side of the injection suppression region 90, above the base region 14 and in contact with the front surface 21. The extraction region 15 can be provided in contact with the dummy trench section 30.

[0112] A base region 14 exposed on the front side 21 is provided in the diode section 80 and the injection suppression region 90. The base region 14 of the diode section 80 operates as the anode.

[0113] A buffer 20 of a first conductivity type can be disposed below the drift region 18. In this example, the buffer 20 is N-type. The doping concentration of the buffer 20 is higher than that of the drift region 18. The buffer 20 can function as a field cutoff layer to prevent the depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0114] In the transistor section 70 and the injection suppression region 90, a collector region 22 is provided below the buffer zone 20. The collector region 22 of the injection suppression region 90 can be provided in connection with the cathode region 82 on the back side 23.

[0115] In the diode section 80, a cathode region 82 is provided below the buffer zone 20. The cathode region 82 can be provided at the same depth as the collector region 22 of the transistor section 70 and the injection suppression region 90. The diode section 80 can function as a freewheeling diode (FWD) that allows freewheeling current to flow in the reverse direction when the transistor section 70 is turned off.

[0116] A gate trench 40 and a dummy trench 30 are provided on the substrate 10. The gate trench 40 and the dummy trench 30 are arranged to extend from the front side 21 through the base region 14 and the accumulation region 16 to the drift region 18. The trenches extending through the doped regions are not limited to being formed in the order of forming the trenches after forming the doped regions. The case where the doped regions are formed between the trenches after the trenches are formed is also included in the case where the trenches extend through the doped regions.

[0117] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 disposed on the front side 21. The gate insulating film 42 is disposed covering the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding a semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is disposed inside the gate trench at a position closer to the inner side than the gate insulating film 42. The upper surface of the gate conductive portion 44 can be located in the same XY plane as the front side 21. The gate insulating film 42 insulates the gate conductive portion 44 from the substrate 10. The gate conductive portion 44 is formed of a semiconductor such as polysilicon doped with impurities.

[0118] The gate conductive portion 44 may be configured to be longer than the base region 14 in the depth direction. The gate trench portion 40 is covered by an interlayer insulating film 38 on the front side 21. If a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in the base region 14 that contacts the gate trench.

[0119] The dummy trench portion 30 can have the same structure as the gate trench portion 40 in the XZ cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 disposed on the front side 21. The dummy insulating film 32 is disposed to cover the inner wall of the dummy trench. The dummy insulating film 32 can be formed by oxidizing or nitriding a semiconductor on the inner wall of the dummy trench. The dummy conductive portion 34 is disposed inside the dummy trench at a position further inward than the dummy insulating film 32. The upper surface of the dummy conductive portion 34 can be located in the same XY plane as the front side 21. The dummy insulating film 32 insulates the dummy conductive portion 34 from the substrate 10. The dummy conductive portion 34 can be formed of the same material as the gate conductive portion 44.

[0120] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the front side 21. It should be noted that the bottom of the dummy trench portion 30 and the gate trench portion 40 can be a downwardly convex curved surface (curved in cross-section).

[0121] In the diode section 80, a lifetime control region 85, which includes a lifetime inhibitor, is locally disposed in the drift region 18. The lifetime control region 85 promotes the recombination of holes generated in the base region 14 and electrons injected from the cathode region 82 when the diode section 80 is turned off, and suppresses the peak current during reverse recovery.

[0122] The lifetime control region 85 can be formed by irradiating protons or helium from the front side 21 or the back side 23. As an example, the area where the lifetime control region 85 is not formed is masked using a metal or photoresist mask, and the transistor section 70 and the diode section 80 are irradiated. Protons or helium are not irradiated on the masked area.

[0123] exist Figure 1B In this diagram, the peak position of the lifetime inhibitor concentration distribution along the Z-axis is indicated by the symbol "×". In this example, the peak position of the lifetime control region 85 along the Z-axis can be equal to the position along the Z-axis of the lower surface of the well region 11, or it can be set at a position lower than the position along the Z-axis of the lower surface of the well region 11. Alternatively, the lifetime control region 85 can also be formed with multiple peaks of the lifetime inhibitor concentration distribution along the Z-axis.

[0124] As an example, lifetime inhibitors can form crystal defects inside a semiconductor substrate 10 by injecting helium or protons that can be injected at a predetermined depth.

[0125] Typically, a lifetime control region is provided throughout the diode section 80 and the transistor section 70. When the diode section is turned on, hole current is generated not only from the base region 14 of the diode section towards the cathode region 82, but also from the base region 14 of the transistor section towards the cathode region 82. This is because, in order to reduce reverse recovery losses during turn-off, it is necessary to provide a lifetime control region 85 to promote carrier dissipation.

[0126] However, when such a lifetime control region 85 is formed, the trench portions of the transistor section 70 and the diode section 80 are irradiated with helium or protons, which damages the trench oxide film and causes changes in the interface energy level.

[0127] Therefore, if a gate voltage is applied, tunneling current flows more easily through the irradiated trench oxide film compared to the unirradiated trench oxide film. Consequently, in the region where the emitter region 12 is present in the lifetime control region 85, the voltage is lower compared to the region of the transistor section 70 where the lifetime control region 85 is not provided.

[0128] Furthermore, in the region where the lifetime control region 85 is located, the threshold voltage is prone to inconsistency due to the uneven change in the interfacial energy levels of the trench oxide film. This unevenness in threshold voltage between layers of the mesa, or between mesa layers in the case of parallel connections, may lead to a decrease in cutoff withstand capability. On the other hand, in the region without the emitter region 12, even if the interfacial energy levels of the trench oxide film change, no electron current flows, so the threshold voltage does not decrease.

[0129] In this example, the lifetime control region 85 is not formed below the emitter region 12 of the transistor section 70. Therefore, the irradiated helium or protons do not cause a change in the interface energy level of the trench oxide film below the emitter region 12 of the transistor section 70, so the threshold voltage in the lifetime control region 85 becomes the same value as the threshold voltage of the transistor section 70 without the lifetime control region 85.

[0130] By not providing the emitter region 12 in the lifetime control region 85, the threshold voltage in the transistor section 70 will not decrease. On the other hand, because the lifetime control region 85 is not provided in the transistor section 70, a large amount of hole injection occurs from the extraction region 15 of the transistor section 70. During reverse recovery, the extraction of charge carriers takes time, increasing reverse recovery and conduction losses. Therefore, by forming the injection suppression region 90, hole injection from the transistor section 70 can be suppressed when the diode section 80 is turned on, thereby reducing reverse recovery and conduction losses.

[0131] In addition, the lifespan control region 85 in this example is... Figure 1BAs shown, at least a portion of the diode section 80 is continuously disposed in the X-axis direction to the injection suppression region 90. The end K on the negative X-axis side of the lifetime control region 85 may be located in a position that is recessed towards the positive X-axis side from the end on the transistor section 70 side of the injection suppression region 90, i.e., within the injection suppression region 90.

[0132] In addition, in the injection suppression region 90, the interval between the end K of the lifetime control region 85 in the arrangement direction (X-axis direction) and the boundary portion L can be more than 1 μm, and the boundary portion L is the boundary between the injection suppression region 90 and the transistor portion 70.

[0133] The lifetime control region 85 is formed by irradiating protons or helium through, for example, the front side 21 through a 30-80 μm thick resist mask. Therefore, if the lifetime control region 85 is not slightly recessed into the injection suppression region 90, the lifetime control region 85 will form in the transistor section 70 when the tilt angle of the thick resist is inconsistent, and the threshold voltage is prone to decrease or become inconsistent.

[0134] Therefore, by setting the lifetime control region 85 to a position slightly recessed into the injection suppression region 90, the lifetime control region 85 will not be formed in the transistor section 70 even if the tilt angle of the resist mask is inconsistent, thereby preventing the threshold voltage from decreasing or becoming inconsistent.

[0135] In addition, in this example, the injection suppression region 90 does not have an extraction region 15 and is separated from the cathode region 82, so the hole current generated in the extraction region 15 when the diode section 80 is turned on can be suppressed.

[0136] Furthermore, in this example, the lifetime control region 85 has a longer distance between the end K and the cathode region 82 compared to the case where the lifetime control region 85 is only provided in the diode section 80. Therefore, by providing the lifetime control region 85, the recombination of the hole current generated in the base region 14 of the injection suppression region 90 and the electrons flowing in from the cathode region 82 is further promoted. Therefore, compared to the case where the lifetime control region 85 is not provided, the peak current of the reverse recovery of the diode section 80 can be suppressed.

[0137] Based on the above, regarding the lifetime control region 85 in this example, compared with the case where the lifetime control region 85 is also provided in the transistor section 70, there will be no decrease or inconsistency in the threshold voltage of the transistor section 70, and when the diode section 80 is turned on, hole injection from the transistor section 70 can be suppressed, thus reducing reverse recovery and conduction losses.

[0138] Next, the effect of the semiconductor device 100 will be explained by comparison with the semiconductor device 1100 of the comparative example.

[0139] Figure 2AThis is an example diagram showing the front of a comparative example semiconductor device 1100. Figure 2B It means Figure 2A A view of section a-a' in the figure. Here, elements common to semiconductor device 100 are labeled with the same reference numerals, and descriptions are omitted.

[0140] The semiconductor device 1100 includes a transistor section 70 and a diode section 80. The mesa section 60 of the transistor section 70 has an emitter region 12 and an extractor region 15 exposed on the front side 21 of the substrate 10. However, in the transistor section 70, the emitter region 12 is not provided on the mesa section 60 adjacent to the diode section 80, but the extractor region 15 is provided instead.

[0141] In the semiconductor device 1100, the cathode region 82 is disposed adjacent to the transistor section 70. Therefore, in the semiconductor device 1100, the distance between the cathode region 82 of the diode section 80 and the base region 14 and the extraction region 15 of the transistor section 70 is closer than the distance between the cathode region 82 of the diode section 80 and the base region 14 and the extraction region 15 of the transistor section 70 in the semiconductor device 1100.

[0142] Therefore, when the diode section 80 is turned on, the electron current diffused from the cathode region 82 flows into the base region 14 and the extraction region 15 of the transistor section 70, promoting hole injection.

[0143] Furthermore, in the transistor section 70 of the semiconductor device 1100, the extraction region 15, with a doping concentration higher than that of the base region 14, is disposed adjacent to the diode section 80. Therefore, in the semiconductor device 1100, more holes are injected into the substrate 10 from the extraction region 15.

[0144] If the hole density increases, the time spent after the diode section 80 is turned off until the holes disappear will be longer. Therefore, in the semiconductor device 1100, the reverse recovery current, reverse recovery loss, and conduction loss are greater than in the semiconductor device 100.

[0145] In contrast, the semiconductor device 100 provides an injection suppression region 90 without the extraction region 15 on the diode section 80 side, thus increasing the distance between the cathode region 82 and the transistor section 70, thereby suppressing hole injection. This reduces reverse recovery current, reverse recovery loss, and conduction loss.

[0146] Furthermore, semiconductor device 1100 and semiconductor device 100 share the characteristic of having a lifetime control region 85 in the drift region 18. However, semiconductor device 1100 differs from semiconductor device 100 in that semiconductor device 1100 does not have an injection suppression region 90, and the lifetime control region 85 extends from the diode section 80 to at least a portion of the transistor section 70.

[0147] When helium or protons are irradiated from the front side 21, for example, to form the lifetime control region 85, the irradiated helium or protons pass through the gate trench portion 40 of the transistor portion 70 where the emitter region 12 is located. As a result, the interface energy level of the trench oxide film changes, and the gate trench portion 40 conducts at a lower voltage compared to the unirradiated gate trench portion 40, thus reducing the threshold voltage of the transistor portion 70.

[0148] On the other hand, when helium or protons are irradiated from the back side 23, the interface energy level of the trench oxide film does not change because a lifetime control region is provided below the trench, bypassing the trench oxide film. However, the distance from the back side 23 to the depth of the lifetime control region 85 is relatively long, thus requiring high energy.

[0149] To control the position of the lifetime control region 85 in the X-axis direction, there is a method of using a metal mask that can withstand high energy to cover the entire wafer, but there is a problem of large positional deviation in the X-axis direction.

[0150] Therefore, when irradiated from the front side 21, the distance to the depth of the lifetime control region 85 is shorter, allowing for irradiation at lower energy levels. Thus, by utilizing a resist mask or similar material, the position along the X-axis can be controlled. However, as mentioned above, irradiation from the front side 21 affects the interface energy levels of the trench oxide film, resulting in a decrease in the threshold voltage.

[0151] In contrast, the semiconductor device 100 does not have a lifetime control region 85 in the transistor section 70. Therefore, since there is no lifetime control region 85 in the emitter region 12 of the transistor section 70, the threshold voltage does not decrease. Furthermore, by providing a lifetime control region 85 in at least a portion of the injection suppression region 90, hole injection from the extraction region 15 of the transistor section 70 when the diode section 80 is turned on is suppressed without causing a decrease in the threshold voltage.

[0152] Figure 3A This is a top view of the semiconductor device 100 according to Embodiment 1 of this invention. Figure 3A The diagram shows the positions of each component projected onto the front surface of the substrate 10. It should be noted that... Figure 3A Only a portion of the components of the semiconductor device 100 are shown, and some components are omitted.

[0153] The substrate 10 of the semiconductor device 100 has two sets of end edges 102 that are opposite each other when viewed from above. Figure 3A In the diagram, the X-axis and Y-axis are parallel to one end edge 102.

[0154] An active region 160 is provided on the substrate 10. The active region 160 is the region from which the main current flows along the depth direction from the emitter region 12 of the substrate 10 when the semiconductor device 100 is operating. Alternatively, the region surrounded by the gate channel 48 when viewed from above may also be considered the active region 160. It should be noted that an emitter is provided above the active region 160, but... Figure 3A Omitted in .

[0155] At least one of a transistor portion 70 and a diode portion 80 is provided in the active region 160. In this example, the transistor portion 70 and the diode portion 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the front side of the substrate 10. In other examples, only one of the transistor portion 70 and the diode portion 80 may be provided in the active region 160.

[0156] The semiconductor device 100 may have more than one pad on top of the substrate 10. As an example, Figure 3A The semiconductor device 100 shown has a gate pad G in the active region 160. When the semiconductor device 100 is mounted, the gate pad G can be connected to an external circuit via wiring such as wires.

[0157] A gate potential is applied to the gate pad G. The gate pad G is electrically connected to the gate channel 48, which surrounds the active region 160 and is electrically connected to the gate conductive portion of the gate trench portion 40 of the active region 160.

[0158] The gate channel 48 is disposed between the active region 160 and the edge termination structure 190 of the substrate 10 when viewed from above. The gate channel 48 may be formed of a metal with aluminum as the main component, such as polysilicon or aluminum-silicon alloy.

[0159] In this example, the semiconductor device 100 has an edge termination structure 190 between the active region 160 and the edge 102. The edge termination structure 190 is disposed between the gate channel 48 and the edge 102. The edge termination structure 190 mitigates the electric field concentration on the front side of the substrate 10.

[0160] The edge termination structure 190 may have multiple guard rings. Each guard ring is a P-type region that contacts the front side of the substrate 10. By providing multiple guard rings, the depletion layer on the upper surface side of the active region 160 can extend outwards, ensuring the withstand voltage of the semiconductor device 100. The edge termination structure 190 may also include at least one of a field plate arranged in an annular shape surrounding the gate flow channel 48 and a surface electric field reduction section.

[0161] Alternatively, the semiconductor device 100 may also include a temperature sensing unit (not shown) that is a PN junction diode formed of polysilicon or the like, and / or a current sensing unit (not shown) that performs the same operation as the transistor unit provided in the active region 160.

[0162] Figure 3B yes Figure 3A A magnified view of part A. Figure 3B Indicates from above (at) Figure 3B An example of an injection suppression region 90 is observed looking downwards (from the positive Z-axis side) to the negative Z-axis side.

[0163] The injection suppression region 90 is also disposed between the extension direction (Y-axis direction) end of the diode section 80 and the outer periphery (gate channel 48) of the active region 160. That is, when viewed from above, both the extension direction end and the alignment direction (X-axis direction) end of the diode section 80 are surrounded by the injection suppression region 90.

[0164] exist Figure 3B In the middle, the area S1 of the diode section 80 and the area S2 of the injection suppression region 90 satisfy the following equation (2).

[0165] S1≥(S1+S2) / 10…[Equation (2)]

[0166] By satisfying [Equation (2)], the smaller the area S1 of the diode section 80 or the larger the total area (S1+S2) of the diode section 80 and the injection suppression region 90, the more effectively hole injection from the transistor section 70 is suppressed, and the lower the reverse recovery and conduction losses. However, reducing the area S1 of the diode section 80 increases the on-state voltage and the thermal resistance of the package. Therefore, to ensure the injection suppression region 90 while reducing the on-state voltage, the area S2 of the substrate 10 is increased.

[0167] On the other hand, if it is desired to increase the total area (S1+S2) of the diode section 80 and the injection suppression region 90, the area of ​​the substrate 10 is also increased by S2. On the other hand, if the impact of inverter losses is small even when the conduction voltage rises, or if the thermal resistance of the package structure is good and the temperature rise of the diode section 80 is good, the area S1 of the diode section 80 can be reduced without increasing the area of ​​the substrate 10. Therefore, the proportion of the area S1 of the diode section 80 can be 10% or more of the total area (S1+S2) of the diode section 80 and the injection suppression region 90.

[0168] If we consider [Equation (2)], the total area of ​​the diode section 80, when viewed from above, can be more than 1.4% and less than 22% of the area of ​​the semiconductor device 100.

[0169] Figure 3C yes Figure 3A A magnified view of part A. Figure 3C A magnified view shows a diode section 80 of the semiconductor device 100 and its surrounding structure. Figure 3C In the diagram, the lifespan control zone 85 is represented by a dashed line. (The remaining text appears to be incomplete and possibly contains errors.)Figure 3C When the lifetime control region 85 is provided from the diode section 80 to a part of the injection suppression region 90, the area S1 of the diode section 80, the area S2 of the injection suppression region 90, and the area S3 of the lifetime control region 85 satisfy the following equation (3).

[0170] (S1+S2)>S3≥S1…[Equation (3)]

[0171] [Example 2]

[0172] Figure 4 This is a partial cross-sectional view of the semiconductor device 200 according to Embodiment 2 of this invention. Here, elements common to the semiconductor device 100 are labeled with the same reference numerals, and descriptions are omitted.

[0173] In the implantation suppression region 90 of the semiconductor device 200, a base region 94 of a second conductivity type is provided instead of the base region 14. The doping concentration of the base region 94 can be 1E+16cm⁻¹. -3 Above and 5E+19cm -3 the following.

[0174] It should be noted that the doping concentration of base region 14 can be 1E+16cm. -3 Above and 1E+18cm -3 The doping concentration of the extraction region 15 can be 5E+18cm. -3 Above and 5E+20cm -3 the following.

[0175] By making the doping concentration of the base region 94 lower than that of the extraction region 15, the effect of suppressing hole injection from the transistor section 70 can be improved. If the concentration of the base region 14 is lower than that of the base region 94, the suppression effect of hole injection can be further improved.

[0176] Furthermore, the processing method for distinguishing the doping concentrations of base region 14 and base region 94 is as follows. When the doping concentration of base region 94 is higher than that of base region 14, both base region 14 and base region 94 are doped, and then a mask is used in base region 14, leaving base region 94 untouched for doping. Conversely, when the doping concentration of base region 94 is lower than that of base region 14, different masks are used to dope base region 14 and base region 94.

[0177] Furthermore, since the doping concentrations of base region 94 and base region 14 are equal, the same mask can be used for processing. Therefore, no additional mask is required, and the cost of the chip can be reduced by improving processability and cutting mask requirements.

[0178] [Example 3]

[0179] Figure 5AThis is a partial top view of the semiconductor device 300 according to Embodiment 3 of this invention. Here, elements common to the semiconductor device 100 are labeled with the same reference numerals, and descriptions are omitted.

[0180] Like semiconductor devices 100 and 200, the implantation suppression region 90 of semiconductor device 300 has a dummy trench portion 30 but no gate trench portion 40. However, unlike semiconductor devices 100 and 200, the implantation suppression region 90 of semiconductor device 300 has an emitter region 12 and an extractor region 15 exposed on the front side 21. However, the ratio of emitter region 12 to extractor region 15 in the implantation suppression region 90 is lower than the ratio of emitter region 12 to extractor region 15 in the transistor portion 70.

[0181] like Figure 5A As shown, in the injection suppression region 90, the emitter region 12 and the extraction region 15 are fewer than in the transistor section 70. Furthermore, in the injection suppression region 90, a base region 14 is provided in the portion where the emitter region 12 and the extraction region 15 are not provided.

[0182] That is, in the transistor section 70, the emitter region 12 and the extractor region 15 extend along the extension direction (in Figure 5A The regions are arranged alternately (with the Y-axis in the middle), but in the injection suppression region 90, the extraction region 15 is arranged around the emission region 12, and the base region 14 is arranged around it.

[0183] Thus, in semiconductor device 300, by reducing the ratio of the extraction region 15 in the injection suppression region 90, hole injection can be suppressed, and losses can be reduced. Furthermore, because the injection suppression regions 90 of semiconductor devices 100 and 200 do not have emitter regions 12, no electron current flows through the emitter regions 12. However, in semiconductor device 300, since the injection suppression region 90 has emitter regions 12, electron current flows through it. Therefore, compared to semiconductor devices 100 and 200, semiconductor device 300 can reduce the on-state voltage.

[0184] Figure 5B yes Figure 5A A magnified view of part B in the diagram. Here, the configuration of the emission region 12 and the extraction region 15 in the injection suppression region 90 is mainly explained.

[0185] exist Figure 5B In this design, the mesa portion of the mesa portion 60 of the transistor portion 70 adjacent to the injection suppression region 90 is designated as the first mesa portion 60a, the mesa portion of the mesa portion 60 of the injection suppression region 90 adjacent to the transistor portion 70 is designated as the second mesa portion 60b, the mesa portion of the mesa portion 60 of the injection suppression region 90 adjacent to the second mesa portion 60b is designated as the third mesa portion 60c, and the mesa portion of the mesa portion 60 of the injection suppression region 90 adjacent to the diode portion 80 is designated as the fourth mesa portion 60d.

[0186] It should be noted that the injection inhibition zone 90 in this example has three facets, namely the second facet 60b to the fourth facet 60d, but the number of facets is not limited to this.

[0187] In the second to fourth face plates 60b, either the emission area 12 or the extraction area 15 is arranged adjacent to the emission area 12 located on the face plate adjacent to the negative side of the X-axis.

[0188] In the first faceplate 60a, six emission zones 12 and six extraction zones 15 are alternately arranged in the Y-axis direction. Three emission zones 12 of the six emission zones 12 of the first faceplate 60a are adjacent to three emission zones 12 arranged in the second faceplate 60b, and the remaining three emission zones 12 of the first faceplate 60a are adjacent to three extraction zones 15 arranged in the second faceplate 60b.

[0189] The three emission zones 12 of the second faceplate 60b are adjacent to the three emission zones 12 of the third faceplate 60c. Alternatively, the extraction zone 15 may be configured instead of a portion of the three emission zones 12 of the third faceplate 60c.

[0190] In the second faceplate 60b and the third faceplate 60c, the emitter region 12 is adjacent to the extractor region 15 in the Y-axis direction. That is, the positive and negative Y-axis sides of the emitter region 12 are surrounded by the extractor region 15. As a result, holes generated in conductivity modulation can be extracted to the extractor region 15, thereby improving latch-up tolerance.

[0191] In the second faceplate 60b and the third faceplate 60c, a base region 14 is provided in the area where the emission region 12 and the extraction region 15 are not provided.

[0192] The fourth face 60d does not have a transmitter region 12. The fourth face 60d has an extraction region 15, which is adjacent to the transmitter region 12 of the adjacent face 60d (the third face 60c in this example) on the negative X-axis side. In the fourth face 60d, a base region 14 is provided in the area where the extraction region 15 is not provided.

[0193] Alternatively, if the emitter region 12 is not configured on the stage adjacent to the fourth stage 60d on the negative X-axis, only the base region 14 is configured on the fourth stage 60d.

[0194] exist Figure 5B In the injection suppression region 90, the extraction region 15 is configured to cover the entire surface of the platform in the X-axis direction, but it can also be about half the length of the platform in the X-axis direction. In the injection suppression region 90, the length of the extraction region 15 in the X-axis direction can be 0.3 μm or more.

[0195] Furthermore, in the injection suppression region 90, the length of the extraction region 15 in the Y-axis direction is less than or equal to the length of the extraction region 15 in the Y-axis direction of the transistor section 70. In the injection suppression region 90, the length of the extraction region 15 in the Y-axis direction can be 0.5 μm or more. This allows for improved latch-up tolerance while suppressing hole injection.

[0196] It should be noted that, in Figure 5B The shaded area of ​​the contact hole 54 shown is configured with a plug area 17.

[0197] Figure 5C It means Figure 5A A diagram of the b-b' cross-section. The b-b' cross-section is the XZ plane exposed on the front side 21, consisting of the emitter region 12, the extraction region 15, and the base region 14. The diode portion 80 of the semiconductor device 300 has a lifetime control region 85 in the drift region 18.

[0198] The end K on the negative X-axis side of the lifetime control region 85 is located at a distance of more than 1 μm and less than 100 μm from the end on the injection suppression region 90 side of the diode section 80 toward the positive X-axis side, that is, it is located inside the diode section 80. That is, in this example, the lifetime control region 85 is not provided in the transistor section 70 and the injection suppression region 90.

[0199] exist Figure 5C In, such as Figure 5B As shown, an extraction region 15 is provided in the injection suppression region 90. Therefore, by setting the lifetime control region 85 to a position slightly recessed into the diode section 80, hole current is suppressed when the diode section 80 is turned on by promoting the recombination of holes and electrons generated from the base region 14 of the diode section 80.

[0200] Furthermore, if we assume that the end K of the lifetime control region 85 extends into the injection suppression region 90, then as described above, because the emitter region 12 is present in the injection suppression region 90, the threshold voltage is reduced. Therefore, compared with... Figure 1B Unlike other regions, it is preferable not to set a lifetime control zone 85 in the injection suppression zone 90.

[0201] Furthermore, the lifetime control region 85 is formed by irradiating protons or helium through, for example, the front side 21 through a 30-80 μm thick resist mask. Therefore, if the lifetime control region 85 is not slightly recessed into the diode section 80, the lifetime control region 85 will form in the injection suppression region 90 when the tilt angle of the thick resist mask is inconsistent, and the threshold voltage is prone to decrease or become inconsistent.

[0202] Therefore, by setting the lifetime control region 85 to a position slightly recessed into the diode section 80, even if the resist tilt angle is inconsistent, the lifetime control region 85 will not be formed in the injection suppression region 90, thereby preventing the threshold voltage from decreasing or becoming inconsistent.

[0203] Although hole current is generated from the extraction region 15 located further on the negative X-axis than the end K, the ratio of the extraction region 15 injected into the suppression region 90 is as follows: Figure 5B Because it is smaller, hole injection can be reduced more than when the transistor section 70 is provided. Therefore, in this example, even if the lifetime control region 85 is not provided in the injection suppression region 90, the hole density can be reduced compared to the case where hole current is injected from the transistor section 70.

[0204] Figure 5D This is an enlarged partial top view of the semiconductor device 300. Because the structure of the semiconductor device 300 in the top view is similar to, except for, the emitter region 12, base region 14, and extraction region 15 in the implantation suppression region 90. Figure 3A The semiconductor device 100 shown has the same structure, so the illustration is omitted.

[0205] Figure 5D and Figure 3C The enlarged partial top view of the semiconductor device 100 also enlarges the structure of a diode section 80 and its surrounding area within the semiconductor device 300. Figure 5D In the middle, the life control zone 85 is represented by a dashed line.

[0206] In such Figure 5D When the lifetime control region 85 is set to a position slightly recessed into the diode section 80, the area S1 of the diode section 80, the area S2 of the injection suppression region 90, and the area S3 of the lifetime control region 85 satisfy the following equation (4).

[0207] (S1+S2)≥S1>S3…[Equation (4)]

[0208] [Example 4]

[0209] Figure 6A This is a partial top view of the semiconductor device 400 of Embodiment 4 of this implementation. Figure 6B It means Figure 6A A view of section a-a' in the figure. Here, elements common to semiconductor device 100 are labeled with the same reference numerals, and descriptions are omitted.

[0210] In this example, a plurality of gate trench portions 40 are provided in the transistor portion 70 along the arrangement direction, and a plurality of dummy trench portions 30 are provided in the diode portion 80 along the arrangement direction.

[0211] In this example, the transistor section 70 is a full-gate structure without the dummy trench section 30. The gate trench sections 40 are connected to the adjacent gate trench sections 40 via the front end section 41.

[0212] In this way, by providing the injection suppression region 90, hole injection from the transistor section 70 is suppressed, and reverse recovery loss is improved. Thus, in the all-gate semiconductor device 400, the same effect as that of the semiconductor devices 100-300 in which the transistor section 70 is provided with the dummy trench section 30 can be obtained.

[0213] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. As can be seen from the claims, such modifications or improvements can also be included within the technical scope of the present invention.

[0214] The execution order of actions, processes, steps, and stages in the apparatus, system, program, and method shown in the claims, specification, and drawings can be implemented in any order, unless specifically stated as "earlier than" or "before," and unless the results of previous processes are used in subsequent processes. Even if the flow of actions in the claims, specification, and drawings is described using terms such as "firstly" or "next" for convenience, it does not mean that they must be implemented in this order.

Claims

1. A semiconductor device, characterized in that, It includes a semiconductor substrate, which has a transistor section and a diode section. The diode-side end of the transistor section, viewed from above on the semiconductor substrate, has an injection suppression region to suppress the injection of second-conductivity carriers. The diode section has a lifetime control region that includes a lifetime inhibitor. Both the transistor portion and the diode portion have a base region of a second conductivity type on the surface of the semiconductor substrate. The transistor portion further comprises an emitter region of a first conductivity type and an extractor region of a second conductivity type with a doping concentration higher than that of the base region on the surface of the semiconductor substrate. The doping concentration of the base region of the diode is 1E+16cm. -3 Above and 1E+18cm -3 the following, The end of the lifetime control region on the injection suppression region side is located at a position that is recessed from the end of the diode portion on the injection suppression region side into the diode portion by a distance of more than 1 μm and less than 100 μm. The transistor portion and the injection suppression region have multiple mesa portions that extend between multiple trench portions along the extending direction of the transistor portion and the diode portion. The multiple trench portions extend along the extending direction and are arranged along the arrangement direction of the transistor portion and the diode portion. On the mesa portion of the injection suppression region, either the emitter region or the extractor region is configured to be adjacent to the emitter region on the mesa portion adjacent to the transistor portion side.

2. The semiconductor device according to claim 1, characterized in that, When viewed from above, the width of the injection suppression region in the arrangement direction of the transistor portion and the diode portion is 20 μm or more and 900 μm or less.

3. The semiconductor device according to claim 1, characterized in that, When viewed from above, the injection suppression region is also disposed between the end of the diode portion in the extending direction and the outer periphery of the active region.

4. The semiconductor device according to claim 2, characterized in that, When viewed from above, the injection suppression region is also disposed between the end of the diode portion in the extending direction and the outer periphery of the active region.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, When viewed from above, the area of ​​the diode portion is 10% or more of the combined area of ​​the diode portion and the injection suppression region.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that, When viewed from above, the total area of ​​the diode portion is 1.4% to 22% of the area of ​​the semiconductor device.

7. The semiconductor device according to claim 5, characterized in that, When viewed from above, the total area of ​​the diode portion is 1.4% to 22% of the area of ​​the semiconductor device.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that, The doping concentration of the base region in the implantation suppression region is lower than or equal to the doping concentration of the base region in the diode portion.

9. The semiconductor device according to claim 5, characterized in that, The doping concentration of the base region in the implantation suppression region is lower than or equal to the doping concentration of the base region in the diode portion.

10. The semiconductor device according to claim 6, characterized in that, The doping concentration of the base region in the implantation suppression region is lower than or equal to the doping concentration of the base region in the diode portion.

11. The semiconductor device according to claim 7, characterized in that, The doping concentration of the base region in the implantation suppression region is lower than or equal to the doping concentration of the base region in the diode portion.

12. The semiconductor device according to claim 8, characterized in that, The doping concentration of the base region in the implantation suppression region is 1E+16cm⁻¹. -3 Above and 5E+19cm -3 the following.

13. The semiconductor device according to claim 9, characterized in that, The doping concentration of the base region in the implantation suppression region is 1E+16cm⁻¹. -3 Above and 5E+19cm -3 the following.

14. The semiconductor device according to claim 10, characterized in that, The doping concentration of the base region in the implantation suppression region is 1E+16cm⁻¹. -3 Above and 5E+19cm -3 the following.

15. The semiconductor device according to claim 11, characterized in that, The doping concentration of the base region in the implantation suppression region is 1E+16cm⁻¹. -3 Above and 5E+19cm -3 the following.

16. The semiconductor device according to any one of claims 1 to 4, characterized in that, The doping concentration of the extraction region is 5E+18cm⁻¹ -3 Above and 5E+20cm -3 the following.

17. The semiconductor device according to claim 1, characterized in that, The emission region of the injection suppression region is adjacent to the extraction region in the extension direction.

18. The semiconductor device according to claim 1 or 17, characterized in that, In the injection suppression region, the emission region is not located on the mesa adjacent to the diode portion.

19. The semiconductor device according to claim 1 or 17, characterized in that, When viewed from above, the length of the extracted region is 0.5 μm or more in the extending direction of the transistor portion and the diode portion.

20. The semiconductor device according to claim 1 or 17, characterized in that, When viewed from above, the length of the extracted region is 0.3 μm or more in the arrangement direction of the transistor portion and the diode portion of the semiconductor substrate.

21. The semiconductor device according to claim 1 or 17, characterized in that, In the injection suppression region, the base region is disposed in the portion of the semiconductor substrate that is not configured with the emitter region and the extractor region when viewed from above.

22. The semiconductor device according to any one of claims 1 to 4, 17, characterized in that, The semiconductor substrate also has an accumulation region of a first conductivity type inside.

23. A semiconductor device, characterized in that, It includes a semiconductor substrate, which has a transistor section and a diode section. The diode-side end of the transistor section, viewed from above on the semiconductor substrate, has an injection suppression region to suppress the injection of second-conductivity carriers. The diode section has a lifetime control region that includes a lifetime inhibitor. Both the transistor portion and the diode portion have a base region of a second conductivity type on the surface of the semiconductor substrate. The transistor portion and the injection suppression region further have an emitter region of a first conductivity type and an extractor region of a second conductivity type with a doping concentration higher than that of the base region on the surface of the semiconductor substrate. The ratio of the area occupied by the emitter region and the extractor region in the injection suppression region is lower than the ratio of the area occupied by the emitter region and the extractor region in the transistor portion.

24. The semiconductor device according to claim 23, characterized in that, The transistor portion and the injection suppression region have multiple mesa portions that extend between multiple trench portions along the extending direction of the transistor portion and the diode portion. The multiple trench portions extend along the extending direction and are arranged along the arrangement direction of the transistor portion and the diode portion. On the mesa portion of the injection suppression region, either the emitter region or the extractor region is configured to be adjacent to the emitter region on the mesa portion adjacent to the transistor portion side.

25. The semiconductor device according to claim 24, characterized in that, The emission region of the injection suppression region is adjacent to the extraction region in the extension direction.

26. The semiconductor device according to any one of claims 23 to 25, characterized in that, In the injection suppression region, the emission region is not located on the mesa adjacent to the diode portion.

27. The semiconductor device according to any one of claims 23 to 25, characterized in that, When viewed from above, the length of the extracted region is 0.5 μm or more in the extending direction of the transistor portion and the diode portion.

28. The semiconductor device according to any one of claims 23 to 25, characterized in that, When viewed from above, the length of the extracted region is 0.3 μm or more in the arrangement direction of the transistor portion and the diode portion of the semiconductor substrate.

29. The semiconductor device according to any one of claims 23 to 25, characterized in that, In the injection suppression region, the base region is disposed in the portion of the semiconductor substrate that is not configured with the emitter region and the extractor region when viewed from above.

30. The semiconductor device according to any one of claims 23 to 25, characterized in that, The semiconductor substrate also has an accumulation region of a first conductivity type inside.

31. The semiconductor device according to claim 26, characterized in that, The semiconductor substrate also has an accumulation region of a first conductivity type inside.

32. The semiconductor device according to claim 27, characterized in that, The semiconductor substrate also has an accumulation region of a first conductivity type inside.

33. The semiconductor device according to claim 28, characterized in that, The semiconductor substrate also has an accumulation region of a first conductivity type inside.

34. The semiconductor device according to claim 29, characterized in that, The semiconductor substrate also has an accumulation region of a first conductivity type inside.

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