Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device that can be miniaturized or highly integrated. The semiconductor device includes a first conductor disposed on a substrate, an oxide disposed so as to be in contact with a top surface of the first conductor, a second conductor disposed on the oxide, a third conductor and a fourth conductor, a first insulator disposed on the second conductor to the fourth conductor and formed with a first opening and a second opening, a second insulator disposed in the first opening, a fifth conductor disposed on the second insulator, a third insulator disposed in the second opening, a sixth conductor disposed on the third insulator, the third conductor is disposed in a manner of being disposed on the first conductor, a region between the second conductor and the third conductor overlaps the first opening, and a region between the third conductor and the fourth conductor overlaps the second opening.

Description

Technical Field

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another aspect relates to a method for manufacturing a semiconductor device. Furthermore, one aspect relates to a semiconductor wafer and module.

[0002] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the properties of semiconductors. Besides semiconductor elements such as transistors, semiconductor circuits, arithmetic processing devices, or storage devices are also types of semiconductor devices. Display devices (liquid crystal displays, light-emitting displays, etc.), projection devices, lighting devices, electro-optical devices, energy storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc., sometimes include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the aforementioned technical fields. One aspect of the invention disclosed in this specification relates to an object, method, or manufacturing method. Additionally, another aspect of the present invention relates to a process, machine, manufacture, or composition of matter. Background Technology

[0004] In recent years, semiconductor devices have been developed, and in particular, the development of using these semiconductor devices for LSIs, CPUs, and memory is becoming increasingly popular. A CPU is an assembly of semiconductor elements that include semiconductor integrated circuits (including at least transistors and memory) separated from a semiconductor wafer and formed with electrodes as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards such as printed circuit boards and used as components in various electronic devices.

[0006] Furthermore, the technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. Among other materials, oxide semiconductors have also garnered interest.

[0007] Furthermore, it is known that the leakage current of transistors using oxide semiconductors is extremely small in the non-conducting state. For example, low-power CPUs utilizing the low leakage current characteristic of transistors using oxide semiconductors have been disclosed (see Patent Document 1). In addition, for example, storage devices that utilize the low leakage current characteristic of transistors using oxide semiconductors to achieve long-term retention of stored content have been disclosed (see Patent Document 2).

[0008] In recent years, with the miniaturization and weight reduction of electronic devices, the demand for further high-density integrated circuits has increased. Furthermore, there is a need to improve the productivity of semiconductor devices containing integrated circuits.

[0009] [Preliminary Technology Documents]

[0010] [Patent Literature]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187

[0012] [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 Summary of the Invention

[0013] The technical problem that the invention aims to solve

[0014] One objective of this invention is to provide a semiconductor device capable of miniaturization or high integration. Another objective is to provide a semiconductor device with large storage capacity. One objective is to provide a semiconductor device with minimal transistor characteristic non-uniformity. Another objective is to provide a semiconductor device with high reliability. Another objective is to provide a semiconductor device with good electrical characteristics. Another objective is to provide a semiconductor device with high on-state current. Another objective is to provide a low-power semiconductor device. Finally, one objective is to provide a novel semiconductor device.

[0015] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the invention does not necessarily require achieving all of the above objectives. Objectives other than those described above are obvious from the description in the specification, drawings, claims, etc., and can be extracted from said description.

[0016] means of solving technical problems

[0017] One aspect of the present invention is a semiconductor device comprising: a first conductor disposed on a substrate; an oxide disposed in contact with the top surface of the first conductor; a second, third, and fourth conductor disposed on the oxide; a first insulator disposed on the second to fourth conductors and having a first opening and a second opening formed therein; a second insulator disposed in the first opening; a fifth conductor disposed on the second insulator; a third insulator disposed in the second opening; and a sixth conductor disposed on the third insulator, wherein the third conductor is disposed in an overlapping manner with the first conductor, the first opening is formed in an overlapping region between the second and third conductors, and the second opening is formed in an overlapping region between the third and fourth conductors.

[0018] The above structure further includes: a first capacitor; and a second capacitor, wherein the first capacitor may also be electrically connected to a second conductor, and the second capacitor may also be electrically connected to a fourth conductor. Furthermore, in the above structure, it is preferable that the first capacitor is disposed on the second conductor, and the second capacitor is disposed on the fourth conductor.

[0019] In the above structure, the first conductor is preferably connected to the wiring disposed under the first conductor. In the above structure, it is preferable that the second insulator is in contact with the top surface of the oxide and the side surface of the first insulator, and that the third insulator is in contact with the top surface of the oxide and the side surface of the first insulator.

[0020] In the above structure, preferably, the oxide includes a first oxide and a second oxide on the first oxide, the first oxide and the second oxide containing indium, element M (M is one or more selected from gallium, aluminum, yttrium and tin), and zinc, and the atomic ratio of the first oxide to the indium of element M is less than the atomic ratio of the second oxide to the indium of element M.

[0021] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first conductor on a substrate; forming an oxide film in contact with the top surface of the first conductor; forming a first conductive film on the oxide film; processing the oxide film and the first conductive film into island shapes to form an oxide and a second conductor; forming a first insulator covering the oxide and the second conductor; removing a portion of the first insulator to form a first opening and a second opening overlapping with the second conductor; removing a portion of the second conductor overlapping with the first opening and the second opening to form a third conductor, a fourth conductor, and a fifth conductor; the fourth conductor being arranged to overlap with the first conductor; exposing regions of the oxide that do not overlap with the third to fifth conductors; forming a first insulating film in contact with the top surface of the oxide; performing microwave treatment in an oxygen-containing atmosphere; forming a second conductive film on the first insulating film; and performing CMP treatment on the first insulating film and the second conductive film until the top surface of the first insulator is exposed, forming a second insulator and a sixth conductor in the first opening, and forming a third insulator and a seventh conductor in the second opening.

[0022] Invention Effects

[0023] According to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with large storage capacity can be provided. According to one aspect of the present invention, a semiconductor device with small transistor characteristic non-uniformity can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Additionally, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with large on-state current can be provided. Additionally, according to one aspect of the present invention, a low-power semiconductor device can be provided. Furthermore, according to one aspect of the present invention, a novel semiconductor device can be provided.

[0024] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the invention does not necessarily require achieving all of the above-described effects. Effects other than those described above are obvious from the description in the specification, drawings, claims, etc., and can be extracted from said description. Attached Figure Description

[0025] FIG. 1A , FIG. 1B , FIG. 1C , FIG. 1D This is a top view and a cross-sectional view of a semiconductor device according to one aspect of the present invention.

[0026] FIG. 2 This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0027] FIG. 3A This is a diagram illustrating the classification of IGZO crystal structures. FIG. 3B This is a graph illustrating the XRD spectrum of the CAAC-IGZO film. FIG. 3C This is a diagram illustrating the nanobeam electron diffraction pattern of the CAAC-IGZO film.

[0028] FIG. 4A , FIG. 4B , FIG. 4C , FIG. 4D This is a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0029] FIG. 5A , FIG. 5B , FIG. 5C , FIG. 5D This is a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0030] FIG. 6A , FIG. 6B , FIG. 6C , FIG. 6D This is a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0031] FIG. 7A , FIG. 7B , FIG. 7C , FIG. 7D This is a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0032] FIG. 8A , FIG. 8B , FIG. 8C , FIG. 8D This is a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0033] FIG. 9A , FIG. 9B , FIG. 9C , FIG. 9D This is a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0034] FIG. 10A , FIG. 10B , FIG. 10C , FIG. 10D This is a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0035] FIG. 11A , FIG. 11B , FIG. 11C , FIG. 11DThis is a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0036] FIG. 12A , FIG. 12B , FIG. 12C , FIG. 12D This is a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0037] FIG. 13 This is a top view illustrating one aspect of the microwave processing apparatus of the present invention.

[0038] FIG. 14 This is a cross-sectional view illustrating one aspect of the microwave processing apparatus of the present invention.

[0039] FIG. 15 This is a cross-sectional view illustrating one aspect of the microwave processing apparatus of the present invention.

[0040] FIG. 16A , FIG. 16B , FIG. 16C , FIG. 16D This is a top view and a cross-sectional view of a semiconductor device according to one aspect of the present invention.

[0041] FIG. 17A , FIG. 17B This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0042] FIG. 18 This is a cross-sectional view illustrating the structure of a storage device according to one embodiment of the present invention.

[0043] FIG. 19 This is a cross-sectional view illustrating the structure of a storage device according to one embodiment of the present invention.

[0044] FIG. 20A , FIG. 20B This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0045] FIG. 21 This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0046] FIG. 22 This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

[0047] FIG. 23A , FIG. 23B This is a block diagram illustrating a structural example of a storage device according to one aspect of the present invention.

[0048] FIG. 24A , FIG. 24B , FIG. 24C This is a circuit diagram illustrating a structural example of a storage device according to one aspect of the present invention.

[0049] FIG. 25A , FIG. 25B This is a schematic diagram of a semiconductor device according to one aspect of the present invention.

[0050] FIG. 26A , FIG. 26B This is a diagram illustrating an example of an electronic component according to one aspect of the present invention.

[0051] FIG. 27A , FIG. 27B This is a schematic diagram of a storage device according to one aspect of the present invention.

[0052] FIG. 28A , FIG. 28B , FIG. 28C , FIG. 28D , FIG. 28E , FIG. 28F , FIG. 28G , FIG. 28H This is a diagram illustrating an electronic device according to one aspect of the present invention. Detailed Implementation

[0053] The embodiments will now be described with reference to the accompanying drawings. It should be noted that those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments shown below.

[0054] In the accompanying drawings, for obvious purposes, sizes, layer thicknesses, or areas are sometimes exaggerated. Therefore, the invention is not limited to the dimensions shown in the drawings. Furthermore, ideal examples are schematically shown in the drawings, and the invention is not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks are sometimes unintentionally thinned due to processes such as etching, but this is sometimes not reflected in the drawings for ease of understanding. Additionally, in the drawings, the same reference numerals are sometimes used across different drawings to denote the same parts or parts with the same function, omitting repeated descriptions. Furthermore, when indicating parts with the same function, the same shading lines are sometimes used without additional reference numerals.

[0055] Furthermore, especially in top views (also known as plan views) or perspective views, descriptions of some constituent elements are sometimes omitted to facilitate understanding of the invention. Additionally, descriptions of some hidden lines, etc., are sometimes omitted.

[0056] Furthermore, in this specification and other documents, ordinal numbers such as "first," "second," etc., are added for convenience, but they do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for description. In addition, the ordinal numbers described in this specification and other documents are sometimes inconsistent with the ordinal numbers used to specify one aspect of the present invention.

[0057] In this specification and other materials, for convenience, terms such as "upper" and "lower" are used to indicate configuration, referring to the accompanying drawings to illustrate the positional relationships of the constituent elements. Furthermore, the positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0058] For example, in this specification, when it is explicitly stated as "X and Y are connected," it means the following: X and Y are electrically connected; X and Y are functionally connected; X and Y are directly connected. Therefore, connection relationships other than those shown in the drawings or text are disclosed in the drawings or text, not limited to those specified therein. Here, X and Y refer to objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0059] In this specification and the like, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as the channel-forming region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) that forms a channel, and current can flow between the source and drain through the channel-forming region. Note that in this specification and the like, the channel-forming region refers to the region through which current primarily flows.

[0060] Furthermore, in cases where transistors with different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may sometimes be interchanged.

[0061] Note that channel length, for example, refers to the distance between the overlapping region of the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on-state) and the gate electrode in a top view of the transistor, or between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel-forming region. Furthermore, the channel length in a transistor is not necessarily the same value in all regions. That is, the channel length of a transistor is sometimes not limited to a single value. Therefore, in this specification, channel length refers to any value, maximum, minimum, or average value in the channel-forming region.

[0062] The channel width, for example, refers to the length of the channel-forming region perpendicular to the channel length direction in the overlapping area of ​​the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on-state) and the gate electrode in a top view of the transistor. Furthermore, the channel width in a transistor is not necessarily the same value in all regions. That is, the channel width of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel width refers to any value, maximum value, minimum value, or average value in the channel-forming region.

[0063] In this specification, depending on the transistor structure, the actual channel width (hereinafter referred to as "effective channel width") in the region forming the channel sometimes differs from the channel width shown in the top view of the transistor (hereinafter referred to as "apparent channel width"). For example, when the gate electrode covers the side of the semiconductor, the effect cannot be ignored because the effective channel width is greater than the apparent channel width. For example, in miniature transistors where the gate electrode covers the side of the semiconductor, the proportion of the channel formation region formed on the side of the semiconductor is sometimes increased. In this case, the effective channel width is greater than the apparent channel width.

[0064] In the aforementioned situations, it can sometimes be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width based on design values, prior knowledge of the assumed shape of the semiconductor is required. Therefore, when the shape of the semiconductor is uncertain, it is difficult to accurately measure the effective channel width.

[0065] In this specification, when simply described as "channel width," it sometimes refers to the apparent channel width. Alternatively, in this specification, when simply referred to as "channel width," it sometimes refers to the actual channel width. Note that the values ​​of channel length, channel width, actual channel width, apparent channel width, etc., can be determined by analyzing cross-sectional TEM images, etc.

[0066] Note that impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can sometimes lead to an increase in the defect state density or a decrease in crystallinity of the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter its properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water sometimes also acts as an impurity. Furthermore, the incorporation of impurities can sometimes lead to oxygen vacancies (also known as V vacancies) in the oxide semiconductor. O The formation of oxygen vacancy.

[0067] Note that in this specification, silicon oxynitride refers to a substance with an oxygen content greater than its nitrogen content. Furthermore, silicon oxynitride refers to a substance with a nitrogen content greater than its oxygen content.

[0068] Note that in this specification, etc., "insulator" may be replaced with "insulating film" or "insulating layer". Additionally, "conductor" may be replaced with "conductive film" or "conductive layer". Furthermore, "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer".

[0069] In this specification, "parallel" refers to a state where the angle formed by two straight lines is -10° or more and less than 10°. Therefore, it also includes a state where the angle is -5° or more and less than 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is -30° or more and less than 30°. Furthermore, "perpendicular" refers to a state where the angle between two straight lines is 80° or more and less than 100°. Therefore, it also includes a state where the angle is 85° or more and less than 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is 60° or more and less than 120°.

[0070] In this specification and other materials, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also abbreviated as OS). For example, when a metal oxide is used as the semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can be referred to as a transistor containing either a metal oxide or an oxide semiconductor.

[0071] Note that in this specification, "normally off" means that the drain current flowing through the transistor per channel width of 1 μm is 1 × 10⁻⁶ at room temperature when no gate potential is applied or when a ground potential is applied to the gate. -20 Below A, at 85℃, it is 1×10 -18 Below A, or 1×10 at 125℃ -16 Below A.

[0072] (Implementation Method 1)

[0073] In this embodiment, refer to FIGS. 1A-17B An example of a semiconductor device including transistors 200a and 200b according to one aspect of the present invention, and a method thereof are described. Note that transistors 200a and 200b are sometimes referred to collectively as transistor 200 below.

[0074] <Examples of semiconductor device structures>

[0075] Reference FIGS. 1A-1D The structure of a semiconductor device including transistor 200a and transistor 200b will be described. FIG. 1A This is a top view of the semiconductor device. FIGS. 1B-1D This is a cross-sectional view of the semiconductor device. FIG. 1B It is along FIG. 1A The cross-sectional view of the dotted line A1-A2 in the figure corresponds to the cross-sectional view of transistors 200a and 200b along the channel length. FIG. 1C It is along FIG. 1A The cross-sectional view of the dashed lines A3-A4 in the figure corresponds to the cross-sectional view of the channel width direction of the transistor 200a. FIG. 1D Is FIG. 1A The cross-sectional view of the portion indicated by the dashed lines A5-A6. FIG. 1A In the top view, some constituent elements are omitted for clarity.

[0076] One aspect of the semiconductor device of the present invention includes: an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, and an insulator 283 on the insulator 282. Insulators 212, 214, 280, 282, and 283 are used as interlayer films. Furthermore, conductors 248 (conductors 248a and 248b) are disposed in a manner embedded in the insulators 212 and 214 and between transistors 200a and 200b. Conductors 248 are electrically connected to transistors 200a and 200b and are used as connectors. Note that it is preferable that the insulator 249 is disposed in such a manner that the side of the conductor 248 used as a connector is in contact with it.

[0077] [Transistor 200]

[0078] like FIGS. 1A-1D As shown, transistor 200a includes an insulator 216 on an insulator 214, conductors 205 (conductors 205a, 205b, and 205c) disposed in the insulator 216, an insulator 222 on the insulator 216 and on the conductors 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, oxides 243a and 243b on the oxide 230b, a conductor 242a on the oxide 243a, a conductor 242b on the oxide 243b, an insulator 250 on the oxide 230b, and conductors 260 (conductors 260a and 260b) located on the insulator 250 and overlapping a portion of the oxide 230b.

[0079] In addition, such as FIGS. 1A-1D As shown, transistor 200b includes an insulator 216 on an insulator 214, a conductor 205 disposed in an insulator 214 or an insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, oxides 243b and 243c on the oxide 230b, a conductor 242b on the oxide 243b, a conductor 242c on the oxide 243c, an insulator 250 on the oxide 230b, and a conductor 260 located on the insulator 250 and overlapping a portion of the oxide 230b.

[0080] Note that oxides 230a and 230b are sometimes collectively referred to as oxide 230. Additionally, oxides 243a, 243b, and 243c are sometimes collectively referred to as oxide 243. Furthermore, conductors 242a, 242b, and 242c are sometimes collectively referred to as conductor 242.

[0081] The insulator 275 is provided in such a manner that it covers the insulator 224, oxide 230, oxide 243, and conductor 242. Furthermore, as... FIG. 1B and FIG. 1C As shown, the top surface of conductor 260 is arranged in a manner that is substantially aligned with the top surfaces of insulator 250 and insulator 280. Furthermore, insulator 282 contacts each of the top surfaces of conductor 260 and insulator 280, as well as the uppermost part of insulator 250.

[0082] Here, as FIGS. 1A-1D As shown, transistor 200b is sandwiched between conductor 248 and disposed on the opposite side of transistor 200a. Except for conductor 242 and oxide 243, it has the same structure as transistor 200a.

[0083] In transistors 200a and 200b, insulators 212, 214, 216, 222, 224, oxides 230a and 230b, insulators 275, 280, 282, and 283 are used in common. On the other hand, conductors 205, 250, and 260 are respectively provided in transistors 200a and 200b. Note that in transistor 200b, conductors 205, 250, and 260 have the same structure as in transistor 200a and are therefore given the same reference numerals.

[0084] Conductors 242a to 242c and oxides 243a to 243c on oxide 230 are arranged in a straight line along the channel length direction (A1-A2 direction). Here, conductor 242b is arranged to overlap with conductor 248. Furthermore, openings are respectively provided overlappingly in the regions between conductors 242a and 242b and between conductors 242b and 242c. An insulator 250 and a conductor 260 disposed on the insulator 250 are provided in each opening.

[0085] Insulators 280 and 275 have two openings leading to oxide 230b, through which insulator 250 and conductor 260 are disposed. That is, in transistor 200a, insulator 250 is disposed in contact with the top surface of oxide 230b, the sides of oxides 243a and 243b, the sides of conductors 242a and 242b, the side of insulator 275, and the side of insulator 280. Furthermore, in transistor 200b, insulator 250 is disposed in contact with the top surface of oxide 230b, the sides of oxides 243b and 243c, the sides of conductors 242b and 242c, the side of insulator 275, and the side of insulator 280. Moreover, in both transistors 200a and 200b, each conductor 260 is disposed in contact with both the top surface and the side surface of each insulator 250.

[0086] In each of transistors 200a and 200b, conductor 260 is used as a first gate (also called a top gate) electrode, and conductor 205 is used as a second gate (also called a back gate) electrode. Furthermore, in each of transistors 200a and 200b, insulator 250 is used as a first gate insulator, and insulators 222 and 224 are used as second gate insulators.

[0087] Conductor 242a is used as one of the source and drain of transistor 200a. Furthermore, conductor 242b is used as the other of the source and drain of transistor 200a and one of the source and drain of transistor 200b. Additionally, conductor 242c is used as the other of the source and drain of transistor 200b. Furthermore, at least a portion of the region of oxide 230 overlapping with conductor 260 is used as a channel forming region of transistor 200a or transistor 200b.

[0088] Here, FIG. 2 Show FIG. 1B A magnified view of the area near the channel formation region. (See image below.) FIG. 2As shown, oxide 230 includes region 232d, which is used as a channel forming region of transistor 200a; region 232a and region 232b, which are disposed in a manner that sandwiches region 232d and are used as a source region or drain region of transistor 200a; region 232e, which is used as a channel forming region of transistor 200b; and region 232c, which is disposed in a manner that sandwiches region 232e with region 232b and is used as a source region or drain region of transistor 200b.

[0089] At least a portion of regions 232d and 232e overlaps with conductor 260. That is, region 232d overlaps with conductor 242b, and region 232e overlaps with conductor 242b and conductor 242c. Region 232a overlaps with conductor 242a, region 232b overlaps with conductor 242b, and region 232c overlaps with conductor 242c.

[0090] Regions 232d and 232e, used as channel forming regions, have fewer oxygen vacancies than regions 232a, 232b, and 232c, or the impurity concentrations in regions 232d and 232e are lower than those in regions 232a, 232b, and 232c. Therefore, regions 232d and 232e are high-resistivity regions with low carrier concentrations. Thus, regions 232d and 232e can be considered type I (intrinsic) or substantially type I.

[0091] Regions 232a, 232b, and 232c, used as source or drain regions, are regions with increased carrier concentration due to abundant oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, thus resulting in low resistance. In other words, regions 232a, 232b, and 232c are n-type regions with high carrier concentration and low resistance compared to regions 232d and 232e.

[0092] Here, the preferred carrier concentration for regions 232d and 232e, which are used as channel forming regions, is 1×10⁻⁶. 18 cm -3 Below, less than 1×10 is preferred. 17 cm -3 Further optimization of less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 Further preferred is less than 1×10 12 cm -3There is no particular limitation on the lower limit of the carrier concentration in regions 232d and 232e, which are used as channel forming regions; for example, it can be set to 1 × 10⁻⁶. -9 cm -3 .

[0093] Additionally, sometimes a region is formed between region 232d and region 232a or region 232b, or between region 232e and region 232b or region 232c, where the carrier concentration is equal to or lower than that of regions 232a, 232b, and 232c, but equal to or higher than that of regions 232d and 232e. In other words, this region is used as a junction region between region 232d or region 232e and regions 232a, 232b, or 232c. The hydrogen concentration in this junction region is sometimes equal to or lower than that of regions 232a, 232b, and 232c, but equal to or higher than that of regions 232d and 232e. Furthermore, the oxygen vacancies in this junction region are sometimes equal to or less than those in regions 232a, 232b, and 232c, but equal to or more than those in regions 232d and 232e.

[0094] In oxide 230, it is sometimes difficult to clearly observe the boundaries between regions. The concentrations of metallic elements and impurity elements such as hydrogen and nitrogen detected in each region do not necessarily need to vary in stages for each region; they can vary gradually within each region. That is, the closer to the channel formation region, the lower the concentration of metallic elements and impurity elements such as hydrogen and nitrogen should be.

[0095] Here, region 232b is used as the source or drain region for both transistors 200a and 200b, or it can be said that it is used together in transistors 200a and 200b. Thus, transistors 200a and 200b have a structure in which the source and drain are connected in series.

[0096] like FIG. 1B and FIG. 1D As shown, oxide 230 contacts at least a portion of the top surface of conductor 248 in region 232b. Thus, by connecting oxide 230 to conductor 248 via region 232b, the resistance between the source or drain of transistors 200a and 200b and conductor 248 can be reduced. Furthermore, since region 232b is formed in a manner overlapping conductor 242b, conductor 242b is configured to overlap at least a portion of conductor 248.

[0097] The conductor 248 is configured to protrude from the top surface of the insulator 224. For example, the conductor 248 may be configured to be embedded in an opening formed in the insulators 212, 214, 216, 222, and 224. At least a portion of the top surface of the conductor 248 protrudes from the insulator 224, and the top surface of the conductor 248 is preferably substantially aligned with the top surface of the insulator 224.

[0098] Here, conductor 248 is used as a plug for electrically connecting wiring, electrodes, terminals, or circuit elements (switches, transistors, capacitors, inductors, resistors, or diodes, etc.) disposed below in insulator 212 to transistors 200a and 200b. For example, conductor 248 can be connected to wiring disposed below insulator 212.

[0099] For example, when transistor 200 is used as a memory cell of a memory device and the memory cell is arranged on peripheral circuitry formed on a substrate, conductor 248 and wiring disposed in contact with conductor 248 are equivalent to bit lines, and conductor 260 of transistor 200 is equivalent to word lines. FIG. 1B As shown, when the conductor 248 is disposed under the oxide 230, the parasitic capacitance generated in the conductor 248 and the conductor 260 can be reduced compared to the case where the conductor 248 is disposed on the oxide 230. In other words, in the aforementioned memory device, the parasitic capacitance generated in the word lines and bit lines can be reduced. Furthermore, when the conductor 248 is disposed under the oxide 230, the bit lines can be shortened compared to the case where the conductor 248 is disposed on the oxide 230. Therefore, the parasitic capacitance generated in the bit lines can be reduced.

[0100] Thus, by reducing the parasitic capacitance of the bit lines in the aforementioned storage device, the design value of the electrostatic capacitance required for the capacitors in the aforementioned storage cells can be reduced. Consequently, since the capacitor can be miniaturized, the aforementioned storage device can be miniaturized or highly integrated.

[0101] At least a portion of the wiring, electrodes, terminals, or circuit elements (switches, transistors, capacitors, inductors, resistors, or diodes, etc.) electrically connected to the conductor 248 preferably overlaps with the oxide 230. This reduces the area occupied by the transistor 200, the aforementioned wiring, electrodes, terminals, or circuit elements when viewed from above, enabling miniaturization or high integration of the semiconductor device of this embodiment.

[0102] exist FIG. 1A , FIG. 1B , FIG. 1DIn this embodiment, the conductor 248 is disposed in contact with the bottom surface of region 232b, but the present invention is not limited thereto. For example, the conductor 248 may be disposed in contact with the bottom surface of region 232a or in contact with the bottom surface of region 232c.

[0103] Preferably, in transistor 200, a metal oxide (hereinafter, sometimes referred to as oxide semiconductor) used as a semiconductor is used in oxide 230, which includes the channel formation region. Oxide 230 preferably includes oxide 230a on insulator 224 and oxide 230b on oxide 230a.

[0104] The metal oxide used as the semiconductor preferably has a bandgap of 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a wider bandgap, the off-state current of the transistor can be reduced. Therefore, by using a metal oxide with a wider bandgap, the off-state current of transistor 200 can be reduced. As described above, by reducing the off-state current of transistor 200, when transistor 200 is used as a memory cell in a memory device, the stored content can be retained for a long time. That is, the memory device does not require refresh operations or the refresh frequency is extremely low. Thus, the power consumption of the memory device can be significantly reduced.

[0105] For example, as oxide 230, an In-M-Zn oxide containing indium, element M, and zinc (element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is preferably used. For example, as oxide 230, In-Ga-Zn oxide or an oxide in which tin is added can be used. Furthermore, In-Ga oxide, In-Zn oxide, and indium oxide can also be used as oxide 230.

[0106] The aforementioned metal oxides can be formed on a substrate using methods such as sputtering. Therefore, transistors 200 can be disposed on and superimposed on peripheral circuits such as drive circuits formed on the silicon substrate. Thus, when transistors 200 are used as memory cells in a memory device, the area occupied by the memory cell array that can be disposed on a single chip can be increased, thereby increasing the storage capacity of the memory device. Furthermore, by stacking multiple of the aforementioned metal oxides, a memory cell array can be stacked. This allows for integrated configuration of cells without increasing the area occupied by the memory cell array. In other words, a stacked structure of memory cell arrays (hereinafter sometimes referred to as a 3D cell array) can be constructed. In this way, high integration of memory cells can be achieved, providing a semiconductor device with a large storage capacity.

[0107] Furthermore, semiconductor devices using the aforementioned metal oxides, especially In-Ga-Zn oxides, can operate normally within a temperature range above -40°C and below 190°C, meaning they exhibit very high heat resistance. Compared to the heat resistance of phase change memory (PCM) (above -40°C and below 150°C), resistance random access memory (ReRAM) (above -40°C and below 125°C), and magnetoresistive random access memory (MRAM) (above -40°C and below 105°C), this semiconductor device demonstrates superior heat resistance.

[0108] Preferably, the ratio of the number of In atoms to the number of elements M in the metal oxide used for oxide 230b is greater than the ratio of the number of In atoms to the number of elements M in the metal oxide used for oxide 230a.

[0109] By arranging oxide 230a below oxide 230b, the diffusion of impurities and oxygen from the structure formed below oxide 230a to oxide 230b can be suppressed.

[0110] Note that oxide 230 is not limited to a two-layer structure consisting of oxides 230a and 230b. For example, oxide 230 may have a single-layer or three-layer stacked structure of oxide 230b, or it may have a structure in which oxides 230a and 230b are each stacked. For example, a structure in which oxide 230 is composed of a single layer of oxide 230b and region 232b is easily formed on the bottom surface of oxide 230 may also be used.

[0111] Furthermore, oxides 230a and 230b contain a common element (as a major component) besides oxygen, which can reduce the defect state density at the interfaces of oxides 230a and 230b. Because the defect state density at the interfaces of oxides 230a and 230b can be reduced, the effect of interface scattering on carrier conduction is small, thereby obtaining a high on-state current.

[0112] Oxide 230b preferably has crystallinity. In particular, CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferably used as oxide 230b.

[0113] CAAC-OS has a dense structure with high crystallinity and is an impurity or defect (e.g., oxygen vacancies (V)).O CAAC-OS contains fewer metal oxides. In particular, by heat-treating the metal oxide after its formation at a temperature at which the metal oxide does not polymorphize (e.g., above 400°C and below 600°C), CAAC-OS can be made to have a denser structure with higher crystallinity. Thus, by further increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0114] On the other hand, distinct grain boundaries are not easily observed in CAAC-OS, thus reducing the likelihood of a decrease in electron mobility due to grain boundaries. Therefore, metal oxides containing CAAC-OS exhibit stable physical properties. Consequently, metal oxides with CAAC-OS demonstrate good heat resistance and reliability.

[0115] Furthermore, in transistors using oxide semiconductors, if impurities and oxygen vacancies exist in the channel formation region of the oxide semiconductor, the electrical characteristics are prone to change, sometimes reducing reliability. Additionally, hydrogen near the oxygen vacancy forms a defect where hydrogen enters the oxygen vacancy (sometimes referred to below as V). O H), electrons that can become charge carriers may be generated even without applying a voltage to the gate electrode of the transistor. Therefore, when oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor exhibits always-on characteristics (the characteristic that current flows through the transistor even without applying a voltage to the gate electrode). Thus, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V. O H. In other words, preferably, the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is either intrinsically or substantially eigentyped without applying a voltage to the gate electrode of the transistor.

[0116] In contrast, by performing heat treatment with an insulator containing oxygen that has been removed by heating (hereinafter, sometimes referred to as excess oxygen) near the oxide semiconductor, oxygen can be supplied to the oxide semiconductor from the insulator, thereby reducing oxygen vacancies and V. O H. Note that supplying excessive oxygen to the source or drain region may cause a decrease in the on-state current or field-effect mobility of transistor 200. Furthermore, when the oxygen supplied to the source or drain region is non-uniform within the substrate surface, non-uniformity occurs in the semiconductor device characteristics, including those of the transistor.

[0117] Therefore, it is preferable that, in the oxide semiconductor, the carrier concentrations of regions 232d and 232e, which are used as channel formation regions, are reduced and are i-typed or substantially i-typed. On the other hand, it is preferable that regions 232a, 232b, and 232c, which are used as source or drain regions, have high carrier concentrations and are n-typed. In other words, it is preferable to reduce the oxygen vacancies and Vo in regions 232d and 232e of the oxide semiconductor. O H. And do not supply excessive oxygen to regions 232a, 232b and 232c.

[0118] Therefore, in this embodiment, with conductors 242a, 242b, and 242c disposed on oxide 230b, microwave treatment is performed in an oxygen-containing atmosphere to reduce oxygen vacancies and V in regions 232d and 232e. O H. Here, microwave processing refers, for example, to processing using a device that includes a power source that utilizes microwaves to generate high-density plasma.

[0119] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high-frequency radio waves (RF), thus enabling the oxygen plasma to act. At this time, regions 232d and 232e can also be irradiated with microwaves or RF. Through the action of plasma, microwaves, etc., the Vo of regions 232d and 232e can be increased. O H separates, removing hydrogen (H) from regions 232d and 232e, and filling oxygen vacancies with oxygen (V). O In other words, "V" occurs in regions 232d and 232e. O H→H+V O The reaction reduces the hydrogen concentration in regions 232d and 232e. This, in turn, reduces oxygen vacancies and V in regions 232d and 232e. O H reduces carrier concentration.

[0120] Furthermore, when microwave processing is performed in an oxygen-containing atmosphere, the effects of high frequencies such as microwaves or RF, and oxygen plasma, are shielded by conductors 242a, 242b, and 242c and do not affect regions 232a, 232b, and 232c. Moreover, the effects of oxygen plasma can be reduced by covering oxide 230b and insulators 275 and 280 of conductor 242. Therefore, since V does not occur in regions 232a, 232b, and 232c during microwave processing... O The reduction of H and the excessive supply of oxygen can prevent the decrease in carrier concentration.

[0121] As described above, oxygen vacancies and V can be selectively removed by regions 232d and 232e of the oxide semiconductor. OH makes regions 232d and 232e i-type or substantially i-type. Furthermore, it can suppress excessive oxygen supply to regions 232a, 232b, and 232c, which are used as source or drain regions, thus maintaining an n-type configuration. Therefore, variations in the electrical characteristics of the transistor 200 can be suppressed, and non-uniformity in the electrical characteristics of the transistor 200 within the substrate surface can be suppressed. Moreover, by making region 232b a low-resistance n-type region, good contact with the conductor 248 can be formed.

[0122] By adopting the above structure, a semiconductor device with small transistor characteristic non-uniformity can be provided. Furthermore, a semiconductor device with good electrical characteristics can be provided. Additionally, a semiconductor device with high reliability can be provided.

[0123] In Figure 1, the side of the opening (including the groove of oxide 230b) into which the conductor 260 is embedded is substantially perpendicular to the surface on which oxide 230b is formed; however, this embodiment is not limited to this. For example, the bottom of the opening may also be a U-shaped form with a gently curved surface. Additionally, for example, the side of the opening may be inclined to the surface on which oxide 230b is formed.

[0124] In addition, such as FIG. 1C As shown, when viewed in cross-section of the channel width of transistor 200, a curved surface may also be present between the side surface and the top surface of oxide 230b. That is, the ends of the side surface and the ends of the top surface may also be curved (hereinafter also referred to as circular).

[0125] The radius of curvature of the aforementioned curved surface is preferably greater than 0 nm and less than the thickness of the oxide 230b in the region overlapping with the conductor 242, or less than half the length of the region without the aforementioned curved surface. Specifically, the radius of curvature of the aforementioned curved surface is greater than 0 nm and less than 20 nm, preferably more than 1 nm and less than 15 nm, and more preferably more than 2 nm and less than 10 nm. By adopting the above shape, the coverage of the oxide 230b of the insulator 250 and the conductor 260 can be improved.

[0126] Oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, the atomic ratio of element M, relative to the main metal element, in the metal oxide used for oxide 230a is preferably greater than that in the metal oxide used for oxide 230b. Furthermore, the atomic ratio of In to element M in the metal oxide used for oxide 230a is preferably greater than that in the metal oxide used for oxide 230b. Also, the atomic ratio of In to element M in the metal oxide used for oxide 230b is preferably greater than that in the metal oxide used for oxide 230a.

[0127] Furthermore, oxide 230b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (oxygen vacancies, etc.). Therefore, oxygen extraction from the source electrode or drain electrode from oxide 230b can be suppressed. Thus, even with heat treatment, oxygen extraction from oxide 230b can be reduced, and the transistor 200 remains stable even at high temperatures (so-called thermal budget) during the manufacturing process.

[0128] Here, at the junction of oxides 230a and 230b, the conduction band bottom changes gradually. In other words, the above situation can also be expressed as the conduction band bottom at the junction of oxides 230a and 230b changing continuously or continuously joined. For this purpose, it is preferable to reduce the defect state density of the mixed layer formed at the interface of oxides 230a and 230b.

[0129] Specifically, by making oxides 230a and 230b contain a common element as a main component in addition to oxygen, a mixed layer with low defect state density can be formed. For example, when oxide 230b is an In-M-Zn oxide, oxides 230a can also be In-M-Zn oxides, M-Zn oxides, oxides of element M, In-Zn oxides, indium oxides, etc.

[0130] Specifically, oxide 230a can be a metal oxide with an In:M:Zn ratio of 1:3:4 or similar, or an In:M:Zn ratio of 1:1:0.5 or similar. Alternatively, oxide 230b can be a metal oxide with an In:M:Zn ratio of 1:1:1 or similar, or an In:M:Zn ratio of 4:2:3 or similar. Note that "similar" includes a range of ±30% of the desired atomic ratio. Furthermore, gallium is preferably used as element M.

[0131] Furthermore, when forming metal oxides by sputtering, the aforementioned atomic ratio is not limited to the atomic ratio of the metal oxides formed, but can also be the atomic ratio of the sputtering target used to form the metal oxides.

[0132] By giving oxides 230a and 230b the aforementioned structure, the defect state density at the interface between oxides 230a and 230b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, resulting in high on-state current and high-frequency characteristics in transistor 200.

[0133] At least one of insulators 212, 214, 275, 282, and 283 is preferably used as a barrier insulating film to suppress the diffusion of impurities such as water and hydrogen from the substrate side or above the transistor 200 to the transistor 200. Therefore, at least one of insulators 212, 214, 275, 282, and 283 is preferably an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (making it difficult for the aforementioned impurities to permeate). Furthermore, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (making it difficult for the aforementioned oxygen to permeate).

[0134] In addition, in this specification, "barrier insulating film" refers to an insulating film with barrier properties. Note that in this specification, barrier properties refer to the function of inhibiting the diffusion of the corresponding substance (or low permeability). Alternatively, it refers to the function of capturing and fixing the corresponding substance (also known as gettering).

[0135] As insulators 212, 214, 275, 282, and 283, materials such as aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride can be used. For example, silicon nitride, which has higher hydrogen barrier properties, is preferred as insulator 212 and 283. Furthermore, aluminum oxide, which has high hydrogen trapping and fixation performance and high oxygen barrier properties, is preferred as insulator 214, 275, and 282. This suppresses the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side via insulators 212 and 214. It also suppresses the diffusion of impurities such as water and hydrogen from the interlayer insulating film disposed outside insulator 283 to the transistor 200 side. Additionally, it suppresses the diffusion of oxygen contained in insulator 224, etc., from insulator 212 and 214 to the substrate side. Alternatively, the diffusion of oxygen contained in insulator 280 through insulator 282 or the like to the top of transistor 200 can be suppressed. Thus, it is preferable to adopt a structure in which transistor 200 is surrounded by insulator 212, insulator 214, insulator 275, insulator 282 and insulator 283, which have the function of suppressing the diffusion of impurities such as water and hydrogen and oxygen.

[0136] Films of insulators 212, 214, 275, 282, and 283 can be formed, for example, by sputtering. Sputtering does not require hydrogen as the film-forming gas, thus reducing the hydrogen concentration in insulators 212, 214, 275, 282, and 283. Besides sputtering, other suitable film-forming methods include chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD).

[0137] Additionally, it is sometimes preferable to reduce the resistivity of insulators 212 and 283. For example, by making the resistivity of insulators 212 and 283 approximately 1 × 10⁻⁶. 13 In semiconductor device manufacturing processes using plasma or similar methods, insulators 212 and 283 can sometimes mitigate charge buildup in conductors 205, 242, or 260. The resistivity of insulators 212 and 283 is 1 × 10⁻⁶ Ωcm. 10 Ωcm or more and 1×10 15 Below Ωcm.

[0138] Furthermore, the dielectric constants of insulators 216 and 280 are preferably lower than those of insulator 214. By using materials with low dielectric constants for the interlayer film, parasitic capacitances generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide can be appropriately used as insulators 216 and 280.

[0139] In transistors 200a and 200b, conductor 205 is arranged to overlap with oxide 230 and conductor 260. For example... FIG. 1A As shown, the conductor 205 can extend in the A3-A4 direction. Furthermore, the conductor 205 is preferably disposed in an opening in the insulator 216. A portion of the conductor 205 may also be disposed in an insulator 214.

[0140] Conductor 205 includes conductor 205a, conductor 205b, and conductor 205c. Conductor 205a contacts the bottom surface and sidewalls of the opening. Conductor 205b is disposed in a recess formed in conductor 205a. Here, the top surface of conductor 205b is lower than the top surface of conductor 205a and the top surface of insulator 216. Conductor 205c contacts the top surface of conductor 205b and the side surface of conductor 205a. Here, the height of the top surface of conductor 205c is approximately the same as the height of the top surface of conductor 205a and the top surface of insulator 216. In other words, conductor 205b is surrounded by conductor 205a and conductor 205c.

[0141] Here, conductive materials that suppress the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms are preferably used as conductors 205a and 205c. Furthermore, conductive materials that suppress the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) are preferably used.

[0142] By using a conductive material that inhibits hydrogen diffusion as conductors 205a and 205c, impurities such as hydrogen contained in conductor 205b can be prevented from diffusing to oxide 230 through insulator 224. Furthermore, by using a conductive material that inhibits oxygen diffusion as conductors 205a and 205c, oxidation of conductor 205b and subsequent decrease in conductivity can be prevented. Examples of conductive materials that inhibit oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, single-layer or multi-layered conductive materials can be used as conductors 205a and 205c. For example, titanium nitride can be used as conductors 205a and 205c.

[0143] Furthermore, the conductor 205b is preferably made of a conductive material with tungsten, copper, or aluminum as its main components. For example, tungsten can be used for the conductor 205b.

[0144] Conductor 205 is sometimes used as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by changing the potential applied to conductor 205 independently of the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, the Vth of transistor 200 can be further increased, thereby reducing the off-state current. Thus, compared to not applying a negative potential to conductor 205, applying a negative potential to conductor 205 can reduce the drain current when the potential applied to conductor 260 is 0V.

[0145] Furthermore, the resistivity of the conductor 205 is designed based on the potential applied to the conductor 205 as described above, and the thickness of the conductor 205 is set according to this resistivity. Additionally, the thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to reduce the thickness of both the conductor 205 and the insulator 216 within the design limits of the conductor 205. By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thus suppressing the diffusion of these impurities into the oxide 230.

[0146] In addition, such as FIG. 1A As shown, the conductor 205 is preferably larger than the region in the oxide 230 that does not overlap with conductors 242a and 242b. In particular, as FIG. 1C As shown, conductor 205 preferably extends to the region outside the ends of oxides 230a and 230b that intersect the channel width direction. That is, conductor 205 and conductor 260 preferably overlap with an insulator on the outer side of the side of oxide 230 in the channel width direction. With the above structure, a region can be formed around the channel of oxide 230 by the electric field of conductor 260, which serves as the first gate electrode, and the electric field of conductor 205, which serves as the second gate electrode. In this specification, the transistor structure in which the electric fields of the first gate and the second gate form a region around the channel is referred to as a surround-channel (S-channel) structure.

[0147] In this specification, an S-channel transistor refers to a transistor structure in which an electric field from one of a pair of gate electrodes surrounds a channel forming a region. Furthermore, the S-channel structure disclosed in this specification differs from Fin-type and planar structures. By employing an S-channel structure, transistors with improved tolerance to short-channel effects can be realized; in other words, transistors less prone to short-channel effects can be achieved.

[0148] In addition, such as FIG. 1C As shown, conductor 205 is extended to be used as wiring. However, the invention is not limited to this; conductors used for wiring may also be provided under conductor 205. Furthermore, it is not necessary to provide a conductor 205 in every transistor. For example, conductor 205 can be shared in multiple transistors.

[0149] Note that the conductor 205 shown is a structure consisting of stacked conductors 205a, 205b, and 205c, but the present invention is not limited thereto. The conductor 205 can have a single-layer structure or a stacked structure with two or more layers. For example, when the conductor 205 has a two-layer stacked structure, a structure can be adopted where the top surface of conductor 205a is aligned with the top surface of conductor 205b without conductor 205c.

[0150] Like conductor 205, conductor 248 may also include conductor 248a and conductor 248b disposed inside conductor 248a. As conductor 248a, any conductor suitable for conductor 205a can be used, preferably a conductor that reduces the permeation of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc., can be used. Furthermore, conductor 248a can be a conductor with good adhesion to conductor 248b. As conductor 248b, any conductor suitable for conductor 205b can be used, preferably a conductive material with tungsten, copper, or aluminum as its main component.

[0151] In addition, FIG. 1A In the top view, the conductor 248 has a circular shape, but is not limited to this. For example, in the top view, the conductor 248 may also have a roughly circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a shape in which the corners of the polygonal shape such as a quadrilateral are rounded.

[0152] Note that while the conductor 248 is shown as a structure of stacked conductors 248a and 248b, the present invention is not limited thereto. The conductor 248 may have a single-layer structure or a stacked structure of three or more layers. For example, similar to conductor 205c, a conductor identical to that of conductor 205a may be disposed between the top surface of conductor 248b and oxide 230.

[0153] The insulator 249 is provided in contact with the inner wall of the openings of insulators 212, 214, 216, 222, and 224, and the conductor 248 is provided in contact with the side of the insulator 249. As the insulator 249, an insulator that reduces the diffusion of impurities such as hydrogen or water, as well as oxygen, is preferably used, such as silicon nitride, aluminum oxide, or silicon oxynitride. This suppresses the mixing of impurities such as water and hydrogen contained in insulators 216 into oxide 230 via the conductor 248. In particular, silicon nitride is preferred because it has high hydrogen barrier properties. Furthermore, it prevents oxygen contained in insulator 216 from being absorbed by the conductor 248. Note that the structure is not limited to the above; a structure without the insulator 249 may also be used.

[0154] Insulators 222 and 224 are used as gate insulators.

[0155] Insulator 222 preferably has the function of inhibiting the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). Furthermore, insulator 222 preferably has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, compared to insulator 224, insulator 222 preferably has the function of inhibiting the diffusion of one or both of hydrogen and oxygen.

[0156] The insulator 222 is preferably an oxide containing one or both of aluminum and hafnium, used as the insulating material. Aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are preferred as this insulator. When this material is used to form the insulator 222, it serves as a layer to suppress the release of oxygen from the oxide 230 to the substrate side or the diffusion of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230. Therefore, by providing the insulator 222, the diffusion of impurities such as hydrogen into the inner side of the transistor 200 can be suppressed, and the generation of oxygen vacancies in the oxide 230 can be suppressed. Furthermore, the reaction between the conductor 205 and the oxygen contained in the insulator 224 or the oxide 230 can be suppressed.

[0157] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, the insulator may be nitrided. Furthermore, silicon oxide, silicon oxynitride, or silicon nitride may be laminated onto the insulator 222.

[0158] Furthermore, as the insulator 222, high-k materials such as alumina, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST) can be used as a single layer or in a stack. When miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0159] Here, the insulator 224 in contact with the oxide 230 preferably contains excess oxygen (oxygen is removed by heating). For example, silicon oxide, silicon oxynitride, etc., can be appropriately used as the insulator 224. By providing the above-mentioned oxygen-containing insulator in a manner that contacts the oxide 230, oxygen vacancies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200.

[0160] Specifically, the insulator 224 preferably uses an oxide material that undergoes partial oxygen removal upon heating, i.e., an insulator material with an excess oxygen region. An oxide that undergoes oxygen removal upon heating is defined as one in which the amount of oxygen molecules removed in TDS (Thermal Desorption Spectroscopy) analysis is 1.0 × 10⁻⁶. 18 molecules / cm 3 The preferred value is 1.0 × 10⁴. 19 molecules / cm 3 The above is further preferred to be 2.0×10 19 molecules / cm 3 Above, or 3.0 × 10 20 molecules / cm 3 The above-mentioned oxide film. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0161] Furthermore, in the manufacturing process of transistor 200, heat treatment is preferably performed with the surface of oxide 230 exposed. This heat treatment is preferably performed at a temperature of 100°C or higher and 600°C or lower, more preferably at 350°C or higher and 550°C or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to oxide 230, thereby reducing oxygen vacancies (V0). OHeat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in a nitrogen or inert gas atmosphere, followed by heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the released oxygen. Alternatively, heat treatment can be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, followed by continuous heat treatment in a nitrogen or inert gas atmosphere.

[0162] By subjecting oxide 230 to oxidation treatment, the supplied oxygen can fill the oxygen vacancies in oxide 230, in other words, it can promote the "V" oxidation process. O The reaction "+O→null" is observed. Furthermore, the hydrogen remaining in oxide 230 reacts with the supplied oxygen to remove the hydrogen as H2O (dehydration). This inhibits the recombination of hydrogen and oxygen vacancies in oxide 230 to form V. O H.

[0163] Furthermore, insulators 222 and 224 may also have a multilayer structure with two or more layers. In this case, it is not limited to a multilayer structure made of the same material; it can also be a multilayer structure made of different materials. Additionally, insulator 224 may be formed as an island and overlap with oxide 230a. In this case, insulator 275 contacts the side surface of insulator 224 and the top surface of insulator 222.

[0164] Oxides 243a, 243b, and 243c are disposed on oxide 230b. Oxides 243a, 243b, and 243c are arranged in the A1-A2 direction and are separated by a conductor 260.

[0165] Oxides 243 (oxides 243a, 243b, and 243c) preferably have the function of suppressing oxygen permeation. By distributing oxide 243, which has the function of suppressing oxygen permeation, between the conductor 242, which is used as a source electrode or drain electrode, and oxide 230b, the resistance between the conductor 242 and oxide 230b is reduced, which is therefore preferred. By adopting such a structure, the electrical characteristics and reliability of the transistor 200 can be improved. Alternatively, if the resistance between the conductor 242 and oxide 230b can be sufficiently reduced, oxide 243 may not be necessary.

[0166] Metal oxides containing element M can also be used as oxide 243. In particular, aluminum, gallium, yttrium, or tin are preferably used as element M. The concentration of element M in oxide 243 is preferably higher than that in oxide 230b. Furthermore, gallium oxide can also be used as oxide 243. In addition, metal oxides such as In-M-Zn oxide can also be used as oxide 243. Specifically, the atomic ratio of In to element M in the metal oxide used for oxide 243 is preferably greater than that in the metal oxide used for oxide 230b. Furthermore, the thickness of oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and even more preferably 1 nm or more and 2 nm or less. In addition, oxide 243 is preferably crystalline. When oxide 243 is crystalline, the release of oxygen in oxide 230 can be appropriately suppressed. For example, when oxide 243 has a hexagonal crystal structure, the release of oxygen in oxide 230 can sometimes be suppressed.

[0167] Preferably, conductor 242a is in contact with the top surface of oxide 243a, conductor 242b is in contact with the top surface of oxide 243b, and conductor 242c is in contact with the top surface of oxide 243c. Conductors 242a, 242b, and 242c are arranged in the A1-A2 direction and separated from each other by conductor 260. Conductors 242a, 242b, and 242c are respectively used as the source electrode or drain electrode of transistor 200a or transistor 200b.

[0168] As conductors 242 (conductors 242a, 242b, and 242c), nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, and nitrides containing titanium and aluminum are preferably used. In one aspect of the invention, nitrides containing tantalum are particularly preferred. Furthermore, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel may also be used, for example. These materials are preferred because they are conductive materials that are not easily oxidized or maintain conductivity even when absorbing oxygen.

[0169] Note that sometimes hydrogen contained in oxides 230b, etc., diffuses into conductors 242a, 242b, and 242c. In particular, by using tantalum-containing nitrides as conductors 242a, 242b, and 242c, hydrogen contained in oxides 230b, etc., readily diffuses into conductors 242a, 242b, and 242c, and this diffused hydrogen bonds with the nitrogen contained in conductors 242a, 242b, and 242c. That is, sometimes hydrogen contained in oxides 230b, etc., is absorbed by conductors 242a, 242b, and 242c.

[0170] Furthermore, it is preferable that no curved surface is formed between the side surface and the top surface of the conductor 242. By eliminating this curved surface in the conductor 242, the following can be achieved: FIG. 1D The cross-sectional area of ​​the conductor 242 in the channel width direction is shown. This increases the conductivity of the conductor 242, thereby increasing the on-state current of the transistor 200.

[0171] Insulator 275 covers insulator 224, oxide 230, oxide 243, and conductor 242, forming openings in the areas where insulator 250 and conductor 260 will be disposed. Insulator 275 preferably contacts the top surface of insulator 224, the side surface of oxide 230, the side surface of oxide 243, the side surface of conductor 242, and the top surface of conductor 242. Furthermore, insulator 275 is preferably used as a barrier insulating film to suppress oxygen permeation. Additionally, insulator 275 is preferably used as a barrier insulating film to suppress the diffusion of impurities such as water and hydrogen from above into insulator 224 or oxide 230, and has the function of trapping impurities such as hydrogen. As insulator 275, insulators such as alumina or silicon nitride are preferably used, for example.

[0172] By providing an insulator 275, which is in contact with insulators 280 and 224 and has the function of trapping impurities such as hydrogen, in the region sandwiched between insulators 212 and 283, impurities such as hydrogen contained in insulators 280 and 224 can be trapped, and the amount of hydrogen in that region can be set to a certain value. In this case, alumina or the like is preferably used as the insulator 275.

[0173] like FIG. 1AAs shown, insulator 250 extends along the A3-A4 direction and is used as the gate insulator for transistors 200a and 200b. In transistors 200a and 200b, insulator 250 is preferably arranged in contact with the top and side surfaces of oxide 230b. Insulator 250 can be silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen added, porous silicon oxide, etc. In particular, silicon oxide and silicon oxynitride have thermal stability and are therefore preferred.

[0174] Similar to insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in insulator 250 is reduced. The thickness of insulator 250 is preferably 1 nm or more and 20 nm or less.

[0175] Note that in FIG. 1B and FIG. 1C The structure of insulator 250 is shown as a single layer, but it can also be a stacked structure of two or more layers. When the structure of insulator 250 is a stacked structure of two layers, it is preferable that the lower layer of insulator 250 is formed using an insulator that releases oxygen upon heating, and the upper layer of insulator 250 is formed using an insulator that has the function of suppressing oxygen diffusion. By adopting this structure, the diffusion of oxygen contained in the lower layer of insulator 250 to conductor 260 can be suppressed. In other words, the reduction of the amount of oxygen supplied to oxide 230 can be suppressed. Furthermore, the oxidation of conductor 260 caused by oxygen contained in the lower layer of insulator 250 can be suppressed. For example, the lower layer of insulator 250 can be provided with a material suitable for the above-described insulator 250, and the upper layer of insulator 250 can be provided with the same material as insulator 222.

[0176] Note that when the lower layer of insulator 250 is formed using silicon oxide or silicon oxynitride, the upper layer of insulator 250 can also be formed using an insulating material with a high relative permittivity (high-k). By employing a stacked structure of the lower and upper layers of insulator 250 as the gate insulator, a stacked structure with thermal stability and a high relative permittivity can be formed. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0177] Specifically, as the upper layer of insulator 250, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or metal oxides suitable for use in oxide 230, can be used. In particular, it is preferable to use an insulator containing one or both of aluminum and hafnium oxides. For example, hafnium oxide can be used as the upper layer of insulator 250.

[0178] Alternatively, a metal oxide may be disposed between the insulator 250 and the conductor 260. This metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By disposing of a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 due to oxygen contained in the insulator 250 can be suppressed.

[0179] Alternatively, the aforementioned metal oxide can also be used as part of the first gate electrode. For example, a metal oxide suitable for oxide 230 can be used as the aforementioned metal oxide. In this case, by forming the conductor 260a using a sputtering method, the resistance value of the aforementioned metal oxide can be reduced, making it a conductor. The aforementioned conductor can be referred to as an OC (Oxide Conductor) electrode.

[0180] By incorporating the aforementioned metal oxide, the on-state current of transistor 200 can be increased without reducing the influence of the electric field from conductor 260. Furthermore, by maintaining the distance between conductor 260 and oxide 230 using the physical thickness of insulator 250 and the aforementioned metal oxide, leakage current between conductor 260 and oxide 230 can be suppressed. Additionally, by providing a stacked structure of insulator 250 and the aforementioned metal oxide, the physical distance between conductor 260 and oxide 230, as well as the electric field strength applied from conductor 260 to oxide 230, can be easily adjusted.

[0181] like FIG. 1A As shown, conductor 260 extends along the A3-A4 direction and serves as the first gate electrode of transistors 200a and 200b. In transistors 200a and 200b, conductor 260 preferably includes conductor 260a and conductor 260b disposed on conductor 260a. For example, conductor 260a is preferably disposed in a manner that surrounds the bottom and side surfaces of conductor 260b. Furthermore, as... FIG. 1B and FIG. 1C As shown, the top surface of the conductor 260 is approximately aligned with the top surface of the insulator 250. Although in FIG. 1B and FIG. 1C The intermediate conductor 260 has a two-layer structure of conductor 260a and conductor 260b, but it can also have a single-layer structure or a stacked structure of three or more layers.

[0182] Here, the conductor 260a preferably uses a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. In addition, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

[0183] Furthermore, when the conductor 260a has the function of inhibiting oxygen diffusion, it can prevent the oxygen contained in the insulator 250 from oxidizing the conductor 260b and causing a decrease in conductivity. Examples of conductive materials with the function of inhibiting oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0184] Furthermore, since conductor 260 is also used for wiring, a conductor with high conductivity is preferred. For example, conductor 260b can be a conductive material with tungsten, copper, or aluminum as the main component. In addition, conductor 260b can have a multilayer structure, for example, it can have a multilayer of titanium, titanium nitride, and the aforementioned conductive material.

[0185] Furthermore, in transistor 200, conductor 260 is formed in a self-aligned manner by filling the openings formed in insulator 280, etc. By forming conductor 260 in this way, conductor 260 can be arranged without alignment in the region between conductor 242a and conductor 242b and in the region between conductor 242b and conductor 242c.

[0186] In addition, such as FIG. 1C As shown, in the channel width direction of transistor 200, with the bottom surface of insulator 222 as a reference, the height of the bottom surface of the region where conductor 260 does not overlap with oxide 230b is preferably lower than the height of the bottom surface of oxide 230b. By adopting a structure in which conductor 260, used as a gate electrode, covers the side and top surfaces of the channel formation region of oxide 230b through insulator 250, the electric field of conductor 260 can easily act on the entire channel formation region of oxide 230b. This improves the on-state current and frequency characteristics of transistor 200. With the bottom surface of insulator 222 as a reference, the difference between the height of the bottom surface of conductor 260 and the height of the bottom surface of oxide 230b in the region where oxide 230a and oxide 230b do not overlap with conductor 260 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0187] An insulator 280 is disposed on an insulator 275, and an opening is formed in the region where the insulator 250 and the conductor 260 are disposed. Furthermore, the top surface of the insulator 280 may be planarized.

[0188] Preferably, the insulator 280 used as the interlayer film has a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between the wirings can be reduced. The insulator 280 is preferably formed, for example, using the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability. Especially, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are preferred because they readily form regions containing oxygen that has been released through heating.

[0189] Similar to insulator 224, insulator 280 preferably contains excess oxygen regions or excess oxygen. Furthermore, the concentration of impurities such as water and hydrogen in insulator 280 is preferably reduced. For example, silicon oxide, silicon oxynitride, etc., can be appropriately used as insulator 280. By providing an insulator containing excess oxygen in contact with oxide 230, oxygen vacancies in oxide 230 can be reduced, thereby improving the reliability of transistor 200.

[0190] The insulator 282 is arranged in contact with the conductor 260, the top surface of the insulator 280, and the uppermost part of the insulator 250. The insulator 282 is preferably used as a barrier insulating film to inhibit the diffusion of impurities such as water and hydrogen from above into the insulator 280 and also has the function of trapping impurities such as hydrogen. Furthermore, the insulator 282 is preferably used as a barrier insulating film to inhibit oxygen permeation. For example, an insulator such as alumina can be used as the insulator 282. By providing an insulator 282 in contact with the insulator 280 and having the function of trapping impurities such as hydrogen in the region sandwiched between the insulator 212 and the insulator 283, impurities such as hydrogen contained in the insulator 280 can be trapped, and the amount of hydrogen in that region can be kept constant.

[0191] Insulator 283 can be used as a barrier insulating film to prevent impurities such as water and hydrogen from diffusing from above into insulator 280. Insulator 283 is disposed on insulator 282. As insulator 283, silicon-containing nitrides such as silicon nitride or silicon oxynitride are preferably used. For example, silicon nitride formed by sputtering is used as insulator 283. By forming insulator 283 by sputtering, a silicon nitride film with high density and low susceptibility to voids can be formed. Alternatively, as insulator 283, silicon nitride formed by CVD may also be stacked on top of silicon nitride formed by sputtering.

[0192] Materials Constituting Semiconductor Devices

[0193] The following describes the constituent materials that can be used in semiconductor devices.

[0194] <<Substrate>>

[0195] For example, insulating substrates, semiconductor substrates, or conductive substrates can be used as substrates for forming the transistor 200. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium-stabilized zirconium oxide substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Additionally, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements.

[0196] <<Insulators>>

[0197] As insulators, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, etc., which have insulating properties.

[0198] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, low voltage can be achieved during transistor operation while maintaining the physical thickness. On the other hand, by using a material with a relatively low permittivity as the insulator used as the interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulator.

[0199] Examples of insulators with relatively high permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0200] Examples of insulators with relatively low permittivity include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide or resin with pores.

[0201] Furthermore, by surrounding a transistor using metal oxides with an insulator that suppresses the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Examples of insulators that suppress the permeation of impurities such as hydrogen and oxygen include single layers or stacks of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride, can be used as insulators that suppress the permeation of impurities such as hydrogen and oxygen.

[0202] Furthermore, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that has been removed by heating. For example, by employing a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that has been removed by heating is contacted with the oxide 230, the oxygen vacancies contained in the oxide 230 can be filled.

[0203] <<Conductors>>

[0204] As a conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even after absorbing oxygen, and are therefore preferred. In addition, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides can also be used.

[0205] Alternatively, multiple conductive layers formed from the above-described materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Alternatively, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Alternatively, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0206] Furthermore, when using oxides in the channel formation region of a transistor, a stacked structure combining a material containing the aforementioned metallic elements and an oxygen-containing conductive material is preferably used as the conductor serving as the gate electrode. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0207] In particular, as the conductor used as the gate electrode, a conductive material containing a metal element and oxygen contained in the metal oxide in which the channel is formed is preferably used. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, nitrogen-containing conductive materials such as titanium nitride or tantalum nitride can be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon can also be used. By using the above materials, hydrogen contained in the metal oxide in which the channel is formed can sometimes be trapped. Or, hydrogen mixed in from external insulators or the like can sometimes be trapped.

[0208] <<Metal Oxides>>

[0209] As oxide 230, a metal oxide (oxide semiconductor) that is used as a semiconductor is preferably used. Hereinafter, a metal oxide that can be used as oxide 230 according to the present invention will be described.

[0210] The metal oxide preferably contains at least indium or zinc. It is particularly preferred to contain both indium and zinc. In addition, it preferably also contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.

[0211] This section considers the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Note that element M is selected from one or more of aluminum, gallium, yttrium, and tin. Other elements that can be used with element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. Note that multiple of the above elements can sometimes be combined as element M.

[0212] In addition, in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Furthermore, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0213] <Classification of Crystal Structures>

[0214] First, the classification of crystal structures in oxide semiconductors is referenced.FIG. 3A Please provide an explanation. FIG. 3A This is a diagram illustrating the classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0215] like FIG. 3A As shown, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." Completely amorphous is included within "Amorphous." "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and poly crystal). However, the "Crystalline" classification does not include single crystal, poly crystal, or completely amorphous. "Crystal" includes both single crystal and poly crystal.

[0216] in addition, FIG. 3A The structure shown in the thickened section of the outline is an intermediate state between "amorphous" and "crystal," belonging to a novel boundary region (New crystalline phase). In other words, this structure is completely different from "crystal" or the energetically unstable "amorphous."

[0217] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. FIG. 3B The XRD pattern of a CAAC-IGZO film classified as "Crystalline" is shown, obtained by GIXD (Grazing-Incidence XRD) measurement. GIXD is also known as the thin film method or the Seemann-Bohlin method. Below, we will... FIG. 3B The XRD spectrum obtained by the GIXD measurement shown is simply denoted as the XRD spectrum. Additionally, FIG. 3B The CAAC-IGZO film shown has a composition of approximately In:Ga:Zn = 4:2:3 [atomic ratio]. Additionally, FIG. 3BThe thickness of the CAAC-IGZO film shown is 500 nm.

[0218] like FIG. 3B As shown, peaks indicating clear crystallinity were detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation was detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Furthermore, as... FIG. 3B As shown, the peak value near 2θ = 31° is asymmetrical about the angle at which the peak intensity is detected.

[0219] In addition, the crystal structure of the film or substrate can be evaluated using diffraction patterns observed by nanobeam electron diffraction (NBED). FIG. 3C The diffraction pattern of the CAAC-IGZO film is shown. FIG. 3C This is a diffraction pattern observed using an NBED (NB-ED) where an electron beam is incident parallel to the substrate. Additionally, FIG. 3C The CAAC-IGZO film shown has an In:Ga:Zn ratio of approximately 4:2:3 [atomic number ratio]. Furthermore, electron diffraction with a beam diameter of 1 nm was performed using nanobeam electron diffraction.

[0220] like FIG. 3C As shown, multiple spots indicating c-axis orientation were observed in the diffraction pattern of the CAAC-IGZO film.

[0221] <<Structure of Oxide Semiconductors>>

[0222] Furthermore, when focusing on the crystal structure of oxide semiconductors, sometimes the classification of oxide semiconductors is related to... FIG. 3A They are different. For example, oxide semiconductors can be classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS and nc-OS, as mentioned above. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors, etc.

[0223] Here, we will explain the details of CAAC-OS, nc-OS, and a-like OS.

[0224] [CAAC-OS]

[0225] CAAC-OS is an oxide semiconductor comprising multiple crystalline regions, whose c-axis is oriented in a specific direction. This specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the formed surface of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film. Furthermore, a crystalline region is a region exhibiting a periodic atomic arrangement. Note that when atomic arrangement is considered as lattice arrangement, a crystalline region is also a region with a consistent lattice arrangement. Moreover, CAAC-OS has regions where multiple crystalline regions are connected along the ab-plane direction, and sometimes these regions exhibit distortion. Distortion refers to the portion of the lattice arrangement direction that changes between regions with consistent lattice arrangement and other regions with consistent lattice arrangement within the region where multiple crystalline regions are connected. In other words, CAAC-OS refers to an oxide semiconductor with c-axis orientation but no obvious orientation along the ab-plane direction.

[0226] Furthermore, each of the aforementioned multiple crystalline regions is composed of one or more microcrystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single microcrystal, the maximum diameter of that region is less than 10 nm. Conversely, when a crystalline region is composed of multiple microcrystals, the size of that region can sometimes be around tens of nm.

[0227] Furthermore, in In-M-Zn oxides (where element M is selected from one or more of aluminum, gallium, yttrium, tin, and titanium), CAAC-OS tends to have a layered crystal structure (also called a layered structure) comprising layers containing stacked indium (In) and oxygen (hereinafter, In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer). In addition, indium and element M can substitute for each other. Therefore, sometimes the (M, Zn) layer contains indium. Also, sometimes the In layer contains element M. Note that sometimes the In layer contains Zn. This layered structure is observed, for example, as a lattice image in high-resolution TEM images.

[0228] For example, when performing structural analysis on CAAC-OS films using an XRD apparatus, a peak value for c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurements using θ / 2θ scanning. Note that the position (2θ value) representing the peak value for c-axis orientation sometimes varies depending on the type and composition of the metallic elements constituting CAAC-OS.

[0229] Additionally, for example, multiple bright spots (spots) were observed in the electron diffraction pattern of the CAAC-OS film. Furthermore, when the spot of the incident electron beam passing through the sample (also known as the direct spot) is taken as the center of symmetry, one spot and other spots are observed at point-symmetrical positions.

[0230] When observing the crystalline region from the aforementioned specific directions, although the lattice arrangement in this region is primarily hexagonal, the unit lattice is not limited to a regular hexagon; there are also cases of non-regular hexagonal lattice arrangements. Furthermore, pentagonal, heptagonal, and other lattice arrangements are sometimes observed in the aforementioned distortions. Additionally, no clear grain boundaries are observed near the distortions in CAAC-OS. That is, the lattice arrangement distortion inhibits grain boundary formation. This may be because CAAC-OS can tolerate distortions caused by factors such as a low density of oxygen atoms along the ab plane or changes in the interatomic bonding distance due to the substitution of metal atoms.

[0231] Furthermore, a crystalline structure with clearly defined grain boundaries is called polycrystalline. Grain boundaries become recombination centers, trapping charge carriers and potentially leading to a decrease in transistor on-state current and field-effect mobility. Therefore, CAAC-OS, which lacks clearly defined grain boundaries, is one of the crystalline oxides that provides an excellent crystalline structure for the semiconductor layer of a transistor. Note that a structure containing Zn is preferred for constructing CAAC-OS. For example, In-Zn oxides and In-Ga-Zn oxides are preferred because they can further suppress grain boundary formation compared to In oxides.

[0232] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, it can be said that in CAAC-OS, the reduction in electron mobility due to grain boundaries is less likely to occur. Furthermore, the crystallinity of oxide semiconductors can sometimes decrease due to the incorporation of impurities or the formation of defects; therefore, CAAC-OS can be considered an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS exhibit stable physical properties. Thus, oxide semiconductors containing CAAC-OS possess high heat resistance and good reliability. In addition, CAAC-OS is also stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, by using CAAC-OS in OS transistors, the degree of freedom in the manufacturing process can be increased.

[0233] [nc-OS]

[0234] In nc-OS, the atomic arrangement in tiny regions (e.g., regions larger than 1 nm and smaller than 10 nm, particularly regions larger than 1 nm and smaller than 3 nm) exhibits periodicity. In other words, nc-OS possesses tiny crystallinity. Furthermore, for example, these tiny crystallins, with sizes between 1 nm and 10 nm, and particularly between 1 nm and 3 nm, are referred to as nanocrystals. Additionally, no regularity in crystallization orientation is observed between different nanocrystals in nc-OS. Therefore, no orientation is observed in the overall film. Thus, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods. For example, when performing structural analysis on nc-OS films using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Moreover, when performing electron diffraction (also known as selected area electron diffraction) on nc-OS films using electron beams with beam diameters larger than those of nanocrystals (e.g., larger than 50 nm), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also known as nanobeam electron ray) is performed on nc-OS films using an electron beam whose beam diameter is close to or smaller than the size of nanocrystals (e.g., more than 1 nm and less than 30 nm), sometimes an electron diffraction pattern of multiple spots is observed in a ring-shaped region centered on a direct spot.

[0235] [a-like OS]

[0236] a-like OS is an oxide semiconductor with a structure intermediate between nc-OS and amorphous oxide semiconductors. a-like OS contains voids or low-density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. Furthermore, the hydrogen concentration in a-like OS films is higher than that in nc-OS and CAAC-OS films.

[0237] <<Structure of Oxide Semiconductors>>

[0238] Next, the details of CAC-OS will be explained. Additionally, it will be explained that CAC-OS is related to material composition.

[0239] [CAC-OS]

[0240] CAC-OS, for example, refers to a composition in which elements are unevenly distributed within a metal oxide, wherein the size of the material containing the unevenly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or approximately. Note that below, the state in which one or more metal elements are unevenly distributed within a metal oxide and the regions containing those metal elements are mixed is also referred to as mosaic or patch-like, where the size of the region is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or approximately.

[0241] Furthermore, CAC-OS refers to a structure in which the material is divided into a first region and a second region, forming a mosaic-like structure, with the first region distributed throughout the film (hereinafter also referred to as cloud-like). In other words, CAC-OS refers to a composite metal oxide having a structure that combines the first and second regions.

[0242] Here, each of the atomic ratios of In, Ga, and Zn, the metal elements constituting the CAC-OS in the In-Ga-Zn oxide, is denoted as [In], [Ga], and [Zn]. For example, in the CAC-OS of the In-Ga-Zn oxide, a first region is a region where [In] is greater than [In] in the composition of the CAC-OS film. A second region is a region where [Ga] is greater than [Ga] in the composition of the CAC-OS film. Alternatively, for example, a first region is a region where [In] is greater than [In] in the second region and [Ga] is less than [Ga] in the second region. A second region is a region where [Ga] is greater than [Ga] in the first region and [In] is less than [In] in the first region.

[0243] Specifically, the first region described above is a region whose main component is indium oxide or indium zinc oxide. Furthermore, the second region described above is a region whose main component is gallium oxide or gallium zinc oxide. In other words, the first region can be referred to as a region whose main component is In. The second region can be referred to as a region whose main component is Ga.

[0244] Note that sometimes the clear boundaries between the first region and the second region mentioned above are not observable.

[0245] For example, in CAC-OS of In-Ga-Zn oxide, based on the EDX surface analysis (mapping) image obtained by Energy Dispersive X-ray spectroscopy (EDX), a structure with a non-uniformly distributed and mixed structure of regions with In as the main component (first region) and regions with Ga as the main component (second region) can be identified.

[0246] When CAC-OS is used in transistors, the complementary effect of conductivity arising from the first region and insulation arising from the second region enables CAC-OS to possess switching functionality (the function of controlling conduction / turn-off). In other words, a portion of the CAC-OS material exhibits conductivity while another portion exhibits insulation, resulting in a semiconductor function within the material as a whole. By separating the conductive and insulating functions, the individual functions can be maximized. Therefore, by using CAC-OS in transistors, high on-state current (If) can be achieved. on It has high field-effect mobility (μ) and good switching performance.

[0247] Oxide semiconductors possess various structures and properties. In one embodiment of the present invention, the oxide semiconductor may also include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0248] <Including transistors of oxide semiconductors>

[0249] Here, we will explain the application of the aforementioned oxide semiconductor in transistors.

[0250] By using the aforementioned oxide semiconductors in transistors, transistors with high field-effect mobility can be realized. Furthermore, transistors with high reliability can also be achieved.

[0251] Furthermore, it is preferable to use oxide semiconductors with low carrier concentrations in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is preferably 1 × 10⁻⁶. 18 cm -3 Below, less than 1×10 is preferred. 17 cm -3 More preferably, less than 1×10 16 cm -3 Further optimization of less than 1×10 13 cm -3 More preferably, less than 1×10 12 cm -3 When aiming to reduce the carrier concentration in an oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to decrease the defect state density. In this specification, a state with low impurity concentration and low defect state density is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". Additionally, oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0252] Because high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have a low defect state density, they may have a low trap state density.

[0253] Furthermore, the charge trapped in the trap level of an oxide semiconductor takes a relatively long time to dissipate, sometimes acting like a fixed charge. Therefore, the electrical characteristics of transistors forming channel formation regions in oxide semiconductors with high trap state density are sometimes unstable.

[0254] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. To further reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0255] <Impurities>

[0256] Here, we will explain the effects of various impurities in oxide semiconductors.

[0257] When an oxide semiconductor contains silicon or carbon, one of Group 14 elements, defect energy levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon or carbon in the channel formation region of the oxide semiconductor, and the concentrations of silicon or carbon near the interface between the oxide semiconductor and the channel formation region (measured by secondary ion mass spectrometry (SIMS)) are set to 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 17 atoms / cm 3 the following.

[0258] Furthermore, when oxide semiconductors contain alkali metals or alkaline earth metals, defect energy levels can sometimes form, leading to the formation of charge carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit always-on characteristics. Consequently, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor, as measured by SIMS analysis, is set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0259] When oxide semiconductors contain nitrogen, electrons are readily generated as charge carriers, increasing the charge carrier concentration and resulting in n-type characteristics. Consequently, transistors using nitrogen-containing oxide semiconductors tend to exhibit normally-on characteristics. Alternatively, nitrogen in oxide semiconductors can sometimes lead to the formation of trapped energy levels. This can result in unstable electrical characteristics in the transistors. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor, as measured by SIMS, is set to be below 5 × 10⁻⁶. 19 atoms / cm 3 Preferably 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0260] Hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as charge carriers. Therefore, transistors with hydrogen-containing oxide semiconductors tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the channel formation region of the oxide semiconductor. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration, measured using SIMS, is set to be less than 1 × 10⁻⁶. 20 atoms / cm 3 Preferably below 5×10 19 atoms / cm 3 More preferably, less than 1×10 19 atoms / cm 3 Further optimization of less than 5×10 18 atoms / cm 3 Furthermore, it is preferred to have a value lower than 1×10 18 atoms / cm 3 .

[0261] By using oxide semiconductors with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0262] <<Other Semiconductor Materials>>

[0263] The semiconductor materials that can be used for oxide 230 are not limited to the aforementioned metal oxides. As oxide 230, semiconductor materials with a band gap (semiconductor materials that are not zero-bandgap semiconductors) can also be used. For example, it is preferable to use single-element semiconductors such as silicon, compound semiconductors such as gallium arsenide, or layered materials used as semiconductors (also called atomic-layer materials, two-dimensional materials, etc.). In particular, it is preferable to use layered materials used as semiconductors as semiconductor materials.

[0264] In this specification and other materials, layered materials are a general term for a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked together by bonds weaker than covalent or ionic bonds, such as van der Waals forces. Layered materials exhibit high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material with high two-dimensional conductivity, intended for use as a semiconductor, in the channel formation region, transistors with large on-state currents can be provided.

[0265] As layered materials, examples include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen elements. Furthermore, chalcogen elements are a collective term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and protium. Other examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0266] As oxide 230, transition metal chalcogenides, which are used as semiconductors, are preferably used, for example. Examples of transition metal chalcogenides that can be used as oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0267] <Methods for Manufacturing Semiconductor Devices>

[0268] Next, use FIGS. 4A-12A , FIGS. 4B-12B , FIGS. 4C-12C and FIGS. 4D-12D illustrate FIGS. 1A-1D The invention illustrates a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0269] FIGS. 4A-12A It's a top view. Also, FIGS. 4B-12B It is equivalent to along FIGS. 4A-12A The cross-sectional view along the dotted line A1-A2 in the diagram is also a cross-sectional view along the channel length direction of transistors 200a and 200b. Additionally, FIGS. 4C-12CIt is equivalent to along FIGS. 4A-12A The cross-sectional view along the dotted lines A3-A4 in the diagram is also a cross-sectional view of the channel width direction of transistor 200a. Additionally, FIGS. 4D-12D It is equivalent to along FIGS. 4A-12A The cross-sectional view of lines A5-A6 in the diagram. Note that, for clarity, in... FIGS. 4A-12A Some constituent elements are omitted in the top view.

[0270] The insulating materials used to form insulators, the conductive materials used to form conductors, or the semiconductor materials used to form semiconductors can be appropriately deposited using sputtering, CVD, MBE, PLD, ALD, or other methods.

[0271] Examples of sputtering methods include RF sputtering, which uses a high-frequency power supply, DC sputtering, which uses a DC power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used when forming insulating films, while DC sputtering is mainly used when forming conductive metallic films. Additionally, pulsed DC sputtering is mainly used when forming compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0272] Note that CVD methods can be categorized into plasma-enhanced CVD (PECVD), thermal CVD (TCVD), and photo CVD. Furthermore, they can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0273] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because plasma is not used in thermal CVD, plasma damage to the processed material can be reduced. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes experience charge buildup due to receiving charge from plasma. This accumulated charge can sometimes damage these components. On the other hand, since thermal CVD, which does not use plasma, does not produce this plasma damage, the yield of semiconductor devices can be improved. Additionally, since plasma damage during film formation is eliminated in thermal CVD, films with fewer defects can be obtained.

[0274] As ALD methods, there are thermal ALD (thermal ALD) methods that use only thermal energy to react the precursors and reactants, and PEALD (Plasma Enhanced ALD) methods that use reactants that have been excited by plasma.

[0275] Furthermore, the ALD method leverages the self-adjusting properties of atoms to deposit atoms in each layer, resulting in advantages such as the ability to form extremely thin films, films with high aspect ratios, films with few defects such as pinholes, films with excellent coverage, and films formed at low temperatures. In the PEALD method, the use of plasma allows for film deposition at even lower temperatures, making it sometimes preferred. The precursors used in the ALD method sometimes contain impurities such as carbon. Therefore, films formed using the ALD method sometimes contain more impurities such as carbon compared to films formed using other deposition methods. Furthermore, the quantification of impurities can be measured using X-ray photoelectron spectroscopy (XPS).

[0276] Unlike film deposition methods that use particles released from a target material, CVD and ALD methods form films based on reactions on the surface of the workpiece. Therefore, films formed by CVD and ALD are less affected by the shape of the workpiece and exhibit good step coverage. In particular, films formed by ALD have excellent step coverage and thickness uniformity, making ALD suitable for forming films covering surfaces with high aspect ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes preferred to combine it with other film deposition methods, such as CVD, which has a faster deposition rate.

[0277] The composition of the resulting film can be controlled by adjusting the flow rate ratio of the source gas in CVD or ALD methods. For example, when using CVD or ALD, films with arbitrary compositions can be formed by adjusting the source gas flow rate ratio. Furthermore, for example, when using CVD or ALD, films with continuously varying compositions can be formed by changing the source gas flow rate ratio while forming the film. When forming a film while changing the source gas flow rate ratio, the time required for pressure adjustment and transmission is eliminated, thus shortening the film formation time compared to using multiple deposition chambers. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0278] First, prepare a substrate (not shown), and form an insulator 212 (see reference) on the substrate. FIGS. 4A-4DThe insulator 212 is preferably formed using a sputtering method. By using a sputtering method that does not require hydrogen as a film-forming gas, the hydrogen concentration in the insulator 212 can be reduced. Note that the film formation of the insulator 212 is not limited to sputtering; CVD, MBE, PLD, ALD, and other methods can also be appropriately used.

[0279] In this embodiment, silicon nitride is formed using a silicon target in a nitrogen-containing atmosphere via pulsed DC sputtering, serving as the insulator 212. By using pulsed DC sputtering, particles generated by arcing on the target surface can be suppressed, resulting in a more uniform thickness. Furthermore, by using pulsed voltage, the rise and fall during discharge can be more rapid compared to high-frequency voltage. This allows for more efficient power supply to the electrodes, thereby improving the sputtering rate and film quality.

[0280] Furthermore, by using an insulator such as silicon nitride that does not easily allow impurities such as water and hydrogen to pass through, the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed. In addition, by using an insulator such as silicon nitride that does not easily allow copper to pass through as the insulator 212, even if a metal such as copper that easily diffuses is used as the conductor in the layer below the insulator 212 (not shown), the diffusion of that metal upward through the insulator 212 can be suppressed.

[0281] Next, an insulator 214 is formed on the insulator 212 (see reference). FIGS. 4A-4D The insulator 214 is preferably formed using a sputtering method. By using a sputtering method that does not require hydrogen as a film-forming gas, the hydrogen concentration in the insulator 214 can be reduced. Note that the film formation of the insulator 214 is not limited to sputtering; CVD, MBE, PLD, ALD, and other methods can also be appropriately used.

[0282] In this embodiment, aluminum oxide is formed using a silicon target in an oxygen-containing gas atmosphere via pulsed DC sputtering, serving as the insulator 214. By using pulsed DC sputtering, the thickness can be made more uniform, thereby improving the sputtering rate and film quality.

[0283] By using alumina, which has high hydrogen-capturing and fixing properties, as insulator 214, hydrogen contained in insulator 216 and the like can be captured or fixed to prevent the hydrogen from diffusing into oxide 230.

[0284] Next, insulator 216 is formed on insulator 214. Insulator 216 is preferably formed by sputtering. By using sputtering, which does not require hydrogen as a film-forming gas, the hydrogen concentration in insulator 216 can be reduced. Note that the film formation of insulator 216 is not limited to sputtering; CVD, MBE, PLD, ALD, etc., can also be used appropriately.

[0285] In this embodiment, silicon oxide is formed using a silicon target in an oxygen-containing atmosphere via pulsed DC sputtering as the insulator 216. By using pulsed DC sputtering, the thickness can be made more uniform, thereby improving the sputtering rate and film quality.

[0286] Insulators 212, 214, and 216 are preferably formed continuously without exposure to the atmosphere. For example, a multi-chamber film-forming apparatus can be used. This reduces the amount of hydrogen in the film while forming insulators 212, 214, and 216, and also reduces hydrogen ingress into the film between each film-forming step.

[0287] Next, two openings extending in the A3-A4 direction leading to the insulator 214 are formed in the insulator 216. Note that the openings may include, for example, grooves or slits. The area where the openings are formed is sometimes referred to as the opening portion. Wet etching can be used to form these openings, but dry etching is preferred for microfabrication. As the insulator 214, it is preferable to select an insulator that is used as an etch stop film when etching the insulator 216 to form the groove. For example, when silicon oxide or silicon oxynitride is used as the insulator 216 for forming the groove, silicon nitride, aluminum oxide, or hafnium oxide are preferably used as the insulator 214.

[0288] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel planar electrodes can be used. The CCP etching apparatus including parallel planar electrodes can also employ a structure in which a high-frequency voltage is applied to one of the parallel planar electrodes. Alternatively, a structure in which multiple different high-frequency voltages are applied to one of the parallel planar electrodes can be used. Alternatively, a structure in which high-frequency voltages of the same frequency are applied to each of the parallel planar electrodes can be used. Alternatively, a structure in which high-frequency voltages of different frequencies are applied to each of the parallel planar electrodes can be used. Alternatively, a dry etching apparatus having a high-density plasma source can also be used. For example, as a dry etching apparatus having a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus can be used.

[0289] After the opening is formed, a conductive film serving as conductor 205a is formed. The conductive film serving as conductor 205a preferably includes a conductor that inhibits oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc., can be used. Alternatively, a laminated film of a conductor that inhibits oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film serving as conductor 205a can be formed using sputtering, CVD, MBE, PLD, ALD, and other methods.

[0290] In this embodiment, titanium nitride is formed as the conductive film used as conductor 205a. By using the aforementioned metal nitride as the lower layer of conductor 205b, oxidation of conductor 205b, such as insulator 216, can be suppressed. Furthermore, even if a metal that easily diffuses, such as copper, is used as conductor 205b, diffusion of the metal from conductor 205a to the outside can be prevented.

[0291] Next, a conductive film, which serves as the conductor 205b, is formed. The conductive film used as the conductor 205b can be made of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be formed using electroplating, sputtering, CVD, MBE, PLD, ALD, or similar methods. In this embodiment, tungsten is formed as the conductive film used as the conductor 205b.

[0292] Next, the conductive film used as conductor 205a and a portion of the conductive film used as conductor 205b are removed by CMP treatment, exposing the insulator 216. As a result, conductors 205a and 205b remain only at the opening. Furthermore, sometimes a portion of the insulator 216 is removed by this CMP treatment.

[0293] Next, etching is performed to remove the top of the conductor 205b. As a result, the top surface of the conductor 205b is lower than the top surface of the conductor 205a and the top surface of the insulator 216. Dry etching or wet etching can be used when etching the conductor 205b; from a microfabrication point of view, dry etching is more preferable.

[0294] Next, a conductive film, which serves as conductor 205c, is formed on insulator 216, conductor 205a, and conductor 205b. Similar to the conductive film used as conductor 205a, the conductive film used as conductor 205c preferably includes a conductor that has the function of inhibiting oxygen permeation.

[0295] In this embodiment, titanium nitride is formed as the conductive film used as conductor 205c. By using the aforementioned metal nitride as the upper layer of conductor 205b, oxidation of conductor 205b, such as insulator 222, can be suppressed. Furthermore, even if a metal that easily diffuses, such as copper, is used as conductor 205b, diffusion of this metal from conductor 205c to the outside can be prevented.

[0296] Next, a portion of the conductive film used as conductor 205c is removed by CMP treatment, exposing insulator 216 (see reference). FIGS. 4A-4DAs a result, conductors 205a, 205b, and 205c remain only at the opening. This allows for the formation of a conductor 205 with a flat top surface. Furthermore, conductor 205b is surrounded by conductors 205a and 205c. Therefore, hydrogen diffusion from conductor 205b to the outside of conductors 205a and 205c is prevented, and oxygen ingress from the outside of conductors 205a and 205c, preventing oxidation of conductor 205b, is also prevented. Additionally, sometimes a portion of the insulator 216 is removed through this CMP process.

[0297] Next, an insulator 222 is formed on the insulator 216 and the conductor 205. The insulator 222 is preferably an insulator containing an oxide of one or both aluminum and hafnium. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) are preferred as the insulator. The insulator containing an oxide of one or both aluminum and hafnium provides barrier properties against oxygen, hydrogen, and water. When the insulator 222 provides barrier properties against hydrogen and water, the diffusion of hydrogen and water contained in the surrounding structure of the transistor 200 through the insulator 222 to the inside of the transistor 200 can be suppressed, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0298] Insulator 222 can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. In this embodiment, hafnium oxide is formed as insulator 222 using sputtering. By using sputtering, which does not require hydrogen as a film-forming gas, the hydrogen concentration in insulator 222 can be reduced.

[0299] Next, heat treatment is preferably performed. The heat treatment is performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when heat treatment is performed in a mixed atmosphere of nitrogen and oxygen gas, the proportion of oxygen gas can be set to about 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the removed oxygen, heat treatment can be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.

[0300] Furthermore, the gas used in the above heat treatment is preferably of high purity. For example, the water content of the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the insulator 222 can be prevented as much as possible.

[0301] In this embodiment, as a heat treatment, after the insulator 222 is formed, a treatment is performed at a temperature of 400°C for 1 hour with a nitrogen gas to oxygen gas flow ratio of 4 slm: 1 slm. This heat treatment removes impurities such as water and hydrogen contained in the insulator 222. Furthermore, when using hafnium-containing oxides as the insulator 222, this heat treatment can sometimes improve the crystallinity of the insulator 222. Alternatively, heat treatment can be performed after the formation of the insulator 224, etc.

[0302] Next, insulator 224 is formed on insulator 222. Insulator 224 can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. In this embodiment, silicon oxide is formed as insulator 224 using sputtering. By using sputtering, which does not require hydrogen as a film-forming gas, the hydrogen concentration in insulator 224 can be reduced. Since insulator 224 comes into contact with oxide 230a in subsequent processes, reducing the hydrogen concentration is preferable.

[0303] Next, an opening is formed in insulators 224, 222, 216, 214, and 212. This opening is formed between the two conductors 205. Wet etching can be used to form this opening, but dry etching is preferred for microfabrication. Note that in FIG. 5A The opening is circular when viewed from above, but it is not limited to this. For example, when viewed from above, the opening may also have a roughly circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a shape in which the corners of the quadrilateral or other polygons are rounded.

[0304] Next, an insulating film is formed to become insulator 249, and the insulating film is anisotropically etched to form insulator 249. The insulating film to become insulator 249 can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. As the insulating film to become insulator 249, an insulating film with the function of reducing oxygen permeability is preferred. For example, alumina is preferably formed by the ALD method. Alternatively, silicon nitride is preferably formed by the PEALD method. Silicon nitride has high hydrogen barrier properties, so it is preferred.

[0305] Furthermore, anisotropic etching of the insulating film, which serves as the insulator 249, can be performed, for example, by dry etching. By providing the insulator 249 on the sidewall of the opening, the permeation of oxygen from the outside can be reduced, and oxidation of the conductor 248 to be formed subsequently can be prevented. In addition, impurities such as water and hydrogen can be prevented from entering the conductor 248 from the outside.

[0306] After the opening is formed, a conductive film 248 is formed. The conductive film 248 can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD. In this embodiment, the conductor 248 is formed having the same structure as the conductor 205. Therefore, the conductive film 248a can be formed in the same way as the conductive film 205a, and the conductive film 248b can be formed in the same way as the conductive film 205b.

[0307] Next, a portion of the conductive film that forms the conductor 248 is removed by CMP treatment, thereby exposing the insulator 224. As a result, the conductive film that forms the conductor 248 remains only at the opening. Thus, conductors 248 with flat top surfaces (conductors 248a and 248b) can be formed (see reference). FIGS. 5A-5D Additionally, sometimes a portion of the insulator 224 is removed during this CMP process.

[0308] To create an excess oxygen region in the insulator 224, an oxygen-containing plasma treatment can be performed under reduced pressure. The oxygen-containing plasma treatment preferably employs a device including a power supply for generating high-density plasma using microwaves. Alternatively, a power supply applying RF (Radio Frequency) to one side of the substrate can also be used. High-density oxygen radicals can be generated using high-density plasma, and applying RF to one side of the substrate allows the oxygen radicals generated by the high-density plasma to be efficiently introduced into the insulator 224. Alternatively, an oxygen-containing plasma treatment can be performed after a plasma treatment containing an inert gas using such a device to replenish the detached oxygen. Furthermore, by appropriately selecting the conditions of this plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In this case, heat treatment may not be necessary.

[0309] Here, an aluminum oxide film can be formed on the insulator 224, for example, by sputtering, and the aluminum oxide can be subjected to CMP treatment until it reaches the insulator 224. This CMP treatment can planarize and smooth the surface of the insulator 224. By placing the aluminum oxide on the insulator 224 and performing CMP treatment, the endpoint of the CMP treatment can be easily detected. Furthermore, sometimes the thickness of the insulator 224 may become thinner due to polishing of a portion of the insulator 224 through CMP treatment, but this can be corrected by adjusting the thickness during film formation on the insulator 224. Planarizing and smoothing the surface of the insulator 224 can sometimes prevent a decrease in the coverage of the oxide film to be formed underneath and prevent a decrease in the yield of the semiconductor device. Furthermore, it is preferable to add oxygen to the insulator 224 by sputtering an aluminum oxide film on the insulator 224.

[0310] Next, oxide films 230A and 230B are sequentially formed on insulator 224 and conductor 248 (see reference). FIGS. 6A-6D Preferably, oxide films 230A and 230B are formed continuously without exposure to the atmospheric environment. By forming oxide films without exposure to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to oxide films 230A and 230B, thus keeping the area near the interface between oxide films 230A and 230B clean.

[0311] Oxide film 230A and oxide film 230B can be formed by sputtering, CVD, MBE, PLD, ALD and other methods.

[0312] For example, when forming oxide films 230A and 230B using sputtering, oxygen or a mixture of oxygen and rare gases is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, excess oxygen in the formed oxide film can be increased. Furthermore, when forming the above-mentioned oxide films using sputtering, a target material such as the aforementioned In-M-Zn oxide can be used, for example.

[0313] In particular, during the formation of the oxide film 230A, a portion of the oxygen contained in the sputtering gas is sometimes supplied to the insulator 224. Therefore, the oxygen content in the sputtering gas can be 70% or more, preferably 80% or more, and more preferably 100%.

[0314] When forming the oxide film 230B using sputtering, an oxygen-excess oxide semiconductor can be formed by forming the film under conditions where the oxygen content in the sputtering gas is more than 30% and less than 100%, preferably more than 70% and less than 100%. Transistors using the oxygen-excess oxide semiconductor in the channel formation region can achieve relatively high reliability. Note that one aspect of the invention is not limited to this. When forming the oxide film 230B using sputtering, an oxygen-deficient oxide semiconductor is formed when the film formation is performed with the oxygen content in the sputtering gas set to more than 1% and less than 30%, preferably more than 5% and less than 20%. Transistors using the oxygen-deficient oxide semiconductor in the channel formation region can have higher field-effect mobility. Furthermore, by forming the film while heating the substrate, the crystallinity of the oxide film can be improved.

[0315] In this embodiment, an oxide film 230A is formed using an oxide target with an In:Ga:Zn ratio of 1:3:4 (atomic number ratio) via sputtering. Additionally, an oxide film 230B is formed using an oxide target with an In:Ga:Zn ratio of 4:2:4.1 (atomic number ratio) via sputtering. The formation conditions and atomic number ratios of the oxide films can be appropriately selected based on the desired characteristics of oxides 230a and 230b.

[0316] Next, oxide film 243A is formed on oxide film 230B (refer to...). FIGS. 6A-6D The oxide film 243A can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. The ratio of Ga atoms relative to In in oxide film 243A is preferably larger than the ratio of Ga atoms relative to In in oxide film 230B. In this embodiment, oxide film 243A is formed using an oxide target with an In:Ga:Zn ratio of 1:3:4 [atomic ratio] via sputtering.

[0317] Here, it is preferable to form insulators 222, 224, oxide films 230A, 230B, and 243A by sputtering in a manner that avoids exposure to the atmosphere. For example, a multi-chamber film-forming apparatus can be used. This reduces the amount of hydrogen in the film while forming insulators 222, 224, 230A, 230B, and 243A, and also reduces hydrogen ingress into the film between each film-forming step.

[0318] Next, heat treatment is preferably performed. The heat treatment can be performed within a temperature range where polycrystalline formation does not occur in oxide films 230A, 230B, and 243A, preferably between 250°C and 650°C, and more preferably between 400°C and 600°C. The heat treatment is performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing 10 ppm, 1%, or 10% or more of an oxidizing gas. For example, when heat treatment is performed in a mixed atmosphere of nitrogen and oxygen gas, the proportion of oxygen gas can be set to approximately 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the released oxygen, heat treatment can be performed in an atmosphere containing 10 ppm, 1%, or 10% or more of an oxidizing gas.

[0319] Furthermore, the gas used in the above heat treatment is preferably of high purity. For example, the water content of the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, it is possible to prevent moisture and other substances from being absorbed by the oxide films 230A, 230B, and 243A as much as possible.

[0320] In this embodiment, as a heat treatment, the process is carried out at 550°C for 1 hour under a nitrogen atmosphere, followed by a continuous process at 550°C for 1 hour under an oxygen atmosphere. This heat treatment removes impurities such as water and hydrogen from oxide films 230A, 230B, and 243A. Furthermore, this heat treatment improves the crystallinity of oxide film 230B, resulting in a denser structure. This reduces the diffusion of oxygen or impurities from oxide film 230B.

[0321] Next, a conductive film 242A is formed on the oxide film 243A (refer to...). FIGS. 6A-6D The conductive film 242A can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. For example, tantalum nitride can be formed as the conductive film 242A using sputtering. Alternatively, heat treatment can be performed before forming the conductive film 242A. This heat treatment can be performed under reduced pressure, and the conductive film 242A is continuously formed without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of the oxide film 243A can be removed, and the moisture and hydrogen concentrations in the oxide films 230A, 230B, and 243A can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower. In this embodiment, the heat treatment temperature is set to 200°C.

[0322] Next, the oxide film 230A, oxide film 230B, oxide film 243A and conductive film 242A are processed into islands using photolithography to form oxide 230a, oxide 230b, oxide layer 243B and conductive layer 242B (see reference). FIGS. 7A-7D Furthermore, this process can be performed using either dry etching or wet etching. Dry etching is suitable for micro-machining. Additionally, oxide films 230A, 230B, 243A, and conductive film 242A can be formed under different conditions. Furthermore, in this process, the thickness of the region in insulator 224 that does not overlap with oxide 230a may sometimes become thinner. Alternatively, in this process, the insulator 224 can be processed into an island shape in a manner that overlaps with oxide 230a.

[0323] Note that in photolithography, the resist is first exposed through a mask. Next, a developer is used to remove or leave the exposed areas, forming a resist mask. Then, etching is performed through this resist mask to process conductors, semiconductors, or insulators into the desired shape. For example, the resist mask can be formed by exposing the resist to a KrF stimulated excimer laser, an ArF stimulated excimer laser, or EUV (Extreme Ultraviolet) light. Alternatively, immersion lithography can be used, where exposure is performed with liquid (e.g., water) filling the space between the substrate and the projection lens. Electron beams or ion beams can also be used instead of the aforementioned light. Note that when using electron beams or ion beams, a mask is not required. Furthermore, when removing the resist mask, dry etching (such as ashing) or wet etching can be performed, or wet etching can be performed after dry etching, or dry etching can be performed after wet etching.

[0324] Furthermore, a hard mask made of an insulator or conductor can also be used under a resist mask. When using a hard mask, an insulating film or conductive film that serves as the hard mask material can be formed on the conductive film 242A, and a resist mask can be formed on it. Then, the hard mask material can be etched to form a hard mask of the desired shape. The etching of the conductive film 242A, etc., can be performed either after removing the resist mask or without removing it. In the latter case, the resist mask may sometimes disappear during etching. The hard mask can be removed by etching after etching the conductive film 242A, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessary to remove the hard mask. For example, when forming a hard mask using an insulating film, the hard mask can remain and be used as a barrier insulating film.

[0325] Here, oxides 230a, 230b, oxide layer 243B, and conductive layer 242B are formed such that at least a portion overlaps with conductor 248 and two conductors 205. Furthermore, the side surfaces of oxides 230a, 230b, oxide layer 243B, and conductive layer 242B are preferably substantially perpendicular to the top surface of insulator 222. When the side surfaces of oxides 230a, 230b, oxide layer 243B, and conductive layer 242B are substantially perpendicular to the top surface of insulator 222, a smaller area and higher density can be achieved when multiple transistors 200 are provided. Alternatively, a structure with a lower angle formed between the side surfaces of oxides 230a, 230b, oxide layer 243B, and conductive layer 242B and the top surface of insulator 222 can also be used. In this case, the angle formed between the side surfaces of oxides 230a, 230b, oxide layer 243B, and conductive layer 242B and the top surface of insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting this shape, the coverage of insulator 275 and the like is improved in the following processes, and defects such as voids can be reduced.

[0326] Furthermore, sometimes byproducts generated during the above-mentioned etching process form in layers on the sides of oxides 230a, 230b, oxide layer 243B, and conductive layer 242B. In this case, the layered byproducts form between oxides 230a, 230b, 243B, conductor 242, and insulator 275. Similarly, sometimes the layered byproducts form on insulator 224. If insulator 275 is formed with these layered byproducts on insulator 224, these layered byproducts hinder the addition of oxygen to insulator 224. Therefore, it is preferable to remove the layered byproducts that contact the top surface of insulator 224.

[0327] Next, an insulator 275 (see reference) is formed on insulator 224, oxide 230a, oxide 230b, oxide layer 243B and conductive layer 242B. FIGS. 8A-8D The insulator 275 can be formed by sputtering, CVD, MBE, PLD, or ALD. Preferably, the insulator 275 is an insulating film that inhibits oxygen permeation. For example, an alumina film can be formed as the insulator 275 by ALD or sputtering. Alternatively, a silicon nitride film can also be formed as the insulator 275 by sputtering.

[0328] Oxygen can be added to insulator 224 by using sputtering to form insulator 275.

[0329] Next, an insulating film, which becomes insulator 280, is formed on insulator 275. This insulating film can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. For example, silicon oxide can be formed as this insulating film by sputtering. By forming the insulating film as insulator 280 using sputtering under an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. By using a sputtering method that does not require hydrogen as the film-forming gas, the hydrogen concentration in insulator 280 can be reduced. Alternatively, heat treatment can be performed before forming this insulating film. This heat treatment can also be performed under reduced pressure, wherein the insulating film is continuously formed without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of insulator 275 can be removed, and the moisture and hydrogen concentrations in oxide 230a, oxide 230b, oxide layer 243B, and insulator 224 can be reduced. This heat treatment can be performed under the conditions described above.

[0330] Next, the insulating film that becomes insulator 280 is subjected to CMP treatment to form an insulator 280 with a flat top surface (see reference). FIGS. 8A-8D Alternatively, silicon nitride can be deposited on insulator 280, for example, by sputtering, and CMP treatment can be performed until the silicon nitride reaches insulator 280.

[0331] Next, a portion of insulator 280, a portion of insulator 275, a portion of conductive layer 242B, a portion of oxide layer 243B, and a portion of oxide 230b are removed to form two openings reaching oxide 230b. These two openings are preferably formed in a manner overlapping with conductor 205. By forming these openings, conductors 242a, 242b, 242c, oxides 243a, 243b, and 243c are formed (see reference). FIGS. 9A-9D Here, conductor 242b is preferably formed in a manner that overlaps with conductor 248. Furthermore, the region of oxide 230b that does not overlap with conductors 242a, 242b, and 242c is exposed.

[0332] When forming the opening described above, sometimes the top of oxide 230b is removed. By removing a portion of oxide 230b, a groove is formed in oxide 230b. Depending on the depth of the groove, the groove can be formed either in the opening formation process or in a different process.

[0333] Alternatively, a portion of insulator 280, a portion of insulator 275, a portion of conductive layer 242B, a portion of oxide layer 243B, and a portion of oxide 230b can be processed using either dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, this processing can be performed under different conditions. For example, a portion of insulator 280 can be processed using dry etching, a portion of insulator 275 using wet etching, and a portion of oxide layer 243B, a portion of conductive layer 242B, and a portion of oxide 230b can be processed using dry etching. In this case, firstly, two openings are formed in insulator 280, and openings are formed in insulator 275, oxide layer 243B, and conductive layer 242B in a manner overlapping these two openings. Furthermore, the processing of a portion of oxide layer 243B and a portion of conductive layer 242B can be performed under different conditions than the processing of a portion of oxide 230b.

[0334] Here, it is preferable to remove impurities adhering to the surfaces of oxides 230a, oxides 230b, etc., or those diffused into their interior. Furthermore, it is preferable to remove the damaged areas formed on the surface of oxide 230b by the aforementioned dry etching method. Examples of such impurities include those originating from: components contained in insulators 280, 275, and conductive layer 242B; components contained in the components used in the apparatus for forming the aforementioned opening; components contained in the gas or liquid used for etching; etc. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0335] In particular, impurities such as aluminum or silicon hinder the CAAC-OS formation of oxide 230b. Therefore, it is preferable to reduce or remove impurity elements such as aluminum or silicon that hinder CAAC-OS formation. For example, the concentration of aluminum atoms in and around oxide 230b can be 5.0 atomic% or less, preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, even more preferably 1.0 atomic% or less, and especially preferably less than 0.3 atomic%.

[0336] Sometimes, the regions of metal oxides that are hindered from CAAC-OS formation by impurities such as aluminum or silicon, thus becoming a-like OS (amorphous-like oxide semiconductor), are called non-CAAC regions. In non-CAAC regions, the density of the crystal structure decreases, thus producing a large amount of V. O H. Transistors are prone to becoming normally-on. Therefore, it is preferable to reduce or remove the non-CAAC region in oxide 230b.

[0337] In contrast, oxide 230b preferably has a layered CAAC structure. In particular, the lower end of the drain of oxide 230b preferably also has a CAAC structure. Here, in transistor 200, conductors 242a, 242b, or 242c and their vicinity are used as drains. In other words, oxide 230b near the lower end of conductors 242a, 242b, or 242c preferably has a CAAC structure. Thus, by removing the damaged region of oxide 230b in the drain end portion that significantly affects the drain breakdown voltage and giving it a CAAC structure, variations in the electrical characteristics of transistor 200 can be further suppressed. Furthermore, the reliability of transistor 200 can be further improved.

[0338] To remove the aforementioned impurities, a washing process can also be performed. Washing methods include wet washing using a washing liquid, plasma treatment using plasma, and washing using heat treatment; combinations of these methods are also possible. Note that this washing process may sometimes deepen the tank area.

[0339] As a wet washing process, an aqueous solution prepared by diluting ammonia, oxalic acid, phosphoric acid, or hydrofluoric acid with carbonated water or pure water, or pure water or carbonated water can be used for washing. Alternatively, ultrasonic washing can be performed using the aforementioned aqueous solution, pure water, or carbonated water. Furthermore, a combination of the above washing methods can be used as appropriate.

[0340] Note that in this specification, etc., an aqueous solution of commercially available hydrofluoric acid diluted with pure water is sometimes referred to as dilute hydrofluoric acid, and an aqueous solution of commercially available ammonia diluted with pure water is sometimes referred to as dilute ammonia. Furthermore, the concentration, temperature, etc., of this aqueous solution can be appropriately adjusted according to the impurities to be removed, the structure of the semiconductor device being cleaned, etc. The ammonia concentration of the dilute ammonia is set to 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. Similarly, the hydrogen fluoride concentration of the dilute hydrofluoric acid is set to 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0341] Furthermore, for ultrasonic cleaning, a frequency of 200 kHz or higher is preferred, and more preferably 900 kHz or higher. By using this frequency, damage to oxides such as 230b can be reduced.

[0342] In addition, the above washing process can be performed multiple times, or the washing solution can be changed for each washing process. For example, the first washing process can be performed using dilute hydrofluoric acid or dilute ammonia, and the second washing process can be performed using pure water or carbonated water.

[0343] As a washing process described above, in this embodiment, a wet wash is performed using dilute hydrofluoric acid, followed by a wet wash with pure water or carbonated water. This washing process removes impurities adhering to the surface of oxides 230a, 230b, etc., or those diffused into their interior. Furthermore, it improves the crystallinity of oxide 230b.

[0344] By performing the above-described dry etching process or the above-described cleaning process, the thickness of the insulator 224 that overlaps the opening but does not overlap the region of oxide 230b is sometimes thinner than the thickness of the insulator 224 that overlaps the region of oxide 230b.

[0345] Heat treatment can be performed after the etching or washing described above. The heat treatment should be performed at a temperature of 100°C or higher and 450°C or lower, preferably 350°C or higher and 400°C or lower. The heat treatment should be performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to oxides 230a and 230b, thereby reducing oxygen vacancies (V0). O Furthermore, the crystallinity of oxide 230b can be improved by performing the above heat treatment. The heat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in an oxygen atmosphere, followed by continuous heat treatment in a nitrogen atmosphere without exposure to the atmosphere.

[0346] Next, an insulating film 250A is formed (refer to...) FIGS. 10A-10D The heat treatment can also be performed before forming the insulating film 250A, and preferably, this heat treatment is performed under reduced pressure so that the insulating film 250A is continuously formed without exposure to the atmosphere. Furthermore, this heat treatment is preferably performed in an atmosphere containing oxygen. By performing this treatment, moisture and hydrogen adhering to the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxides 230a and 230b are reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower.

[0347] The insulating film 250A can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. Preferably, the insulating film 250A is formed using a film-forming method that reduces or removes hydrogen atoms from the gas. This reduces the hydrogen concentration of the insulating film 250A. Since the insulating film 250A becomes the insulator 250 in contact with the oxide 230b in subsequent processes, further reduction in hydrogen concentration is preferable.

[0348] Furthermore, the insulating film 250A is preferably formed using the ALD method. The insulator 250, which serves as the gate insulating film of the miniaturized transistor 200, needs to be very thin (e.g., 5 nm or more and about 30 nm less) and have minimal non-uniformity. For this purpose, the ALD method is a film formation method that alternately introduces precursors and reactants (oxidants). Since the film thickness can be adjusted according to the number of cycles, the ALD method allows for precise thickness control. Therefore, the necessary precision in the thickness of the gate insulating film for the miniaturized transistor 200 can be achieved. Additionally, as... FIG. 10B and FIG. 10C As shown, the insulating film 250A needs to be formed with high coverage on the bottom and side surfaces of the opening formed by the insulator 280, etc. Since each atomic layer can be deposited on the bottom and side surfaces of the opening, the insulating film 250A can be formed with high coverage on the opening.

[0349] Additionally, for example, during the deposition of insulating film 250A using PECVD, the hydrogen-containing film-forming gas is decomposed in the plasma, generating a large number of hydrogen free radicals. In the reduction reaction of these hydrogen free radicals, oxygen in oxide 230b is extracted to form V. O At H, the hydrogen concentration in oxide 230b increases. However, when forming the insulating film 250A using the ALD method, the generation of hydrogen free radicals can be suppressed during both the introduction of the precursor and the introduction of the reactants. Therefore, by using the ALD method to form the insulating film 250A, the increase in the hydrogen concentration in oxide 230b can be prevented. For example, a silicon oxide film such as silicon oxide can be formed using the ALD method as the insulating film 250A.

[0350] Note that in FIG. 10B , FIG. 10C and FIG. 10D The insulating film 250A is shown to be a single layer, but it can also be a stacked structure of two or more layers. When the insulating film 250A is a stacked structure of two layers, it is preferable that the lower layer of the insulating film 250A is formed using an insulator that releases oxygen upon heating, and the upper layer of the insulating film 250A is formed using an insulator that has the function of inhibiting oxygen diffusion. By adopting this structure, the diffusion of oxygen contained in the lower layer of the insulator 250 to the conductor 260 can be suppressed. In other words, the reduction of the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, the oxidation of the conductor 260 caused by oxygen contained in the lower layer of the insulator 250 can be suppressed. For example, the lower layer of the insulating film 250A can be made of a material suitable for the aforementioned insulator 250, and the upper layer of the insulating film 250A can be made of the same material as the insulator 222.

[0351] As the upper layer of the insulating film 250A, specifically, a metal oxide comprising one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide capable of being used for oxide 230, may be used. In particular, an insulator comprising an oxide of one or both of aluminum and hafnium is preferred.

[0352] In this embodiment, when the insulating film 250A has a two-layer stacked structure, silicon oxide can be formed as the lower layer by the PEALD method and hafnium oxide can be formed as the upper layer by the thermal ALD method.

[0353] Note that when the insulating film 250A has a two-layer laminated structure, the lower insulating film and the upper insulating film of the insulating film 250A are preferably formed continuously in a manner that does not expose them to the atmosphere. By forming them in a manner that does not expose them to the atmosphere, impurities such as hydrogen or moisture from the atmospheric environment can be prevented from adhering to the lower and upper insulating films of the insulating film 250A. Therefore, the area near the interface between the lower and upper insulating films of the insulating film 250A can be kept clean.

[0354] Next, microwave treatment was performed in an oxygen-containing atmosphere (see reference). FIGS. 10A-10D Here, FIG. 10B , FIG. 10C , FIG. 10D The dashed lines represent high-frequency oxygen plasma or oxygen free radicals, such as microwaves or RF. Microwave processing preferably uses a microwave processing apparatus that includes a power supply for generating high-density plasma using microwaves. Furthermore, the microwave processing apparatus may also include a power supply that applies RF to one side of the substrate. By using high-density plasma, a high density of oxygen free radicals can be generated. Furthermore, by applying RF to one side of the substrate, oxygen ions generated by the high-density plasma can be efficiently introduced into the oxide 230b. Moreover, the above microwave processing is preferably performed under reduced pressure, with a pressure of 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. The oxygen flow rate ratio (O2 / O2+Ar) is 50% or less, preferably 10% to 30% or less. Furthermore, the processing temperature is 750°C or less, preferably 500°C or less, for example, around 400°C. Alternatively, after oxygen plasma processing, continuous heating processing can be performed without exposure to the atmosphere.

[0355] like FIG. 10B , FIG. 10C , FIG. 10DAs shown, by performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high frequencies such as RF, and this oxygen plasma can act on the region between conductors 242a and 242b of oxide 230b, as well as between conductors 242b and 242c. At this time, high frequencies such as microwaves or RF can also be used for irradiation. In other words, the high-frequency oxygen plasma, such as microwaves or RF, can be used to... FIG. 2 The effects are shown in regions 232d and 232e. Through the action of plasma, microwaves, etc., the V in regions 232d and 232e can be increased. O H separates and removes hydrogen H from regions 232d and 232e. In other words, "V" occurs in regions 232d and 232e. O H→H+V O The reaction reduces the hydrogen concentration contained in regions 232d and 232e. Therefore, it can reduce oxygen vacancies and V in regions 232d and 232e. O H reduces the carrier concentration. In addition, by supplying oxygen free radicals generated in the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancies formed in regions 232d and 232e, the oxygen vacancies in regions 232d and 232e can be further reduced, thereby reducing the carrier concentration.

[0356] On the other hand, conductors 242a, 242b, and 242c are provided in regions 232a, 232b, and 232c, respectively. For example... FIG. 10B , FIG. 10C , FIG. 10D As shown, conductors 242a, 242b, and 242c shield against high-frequency radiation such as microwaves or RF, and oxygen plasma, and therefore do not affect regions 232a, 232b, and 232c. Consequently, microwave processing does not affect V in regions 232a, 232b, and 232c. O The decrease in H and the excessive supply of oxygen can prevent the decrease in carrier concentration.

[0357] As described above, oxygen vacancies and V can be selectively removed by regions 232d and 232e of the oxide semiconductor. OH makes regions 232d and 232e i-type or substantially i-type. Furthermore, it can suppress excessive oxygen supply to regions 232a, 232b, and 232c, which are used as source or drain regions, thus maintaining n-type characteristics. Therefore, variations in the electrical characteristics of transistor 200 can be suppressed, and non-uniformity in the electrical characteristics of transistor 200 within the substrate surface can be suppressed. Moreover, by providing conductor 248 in a manner overlapping with conductor 242b, and with the top surface of conductor 248 contacting region 232b in a self-aligned manner, good contact can be formed between transistor 200a and transistor 200b and conductor 248.

[0358] Therefore, a semiconductor device with small non-uniformity in transistor characteristics can be provided. Furthermore, a semiconductor device with good electrical characteristics can be provided. Additionally, a semiconductor device with high reliability can be provided.

[0359] exist FIGS. 10A-10D In the process shown, microwave treatment is performed after the insulating film 250A is formed, but the present invention is not limited thereto. For example, microwave treatment can be performed either before the insulating film 250A is formed, or it can be performed both before and after the insulating film 250A is formed.

[0360] For example, when the insulating film 250A has the above-described two-layer structure, microwave processing is performed to form a silicon oxide film as the lower layer of the insulating film 250A using the PEALD method, and a hafnium oxide film as the upper layer of the insulating film 250A using the thermal ALD method. Here, the microwave processing, the PEALD deposition of silicon oxide, and the thermal ALD deposition of hafnium oxide are performed continuously without exposure to the atmosphere. For example, a multi-chamber processing apparatus can be used. Alternatively, plasma-excited reactant (oxidant) processing using a PEALD apparatus can replace the microwave processing described above. Here, oxygen gas can be used as the reactant (oxidant).

[0361] Alternatively, heat treatment can be performed under reduced pressure after microwave treatment. This treatment efficiently removes hydrogen from the insulating film 250A, oxide 230b, and oxide 230a. Additionally, some hydrogen may be attracted by the conductors 242 (conductors 242a and 242b). Furthermore, the step of performing heat treatment under reduced pressure after microwave treatment can be repeated. Repeated heat treatment further efficiently removes hydrogen from the insulating film 250A, oxide 230b, and oxide 230a. Note that the heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0362] Furthermore, by altering the film quality of the insulating film 250A through microwave treatment, the diffusion of hydrogen, water, impurities, etc., can be suppressed. This prevents the diffusion of hydrogen, water, impurities, etc., through the insulator 250 to oxides 230b, oxides 230a, etc., due to subsequent processes such as film formation or heat treatment that make the conductive film 260 a conductor.

[0363] Next, a conductive film becoming conductor 260a and a conductive film becoming conductor 260b are formed sequentially. The conductive films becoming conductor 260a and conductor 260b can be formed by sputtering, CVD, MBE, PLD, or ALD. In this embodiment, the conductive film becoming conductor 260a is formed using the ALD method, and the conductive film becoming conductor 260b is formed using the CVD method.

[0364] Next, the insulating film 250A, the conductive film that becomes conductor 260a, and the conductive film that becomes conductor 260b are polished by CMP processing until the insulator 280 is exposed, thereby forming the insulator 250 and conductor 260 (conductor 260a and conductor 260b) of transistor 200a and transistor 200b (see reference). FIGS. 11A-11D Therefore, the insulator 250 of transistors 200a and 200b is arranged to cover the two openings reaching oxide 230b and the inner wall (side wall and bottom surface) of the groove of oxide 230b. In addition, the conductor 260 of transistors 200a and 200b is arranged to fill the two openings and the groove through the insulator 250.

[0365] Next, heat treatment can be performed under the same conditions as described above. In this embodiment, the treatment is carried out at 400°C for 1 hour under a nitrogen atmosphere. This heat treatment can reduce the moisture concentration and hydrogen concentration in insulators 250 and 280. Furthermore, after the above heat treatment, insulator 282 is continuously formed without exposure to the atmosphere.

[0366] Next, an insulator 282 is formed on the insulator 250, the conductor 260, and the insulator 280 (see reference). FIGS. 12A-12D The insulator 282 can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. Sputtering is the preferred method for forming the insulator 282. By using sputtering, which eliminates the need for hydrogen as the film-forming gas, the hydrogen concentration in the insulator 282 can be reduced. Furthermore, by forming the insulator 282 in an oxygen-containing atmosphere using sputtering, oxygen can be added to the insulator 280 during film formation. This allows the insulator 280 to contain excess oxygen. In this case, it is preferable to form the insulator 282 while heating the substrate.

[0367] In this embodiment, aluminum oxide is formed using an aluminum target in an oxygen-containing gas atmosphere via pulsed DC sputtering, serving as the insulator 282. By using pulsed DC sputtering, the thickness can be made more uniform, thereby improving the sputtering rate and film quality.

[0368] Next, insulator 283 is formed on insulator 282 (see reference). FIGS. 1A-1D The insulator 283 can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. Sputtering is the preferred method for forming the insulator 283. By using sputtering, which eliminates the need for hydrogen as the film-forming gas, the hydrogen concentration in the insulator 283 can be reduced. Furthermore, the insulator 283 can also have a multilayer structure. For example, silicon nitride can be formed by sputtering, and then silicon nitride can be formed on top of this silicon nitride using CVD. By surrounding the transistor 200 with highly barrier insulator 283 and insulator 212, moisture and hydrogen can be prevented from entering from the outside.

[0369] Next, heat treatment can be performed. In this embodiment, the treatment is carried out at 400°C for 1 hour under a nitrogen atmosphere. FIG. 2 As shown, this heat treatment allows oxygen added during the formation of insulator 282 to diffuse into insulators 280 and 250, and selectively supply oxygen to the channel formation region of oxide 230. Furthermore, this heat treatment is not limited to being performed after the formation of insulator 283, but can also be performed after the formation of insulator 282, etc.

[0370] Through the above processes, it is possible to manufacture including FIGS. 4A-12A The semiconductor device shown is transistor 200. (As shown) FIGS. 4B-12B , FIGS. 4C-12C , FIGS. 4D-12D and FIG. 13 As shown, transistor 200 can be manufactured by using the semiconductor device manufacturing method shown in this embodiment.

[0371] Microwave Processing Device

[0372] The following describes a microwave processing apparatus that can be used in the manufacturing method of the above-described semiconductor device.

[0373] First, refer to FIG. 14 , FIG. 15 and FIG. 13 The structure of a manufacturing apparatus that can reduce the introduction of impurities when manufacturing semiconductor devices is explained.

[0374] FIG. 14A schematic top view of a monolithic multi-chamber manufacturing apparatus 2700 is shown. The manufacturing apparatus 2700 includes: an atmospheric-side substrate supply chamber 2701 equipped with a cassette port 2761 for receiving substrates and an alignment port 2762 for aligning substrates; an atmospheric-side substrate transfer chamber 2702 for transferring substrates from the atmospheric-side substrate supply chamber 2701; a loading lock chamber 2703a for loading substrates and switching the pressure inside the chamber from atmospheric pressure to depressurization or from depressurization to atmospheric pressure; an unloading lock chamber 2703b for unloading substrates and switching the pressure inside the chamber from depressurization to atmospheric pressure or from atmospheric pressure to depressurization; a transfer chamber 2704 for transferring substrates in a vacuum; and processing chambers 2706a, 2706b, 2706c, and 2706d.

[0375] In addition, the atmospheric side substrate transfer chamber 2702 is connected to the loading lock chamber 2703a and the unloading lock chamber 2703b, the loading lock chamber 2703a and the unloading lock chamber 2703b are connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the processing chambers 2706a, 2706b, 2706c and 2706d.

[0376] A gate valve GV is provided at the connection between the chambers, thereby allowing each chamber, except for the atmospheric substrate supply chamber 2701 and the atmospheric substrate transfer chamber 2702, to be independently maintained in a vacuum state. A transfer robot 2763a is provided in the atmospheric substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. The substrate can be transferred in the manufacturing apparatus 2700 using the transfer robots 2763a and 2763b.

[0377] The back pressure (total pressure) of transfer chamber 2704 and each processing chamber is, for example, 1×10⁻⁶. -4 Pa or less, preferably 3×10 Pa -5 Pa or less, more preferably 1×10 Pa -5 Below Pa. The mass-to-charge ratio (m / z) of the transfer chamber 2704 and each processing chamber is 18, and the partial pressure of gas molecules (atoms) is, for example, 3 × 10⁻⁸. -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 Pa -6 Below Pa. Furthermore, the partial pressure of gas molecules (atoms) with an m / z of 28 in the transfer chamber 2704 and each processing chamber is, for example, 3 × 10⁻⁸. -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 Pa -6Below Pa. The partial pressure of gas molecules (atoms) at m / z 44 in the transfer chamber 2704 and each processing chamber is, for example, 3 × 10⁴. -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 Pa -6 Below Pa.

[0378] The total and partial pressures in transfer chamber 2704 and each processing chamber can be measured using a mass analyzer. For example, a four-pole mass analyzer (also known as a Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. can be used.

[0379] Furthermore, the transfer chamber 2704 and each processing chamber preferably have a structure with minimal external or internal leakage. For example, the leakage rate of the transfer chamber 2704 and each processing chamber is 3 × 10⁻⁶. -6 Pa·m 3 Below / s, preferably 1×10 -6 Pa·m 3 / s or less. Additionally, for example, the leakage rate of gas molecules (atoms) with m / z of 18 is set to 1 × 10⁻⁶. -7 Pa·m 3 For speeds below / s, a setting of 3×10 is preferred. - 8 Pa·m 3 / s or less. Additionally, for example, the leakage rate of gas molecules (atoms) with m / z of 28 is set to 1 × 10⁻⁶. -5 Pa·m 3 For speeds below / s, a setting of 1×10 is preferred. -6 Pa·m 3 / s or less. Additionally, for example, the leakage rate of gas molecules (atoms) with m / z of 44 is set to 3 × 10⁻⁶. -6 Pa·m 3 For speeds below / s, a setting of 1×10 is preferred. -6 Pa·m 3 / s or less.

[0380] The leakage rate can be calculated based on the total pressure and partial pressure measured using the aforementioned mass analyzer. The leakage rate depends on both external and internal leakage. External leakage refers to the inflow of gas from outside the vacuum system due to small holes or poor sealing. Internal leakage originates from leaks in valves or other baffles within the vacuum system, or from released gas from internal components. To keep the leakage rate below the aforementioned values, measures need to be taken to address both external and internal leakage.

[0381] For example, metal gaskets are preferably used to seal the opening and closing parts of the transfer chamber 2704 and each processing chamber. The metal gaskets are preferably made of metal coated with iron fluoride, alumina, or chromium oxide. Metal gaskets offer higher tightness than O-rings, thus reducing external leakage. By utilizing a passivated metal coated with iron fluoride, alumina, chromium oxide, etc., the release of gases containing impurities from the metal gaskets can be suppressed, thereby reducing internal leakage.

[0382] As components constituting the manufacturing apparatus 2700, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which contain few impurities and release gases, are used. Alternatively, the aforementioned components can be coated with alloys containing iron, chromium, and nickel. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and easy to process. Here, by reducing the surface roughness of the component through polishing or other methods to decrease the surface area, the release of gases can be reduced.

[0383] Alternatively, ferric fluoride, alumina, chromium oxide, etc., can be used to cover the components of the manufacturing apparatus 2700.

[0384] The components of the manufacturing apparatus 2700 are preferably made of metal as much as possible. For example, when a viewing window made of quartz or the like is provided, in order to suppress the release of gas, the surface of the viewing window is preferably covered with a thin layer of iron fluoride, aluminum oxide or chromium oxide.

[0385] Although the deposits present in the transfer chamber 2704 and each processing chamber adhere to the inner walls and do not affect the pressure of the transfer chamber 2704 and each processing chamber, these deposits become the cause of gas release during venting of the transfer chamber 2704 and each processing chamber. Therefore, although the leakage rate is not related to the venting rate, it is very important to use a pump with high venting capacity to remove the deposits present in the transfer chamber 2704 and each processing chamber as much as possible and to vent them in advance. To promote the removal of deposits, the transfer chamber 2704 and each processing chamber can also be baked. By baking, the removal rate of adsorbates can be increased by about 10 times. Baking can be carried out at a temperature of 100°C or higher and 450°C or lower. At this time, by introducing inert gas into the transfer chamber 2704 and each processing chamber while removing deposits, the removal rate of water and other substances that are not easily removed by venting alone can be further improved. In addition, by heating the introduced inert gas at a temperature similar to the baking temperature, the removal rate of adsorbates can be further improved. Here, a rare gas is preferably used as the inert gas.

[0386] Furthermore, it is preferable to increase the pressure in the transfer chamber 2704 and each processing chamber by introducing a heated rare gas or oxygen, and then exhaust the transfer chamber 2704 and each processing chamber again after a certain period of time. The introduction of the heated gas can cause deposits in the transfer chamber 2704 and each processing chamber to detach, thereby reducing impurities present in the transfer chamber 2704 and each processing chamber. Effectively, this process should be repeated at least twice and no more than 30 times, preferably at least five times and no more than 15 times. Specifically, the pressure in the transfer chamber 2704 and each processing chamber is set to 0.1 Pa or more and 10 kPa or less, preferably 1 Pa or more and 1 kPa or less, more preferably 5 Pa or more and 100 Pa or less, by introducing an inert gas or oxygen at a temperature of 40°C or higher and 400°C or lower, preferably 50°C or higher and 200°C, and the pressure is maintained for at least one minute and no more than 300 minutes, preferably 5 minutes or more and 120 minutes or less. Then, exhaust air from the transfer chamber 2704 and each processing chamber for 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0387] Next, use FIG. 15 The cross-sectional schematic diagram shown illustrates processing chambers 2706b and 2706c.

[0388] Processing chambers 2706b and 2706c are, for example, processing chambers capable of performing microwave processing on the workpiece. Note that the only difference between processing chambers 2706b and 2706c is the atmosphere during microwave processing. Since the other structures of processing chambers 2706b and 2706c are the same, they will be described together below.

[0389] Processing chambers 2706b and 2706c include a slotted antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Additionally, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are disposed outside processing chambers 2706b and 2706c.

[0390] A high-frequency generator 2803 is connected to a mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slotted antenna plate 2808 via a waveguide 2807. The slotted antenna plate 2808 is grounded in contact with a dielectric plate 2809. Furthermore, a gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is introduced into processing chambers 2706b and 2706c via a gas pipe 2806 passing through the mode converter 2805, waveguide 2807, and dielectric plate 2809. Additionally, a vacuum pump 2817 functions to discharge gas from processing chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. Finally, a high-frequency power supply 2816 is connected to a substrate holder 2812 via a matching adapter 2815.

[0391] The substrate holder 2812 is capable of holding the substrate 2811. For example, the substrate holder 2812 has the function of electrostatic chuck or mechanical chuck for holding the substrate 2811. In addition, the substrate holder 2812 has the function of electrodes powered by a high-frequency power supply 2816. Furthermore, the substrate holder 2812 includes a heating mechanism 2813 inside and has the function of heating the substrate 2811.

[0392] As the vacuum pump 2817, various types of pumps can be used, such as drying pumps, mechanical booster pumps, ion pumps, titanium sublimation pumps, cryogenic pumps, or turbomolecular pumps. In addition to the vacuum pump 2817, a cryogenic cold trap can also be used. Using both a cryogenic pump and a cryogenic cold trap allows for efficient water removal, which is particularly preferred.

[0393] As the heating mechanism 2813, a heating mechanism that uses a resistance heating element or the like for heating can be used. Alternatively, a heating mechanism that uses heat conduction or heat radiation from a medium such as a gas to be heated can also be used. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA uses a high-temperature gas for heat treatment. An inert gas is used as the gas.

[0394] Additionally, the gas supply source 2801 can be connected to the purifier via a mass flow controller. Preferably, a gas with a dew point below -80°C, and more preferably below -100°C, is used. For example, oxygen gas, nitrogen gas, and rare gases (such as argon) can be used.

[0395] For example, silicon dioxide (quartz), aluminum oxide, or yttrium oxide can be used as the dielectric plate 2809. Alternatively, other protective layers can be further formed on the surface of the dielectric plate 2809. These protective layers can be made of materials such as magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon dioxide, aluminum oxide, or yttrium oxide. Because the dielectric plate 2809 is exposed to the particularly high-density region of the high-density plasma 2810 (described later), damage can be mitigated by providing a protective layer. As a result, the increase of particles during processing can be suppressed.

[0396] The high-frequency generator 2803 is capable of generating microwaves, for example, at frequencies above 0.3 GHz and below 3.0 GHz, above 0.7 GHz and below 1.1 GHz, or above 2.2 GHz and below 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to a mode converter 2805 via a waveguide 2804. In the mode converter 2805, the transmitted TE-mode microwaves are converted to TEM-mode microwaves. These microwaves are then transmitted to a slotted antenna plate 2808 via a waveguide 2807. Multiple slots are provided in the slotted antenna plate 2808, through which microwaves pass and through a dielectric plate 2809. An electric field is then generated below the dielectric plate 2809, thereby generating a high-density plasma 2810. The high-density plasma 2810 includes ions and free radicals depending on the type of gas supplied from the gas supply source 2801. For example, the high-density plasma 2810 includes oxygen free radicals, etc.

[0397] At this time, the film quality on the substrate 2811 can be improved by utilizing the ions and free radicals generated in the high-density plasma 2810. Furthermore, it is sometimes preferable to apply a bias voltage to one side of the substrate 2811 using a high-frequency power supply 2816. For example, an RF (Radio Frequency) power supply with frequencies such as 13.56 MHz or 27.12 MHz can be used as the high-frequency power supply 2816. By applying a bias voltage to one side of the substrate, ions in the high-density plasma 2810 can be efficiently directed to the depth of the openings in the film on the substrate 2811.

[0398] For example, oxygen radical treatment using high-density plasma 2810 can be performed in processing chamber 2706b or processing chamber 2706c by introducing oxygen from gas supply source 2801.

[0399] Next, use FIGS. 16A-16D The cross-sectional schematic diagram shown illustrates processing chambers 2706a and 2706d.

[0400] Processing chambers 2706a and 2706d are, for example, processing chambers capable of irradiating the object being processed with electromagnetic waves. Note that the only difference between processing chambers 2706a and 2706d is the type of electromagnetic wave. Since the other structures of processing chambers 2706a and 2706d are the same, they will be described together below.

[0401] Processing chambers 2706a and 2706d include one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust outlet 2830. Additionally, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the processing chambers 2706a and 2706d.

[0402] A gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. A vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. A lamp 2820 is configured opposite to a substrate holder 2825. The substrate holder 2825 functions to hold the substrate 2824. Additionally, the substrate holder 2825 includes a heating mechanism 2826 internally and functions to heat the substrate 2824.

[0403] As for lamp 2820, a light source that can emit electromagnetic waves such as visible light or ultraviolet light can be used, for example. For example, a light source that can emit electromagnetic waves with peak values ​​in the wavelength regions of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm can be used.

[0404] For example, as lamp 2820, light sources such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps can be used.

[0405] For example, some or all of the electromagnetic waves emitted from lamp 2820 can be drawn into substrate 2824, thereby improving the quality of films, etc., on substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. In addition, when defects are generated or reduced, or impurities are removed while heating substrate 2824, defects can be generated or reduced, or impurities can be removed efficiently.

[0406] Alternatively, for example, electromagnetic waves emitted from lamp 2820 can be used to heat substrate holder 2825, thereby heating substrate 2824. In this case, it is not necessary to include heating mechanism 2826 inside substrate holder 2825.

[0407] Vacuum pump 2828 can be found in the description of vacuum pump 2817. Heating mechanism 2826 can be found in the description of heating mechanism 2813. Gas supply source 2821 can be found in the description of gas supply source 2801.

[0408] By using the manufacturing apparatus described above, impurities can be prevented from entering the processed material and the membrane quality can be improved.

[0409] <Examples of variations of semiconductor devices>

[0410] The following uses FIG. 16A An example of a semiconductor device illustrating one aspect of the present invention.

[0411] FIG. 16B This is a top view of a semiconductor device. FIG. 16A It is along FIG. 16C A cross-sectional view of the section with the dotted and dashed lines A1-A2 in the diagram. FIG. 16A It is along FIG. 16D The cross-sectional view of the section with dotted lines A3-A4 in the figure. FIG. 16A It is along FIG. 16A The cross-sectional view of the section marked with dashed lines A5-A6. For clarity, in FIGS. 16A-16D Some constituent elements are omitted in the top view.

[0412] Note that in FIGS. 16A-16D In the semiconductor device shown, the same reference numerals are used for components that have the same function as those in the semiconductor device shown in the <Structure Examples of Semiconductor Devices>. Note that the materials constituting the semiconductor device in this section may be the materials described in detail in the <Structure Examples of Semiconductor Devices>.

[0413] FIGS. 1A-1D The semiconductor device shown is FIGS. 16A-16D The example shown is a modified version of the semiconductor device. FIGS. 1A-1D The semiconductor device shown is FIGS. 16A-16D The semiconductor device shown differs in that it includes oxides 230c and 230d; and includes insulators 271, 272 and 273.

[0414] FIGS. 16A-16D The semiconductor device shown includes oxide 230c on oxide 230b and oxide 230d on oxide 230c in transistors 200a and 200b. Oxides 230c and 230d are disposed in openings formed in insulators 280 and 275. Furthermore, oxide 230c is in contact with the top surface of insulator 224, the side surface of oxide 230a, the top surface and side surface of oxide 230b, the side surface of oxide 243, the side surface of conductor 242, the side surface of insulator 271, the side surface of insulator 273, the side surface of insulator 275, and the side surface of insulator 280. Additionally, the uppermost part of oxide 230c and the uppermost part of oxide 230d are in contact with insulator 282.

[0415] Furthermore, by configuring oxide 230d on oxide 230c, the diffusion of impurities from the structure formed above oxide 230d to oxide 230b or oxide 230c can be suppressed. Additionally, by configuring oxide 230d on oxide 230c, the upward diffusion of oxygen from oxide 230b or oxide 230c can be suppressed.

[0416] Furthermore, when viewed in cross-section along the channel length of the transistor, it is preferable that the oxide 230b has a trench and the oxide 230c is embedded in the trench. In this case, the oxide 230c is arranged to cover the inner wall (sidewalls and bottom surface) of the trench. Additionally, the thickness of the oxide 230c is preferably approximately the same as the depth of the trench. By employing the above structure, even if a damaged area is formed on the surface of the oxide 230b corresponding to the bottom of the opening when forming the opening for embedding the conductor 260, etc., this damaged area can be removed. Therefore, undesirable electrical characteristics of the transistor 200 caused by the damaged area can be suppressed.

[0417] Preferably, the ratio of the number of In atoms to element M in the metal oxide used for oxide 230c is greater than the ratio of the number of In atoms relative to element M in the metal oxides used for oxide 230a or oxide 230d.

[0418] Note that when making oxide 230c the dominant pathway for charge carriers, it is preferable that the atomic ratio of indium to the dominant metal element in oxide 230c is greater than that in oxide 230b. Furthermore, the atomic ratio of In to element M in oxide 230c is preferably greater than that in oxide 230b. By using a metal oxide with a high indium content in the channel formation region, the on-state current of the transistor can be increased. Therefore, by making the atomic ratio of indium to the dominant metal element in oxide 230c greater than that in oxide 230b, oxide 230c can become the dominant pathway for charge carriers. Additionally, it is preferable that the conduction band bottom of oxide 230c is further from the vacuum level than the conduction band bottoms of oxides 230a and 230b. In other words, the electron affinity of oxide 230c is preferably greater than that of oxides 230a and 230b. At this point, the main pathway for charge carriers is oxide 230c.

[0419] Specifically, as oxide 230c, metal oxides or indium oxides with an In:M:Zn ratio of 4:2:3 or similar, an In:M:Zn ratio of 5:1:3 or similar, or an In:M:Zn ratio of 10:1:3 or similar can be used.

[0420] Furthermore, CAAC-OS is preferably used as oxide 230c, and the c-axis of the crystals contained in oxide 230c is preferably oriented in a direction substantially perpendicular to the formed surface or top surface of oxide 230c. CAAC-OS has the property of readily moving oxygen in a direction perpendicular to the c-axis. Therefore, the oxygen contained in oxide 230c can be supplied to oxide 230b with high efficiency.

[0421] Oxide 230d preferably contains at least one of the metal elements constituting the metal oxide for oxide 230c, and more preferably contains all of these metal elements. For example, it is preferred that In-M-Zn oxide, In-Zn oxide, or indium oxide is used as oxide 230c, and In-M-Zn oxide, M-Zn oxide, or an oxide of element M is used as oxide 230d. This reduces the defect state density at the interface between oxide 230c and oxide 230d.

[0422] Preferably, the conduction band bottom of oxide 230d is closer to the vacuum level than that of oxide 230c. In other words, the electron affinity of oxide 230d is preferably smaller than that of oxide 230c. In this case, oxide 230d is preferably a metal oxide that can be used for oxide 230a or oxide 230b. In this case, the dominant pathway for charge carriers is oxide 230c.

[0423] Specifically, for oxide 230c, a metal oxide or indium oxide can be used with an In:M:Zn ratio of 4:2:3 or similar, an In:M:Zn ratio of 5:1:3 or similar, or an In:M:Zn ratio of 10:1:3 or similar. For oxide 230d, a metal oxide or oxide of element M can be used with an In:M:Zn ratio of 1:3:4 or similar, an M:Zn ratio of 2:1 or similar, or an M:Zn ratio of 2:5 or similar. Note that "similar" includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as element M.

[0424] Furthermore, oxide 230d is preferably a metal oxide that inhibits oxygen diffusion or permeation more than oxide 230c. By providing oxide 230d between insulator 250 and oxide 230c, oxygen can be efficiently supplied to oxide 230b through oxide 230c.

[0425] Furthermore, when the atomic ratio of In to the main metal element in the metal oxide used for oxide 230d is less than that in the metal oxide used for oxide 230c, In diffusion to the insulator 250 side can be suppressed. Additionally, the atomic ratio of In to element M in oxide 230d is preferably greater than that in oxide 230c. Since insulator 250 is used as a gate insulator, In entering insulator 250 or the like leads to poor transistor characteristics. Therefore, by providing oxide 230d between oxide 230c and insulator 250, a highly reliable semiconductor device can be provided.

[0426] Note that oxide 230c can also be disposed in each transistor 200. In other words, the oxide 230c of transistor 200 may not contact the oxide 230c of transistor 200 adjacent to transistor 200 in the channel width direction. Alternatively, the oxide 230c of transistor 200 and the oxide 230c of transistor 200 adjacent to transistor 200 in the channel width direction may be separated. In other words, oxide 230c may not be disposed between transistor 200 and transistor 200 adjacent to transistor 200 in the channel width direction.

[0427] When a semiconductor device having the above-described structure has multiple transistors 200 arranged in the channel width direction, oxide 230c is independently provided in each transistor 200. Therefore, the generation of parasitic transistors between transistors 200 and transistors 200 adjacent to each other in the channel width direction can be suppressed, thereby suppressing the aforementioned leakage paths. Thus, a semiconductor device with good electrical characteristics that can be miniaturized or highly integrated can be provided.

[0428] FIG. 1B The semiconductor device shown includes an insulator 271 on a conductor 242, an insulator 273 on the insulator 271, and an insulator 272 in contact with the side surface of oxide 230b, the side surface of oxide 243, and the side surface of conductor 242.

[0429] Insulator 271 preferably has an insulating film that at least has the function of blocking oxygen. Therefore, insulator 271 preferably has the function of inhibiting oxygen diffusion. For example, compared with insulator 280, insulator 271 preferably has the function of further inhibiting oxygen diffusion. As insulator 271, for example, a silicon-containing nitride such as silicon nitride can be used.

[0430] Similar to insulator 224, insulator 273 preferably contains an excess oxygen region or excess oxygen. Furthermore, the concentration of impurities such as water and hydrogen in insulator 273 is preferably reduced. For example, silicon oxide, silicon oxynitride, etc., can be appropriately used as insulator 273. By providing an insulator containing excess oxygen in contact with insulator 250, the oxygen vacancies in oxide 230 are reduced by oxygen diffusing through insulator 250 to oxide 230, thereby improving the reliability of transistor 200.

[0431] Insulator 272 is preferably used as an insulating film that at least blocks oxygen. Therefore, insulator 272 preferably has the function of inhibiting oxygen diffusion. For example, compared to insulator 280, insulator 272 preferably has a further function of inhibiting oxygen diffusion. As insulator 272, a silicon-containing nitride, such as silicon nitride, can be used.

[0432] By providing the aforementioned insulators 271 and 272, the conductor 242 can be surrounded by an insulator that blocks oxygen. In other words, the diffusion of oxygen added during the formation of insulator 275 or oxygen contained in insulator 273 into the conductor 242 can be suppressed. Therefore, the direct oxidation of the conductor 242 due to oxygen added during the formation of insulator 275 or oxygen contained in insulator 273, which would otherwise increase resistivity and reduce current, can be prevented.

[0433] Notice, FIGS. 17A-22 The diagram shows a structure in which insulator 272 contacts the sides of oxides 230a, 230b, 243, conductor 242, insulator 271, and insulator 273. However, insulator 272 only needs to contact the sides of insulator 271 and conductor 242. For example, sometimes insulator 272 contacts the sides of oxides 230a, 230b, 243, conductor 242, and insulator 271 but not insulator 273. In this case, the side of insulator 273 contacts insulator 275.

[0434] According to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with large storage capacity can be provided. According to one aspect of the present invention, a semiconductor device with small transistor characteristic non-uniformity can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Additionally, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with large on-state current can be provided. Additionally, according to one aspect of the present invention, a low-power semiconductor device can be provided. Furthermore, according to one aspect of the present invention, a novel semiconductor device can be provided.

[0435] As described above, the structures and methods shown in this embodiment can be appropriately combined with other structures and methods shown in this embodiment or other embodiments.

[0436] (Implementation Method 2)

[0437] In this embodiment, refer to FIG. 17A One method of using a semiconductor device as a storage device is described.

[0438] [Storage Device 1]

[0439] FIG. 17A An example of a semiconductor device (memory device) according to one aspect of the present invention is shown. FIG. 17A The semiconductor device shown has a capacitor 100a disposed on transistor 200a and a capacitor 100b disposed on transistor 200b. Note that capacitors 100a and 100b are sometimes referred to collectively as capacitor 100 below.

[0440] Transistors 200a and 200b as described in the above embodiments can be used. That is, FIGS. 1A-1D The semiconductor device shown has in FIG. 17A The semiconductor device shown has a structure in which capacitors 100a and 100b are provided. Note that the structures of transistors 200a and 200b can be referred to the description of transistors 200a and 200b in the above embodiment.

[0441] Here, one of the source and drain of transistor 200a is electrically connected to the first electrode of capacitor 100a, the other of the source and drain of transistor 200a is electrically connected to one of the source and drain of transistor 200b, and the other of the source and drain of transistor 200b is electrically connected to the first electrode of capacitor 100b. Transistor 200a and capacitor 100a, and transistor 200b and capacitor 100b, connected in this way, are used as storage cells in a storage device. Therefore, the following sometimes... FIG. 17A The semiconductor device shown, including transistor 200a, transistor 200b, capacitor 100a, and capacitor 100b, is called memory cell 400.

[0442] In the memory cell 400, by placing the conductor 248 under the oxide 230, the parasitic capacitance of the conductor 248 and the bit lines disposed in contact with the conductor 248 can be reduced. As a result, the electrostatic capacitance required by the capacitor 100 is reduced, thus allowing for miniaturization of the capacitor 100. For example, capacitor 100a can overlap with transistor 200a, and capacitor 100b can overlap with transistor 200b. Therefore, by miniaturizing the capacitor 100, the memory cell 400 can be miniaturized or highly integrated. Furthermore, by miniaturizing or highly integrating the memory cell 400, a semiconductor device with a large storage capacity can be provided.

[0443] In the memory cell 400, by placing the conductor 248 under the oxide 230, interference between the capacitors 100a and 100b and the leads of the memory cell 400 can be prevented. Therefore, the electrostatic capacitance of the capacitors 100a and 100b can be increased without increasing the area occupied by the memory cell 400.

[0444] The capacitor 100 is disposed on the insulator 283. The capacitor 100 includes a conductor 110 used as a first electrode, a conductor 120 used as a second electrode, and an insulator 130 used as a dielectric.

[0445] Conductors 110 and 120 can be made of conductors that can be used in conductors 205, etc. Note that in FIG. 17B and FIG. 17A In this embodiment, conductors 110 and 120 are single-layer structures, but are not limited to this structure and may also have two or more layers in a stacked structure. For example, a conductor with high density between the barrier conductor and the highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0446] In addition, the insulator 130 may be made of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride, hafnium nitride, etc., and may be provided in a stacked or single layer.

[0447] For example, the insulator 130 preferably uses a laminated structure of materials with high insulating stress resistance, such as silicon oxynitride, and materials with high dielectric constant (high-k). By adopting this structure, the capacitor 100 can include an insulator with high dielectric constant (high-k) to ensure sufficient capacitance, and can include an insulator with high insulating stress resistance to improve insulating stress resistance, thereby suppressing electrostatic damage to the capacitor 100.

[0448] Note that insulators that are high-k materials (materials with relatively high dielectric constants) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0449] On the other hand, materials with high insulation and stress resistance (materials with relatively low dielectric constant) include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, and resins.

[0450] In addition, a conductor 240 is provided, which serves as a plug for electrically connecting transistor 200a and capacitor 100a, and a plug for electrically connecting transistor 200b and capacitor 100b.

[0451] like FIG. 17A As shown, the bottom surface of the conductor 240 disposed between transistor 200a and capacitor 100a contacts conductor 242a, and the top surface contacts conductor 110 of capacitor 100a. Furthermore, the bottom surface of the conductor 240 disposed between transistor 200b and capacitor 100b contacts conductor 242c, and the top surface contacts conductor 110 of capacitor 100b. Moreover, it is preferable that the insulator 241 is disposed in contact with the side surface of the conductor 240 used as a plug.

[0452] Furthermore, an insulator 241 is provided in contact with the inner wall of the openings of insulators 275, 280, 282, and 283, a first conductor of a conductor 240 is provided in contact with the side of the insulator 241, and a second conductor of the conductor 240 is provided inside the conductor 240. Additionally, in FIG. 17B and FIG. 17BIn this embodiment, a first conductor 240 and a second conductor 240 are stacked together, but the present invention is not limited thereto. For example, the conductor 240 may also have a single-layer structure or a stacked structure of three or more layers.

[0453] The conductor 240 is preferably made of a conductive material with tungsten, copper, or aluminum as its main components. Furthermore, the conductor 240 may also have a multilayer structure. When the conductor 240 adopts a multilayer structure, the conductor in contact with the insulators 283, 282, 280, and 275 is preferably made of a conductive material that inhibits the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc., are preferred. The conductive material that inhibits the permeation of impurities such as water and hydrogen can be used as a single layer or in multilayers. This prevents impurities such as water and hydrogen contained in the layer above the insulator 283 from mixing into the oxide 230 through the conductor 240.

[0454] For example, silicon nitride, aluminum oxide, silicon oxynitride, etc., can be used as the insulator 241. Because the insulator 241 is disposed in contact with insulators 283, 282, and 275, impurities such as water and hydrogen contained in insulators 280 can be suppressed from being mixed into oxide 230 through conductor 240. In particular, silicon nitride has high hydrogen-blocking properties and is therefore preferred. Furthermore, it can prevent oxygen contained in insulator 280 from being absorbed by conductor 240.

[0455] like FIG. 17B As shown, memory cells 400 and memory cells 401 having the same structure as memory cells 400 can also be arranged in the channel length direction.

[0456] exist FIG. 18 In the semiconductor device shown, an insulator 210 is disposed beneath an insulator 212, and a conductor 288 is disposed beneath the insulator 210. The top surface of the conductor 288 is in contact with the bottom surface of the conductor 248 of the memory cell 400 and the memory cell 401. Here, the insulator 212 can be any insulator that can be used for the insulator 280. Furthermore, the conductor 288 can be any conductor that can be used for the conductor 205.

[0457] Conductor 288 is used as wiring. That is, memory cell 400 and memory cell 401 are electrically connected to conductor 288, which is used as wiring, through conductor 248.

[0458] Here, the conductors 288 used as bit lines and the conductors 260 used as word lines are preferably arranged orthogonally. Transistors 200 and capacitors 100 are formed in the regions where the conductors 288 and 260 are orthogonal, and the memory cells including the transistors 200 and capacitors 100 are arranged in a matrix.

[0459] Thus, by arranging memory cells in a matrix within the same layer, a cell array (also known as a memory cell layer) can be constructed. By adopting the above cell array structure, the spacing between adjacent cells can be reduced, thereby reducing the projected area of ​​the cell array and achieving high integration.

[0460] [Storage Device 2]

[0461] then, FIG. 17A An example of a semiconductor device (memory device) according to one aspect of the present invention is shown. In the semiconductor device according to one aspect of the present invention, FIG. 18 The memory cell 400 shown is positioned above the transistor 300. That is, transistors 200a and 200b are positioned above transistor 300, and capacitors 100a and 100b are positioned above transistors 200a and 200b. Note that the capacitor 100 and transistor 200 described above can be used as the capacitor 100 and transistor 200, and a detailed structure can be referenced.

[0462] Transistor 200 is a transistor whose channel is formed in a semiconductor layer containing oxide semiconductor. Because transistor 200 has a low off-state current, it can retain stored content for a long time when used in a memory device. In other words, since refresh operations are not required or occur at extremely low frequencies, the power consumption of the memory device can be significantly reduced.

[0463] As described in the above embodiments, metal oxides such as In-M-Zn oxide can be formed on a substrate using sputtering or the like. Therefore, a memory cell 400, consisting of transistors 200 and capacitors 100, can be disposed on and superimposed on a drive circuit, such as transistors 300, formed on the silicon substrate. This reduces the area occupied by peripheral circuitry within a single chip and increases the area occupied by the memory cell array, thereby increasing the storage capacity of the semiconductor device.

[0464] By FIG. 18 The storage devices shown are configured in a matrix shape, which can form a storage cell array.

[0465] <Transistor 300>

[0466] Transistor 300 is disposed on substrate 311 and includes: a conductor 316 used as a gate, an insulator 315 used as a gate insulator, a semiconductor region 313 formed by a portion of substrate 311, and low-resistance regions 314a and 314b used as source or drain regions. Transistor 300 may be p-channel or n-channel.

[0467] Here, in FIG. 18 In the transistor 300 shown, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. Furthermore, a conductor 316 is provided such that it covers the side and top surfaces of the semiconductor region 313 with an insulator 315 in between. The conductor 316 can be made of a material with an adjustable work function. Because of the convex portion of the semiconductor substrate, this transistor 300 is also called a FIN-type transistor. Alternatively, an insulator used to form a mask for the convex portion can be provided in contact with the upper surface of the convex portion. Furthermore, although the case where the convex portion is formed by processing a portion of the semiconductor substrate is shown here, a semiconductor film with convex portions can also be formed by processing an SOI substrate.

[0468] Notice, FIG. 18 The structure of transistor 300 shown is just an example and is not limited to the above structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0469] <Wiring Layer>

[0470] Wiring layers, including interlayer films, wiring, and plugs, can also be provided between the various structures. Furthermore, multiple wiring layers can be provided depending on the design. Here, in conductive bodies that function as plugs or wiring, multiple structures are sometimes represented by the same reference numeral. Furthermore, in this specification, wiring and plugs electrically connected to wiring can also be considered as a single component. That is, a portion of the conductive body is sometimes used as wiring, and a portion of the conductive body is sometimes used as a plug.

[0471] For example, in transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductors 328 and 330, which are electrically connected to capacitor 100 or transistor 200, are embedded within insulators 320, 322, 324, and 326. Additionally, conductors 328 and 330 are used as connectors or wiring.

[0472] Furthermore, the insulator used as an interlayer film can be used as a planarization film covering the uneven shape underneath. For example, to improve the flatness of the top surface of insulator 322, planarization can also be achieved by using a planarization process such as chemical mechanical polishing (CMP).

[0473] A wiring layer can also be provided on the insulator 326 and the conductor 330. For example, in FIG. 18 In the structure, insulators 350, 352, and 354 are stacked sequentially. Furthermore, a conductor 356 is formed within insulators 350, 352, and 354. The conductor 356 is used as a plug or wiring.

[0474] An insulator 358 is provided on insulator 354 and conductor 356, and a conductor 288 used for wiring is provided on insulator 358. Furthermore, an insulator 210 is provided on conductor 288. Insulators 212, 214, 216, 222, 224, 280, 282, and 283 as shown in the above embodiment are provided on insulator 210, and transistors 200a and 200b are formed in these insulators.

[0475] Conductors 248 and 249 are embedded in insulators 210, 212, 214, 216, 222, and 224. Here, conductor 248 is arranged in contact with the top surface of conductor 288.

[0476] As described above, the conductor 240, which serves as a plug, is provided in contact with the top surface of the conductor 242. Furthermore, an insulator 241 is provided in contact with the side surface of the conductor 240. Additionally, a conductor 110 is provided on both the insulator 283 and the conductor 240 in contact with the conductor 240. Furthermore, an insulator 274 is provided on the insulator 283 in a region that does not overlap with the insulator 280.

[0477] The capacitors 100a and 100b described above are formed on the insulator 283. Furthermore, an insulator 150 is provided on the conductor 120 and the insulator 130 that form the capacitor 100.

[0478] As insulators that can be used as interlayer films, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, etc., which have insulating properties.

[0479] For example, by using a material with a low relative permittivity in the insulator used as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select the material according to the function of the insulator.

[0480] For example, insulators 150, 274, 210, 358, 352, and 354 preferably have a low relative permittivity. For example, the insulator preferably contains silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, or resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon oxynitride, fluorinated silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide and resin. Since silicon oxide and silicon oxynitride are thermally stable, by combining them with resin, a laminated structure with thermal stability and a low relative permittivity can be achieved. Examples of resins include polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, and acrylic resins.

[0481] Furthermore, by surrounding the transistor using an oxide semiconductor with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, it is sufficient to use an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen as insulators 283, 282, 214, 212 and 350.

[0482] As an insulator that suppresses impurities such as hydrogen and oxygen permeation, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used, either as a single layer or in layers. Specifically, as an insulator that suppresses impurities such as hydrogen and oxygen permeation, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as silicon oxynitride and silicon nitride, can be used.

[0483] The preferred conductor for use in wiring and plugs is a material containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. Alternatively, highly conductive semiconductors such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides may also be used.

[0484] For example, conductors 328, 330, 356, 288, 110, and 120 can be made of conductive materials such as metallic materials, alloy materials, metal nitride materials, and metal oxide materials formed from the above-mentioned materials, either in a single layer or in layers. High-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred, with tungsten being particularly preferred. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0485] <Wires or connectors with oxide semiconductor layers>

[0486] Note that when an oxide semiconductor is used in a transistor 200, an insulator with an excess oxygen region is sometimes provided near the oxide semiconductor. In this case, it is preferable to provide a barrier insulator between the insulator with the excess oxygen region and the conductor provided in the insulator with the excess oxygen region.

[0487] For example, in ​ Preferably, an insulator 241 is disposed between an insulator 280 having excess oxygen and a conductor 240. By disposing the insulator 241 in contact with insulators 275, 282, and 283, the insulator 224 and the transistor 200 can have a structure sealed by a barrier insulator.

[0488] In other words, by providing insulator 241, the absorption of excess oxygen in insulator 280 by conductor 240 can be suppressed. Furthermore, by having insulator 241, the diffusion of hydrogen as an impurity through conductor 240 to transistor 200 can be suppressed.

[0489] Furthermore, as the insulator 241, an insulating material with the function of suppressing the diffusion of impurities such as water, hydrogen, and oxygen is preferably used. For example, silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide are preferred. In particular, silicon nitride has high hydrogen barrier properties, so it is preferred. In addition, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide can also be used.

[0490] like Figure 18 As shown, a structure can also be adopted in which insulator 280 is patterned and insulator 212 is in contact with insulator 283. That is, transistor 200 is sealed by insulator 212, insulator 214, insulator 282, and insulator 283. By adopting this structure, the mixing of hydrogen contained in insulator 274, insulator 150, etc. into insulator 280, etc., can be reduced.

[0491] Here, the conductor 240 penetrates the insulators 283 and 282, and as described above, the insulator 241 is disposed in contact with the conductor 240. This reduces the amount of hydrogen that may enter the inner surfaces of the insulators 212, 214, 282, and 283 through the conductor 240. Thus, the transistor 200 can be sealed by the insulators 212, 214, 282, 283, and 241, while reducing the ingress of impurities such as hydrogen contained in the insulator 274 from the outside.

[0492] <cut line>

[0493] The following describes the dicing lines (sometimes called dividing lines, severing lines, or cut-off lines) used when dividing a large-area substrate into multiple semiconductor devices in the shape of a chip by dividing each semiconductor component. As a dicing method, for example, sometimes a groove (dicing line) for dividing the semiconductor components is first formed in the substrate, and then the substrate is cut off at the dicing line to obtain multiple semiconductor devices that have been divided (segmented).

[0494] Here, for example, such as Figure 18 As shown, it is preferable to design the area in contact with insulator 283 and insulator 212 to overlap with the cutting line. That is, openings are provided in insulator 282, insulator 280, insulator 275, insulator 224, insulator 222, insulator 216 and insulator 214 near the area that forms the cutting line at the edge of the multiple storage cells 400.

[0495] In other words, insulator 212 and insulator 283 are in contact with each other in the openings provided in insulators 282, 280, 275, 224, 222, 216, and 214. In this case, insulators 212 and 283 can be formed using the same material and the same method, for example. By using the same material and the same method to form insulators 212 and 283, the tightness can be improved. For example, silicon nitride is preferably used.

[0496] By employing this structure, the transistor 200 can be surrounded by insulators 212, 214, 282, and 283. At least one of insulators 212, 214, 282, and 283 has the function of suppressing the diffusion of oxygen, hydrogen, and water. Therefore, even if the substrate is divided into multiple chips according to each circuit region where the semiconductor component shown in this embodiment is formed, it is possible to prevent impurities such as hydrogen or water from being mixed in from the side direction of the truncated substrate and to prevent such impurities from diffusing into the transistor 200.

[0497] Furthermore, by employing this structure, excess oxygen in insulators 280 and 224 can be prevented from diffusing to the outside. Therefore, excess oxygen in insulators 280 and 224 is efficiently supplied to the oxide forming the channel in transistor 200. This oxygen reduces oxygen vacancies in the oxide forming the channel in transistor 200. Consequently, the oxide forming the channel in transistor 200 can become an oxide semiconductor with low defect state density and stable characteristics. In other words, good reliability can be improved while suppressing variations in the electrical characteristics of transistor 200.

[0498] Note that in Figure 17A , Figure 17B and Figure 18 The storage device shown uses a planar shape for capacitors 100a and 100b, but the storage device shown in this embodiment is not limited to this. For example, such as Figure 19 As shown, the shapes of capacitors 100a and 100b can also be cylindrical. Figure 19 The structure below the insulator 150 of the storage device shown is similar to Figure 18 The semiconductor device shown is the same.

[0499] Figure 19 The capacitors 100a and 100b shown include an insulator 150 on an insulator 130, an insulator 142 on an insulator 150, a conductor 115 disposed in an opening formed in the insulator 150 and the insulator 142, a conductor 115 and an insulator 145 on the insulator 142, a conductor 125 on the insulator 145, and a conductor 125 and an insulator 152 on the insulator 145. At least a portion of the conductors 115, 145, and 125 are disposed in the two openings formed in the insulators 150 and 142. Additionally, an insulator 154 is disposed on the insulator 152, and conductors 153 and 156 are disposed on the insulator 154. Furthermore, a conductor 140 is disposed within an opening in the insulator 152 and the insulator 154.

[0500] Conductor 115 is used as the lower electrode of capacitor 100, conductor 125 is used as the upper electrode of capacitor 100, and insulator 145 is used as the dielectric of capacitor 100. Capacitor 100 has a structure in which the upper and lower electrodes are separated by a dielectric material not only on the bottom surface but also on the side surfaces within the openings of insulators 150 and 142, thus increasing the electrostatic capacitance per unit area. The deeper the opening, the greater the electrostatic capacitance of capacitor 100. In this way, by increasing the electrostatic capacitance per unit area of ​​capacitor 100, miniaturization or high integration of semiconductor devices can be advanced.

[0501] As insulator 152, an insulator that can be used as insulator 280 can be used. Alternatively, as insulator 142, an insulator that is used as an etch stop layer when forming the opening of insulator 150 and can be used as insulator 214 is preferably used.

[0502] Furthermore, the top-view shape of the openings formed in insulators 150 and 142 can be a quadrilateral, a polygon other than a quadrilateral, a polygon with rounded corners, or a circular shape such as an ellipse. Here, it is preferable that the area of ​​the opening overlapping with the transistor 200 is large when viewed from above. By adopting this structure, the area occupied by the semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0503] The conductor 115 is disposed in contact with openings formed in the insulators 142 and 150. The top surface of the conductor 115 is preferably substantially aligned with the top surface of the insulator 142. Furthermore, the bottom surface of the conductor 115 contacts the conductor 110 through an opening in the insulator 130. The conductor 115 is preferably formed by an ALD or CVD method, for example, using a conductor suitable for conductor 205.

[0504] The insulator 145 is configured to cover both the conductor 115 and the insulator 142. For example, the insulator 145 is preferably formed by an ALD or CVD method. As the insulator 145, for example, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride, etc., can be used, and a multilayer or single-layer structure can be employed. For example, as the insulator 145, an insulating film sequentially stacked with zirconium oxide, aluminum oxide, and zirconium oxide can be used.

[0505] Furthermore, the insulator 145 preferably uses a laminated structure of materials with high insulating stress resistance, such as silicon oxynitride, or materials with high dielectric constant (high-k). Alternatively, a laminated structure of materials with both high insulating stress resistance and high dielectric constant (high-k) materials can be used.

[0506] Note that insulators that are high-k materials (materials with relatively high dielectric constants) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. By using such a high-k material, the electrostatic capacitance of the capacitor 100 can be sufficiently ensured even if the insulator 145 is thickened. By thickening the insulator 145, leakage current generated between the conductor 115 and the conductor 125 can be suppressed.

[0507] On the other hand, materials with high insulation and stress resistance include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with both carbon and nitrogen, porous silicon oxide, and resins. For example, silicon nitride (SiN) formed by the ALD method can be used in sequence. x ), silicon dioxide (SiO2) formed by the PEALD method x Silicon nitride (SiN) formed by ALD method x The insulating film of the capacitor 100 is used. By using such an insulator with high insulation stress resistance, the insulation stress resistance is improved, thereby suppressing electrostatic damage.

[0508] The conductor 125 is disposed in such a way that it fills the openings formed in the insulator 142 and the insulator 150. Furthermore, the conductor 125 is electrically connected to the conductor 153, which is used as a wiring conductor, via the conductor 140. The conductor 125 is preferably formed by an ALD or CVD method, for example, using a conductor suitable for conductor 205.

[0509] Additionally, conductor 153 is disposed on insulator 154 and covered by insulator 156. Conductor 153 can be a conductor that can be used for conductor 110, and insulator 156 can be an insulator that can be used for insulator 152. Here, conductor 153 is in contact with the top surface of conductor 140.

[0510] [Storage Device 3]

[0511] Figure 20A , Figure 20B and Figure 21 An example of a semiconductor device (memory device) according to one aspect of the present invention is shown.

[0512] Figure 20A The memory cell 400 shown is Figure 17A The difference in the memory cell 400 shown is the shape of capacitors 100a and 100b.

[0513] Capacitor 100a includes a conductor 242a, an insulator 275 disposed to cover the conductor 242a, and a conductor 294a on the insulator 275. Furthermore, capacitor 100b includes a conductor 242c, an insulator 275 disposed to cover the conductor 242c, and a conductor 294b on the insulator 275. In other words, capacitors 100a and 100b constitute a MIM (Metal-Insulator-Metal) capacitor.

[0514] Here, one of the pair of electrodes included in the capacitor 100, namely the conductor 242, can also serve as the source or drain electrode of the transistor 200. Furthermore, the dielectric layer included in the capacitor 100 can also serve as the protective layer, namely the insulator 275, disposed in the transistor 200. Therefore, the manufacturing process of the capacitor 100 can be combined with the manufacturing process of the transistor, enabling the manufacture of highly productive semiconductor devices. Moreover, since one of the pair of electrodes included in the capacitor 100, namely the conductor 242, is used as the source or drain electrode of the transistor 200, the area in which the transistor 200 and the capacitor 100 are disposed can be reduced.

[0515] Note that, for example, materials suitable for conductor 242 can be used as conductors 294a and 294b.

[0516] For example, such as Figure 20B As shown, a structure can also be used in which memory cell 400 and memory cell 401 having the same structure as memory cell 400 are connected via a capacitor section. Here, Figure 20B The memory unit 400 and memory unit 401 shown have the same as Figure 20A The memory cell 400 shown has the same structure. Therefore, Figure 20B The detailed structure of memory cell 400 and memory cell 401 shown can be found in [reference]. Figure 20A The memory unit 400 shown is described.

[0517] exist Figure 20B In the cross-sectional view, a memory cell 400 including transistor 200a, transistor 200b, capacitor 100a and capacitor 100b and a memory cell 401 having the same structure as the memory cell 400 are connected to each other through a capacitor section.

[0518] like Figure 20B As shown, the conductor 294b, which serves as one electrode of the capacitor 100b included in the memory cell 400, also serves as one electrode of the capacitor included in the memory cell 401, which has the same structure as the memory cell 400. Additionally, although not shown, the conductor 294a, which serves as one electrode of the capacitor 100a included in the memory cell 400, also serves as an electrode on the left side of the memory cell 400, i.e. Figure 20B An electrode of a capacitor element of an adjacent semiconductor device in the A1 direction. Furthermore, the right side of memory cell 401, i.e. Figure 20B The units in the A2 direction also have the same structure.

[0519] Thus, by arranging memory cells in a matrix within the same layer, a cell array can be constructed. By adopting the above-described cell array structure, the spacing between adjacent cells can be reduced, thereby reducing the projected area of ​​the cell array and achieving high integration.

[0520] In addition, with Figure 17B Similarly, in Figure 20B In the semiconductor device shown, an insulator 210 is disposed beneath an insulator 212, and a conductor 288 is disposed beneath the insulator 210. Furthermore, the top surface of the conductor 288 contacts the bottom surface of the conductor 248 of the memory cell 400 and the memory cell 401. Therefore, the memory cell 400 and the memory cell 401 are electrically connected to the conductor 288 used as wiring via the conductor 248. Moreover, the conductor 288 used as bit lines and the conductor 260 used as word lines are preferably arranged orthogonally.

[0521] also, Figure 20A , Figure 20BThe cell array of the memory cell 400 shown is not only a single layer but can also be stacked. Figure 21 A cross-sectional view is shown of a structure consisting of n stacked cell arrays 610, each including memory cells 400. (See diagram below.) Figure 21 As shown, by stacking multiple unit arrays (unit arrays 610_1 to 610_n), the units can be integrated without increasing the area occupied by the unit arrays. That is, a 3D unit array can be constructed. Furthermore, since... Figure 20A , Figure 20B The capacitor 100 shown can be formed at a position lower than the top surface of the conductor 260, thus reducing the height of each cell array compared to capacitors using a cylinder structure. This allows for easier stacking of multiple cell arrays. Consequently, high integration of memory cells can be achieved, providing a semiconductor device with a large storage capacity.

[0522] [Storage device 4]

[0523] Figure 22 An example of a semiconductor device (memory device) using one aspect of the present invention is shown.

[0524] Figure 22 An example is shown where memory 470 has a transistor layer 413 including transistor 200T and four layers of memory cell layers 415 (memory cell layers 415_1 to memory cell layers 415_4). Note that transistor 200T has the same structure as transistor 200 shown in the above embodiment.

[0525] Memory cell layers 415_1 to 415_4 each include a plurality of memory cells 400. The memory cells 400 included in memory cell layers 415_1 to 415_4 have the same characteristics as... Figure 20A The memory cell 400 shown has the same structure. Therefore, detailed information about the memory cell 400 can be found in [reference needed]. Figure 20A Records, etc.

[0526] Here, conductor 248_1 in memory cell layer 415_1 is electrically connected to transistor 200T; conductor 248_2 in memory cell layer 415_2 is connected to conductor 242b in memory cell layer 415_1; conductor 248_3 in memory cell layer 415_3 is connected to conductor 242b in memory cell layer 415_2; and conductor 248_4 in memory cell layer 415_4 is connected to conductor 242b in memory cell layer 415_3. Note that in... Figure 22In this invention, conductor 248_1 is connected to the gate electrode of transistor 200T. However, the invention is not limited to this. The connection of conductor 248_1 can be appropriately set according to the circuit structure of memory 470.

[0527] As shown in the above embodiment, since region 232b of oxide 230b overlaps with conductor 242b, it has high carrier concentration and conductivity. Therefore, by adopting the above structure, region 232b of memory cell 400 disposed in each memory cell layer 415 can be electrically connected to transistor 200T through conductor 248.

[0528] As described above, since multiple memory cell layers can be stacked, the memory cells can be integrated and configured without increasing the area occupied by the cell array. Therefore, high integration of memory cells can be achieved, and a semiconductor device with large storage capacity can be provided.

[0529] The memory 470 is sealed by insulators 212, 214, 282, and 283 (hereinafter referred to as the sealing structure for convenience). An insulator 274 is disposed around the insulator 283. In addition, conductors 440 are disposed on the insulators 274, 283, and 212 and are electrically connected to the element layer 411.

[0530] Additionally, an insulator 280 is provided inside the sealed structure. The insulator 280 has the function of releasing oxygen by heating. Alternatively, the insulator 280 has an excess oxygen region.

[0531] Insulators 212 and 283 are preferably made of materials that have high hydrogen barrier properties. In addition, insulators 214 and 282 are preferably made of materials that have the function of capturing or fixing hydrogen.

[0532] For example, silicon nitride and silicon oxynitride are examples of materials that have high hydrogen barrier properties. In addition, aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are examples of materials that have the function of capturing or fixing hydrogen.

[0533] There are no particular restrictions on the crystal structure of the materials used for insulators 212, 214, 282, and 283; either amorphous or crystalline structures can be used. For example, amorphous alumina films are preferred as materials with the function of capturing or fixing hydrogen. Amorphous alumina sometimes captures or fixes more hydrogen than highly crystalline alumina.

[0534] Furthermore, it is preferable to also provide insulators 282 and 214 between transistor layer 413 and memory cell layer 415, or between each memory cell layer 415. Furthermore, it is preferable to provide insulator 296 between insulator 282 and insulator 214. Insulator 296 can be made of the same material as insulator 283. Alternatively, silicon oxide or silicon oxynitride can be used. Alternatively, known insulating materials can also be used.

[0535] Here, the following model can be considered as a model for the diffusion of excess oxygen in the insulator 280 relative to hydrogen in the oxide semiconductor in contact with the insulator 280.

[0536] Hydrogen in the oxide semiconductor diffuses to other structures through the insulator 280 in contact with the oxide semiconductor. Due to this hydrogen diffusion, excess oxygen in the insulator 280 reacts with the hydrogen in the oxide semiconductor to form OH bonds, which diffuse as OH atoms within the insulator 280. When the hydrogen atoms with OH bonds reach a material that has the function of capturing or fixing hydrogen (typically, insulator 282), they react with oxygen atoms bonded to atoms (e.g., metal atoms) in the insulator 282 and are captured or fixed by the insulator 282. On the other hand, the oxygen atoms with OH bonds can be considered to remain in the insulator 280 as excess oxygen. In other words, in this hydrogen diffusion, the excess oxygen in the insulator 280 is highly likely to play an intermediary role.

[0537] To meet the requirements of the above model, the manufacturing process of semiconductor devices is one of the important factors.

[0538] As an example, an insulator 280 containing excess oxygen is formed on an oxide semiconductor, followed by the formation of an insulator 282. Afterward, heat treatment is preferably performed. Specifically, this heat treatment is carried out in an oxygen-containing atmosphere, a nitrogen-containing atmosphere, or a mixed atmosphere of oxygen and nitrogen at a temperature of 350°C or higher, preferably 400°C or higher. The heat treatment time is set to 1 hour or more, preferably 4 hours or more, and more preferably 8 hours or more.

[0539] By performing the above heat treatment, the diffusion of hydrogen from the oxide semiconductor to the outside through insulators 280 and 282 can be suppressed. In other words, the absolute amount of hydrogen present in and around the oxide semiconductor can be reduced.

[0540] After the above heat treatment, insulator 283 is formed. Insulator 283 is a material with high hydrogen barrier properties, so it can suppress hydrogen from diffusing to the outside or hydrogen present on the outside from entering the inside, specifically the oxide semiconductor or insulator 280 side.

[0541] Note that the structure shown is formed after the heat treatment is performed on insulator 282, but it is not limited to this. For example, the heat treatment may also be performed after the formation of transistor layer 413 or after the formation of memory cell layers 415_1 to 415_3. Furthermore, when hydrogen diffuses to the outside through the heat treatment, the hydrogen diffuses upwards or laterally into transistor layer 413. Similarly, when heat treatment is performed after the formation of memory cell layers 415_1 to 415_3, hydrogen diffuses upwards or laterally.

[0542] The above-described sealing structure can be obtained by bonding insulator 212 and insulator 283 together using the above-described manufacturing process.

[0543] Thus, by employing the above-described structure and manufacturing process, a semiconductor device using an oxide semiconductor with reduced hydrogen concentration can be provided. This results in a semiconductor device with high reliability. Furthermore, according to one aspect of the present invention, a semiconductor device with excellent electrical characteristics can be provided.

[0544] The configurations and methods shown in this embodiment can be appropriately combined with the configurations, structures, and methods shown in other embodiments.

[0545] (Implementation Method 3)

[0546] In this embodiment, refer to Figure 23A , Figure 23B as well as Figures 24A to 24C The following describes a storage device (hereinafter sometimes referred to as an OS storage device) using an oxide-based semiconductor transistor (hereinafter sometimes referred to as an OS transistor) and a capacitor, according to one embodiment of the present invention. An OS storage device is a storage device comprising at least a capacitor and an OS transistor that controls the charging and discharging of the capacitor. Because the off-state current of an OS transistor is extremely small, an OS storage device has excellent retention characteristics and can therefore be used as a non-volatile memory.

[0547] <Example of storage device structure>

[0548] Figure 23A An example of the structure of an OS storage device is shown. Storage device 1400 includes peripheral circuitry 1411 and a storage cell array 1470. Peripheral circuitry 1411 includes row circuitry 1420, column circuitry 1430, output circuitry 1440, and control logic circuitry 1460.

[0549] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit precharges the wiring. The sense amplifier amplifies the data signal read from the memory cell. Note that the wiring described above is the wiring connected to the memory cells included in the memory cell array 1470, and its details are described below. The amplified data signal, as the data signal RDATA, is output to the outside of the memory device 1400 via the output circuit 1440. Furthermore, the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select the row to be accessed.

[0550] The storage device 1400 is supplied with a low power supply voltage (VSS), the peripheral circuit 1411 is supplied with a high power supply voltage (VDD), and the memory cell array 1470 is supplied with a high power supply voltage (VIL). In addition, the storage device 1400 receives external control signals (CE, WE, RE), address signals ADDR, and data signals WDATA. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

[0551] The control logic circuit 1460 processes externally input control signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. Control signal CE is the chip enable signal, control signal WE is the write enable signal, and control signal RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals can be input as needed.

[0552] The storage cell array 1470 includes a plurality of storage cells MCa and MCb configured in a row and column arrangement, and a plurality of wirings. Note that the storage device shown in this embodiment is as follows: Figure 23A As shown, a memory cell is formed by grouping memory cells MCa and MCb together. Furthermore, memory cells MCa and MCb are sometimes collectively referred to as memory cell MC. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MC, the number of memory cells MC included in a column, etc. Similarly, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MC, the number of memory cells MC included in a row, etc.

[0553] In addition, although Figure 23A An example is shown where the peripheral circuitry 1411 and the memory cell array 1470 are formed on the same plane, but this embodiment is not limited thereto. For example, as Figure 23BAs shown, the memory cell array 1470 can also be arranged overlapping a portion of the peripheral circuitry 1411. For example, the readout amplifier can also be arranged overlapping the memory cell array 1470.

[0554] As described in the above embodiment, metal oxides such as In-M-Zn oxide can be formed on a substrate using sputtering or the like. Therefore, the memory cell array 1470 can be disposed on and overlapped with the peripheral circuit 1411 formed on the silicon substrate. As a result, since the occupied area of ​​the memory cell array that can be disposed in one chip can be increased, the storage capacity of the semiconductor device can be increased.

[0555] Alternatively, a structure of stacked memory cell arrays 1470 can be adopted. By stacking multiple memory cell arrays 1470, memory cells can be integrated without increasing the area occupied by the cell arrays 1470. In other words, a 3D cell array can be formed. Thus, high integration of memory cells can be achieved, and a semiconductor device with large storage capacity can be provided.

[0556] exist Figures 24A to 24C The text describes a structural example of a storage cell that can be used for the aforementioned storage cells MCa and MCb.

[0557] [DOSRAM]

[0558] Figures 24A to 24C An example of the circuit structure of a DRAM memory cell is shown. In this specification and other materials, DRAM using a 1000 transistors and 1 capacitor type memory cell is sometimes referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Figure 24A The memory cell 1471 shown includes memory cells MCa and MCb. Here, memory cell MCa includes transistor M1a and capacitor CAa, and memory cell MCb includes transistor M1b and capacitor CAb. Note that transistors M1a and M1b include a gate (sometimes also called a top gate) and a back gate.

[0559] Transistor M1a's first terminal is connected to capacitor CAa's first terminal; transistor M1a's second terminal is connected to wiring BIL; transistor M1a's gate is connected to wiring WOLa; and transistor M1a's back gate is connected to wiring BGLa. Capacitor CAa's second terminal is connected to wiring CAL. Similarly, transistor M1b's first terminal is connected to capacitor CAb's first terminal; transistor M1b's second terminal is connected to wiring BIL; transistor M1b's gate is connected to wiring WOLb; and transistor M1b's back gate is connected to wiring BGLb. Capacitor CAb's second terminal is connected to wiring CAL.

[0560] Wiring BIL is used as the bit line, and wiring WOLa and WOLb are used as word lines. Wiring CAL is used to apply a specified potential to the second terminals of capacitors CAa and CAb. During data writing and reading, it is preferable to apply a low-level potential to wiring CAL. Wiring BGLa is used to apply a potential to the back gate of transistor M1a, and wiring BGLb is used to apply a potential to the back gate of transistor M1b. By applying any potential to wiring BGLa (wiring BGLb), the threshold voltage of transistor M1a (transistor M1b) can be increased or decreased.

[0561] here, Figure 24A The memory cell 1471 shown corresponds to Figure 17A The memory cell 400 is shown in the figure. That is, transistor M1a, capacitor CAa, transistor M1b, and capacitor CAb correspond to transistor 200a, capacitor 100a, transistor 200b, and capacitor 100b, respectively. In addition, wiring WOLa, wiring WOLb, and wiring BIL correspond to conductor 260 of transistor 200a, conductor 248 of transistor 200b, and conductor 288, respectively.

[0562] The storage device in this embodiment is not limited to the memory cell 1471, and the circuit structure can be changed. For example, in the storage device of this embodiment, such as Figure 24B As shown in memory cell 1472, the back gate of transistor M1a is connected to wiring WOLa but not to wiring BGLa, and the back gate of transistor M1b is connected to wiring WOLb but not to wiring BGLb. Furthermore, for example, the memory device of this embodiment... Figure 24C The memory cell 1473 shown can also be composed of a single-gate transistor, that is, transistors M1a and M1b excluding the back gate.

[0563] When the semiconductor device shown in the above embodiment is used in memory cell 1471, transistor 200a and transistor 200b can be used as transistor M1a, capacitor 100a and capacitor 100b can be used as capacitor CAa and capacitor CAb, respectively. By using OS transistors as transistors M1a and M1b, the leakage current of transistors M1a and M1b can be kept extremely low. In other words, since the written data can be held by transistors M1a and M1b for a long time, the refresh frequency of the memory cell can be reduced. Furthermore, the memory cell refresh operation can be eliminated. In addition, since the leakage current is extremely low, multi-valued data or analog data can be stored in memory cells 1471, 1472, and 1473.

[0564] Furthermore, in DOSRAM, when the read amplifier is arranged in a manner overlapping the memory cell array 1470, the bit lines can be shortened. In particular, as shown in the above embodiment, by providing the conductor 248 under the oxide 230, the bit lines can be shortened compared to the case where the conductor 248 is provided on the oxide 230. As a result, the bit line capacitance is reduced, thereby reducing the retention capacitance of the memory cell.

[0565] Note that the structure of the peripheral circuit 1411 and the memory cell array 1470 shown in this embodiment is not limited to the structure described above. Furthermore, the configuration or function of these circuits and the wiring and circuit elements connected to them can be changed, removed, or added as needed.

[0566] The structure shown in this embodiment can be implemented by appropriately combining it with structures described in other embodiments, etc.

[0567] (Implementation Method 4)

[0568] In this embodiment, refer to Figure 25A and Figure 25B An example of a chip 1200 in which the semiconductor device of the present invention is mounted is described. Multiple circuits (systems) are mounted on the chip 1200. Thus, the technology of integrating multiple circuits (systems) on a single chip is sometimes referred to as a System on Chip (SoC).

[0569] like Figure 25A As shown, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog computing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.

[0570] A bump (not shown) is provided on chip 1200, and the bump is as follows: Figure 25B It is connected to the first side of the printed circuit board (PCB) 1201 as shown. In addition, a plurality of bumps 1202 are provided on the back side of the first side of the PCB 1201, and the bumps 1202 are connected to the motherboard 1203.

[0571] Alternatively, storage devices such as DRAM 1221 and flash memory 1222 can be provided on the motherboard 1203. For example, the DOSRAM shown in the above embodiment can be applied to DRAM 1221. Furthermore, for example, by using the DOSRAM shown in the above embodiment to DRAM 1221, the storage capacity of DRAM 1221 can be increased.

[0572] CPU 1211 preferably has multiple CPU cores. Furthermore, GPU 1212 preferably has multiple GPU cores. Additionally, CPU 1211 and GPU 1212 may each have a memory for temporary data storage. Alternatively, a memory shared by both CPU 1211 and GPU 1212 may be provided on chip 1200. The aforementioned DOSRAM or similar memory can be used in this memory. Furthermore, GPU 1212 is suitable for parallel computation of multiple data sets, and can be used for image processing or product operations. By incorporating an image processing circuit or product operation circuit using the oxide semiconductor of the present invention as GPU 1212, image processing and product operations can be performed with low power consumption.

[0573] Furthermore, since the CPU1211 and GPU1212 are located on the same chip, the wiring between the CPU1211 and GPU1212 can be shortened, and data transfer from the CPU1211 to the GPU1212, data transfer between the memory of the CPU1211 and GPU1212, and transfer of the operation result from the GPU1212 to the CPU1211 after the operation in the GPU1212 is completed can be performed at high speed.

[0574] The analog arithmetic unit 1213 includes one or both of an analog-to-digital (A / D) conversion circuit and a digital-to-analog (D / A) conversion circuit. Alternatively, the aforementioned product summation circuit may also be provided in the analog arithmetic unit 1213.

[0575] The storage controller 1214 has circuitry that serves as a controller for the DRAM 1221 and circuitry that serves as an interface for the flash memory 1222.

[0576] Interface 1215 has interface circuitry for connecting to external devices such as display devices, speakers, microphones, imaging devices, and controllers. Controllers include mice, keyboards, and game console controllers. As the aforementioned interface, USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface) (registered trademark), etc., can be used.

[0577] The network circuit 1216 has the function of controlling the connection with LAN (Local Area Network) and the like. In addition, it may also have a network security circuit.

[0578] The aforementioned circuit (system) can be formed on chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, no additional manufacturing process is required, and chip 1200 can be manufactured at low cost.

[0579] The motherboard 1203, which includes a PCB 1201 with a chip 1200 having a GPU 1212, a DRAM 1221, and a flash memory 1222, can be referred to as a GPU module 1204.

[0580] The GPU module 1204 can reduce its size due to the presence of the chip 1200 using SoC technology. Furthermore, the GPU module 1204, with its high image processing capabilities, is suitable for use in portable electronic devices such as smartphones, tablets, laptops, and portable game consoles. Moreover, by utilizing the product-sum operation circuitry of the GPU 1212, methods such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN) can be executed. Thus, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0581] The structure shown in this embodiment can be implemented by appropriately combining it with structures shown in other embodiments, etc.

[0582] (Implementation Method 5)

[0583] This embodiment shows an example of an electronic component and electronic device equipped with the storage device or the like described in the above embodiment.

[0584] <Electronic Components>

[0585] First, refer to Figure 26A and Figure 26B An example of an electronic component assembled with a storage device 720 will be described.

[0586] Figure 26A A perspective view of the electronic component 700 and the substrate (circuit board 704) on which the electronic component 700 is mounted is shown. Figure 26A The electronic component 700 shown includes a storage device 720 within the mold 711. Figure 26A In this diagram, a portion of the electronic component 700 is omitted to represent its interior. The electronic component 700 includes a connection land 712 on the outside of the mold 711. The connection land 712 is electrically connected to electrode pads 713, which are electrically connected to the storage device 720 via leads 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. Circuit board 704 is completed by combining multiple such electronic components and electrically connecting them individually on the printed circuit board 702.

[0587] The storage device 720 includes a drive circuit layer 721 and a storage circuit layer 722. For example, the storage circuit layer 722 can be formed by using the 3D cell array shown in the above embodiment.

[0588] Figure 26B A perspective view of electronic component 730 is shown. Electronic component 730 is an example of SiP (System in Package) or MCM (Multi-Chip Module). In electronic component 730, an interposer 731 is disposed on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple memory devices 720 are disposed on the interposer 731.

[0589] Electronic component 730 illustrates an example of using storage device 720 as high-bandwidth memory (HBM). Additionally, semiconductor device 735 may utilize integrated circuits (semiconductor devices) such as CPUs, GPUs, and FPGAs.

[0590] The packaging substrate 732 can be a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. The through-hole board 731 can be a silicon through-hole board, a resin through-hole board, etc.

[0591] The through-hole board 731 has multiple wirings and electrically connects multiple integrated circuits with different terminal spacings. These wirings can be single-layered or multi-layered. Additionally, the through-hole board 731 has the function of electrically connecting the integrated circuits disposed on the through-hole board 731 to electrodes disposed on the packaging substrate 732. Therefore, the through-hole board is sometimes referred to as a "rewiring substrate" or "intermediate substrate." Furthermore, sometimes a through-electrode is provided in the through-hole board 731 to electrically connect the integrated circuits to the packaging substrate 732. Alternatively, when using a silicon through-hole board, a TSV (Through Silicon Via) can also be used as the through-electrode.

[0592] Silicon interposers are preferably used as the interposer 731. Since silicon interposers do not require active components, they can be manufactured at a lower cost than integrated circuits. On the other hand, the wiring of silicon interposers can be formed in semiconductor processes, making it easy to form fine wiring that is difficult to form when using resin interposers.

[0593] In HBM, numerous wirings are required to achieve wide memory bandwidth. Therefore, the mounting board for HBM must be capable of forming fine wirings at high density. Consequently, silicon mounting boards are preferred as mounting boards for HBM.

[0594] Furthermore, in SiP or MCM applications using silicon interposers, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuit and the interposer is less likely to occur. Additionally, due to the high surface flatness of the silicon interposer, poor connection between the integrated circuit and the interposer is less likely to occur. Silicon interposers are particularly preferred for 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged horizontally on the interposer.

[0595] Alternatively, a heat sink (heat plate) may be provided overlapping with the electronic component 730. When a heat sink is provided, it is preferable that the integrated circuits provided on the insert 731 are at the same height. For example, in the electronic component 730 shown in this embodiment, it is preferable that the storage device 720 and the semiconductor device 735 are at the same height.

[0596] In order to mount the electronic component 730 on other substrates, an electrode 733 can be provided on the bottom of the package substrate 732. Figure 26B An example of forming electrode 733 using solder balls is shown. BGA (Ball Grid Array) mounting can be achieved by arranging solder balls in a matrix on the bottom of the package substrate 732. Alternatively, electrode 733 can also be formed using conductive pins. PGA (Pin Grid Array) mounting can be achieved by arranging conductive pins in a matrix on the bottom of the package substrate 732.

[0597] Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. For example, it can be mounted using SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package).

[0598] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0599] (Implementation Method 6)

[0600] In this embodiment, an application example of a storage device using the semiconductor device described in the above embodiments is explained. The semiconductor device described in the above embodiments can be applied, for example, to the storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including camcorders), video recording devices, navigation systems, etc.). Note that here, "computer" includes tablet computers, notebook computers, desktop computers, and mainframe computers such as server systems. Alternatively, the semiconductor device described in the above embodiments can be applied to various portable storage devices such as SSDs (solid-state drives). Figure 27A and Figure 27B An example structure of a removable storage device is schematically illustrated. For example, the semiconductor device shown in the above embodiments is fabricated into a packaged memory chip and used in various storage devices or removable memories.

[0601] Figure 27A This is a schematic diagram of the SSD's appearance. Figure 27B This is a schematic diagram of the internal structure of an SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed within the housing 1151. For example, memory chips 1154 and 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 serves as the working memory for the controller chip 1156; for example, a DOSRAM chip as shown in the above embodiment can be used. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased.

[0602] This embodiment can be implemented by appropriately combining it with the structures described in other embodiments, etc.

[0603] (Implementation Method 7)

[0604] The semiconductor device according to one aspect of the present invention can be applied to processors or chips such as CPUs and GPUs. Figures 28A to 28H Specific examples of electronic devices having a processor or chip such as a CPU or GPU according to one aspect of the present invention are shown.

[0605] <Electronic Devices and Systems>

[0606] The GPU or chip according to one aspect of the present invention can be installed in a wide variety of electronic devices. Examples of electronic devices include, in addition to television sets, displays for desktop or laptop information terminals, digital signage, and large-screen game consoles such as pinball machines, digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices. Furthermore, by incorporating the GPU or chip according to one aspect of the present invention into an electronic device, the electronic device can possess artificial intelligence.

[0607] An electronic device according to one aspect of the present invention may also include an antenna. By receiving signals through the antenna, images or information can be displayed on a display unit. Furthermore, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0608] An electronic device according to one aspect of the present invention may also include a sensor (the sensor having the function of measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation).

[0609] An electronic device according to one aspect of the present invention can have various functions. For example, it can have the following functions: displaying various information (static images, animated images, text images, etc.) on a display unit; a touch panel; displaying a calendar, date, or time; executing various software (programs); performing wireless communication; reading programs or data stored in a storage medium; etc. Figures 28A to 28H Examples of electronic devices are shown.

[0610] [Information Terminal]

[0611] Figure 28A A mobile phone (smartphone) is shown as one of the information terminals. The information terminal 5100 includes a housing 5101 and a display unit 5102. The display unit 5102 has a touch panel as an input interface, and buttons are provided on the housing 5101.

[0612] By applying a chip according to one aspect of the present invention to an information terminal 5100, applications utilizing artificial intelligence can be executed. Examples of such applications utilizing artificial intelligence include applications that identify a session and display the content of that session on a display unit 5102, applications that identify text or graphics input by a user to a touch panel provided with the display unit 5102 and display that text or graphics on the display unit 5102, and applications that perform biometric identification such as fingerprints or voiceprints.

[0613] Figure 28B A notebook-type information terminal 5200 is shown. The notebook-type information terminal 5200 includes an information terminal body 5201, a display unit 5202, and a keyboard 5203.

[0614] Similar to the aforementioned information terminal 5100, by applying a chip according to one aspect of the present invention to the notebook information terminal 5200, applications utilizing artificial intelligence can be executed. Examples of such applications utilizing artificial intelligence include design support software, document proofreading software, and automatic menu generation software. Furthermore, by using the notebook information terminal 5200, novel artificial intelligence technologies can be developed.

[0615] Note that in the example above, Figure 28A and Figure 28B Examples of smartphones and laptops as electronic devices are shown, but other information terminals besides smartphones and laptops can also be applied. Examples of information terminals other than smartphones and laptops include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0616] [Game console]

[0617] Figure 28C A portable game console 5300 is shown as an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connector 5305, and operation keys 5306. The housings 5302 and 5303 can be detached from the housing 5301. By attaching the connector 5305 provided in the housing 5301 to another housing (not shown), the image output to the display unit 5304 can be output to another video display device (not shown). At this time, the housings 5302 and 5303 can each be used as operation units. Thus, multiple players can play the game simultaneously. Chips, etc., as shown in the above embodiment, can be embedded in the substrates provided in the housings 5301, 5302, and 5303.

[0618] in addition, Figure 28D The image shows a stationary game console 5400, one of the game consoles. The stationary game console 5400 is connected to a controller 5402 via wireless or wired connection.

[0619] By applying a GPU or chip according to one aspect of the present invention to game consoles such as the portable game console 5300 and the stationary game console 5400, a low-power game console can be achieved. Furthermore, the low power consumption reduces heat generation from the circuitry, thereby minimizing the negative impacts of heat generation on the circuitry itself, peripheral circuits, and modules.

[0620] Furthermore, by applying a GPU or chip according to one aspect of the present invention to a portable game console 5300, a portable game console 5300 with artificial intelligence can be realized.

[0621] The progress of a game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are normally governed by the game's programming. However, by applying artificial intelligence to the portable game console 5300, it is possible to achieve performances that are not limited to the game's programming. For example, it is possible to display the content of the player's questions, the progress of the game, the time elapsed, and changes in the behavior of characters appearing in the game.

[0622] Furthermore, when playing games that require multiple players using the portable game console 5300, artificial intelligence can be used to create human-like game players, allowing one person to play a game that can be played by multiple people.

[0623] Although Figure 28C and Figure 28D Portable and stationary game consoles are shown as examples of game consoles, but game consoles using GPUs or chips according to one aspect of the present invention are not limited to these. Examples of game consoles using GPUs or chips according to one aspect of the present invention include arcade game consoles installed in entertainment facilities (game centers, amusement parks, etc.) and ball-throwing machines installed in sports facilities.

[0624] [Mainframe Computer]

[0625] A GPU or chip based on one aspect of this invention can be applied to large-scale computers.

[0626] Figure 28E The image shows the Supercomputer 5500 as an example of a large computer. Figure 28F The image shows the rack-mount computer 5502 included in the supercomputer 5500.

[0627] The supercomputer 5500 includes a rack 5501 and multiple rack-mounted computers 5502. Note that the multiple computers 5502 are housed in the rack 5501. Additionally, each computer 5502 has multiple substrates 5504 on which the GPU or chip described in the above embodiments can be mounted.

[0628] The Supercomputer 5500 is primarily a large-scale computer suitable for scientific computing. Scientific computing requires massive calculations at high speeds, resulting in high power consumption and significant chip heat generation. By applying a GPU or chip according to one aspect of this invention to the Supercomputer 5500, a low-power supercomputer can be realized. Furthermore, the low power consumption reduces heat generation from the circuitry, thereby minimizing the negative impacts of heat on the circuitry itself, peripheral circuits, and modules.

[0629] exist Figure 28E and Figure 28F The example shown is a supercomputer, but the supercomputer using a GPU or chip according to one aspect of the present invention is not limited to this. Examples of supercomputers using a GPU or chip according to one aspect of the present invention include service-providing computers (servers), large general-purpose computers (hosts), etc.

[0630] [Moving Object]

[0631] One embodiment of the present invention is that the GPU or chip can be applied to a car as a moving body and the area around the driver's seat of the car.

[0632] Figure 28G This is a diagram showing the perimeter of the windshield inside a car interior, illustrating an example of a moving object. Figure 28G Display panels 5701, 5702, and 5703 are shown mounted on the dashboard, and display panel 5704 is mounted on the support column.

[0633] Display panels 5701 to 5703 can provide various other information by displaying speedometer, tachometer, distance traveled, fuel gauge, gear position, and air conditioning settings. Furthermore, users can appropriately change the displayed content and layout of the display panels according to their preferences, enhancing design flexibility. Display panels 5701 to 5703 can also be used as lighting devices.

[0634] By displaying images captured by a camera (not shown) installed in the vehicle on the display panel 5704, blind spots (obstructions to the view) can be filled. In other words, by displaying images captured by a camera installed on the exterior of the vehicle, blind spots can be filled, thereby improving safety. Furthermore, by displaying images that supplement areas that are not visible, safety can be confirmed more naturally and comfortably. The display panel 5704 can also be used as a lighting device.

[0635] Because the GPU or chip of one aspect of the present invention can be used as a component of artificial intelligence, for example, the chip can be used in an autonomous driving system for automobiles. The chip can also be used in systems for navigation, hazard prediction, etc. Furthermore, navigation, hazard prediction, and other information can be displayed on display panels 5701 to 5704.

[0636] While the automobile was used as an example of a mobile body in the above example, mobile bodies are not limited to automobiles. For example, trams, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles, airplanes, rockets) can also be cited as mobile bodies, and the chip of one aspect of the present invention can be applied to these mobile bodies to provide a system utilizing artificial intelligence.

[0637] [Electrical Products]

[0638] Figure 28H An example of an electrical appliance is shown: an electric refrigerator / freezer 5800. The electric refrigerator / freezer 5800 includes an outer casing 5801, a refrigerator door 5802, and a freezer door 5803, etc.

[0639] By applying a chip according to one aspect of the present invention to an electric refrigerator / freezer 5800, an electric refrigerator / freezer 5800 equipped with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator / freezer 5800 can have the function of automatically generating a menu based on the food stored in the electric refrigerator / freezer 5800 or the consumption period of the food, and automatically adjusting the temperature of the electric refrigerator / freezer 5800 according to the stored food.

[0640] Electric refrigerators and freezers are one example of electrical appliances, but other electrical appliances that can be cited include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners (including air conditioners with heating and cooling), washing machines, dryers, and audio-visual equipment.

[0641] The electronic device described in this embodiment, its functions, examples of artificial intelligence applications, and their effects can be implemented by appropriately combining them with descriptions of other electronic devices.

[0642] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0643] [Symbol Explanation]

[0644] BGLa: Wiring, BGLb: Wiring, BIL: Wiring, CAa: Capacitor, CAb: Capacitor, CAL: Wiring, MCa: Memory Cell, MCb: Memory Cell, M1a: Transistor, M1b: Transistor, WOLa: Wiring, WOLb: Wiring, 100: Capacitor, 100a: Capacitor, 100b: Capacitor, 110: Conductor, 115: Conductor, 120: Conductor, 125: Conductor, 130: Insulator, 140: Conductor, 142: Insulator, 145: Insulator, 150: Insulator, 152: Insulator, 153: Conductor, 154: Insulator, 156: Insulator, 200: Transistor, 200a: Transistor, 200b: Transistor Body tube, 200T: transistor, 205: conductor, 205a: conductor, 205b: conductor, 205c: conductor, 210: insulator, 212: insulator, 214: insulator, 216: insulator, 222: insulator, 224: insulator, 230: oxide, 230a: oxide, 230A: oxide film, 230b: oxide, 230B: oxide film, 230c: oxide, 230d: oxide, 232a: region, 232b: region, 232c: region, 232d: region, 232e: region, 240: conductor, 241: insulator, 242: conductor, 242a: conductor, 242A: conductive film, 242b: conductor, 2 42B: Conductive layer, 242c: Conductor, 243: Oxide, 243a: Oxide, 243A: Oxide film, 243b: Oxide, 243B: Oxide layer, 243c: Oxide, 248: Conductor, 248_1: Conductor, 248_2: Conductor, 248_3: Conductor, 248_4: Conductor, 248a: Conductor, 248b: Conductor, 249: Insulator, 250: Insulator, 250A: Insulating film, 260: Conductor, 260a: Conductor, 260b: Conductor, 271: Insulator, 272: Insulator, 273: Insulator, 274: Insulator, 275: Insulator, 280: Insulator, 282: Insulator, 283: Insulator 288: Conductor, 294a: Conductor, 294b: Conductor, 296: Insulator, 300: Transistor, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 358: Insulator, 400: Memory cell, 401: Memory cell, 411: Component layer, 413: Transistor layer, 415: Memory cell layer, 415_1: Memory cell layer415_2: Memory cell layer, 415_3: Memory cell layer, 415_4: Memory cell layer, 440: Conductor, 470: Memory, 610: Cell array, 610_n: Cell array, 610_1: Cell array, 700: Electronic component, 702: Printed circuit board, 704: Circuit board, 711: Mold, 712: Connector pad, 713: Electrode pad, 714: Lead, 720: Storage device, 721: Driver circuit layer, 722: Storage circuit layer, 730: Electronic component, 731: Through-hole board, 732: Packaging substrate, 733: Electrode, 735: Semiconductor device, 1150: SSD, 1151: Housing, 1152: Connector, 1153: Substrate 1154: Memory chip; 1155: Memory chip; 1156: Controller chip; 1200: Chip; 1201: PCB; 1202: Bump; 1203: Motherboard; 1204: GPU module; 1211: CPU; 1212: GPU; 1213: Analog processing unit; 1214: Memory controller; 1215: Interface; 1216: Network circuit; 1221: DRAM; 1222: Flash memory; 1400: Storage device; 1411: Peripheral circuit; 1420: Row circuit; 1430: Column circuit; 1440: Output circuit; 1460: Control logic circuit; 1470: Memory cell array; 1471: Memory cell; 1472: Storage 1473: Memory unit; 2700: Manufacturing apparatus; 2701: Atmospheric substrate supply chamber; 2702: Atmospheric substrate transfer chamber; 2703a: Loading lock chamber; 2703b: Unloading lock chamber; 2704: Transfer chamber; 2706a: Processing chamber; 2706b: Processing chamber; 2706c: Processing chamber; 2706d: Processing chamber; 2761: Box interface; 2762: Alignment interface; 2763a: Transfer robot; 2763b: Transfer robot; 2801: Gas supply source; 2802: Valve; 2803: High frequency generator; 2804: Waveguide; 2805: Mode converter; 2806: Gas pipe; 2807: Waveguide; 2808: Slotted antenna plate 2809: Dielectric plate; 2810: High-density plasma; 2811: Substrate; 2812: Substrate holder; 2813: Heating mechanism; 2815: Matching device; 2816: High-frequency power supply; 2817: Vacuum pump; 2818: Valve; 2819: Exhaust port; 2820: Lamp; 2821: Gas supply source; 2822: Valve; 2823: Gas inlet; 2824: Substrate; 2825: Substrate holder; 2826: Heating mechanism; 2828: Vacuum pump; 2829: Valve; 2830: Exhaust port; 5100: Information terminal; 5101: Housing; 5102: Display unit; 5200: Notebook information terminal; 5201: Main body; 5202: Display unit; 5203: Keyboard.5300: Portable game console; 5301: Casing; 5302: Casing; 5303: Casing; 5304: Display unit; 5305: Connector; 5306: Control keys; 5400: Fixed game console; 5402: Controller; 5500: Supercomputer; 5501: Rack; 5502: Computer; 5504: Substrate; 5701: Display panel; 5702: Display panel; 5703: Display panel; 5704: Display panel; 5800: Electric refrigerator / freezer; 5801: Casing; 5802: Refrigerator door; 5803: Freezer door;

Claims

1. A semiconductor device, comprising: A first conductor disposed on a substrate; An oxide configured to contact the top surface of the first conductor; A second conductor, a third conductor, and a fourth conductor disposed on the oxide; A first insulator having a first opening and a second opening is disposed on the second to the fourth conductors; A second insulator disposed in the first opening; A fifth conductor disposed on the second insulator; A third insulator disposed in the second opening; as well as The sixth conductor disposed on the third insulator, The third conductor is configured to overlap with the first conductor. The first opening is formed by overlapping in the region between the second conductor and the third conductor. The second opening is formed by overlapping in the region between the third conductor and the fourth conductor. The second insulator is in contact with the top surface of the oxide and the side surface of the first insulator. Furthermore, the third insulator is in contact with the top surface of the oxide and the side surface of the first insulator.

2. The semiconductor device according to claim 1, further comprising: The first capacitor and the second capacitor, The first capacitor is electrically connected to the second conductor. Furthermore, the second capacitor is electrically connected to the fourth conductor.

3. The semiconductor device according to claim 2, The first capacitor is disposed on the second conductor. The second capacitor is disposed on the fourth conductor.

4. The semiconductor device according to any one of claims 1 to 3, The first conductor is connected to the wiring disposed under the first conductor.

5. The semiconductor device according to any one of claims 1 to 3, The oxide includes a first oxide and a second oxide on the first oxide. Both the first oxide and the second oxide contain indium, element M, and zinc, where M is selected from one or more of gallium, aluminum, yttrium, and tin. Furthermore, the atomic ratio of the first oxide to indium relative to element M is less than the atomic ratio of the second oxide to indium relative to element M.

6. A method for manufacturing a semiconductor device, comprising the following steps: A first conductor is formed on the substrate; An oxide film is deposited in a manner that makes contact with the top surface of the first conductor; A first conductive film is deposited on the oxide film; The oxide film and the first conductive film are processed into island shapes to form an oxide and a second conductor; The first insulator is formed by covering the oxide and the second conductor; A portion of the first insulator is removed to form a first opening and a second opening in a manner that overlaps with the second conductor; A portion of the second conductor that overlaps with the first opening and the second opening is removed to form a third conductor, a fourth conductor, and a fifth conductor, wherein the fourth conductor is configured to overlap with the first conductor. The region of the oxide that does not overlap with the third conductor, the fourth conductor, and the fifth conductor is exposed; A first insulating film is deposited in contact with the top surface of the oxide; Microwave treatment is performed in an oxygen-containing atmosphere; A second conductive film is deposited on the first insulating film; as well as The first insulating film and the second conductive film are subjected to CMP treatment until the top surface of the first insulator is exposed, forming a second insulator and a sixth conductor in the first opening, and forming a third insulator and a seventh conductor in the second opening.

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