Integrated component having vertically spaced channel material sections and method of forming an integrated component

Abstract

Some embodiments include a vertically stacked NAND memory array having alternating insulating levels and conductive levels. The conductive levels include control gate regions. A high-k dielectric material is adjacent to the control gate regions and is configured as an arrangement of first vertically extending linear segments that are vertically spaced apart from each other. A charge blocking material is adjacent to the high-k dielectric material and is configured as an arrangement of second vertically extending linear segments that are vertically spaced apart from each other. A charge storage material is adjacent to the charge blocking material and is configured as an arrangement of third vertically extending linear segments that are vertically spaced apart from each other. A gate dielectric material is adjacent to the charge storage material. A channel material extends vertically along the stack and is adjacent to the gate dielectric material. Some embodiments include integrated components and methods of forming integrated components.

Description

[0001] Relevant patent data

[0002] This patent claims priority to U.S. Patent Application No. 16 / 548,320, filed Aug. 22, 2019, the disclosure of which is incorporated herein by reference. Field of the Invention

[0003] The present disclosure relates to integrated components (e.g., integrated NAND memories) having vertically spaced channel material segments and methods of forming integrated components. Background of the Invention

[0004] Memories provide data storage devices for electronic systems. Flash memory is a type of memory and is widely used in modern computers and devices. For example, modern personal computers may store the BIOS on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid state drives to replace conventional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because flash memory enables manufacturers to support new communication protocols as they become standardized and enables manufacturers to provide the ability to remotely upgrade devices for enhanced features.

[0005] NAND can be a basic architecture of flash memory and can be configured to include vertically stacked memory cells.

[0006] Before specifically describing NAND, it may be helpful to more generally describe the relationship of memory arrays within an integrated arrangement. Figure 1A block diagram showing a prior art device 1000, the device including a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns, and access lines 1004 (e.g., word lines for conducting signals WL0 to WLm) and first data lines 1006 (e.g., bit lines for conducting signals BL0 to BLn). The access lines 1004 and the first data lines 1006 can be used to transfer information to and from the memory cells 1003. A row decoder 1007 and a column decoder 1008 decode the address signals A0 to AX on the address lines 1009 to determine which of the memory cells 1003 in the memory array 1002 are to be accessed. A sense amplifier circuit 1015 is used to determine the value of the information read from the memory cells 1003. An I / O circuit 1017 transfers the value of the information between the memory array 1002 and input / output (I / O) lines 1005. The signals DQ0 to DQN on the I / O lines 1005 can represent the value of the information read from or to be written to the memory cells 1003. Other devices can communicate with the device 1000 via the I / O lines 1005, the address lines 1009, or the control lines 1020. A memory control unit 1018 is used to control the memory operations to be performed on the memory cells 1003 and utilizes the signals on the control lines 1020. The device 1000 can receive power voltage signals Vcc and Vss on a first supply line 1030 and a second supply line 1032, respectively. The device 1000 includes a selection circuit 1040 and an input / output (I / O) circuit 1017. The selection circuit 1040 can respond to signals CSEL1 to CSELn via the I / O circuit 1017 to select signals on the first data lines 1006 and second data lines 1013 that can represent the value of the information to be read from or programmed to the memory cells 1003. The column decoder 1008 can selectively activate the CSEL1 to CSELn signals based on the A0 to AX address signals on the address lines 1009. The selection circuit 1040 can select the signals on the first data lines 1006 and second data lines 1013 to provide communication between the memory array 1002 and the I / O circuit 1017 during read and program operations.

[0007] Figure 1 The memory array 1002 can be a NAND memory array, and Figure 2 is shown that can be used for Figure 1Schematic diagram of a 3D NAND memory device 200 of a memory array 1002. The device 200 includes multiple strings of charge storage devices. In a first direction (Z-Z'), each string of charge storage devices may include, for example, thirty-two charge storage devices stacked on top of each other, where each charge storage device corresponds to one of, for example, thirty-two tiers (e.g., tier 0 to tier 31). The charge storage devices of a corresponding string may share a common channel region, such as a common channel region formed in a corresponding pillar of a semiconductor material (e.g., polysilicon), and the strings of charge storage devices are formed around the corresponding pillar. In a second direction (X-X'), each first group of the multiple strings, such as sixteen first groups, may include, for example, eight strings that share multiple (e.g., thirty-two) access lines (i.e., "global control gate (CG) lines", also referred to as word lines WL). Each of the access lines may couple the charge storage devices within a tier. When each charge storage device includes a cell capable of storing two information bits, the charge storage devices coupled by the same access line (and thus corresponding to the same tier) may be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. In a third direction (Y-Y'), each second group of the multiple strings, such as eight second groups, may include sixteen strings coupled by a corresponding one of eight data lines. The size of a memory block may include 1,024 pages and be approximately 16 MB in total (e.g., 16 WL × 32 tiers × 2 bits = 1,024 pages / block, block size = 1,024 pages × 16 KB / page = 16 MB). The number of strings, tiers, access lines, data lines, first groups, second groups, and / or pages may be greater than or less than Figure 2 the numbers shown in

[0008] Figure 3 Shown Figure 2 is a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 in the X-X' direction, including fifteen strings of charge storage devices in one of the sixteen first groups of strings described with respect to Figure 2 The multiple strings of the memory block 300 may be grouped into multiple subsets 310, 320, 330 (e.g., strip columns), such as strip column I , strip column j and strip column K, where each subset (e.g., a slice column) includes "partial blocks" of the memory block 300. The global source side select gate (SGD) line 340 can be coupled to the SGDs of multiple strings. For example, the global SGD line 340 can be coupled to multiple (e.g., three) sub-SGD lines 342, 344, 346 via corresponding sub-SGD drivers among multiple (e.g., three) sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a respective subset (e.g., a slice column). Each of the sub-SGD drivers 332, 334, 336 can independently couple or disconnect the SGD of the string of the corresponding partial block while being independent of the SGDs of the strings of other partial blocks (e.g., slice columns). The global source side select gate (SGS) line 360 can be coupled to the SGSs of multiple strings. For example, the global SGS line 360 can be coupled to multiple sub-SGS lines 362, 364, 366 via corresponding sub-SGS drivers among multiple sub-SGS drivers 322, 324, 326, where each sub-SGS line corresponds to a respective subset (e.g., a slice column). Each of the sub-SGS drivers 322, 324, 326 can independently couple or disconnect the SGS of the string of the corresponding partial block while being independent of the SGSs of the strings of other partial blocks (e.g., slice columns). The global access line (e.g., global CG line) 350 can be coupled to the charge storage devices of the respective stacks corresponding to each of the multiple strings. Each global CG line (e.g., global CG line 350) can be coupled to multiple sub-access lines (e.g., sub-CG lines) 352, 354, 356 via a corresponding one of multiple sub-string drivers 312, 314, and 316. Each of the sub-string drivers can independently couple or disconnect the charge storage devices corresponding to the respective partial block and / or stack while being independent of the corresponding charge storage devices of other partial blocks and / or other stacks. The charge storage devices corresponding to the respective subsets (e.g., partial blocks) and the respective stacks can include charge storage devices of "partial stacks" (e.g., a single "slice"). The strings corresponding to the respective subsets (e.g., partial blocks) can be coupled to a corresponding one of sub-source electrodes 372, 374, and 376 (e.g., "slice source electrodes"), where each sub-source electrode is coupled to a respective power supply.

[0009] Alternatively, referring to Figure 4 the schematic illustration of

[0010] The memory array 200 includes word lines 2021 to 202 N , and bit lines 2281 to 228 M .

[0011] The memory array 200 further includes NAND strings 2061 to 206 M . Each NAND string includes charge storage transistors 2081 to 208 N。A charge storage transistor can store charge using a floating gate material (such as polysilicon), or can store charge using a charge trapping material (such as silicon nitride, metal nanodots, etc.).

[0012] The charge storage transistor 208 is located at the intersection of the word line 202 and the string 206. The charge storage transistor 208 represents a non-volatile memory cell for storing data. The charge storage transistors 208 of each NAND string 206 are source-drain series-connected between a source selection device (such as a source-side select gate SGS) 210 and a drain selection device (such as a drain-side select gate SGD) 212. Each source selection device 210 is located at the intersection of the string 206 and the source selection line 214, and each drain selection device 212 is located at the intersection of the string 206 and the drain selection line 215. The selection devices 210 and 212 can be any suitable access device, and are generally illustrated by the Figure 4 boxes in.

[0013] The source of each source selection device 210 is connected to a common source line 216. The drain of each source selection device 210 is connected to the source of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the drain of the source selection device 2101 is connected to the source of the charge storage transistor 2081 of the corresponding NAND string 2061. The source selection device 210 is connected to the source selection line 214.

[0014] The drain of each drain selection device 212 is connected to a bit line (i.e., a digital line) 228 at a drain contact. For example, the drain of the drain selection device 2121 is connected to the bit line 2281. The source of each drain selection device 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the source of the drain selection device 2121 is connected to the drain of the charge storage transistor 208 N of the corresponding NAND string 2061.

[0015] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The charge storage transistor 208 couples its control gate 236 to the word line 202. The column of the charge storage transistors 208 is those transistors within the NAND string 206 that are coupled to a given bit line 228. The row of the charge storage transistors 208 is those transistors that are commonly coupled to a given word line 202.

[0016] It is desirable to develop improved NAND architectures and improved methods for manufacturing NAND architectures. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1Block diagram showing a prior art memory device having a memory array including memory cells.

[0018] Figure 2 Showing a prior art memory array in the form of a 3D NAND memory device Figure 1 schematic diagram.

[0019] Figure 3 Showing Figure 2 cross-sectional view of a prior art 3D NAND memory device in the X-X' direction.

[0020] Figure 4 is a schematic diagram of a prior art NAND memory array.

[0021] Figure 5 and 6 are schematic cross-sectional side views of regions of integrated components shown at an example sequential process stage of an example method for forming an example NAND memory array.

[0022] Figure 6A is Figure 6 top view illustration of a part of the integrated component.

[0023] Figures 7 to 19 is a schematic cross-sectional side view of a region of an integrated component shown at an example sequential process stage of an example method for forming an example NAND memory array. Figure 5 The process stage of Figure 7 can be after the process stage of Figure 6 .

[0024] Figure 19A is Figure 19 top view illustration of a part of the integrated component.

[0025] Figure 20 is a schematic cross-sectional side view of an integrated component showing a region of an example NAND memory array.

[0026] Figures 21 to 30 is a schematic cross-sectional side view of a region of an integrated component shown at an example sequential process stage of an example method for forming an example NAND memory array. Figure 21 The process stage of Figure 6 can be after the process stage of

[0027] Figures 31 to 40 is a schematic cross-sectional side view of a region of an integrated component shown at an example sequential process stage of an example method for forming an example NAND memory array. Figure 31 The process stage of Figure 7 is the same as the process stage of

[0028] Figure 40A is a schematic cross-sectional side view of an integrated component of a region of an example NAND memory array at a process subsequent to the process that can be performed in some embodiments Figure 40 and is shown in FIG. 1A. FIG. 1A shows a cross-sectional view of an integrated component of a region of an example NAND memory array at a process subsequent to the process that can be performed in some embodiments

[0029] Figure 41 is a schematic cross-sectional side view of an integrated component of a region of an example NAND memory array at a process subsequent to the process that can be performed Figure 40 and is shown in FIG. 1B. FIG. 1B shows a cross-sectional view of an integrated component of a region of an example NAND memory array at a process subsequent to the process that can be performed

[0030] Figure 41A is a schematic cross-sectional side view of an integrated component of a region of an example NAND memory array at a process subsequent to the process that can be performed Figure 40A and is shown in FIG. 1C. FIG. 1C shows a cross-sectional view of an integrated component of a region of an example NAND memory array at a process subsequent to the process that can be performed DETAILED DESCRIPTION

[0031] The operation of a NAND memory cell involves the movement of charge between a channel material and a charge storage material. For example, programming of a NAND memory cell can include moving charge (i.e., electrons) from the channel material into the charge storage material and then storing the charge within the charge storage material. Erasing of a NAND memory cell can include moving holes into the charge storage material to recombine with electrons stored in the charge storage material and thereby releasing the charge from the charge storage material. The charge storage material can include a charge trapping material (e.g., silicon nitride, metal dots, etc.). One problem with conventional NANDs can be that the charge trapping material extends across multiple memory cells of the memory array and this can lead to charge migration from one memory cell to another. Charge migration can lead to data retention problems. Some embodiments include a NAND architecture having discontinuities in the charge trapping material in the regions between the memory cells; and such discontinuities can advantageously impede charge migration between the memory cells. Reference Figures 5 to 41 is made to the example embodiments described below with reference to FIGS. 1A-1C

[0032] Reference Figure 5, the structure (integrated component, integrated structure) 10 includes a vertical stack 12 of alternating first levels 14 and second levels 16. The first level 14 includes a first material 60, and the second level 16 includes a second material 62. The first material and the second material can include any suitable compositions and have different compositions relative to each other. In some embodiments, the first material 60 can include silicon dioxide, consist essentially of silicon dioxide, or consist of silicon dioxide; and the second material 62 can include silicon nitride, consist essentially of silicon nitride, or consist of silicon nitride. The levels 14 and 16 can have any suitable thickness; and can have the same thickness as each other, or can have different thicknesses relative to each other. In some embodiments, the levels 14 and 16 can have a vertical thickness in the range from about 10 nanometers (nm) to about 400 nm. In some embodiments, the levels 14 and 16 can have a thickness in the range from about 10 nm to about 50 nm.

[0033] The stack 12 is shown as being supported above the substrate 18. The substrate 18 can include a semiconductor material; and can include, for example, single-crystalline silicon, consist essentially of single-crystalline silicon, or consist of single-crystalline silicon. The substrate 18 can be referred to as a semiconductor substrate. The term "semiconductor substrate" means any structure including a semiconducting material, including but not limited to bulk semiconducting materials, such as (alone or in components including other materials) semiconducting wafers, and (alone or in components including other materials) semiconducting material layers. The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrates described above. In some applications, the substrate 18 can correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials can include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

[0034] A gap is provided between the stack 12 and the substrate 18 to indicate that other components and materials can be provided between the stack 12 and the substrate 18. Such other components and materials can include additional stack levels, source line levels, source-side select gates (SGS), etc.

[0035] Reference Figure 6 , an opening 64 is formed to extend through the stack 12. The opening has sidewalls 65 that extend along the first material 60 and the second material 62.

[0036] Figure 6A is Figure 6 a top view of a region of the component 10 at a process stage of, and shows that when viewed from above, the opening 64 can have a closed shape (circular, elliptical, square, or other polygon, etc.). In the illustrated embodiment, the opening 64 is circular when viewed from above. Along Figure 6 the cross-section of, the sidewalls 65 are part of the continuous sidewalls 65, as shown by Figure 6Aas shown in the top view. Sidewall 65 may be referred to as the peripheral sidewall of the opening, or the peripheral sidewall surface of the opening. The terms "peripheral sidewall" and "peripheral sidewall surface" may be used interchangeably. In some cases using one term and in other cases using the other term may be for providing language variation within the present disclosure to simplify the premise basis within the appended claims.

[0037] Opening 64 may represent a large number of substantially identical openings for fabricating NAND memory cells of a NAND memory array formed at the process stage of Figure 6 and 6A The term "substantially identical" means identical within reasonable manufacturing and measurement tolerances.

[0038] Referring to Figure 7 , first level 14 is recessed relative to second level 16 along sidewall 65 of opening 64. After the recessing, second level 16 has a protruding end 66 that extends beyond the recessed first level 14. End 66 has a surface 67 of second material 62. The recessed first level 14 has a surface 69 of first material 60. Cavity (gap) 68 is vertically between ends 66. Surface 69 may be regarded as along the inner edge of cavity 68.

[0039] Surfaces 67 and 69 together form the peripheral sidewall surface 65 of opening 64 into a undulating sidewall surface at the process stage of Figure 7 .

[0040] Referring to Figure 8 , cavity 68 is filled with sacrificial material 70. Sacrificial material 70 may include any suitable composition; and in some embodiments, may include silicon (e.g., polysilicon), consist essentially of silicon (e.g., polysilicon), or consist of silicon (e.g., polysilicon).

[0041] Sacrificial material 70 has a surface 71 along sidewall 65 of opening 64. In the illustrated embodiment, surface 71 is formed to be aligned with surface 67 of second material 62 to form the peripheral sidewall surface 65 of opening 64 into a substantially straight sidewall surface (and substantially vertically extending in the illustrated embodiment). The term "substantially straight" means straight within reasonable manufacturing and measurement tolerances, and the term "substantially vertical" means vertical within reasonable manufacturing and measurement tolerances.

[0042] Referring to Figure 9, a charge blocking material 34 is formed along a substantially straight sidewall surface 65 (i.e., along the peripheral sidewall of the opening 64). The charge blocking material 34 can include any suitable composition; and in some embodiments, can include one or both of silicon oxynitride (SiON) and silicon dioxide (SiO2), consist essentially of one or both of silicon oxynitride and silicon dioxide, or be composed of one or both of silicon oxynitride and silicon dioxide.

[0043] The charge blocking material 34 has a substantially flat configuration along the substantially straight sidewall surface 65.

[0044] Reference Figure 10 , a charge storage material 38 is formed adjacent to the charge blocking material 34. The charge storage material 38 can include any suitable composition. In some embodiments, the charge storage material 38 can include a charge trapping material; such as silicon nitride, silicon oxynitride, conductive nanodots, etc. For example, in some embodiments, the charge storage material 38 can include silicon nitride, consist essentially of silicon nitride, or be composed of silicon nitride. In alternative embodiments, the charge storage material 38 can be configured to include a floating gate material (such as polysilicon).

[0045] The charge storage material 38 is formed along the flat configuration of the charge blocking material 34 and has a flat configuration in Figure 10 the illustrated embodiment. The term "flat configuration" means that the material 38 has a substantially continuous thickness and extends substantially vertically straight as opposed to being undulating.

[0046] A gate dielectric material (i.e., a tunneling material, a charge transfer material) 42 is formed adjacent to the charge storage material 38. The gate dielectric material 42 can include any suitable composition. In some embodiments, the gate dielectric material 42 can include one or more of, for example, silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, etc. The gate dielectric material 42 can be bandgap engineered to achieve the desired electrical properties; and thus can include a combination of two or more different materials.

[0047] A channel material 44 is formed adjacent to the gate dielectric material 42 and extends vertically along the stack 12. The channel material 44 includes a semiconductor material; and can include any suitable composition or combination of compositions. For example, the channel material 44 can include one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; where the term III / V semiconductor material refers to a semiconductor material that includes elements selected from Group III and Group V of the periodic table (where Group III and Group V are old terms and are now called Group 13 and Group 15). In some embodiments, the channel material 44 can include silicon, consist essentially of silicon, or be composed of silicon.

[0048] The insulating material 46 is formed adjacent to the channel material 44 and fills the remainder of the opening 64. The insulating material 46 can include any suitable composition; and in some embodiments, can include silica, consist essentially of silica, or consist of silica.

[0049] In Figure 10 the illustrated embodiment, the channel material 44 is configured as an annular ring surrounding the insulating material 46. Such a configuration of the channel material can be considered to include a hollow channel configuration, since the insulating material 46 is provided within the "hollow" of the annular channel configuration. In other embodiments (not shown), the channel material can be configured as a solid column configuration.

[0050] Referring Figure 11 , the second material 62 ( Figure 10 ) is removed to leave a void 76. The void 76 can be referred to as a first void to distinguish it from other voids formed at later process stages.

[0051] Referring Figure 12 , a high-k dielectric material 28 is formed within the first void 76 ( Figure 11 ) to line the first void, and then a conductive region 22 is formed within the lined void.

[0052] The term "high-k" means a dielectric constant greater than that of silica. In some embodiments, the high-k dielectric material 28 can include one or more of the following, consist essentially of one or more of the following, or consist of one or more of the following: aluminum oxide (AlO), hafnium oxide (HfO), hafnium silicate (HfSiO), zirconium oxide (ZrO), and zirconium silicate (ZrSiO); where the chemical formulas indicate the main components rather than specific stoichiometry.

[0053] The high-k dielectric material 28 has a substantially uniform thickness along the inner peripheral of the void 76 ( Figure 11 ), where the term "substantially uniform" means uniform within reasonable manufacturing and measurement tolerances. The high-k dielectric material 28 can be formed to any suitable thickness; and in some embodiments, can be formed to a thickness in the range from about 1 nm to about 5 nm.

[0054] The conductive region 22 may include two or more conductive materials; and in the illustrated embodiment includes a pair of conductive materials 24 and 26. The conductive materials 24 and 26 may include any suitable conductive composition, such as one or more of the following: various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). The conductive materials 24 and 26 differ from each other in composition. In some embodiments, the core material 24 may include one or more metals (e.g., may include tungsten), and the outer conductive material 26 may include one or more metal nitrides (e.g., may include titanium nitride).

[0055] In the illustrated embodiment, the high-k dielectric material 28 abuts directly against the conductive material 26.

[0056] Level 16 may be regarded as Figure 12 a conductive level at a process stage of

[0057] The conductive region 22 has a front end 78 facing the vertically extending materials 34, 38, 42, and 44. The front end 78 has a front surface 79 that also faces the vertically extending materials 34, 38, 42, and 44. The conductive level has an upper surface (top surface) 77 and a lower surface (i.e., bottom surface) 81 that extend rearward from the front surface 79.

[0058] Referring to Figure 13 , a first material 60 ( Figure 12 ) is removed to form a second void 82.

[0059] Referring to Figure 14 , a sacrificial material 70 ( Figure 13 ) is removed to extend the second void 82.

[0060] After the materials 60 ( Figure 12 ) and 70 ( Figure 13 ) are removed, the high-k material 28 has exposed portions 84 along the upper surface 77 and the lower surface 81 of the conductive region 22.

[0061] Referring to Figure 15 , the exposed portions 84 ( Figure 14 ) of the high-k dielectric material 28 are removed to leave the remaining portion 86 of the high-k dielectric material 28 along the front end 78 of the conductive region 22. The remaining portions 86 of the high-k dielectric material are configured as vertically extending linear segments 88, where such linear segments are vertically spaced apart from each other. In Figure 15In the illustrated embodiments, the segments 88 of the high-k dielectric material 28 are vertically spaced from each other along the gaps in the second tier 14 (where such gaps are part of the voids 82). The segments 88 of the high-k dielectric material 28 abut directly against the front surface 79 of the conductive region 22 and are between such front surface and the charge blocking material 34. It is noted that the high-k dielectric material 28 is maintained only along the front surface 79 of the conductive region 22 and does not surround the front end 78 of the conductive region 22 (i.e., the high-k dielectric material 28 does not extend along the top surface 77 and the bottom surface 81 of the conductive region 22).

[0062] The void 82 can be considered to have a first vertical thickness T1 at a Figure 15 process stage.

[0063] Referring Figure 16 to, a strip 90 is formed within the second void 82 to narrow the second void to a second vertical thickness T2. The strip 90 includes a strip material 92. The strip material 92 can include any suitable composition. In some embodiments, the strip 90 includes a sacrificial material 92. Such a sacrificial material can be electrically insulating or conductive; and in some embodiments can include silicon nitride, consist essentially of silicon nitride, or consist of silicon nitride. In some embodiments, the strip 90 can include an insulating material 92 that remains in the final configuration.

[0064] Referring Figure 17 to, the second void 82 extends through the charge blocking material 34 and then through the charge storage material 38. The extended void 82 divides the charge blocking material 34 into vertically spaced linear segments 36 and divides the charge storage material into vertically spaced linear segments 40. In some embodiments, the segments 88 of the high-k dielectric material 28 can be referred to as a first segment, the segments 36 of the charge blocking material 34 can be referred to as a second segment, and the segments 40 of the charge storage material 38 can be referred to as a third segment. In the illustrated embodiment, the segments 36 of the charge blocking material 34 are directly adjacent to the segments 88 of the high-k dielectric material 28; and the segments 40 of the charge storage material 38 are directly adjacent to the segments 36 of the charge blocking material 34.

[0065] The front surface 79 of the conductive layer 22 has a first vertical dimension D1 that can be regarded as corresponding to the thickness of the conductive region 22 (or the conductive layer 16). The first section 88 has a second vertical dimension D2, the section 36 has a third vertical dimension D3, and the section 40 has a fourth vertical dimension D4. In the illustrated embodiment, the second vertical dimension D2 is approximately the same as the first vertical dimension D1 (where the term "approximately the same" means the same within reasonable manufacturing and measurement tolerances), the third vertical dimension D3 is greater than the second vertical dimension, and the fourth vertical dimension D4 is greater than the third vertical dimension. The relative sizes of the vertical dimensions D1, D2, D3, and D4 can be customized by the thickness of the strip 90 (and in some embodiments, the strip 90 can even be omitted); customized by the duration and composition of the etching used to penetrate the various materials 28, 34, and 36; customized by the composition of the materials 28, 34, and 36; and so on.

[0066] It may be advantageous for the dimensions D2, D3, and D4 to all be at least approximately as large as the dimension D1 of the front surface of the conductive region 22, such that the NAND memory cells (described below) utilize the entire extent of the front surface of the conductive region. However, in some embodiments, the etching can reduce the vertical dimension of one or more of the sections 88, 36, and 40 such that such sections have a vertical dimension less than the vertical dimension D1 of the front surface 79. In such embodiments, the NAND memory cells can still be formed with suitable operating characteristics for some applications.

[0067] In Figure 17 the illustrated embodiment, the sections 36 and 40 have a substantially flat configuration. Additionally, the channel material 44 has a substantially flat configuration. The flat channel material can have a positive effect on the string current as compared to a non-flat configuration. Additionally, the flat section 40 of the charge storage material can have a favorable charge distribution.

[0068] Figure 17 the embodiment of

[0069] shows a void 82 that extends through the materials 34 and 38 and stops at the tunneling material 42. In other embodiments, the void 82 can extend through the tunneling material. Figure 18 Reference Figure 17 is made to

[0070] Reference Figure 19 is made to Figure 18 where an insulating material 56 is formed within the second void 82 ( Figure 19 )). The insulating material 56 can include any suitable composition; and in some embodiments, can include silicon dioxide, consist essentially of silicon dioxide, or consist of silicon dioxide. In Figure 18 the illustrated embodiment, the insulating material 56 completely fills the second void 82 (

[0071] Figure 19 The integrated component 10 can be regarded as including a stack of alternating insulating layers 14 and conductive layers 16.

[0072] The conductive layer 16 can be regarded as a memory cell layer in a NAND configuration (also referred to herein as a word line layer). The NAND configuration includes a string of memory cells (i.e., a NAND string), where the number of memory cells in the string is determined by the number of vertically stacked layers 16. The NAND string can include any suitable number of memory cell layers. For example, the NAND string can have 8 memory cell layers, 16 memory cell layers, 32 memory cell layers, 64 memory cell layers, 512 memory cell layers, 1024 memory cell layers, etc. It is indicated that the vertical stack 12 extends vertically beyond the illustrated area to show that there may be more vertically stacked layers than Figure 19 the vertically stacked layers specifically illustrated in the figure of.

[0073] The NAND memory cell 52 includes a dielectric barrier material 28, a charge blocking material 34, a charge storage material 38, a gate dielectric material 42, and a channel material 44. The illustrated NAND memory cell 52 forms part of a vertically extending string of memory cells. Such a string can represent a large number of substantially identical NAND strings (the term "substantially identical" means identical within reasonable tolerances of manufacturing and measurement) formed during the fabrication of a NAND memory array.

[0074] Each of the NAND memory cells 52 includes a control gate region 54 within the conductive layer 16. The control gate region 54 includes a control gate similar to the control gate described above with reference to Figures 1 to 4 The conductive layer 16 includes a region 58 adjacent to or near the control gate region 54. The region 58 can be referred to as a second region, a distal region, or a word line region.

[0075] Figure 19A Shown is a top view of a region of the component 10 at the Figure 19 processing stage, and it is shown that in some example embodiments, the various materials 28, 34, 38, 42, and 44 can be configured as annular rings.

[0076] In Figure 19 the embodiment of, the insulating layer 14 is completely filled with an insulating material 56. In other embodiments, a portion of the void 82 may remain within the insulating layer 14. For example, Figure 20 Shown is a configuration similar to the Figure 19 configuration of, but where the void 82 is only partially filled with the insulating material 56. Thus, a portion of the void 82 remains within the insulating layer 14. The remaining portion of the void 82 is capped with the insulating material 56. The void 82 can be filled with air or any other suitable gas.

[0077] Figure 20 The advantage of the configuration (i.e., the configuration with voids within the insulating layer 14) is that this can reduce such capacitive coupling in cases where capacitive coupling between vertically adjacent materials causes problems.

[0078] Refer to Figures 21 to 30 for another example process for manufacturing NAND memory cells.

[0079] Refer to Figure 21 , which shows the structure (component) 10a at a process stage after the process stage that can be at Figure 6 . The high-k dielectric material 28 is formed as a layer 30 along a substantially straight sidewall surface 65 (i.e., along the peripheral sidewalls of the opening 64), and the layer 30 extends through the stack 12.

[0080] Refer to Figure 22 . A charge blocking material 34 is formed adjacent to the layer 30, a charge storage material 38 is formed adjacent to the charge blocking material 34, a gate dielectric material (i.e., a tunneling material) 42 is formed adjacent to the charge storage material 38, a channel material 44 is formed adjacent to the gate dielectric material 42, and an insulating material 46 is formed adjacent to the channel material 44.

[0081] Refer to Figure 23 , the second material 62 ( Figure 22 ) is removed to leave a void 76.

[0082] Refer to Figure 24 . A conductive region 22 is formed within the void 76 ( Figure 23 ). The layer 16 can be regarded as a conductive layer including the conductive region 22 at the process stage of Figure 24 .

[0083] Refer to Figure 25 . The first material 60 ( Figure 24 ) is removed to form a second void 82. The region of the high-k dielectric material is exposed through the second void 82.

[0084] Refer to Figure 26 . A strip 90 is formed within the void 82 to narrow the void 82. The narrowing of the void 82 reduces the amount of the high-k dielectric material 28 exposed through the void 82.

[0085] Refer to Figure 27 . The narrowed second void 82 extends through the high-k dielectric material 28 to form a vertically stacked first section 88 (i.e., the exposed region of the high-k material 28 is removed to form the section 88). In the embodiment of Figure 27 , the section 88 has a vertical dimension D2 that is greater than the vertical dimension D1 of the front surface 79 of the conductive region 22 (i.e., the front surface within the conductive layer 16).

[0086] Reference Figure 28 , the narrowed gap 82 extends through the charge blocking material 34 and then through the charge storage material 38. The extended gap 82 divides the charge blocking material 34 into vertically spaced linear segments 36 and divides the charge storage material into vertically spaced linear segments 40.

[0087] Figure 28 An embodiment of shows a gap 82 that extends through materials 34 and 38 and terminates at the tunneling material 42. In other embodiments, the gap 82 may extend through the tunneling material.

[0088] Reference Figure 29 , the strip 90( Figure 28 ) is removed.

[0089] Reference Figure 30 , an insulating material 56 is formed within the second gap 82( Figure 29 ). Figure 30 The component 10a of includes a NAND memory cell 52, similar to the NAND memory cell described above with reference to Figure 19 .

[0090] Although the gap 82( Figure 30 ) is shown as being completely filled with the insulating material 56 at the process stage of, in other embodiments, the gap may be only partially filled to form a configuration similar to the configuration described above with reference to Figure 29 . Figure 20

[0091] Reference Figures 31 to 41 Describes another example process for manufacturing a NAND memory cell.

[0092] Reference Figure 31 , shows a structure (component) 10b at a process stage that may be the same as the process stage of Figure 7 . The structure includes an opening 64 that extends through the stack 12 and has a undulating peripheral sidewall surface 65. A cavity 68 extends into the region of the peripheral surface 65.

[0093] Reference Figure 32 , a layer of material 94 is formed along the undulating surface 65. The material 94 may include any suitable composition; and in some embodiments, may include silicon, consist essentially of silicon, or consist of silicon.

[0094] Reference Figure 33 , the material 94 is partially oxidized to form an oxide 96 (e.g., silicon dioxide) on the lateral outside of the remaining material 94. The remaining material 94 is within the cavity 68.

[0095] Reference Figure 34, the oxide 96 ( Figure 33 ) is removed. After removing the oxide, the peripheral sidewall 65 of the opening 64 has a undulating surface that extends along the second material 62 and along the remaining material 94. In some embodiments, the undulating sidewall of the opening 64 at the process stage of Figure 34 may be referred to as the second undulating sidewall to distinguish it from the first undulating sidewall shown at the process stage of Figure 31 .

[0096] Referring to Figure 35 , a charge blocking material 34 is formed adjacent to the undulating surface 65, a charge storage material 38 is formed adjacent to the charge blocking material 34, a gate dielectric material (i.e., tunneling material) 42 is formed adjacent to the charge storage material 38, a channel material 44 is formed adjacent to the gate dielectric material 42, and an insulating material 46 is formed adjacent to the channel material 44. The materials 34, 38, 42, and 44 are all configured as vertically extending layers that have a undulating configuration that is substantially conformal to the undulating configuration of the peripheral sidewall 65 of the opening 64.

[0097] Referring to Figure 36 , the second material 62 ( Figure 35 ) is removed to form a void 76.

[0098] Referring to Figure 37 , a high-k dielectric material 28 is formed within the void 76 ( Figure 36 ) to line the void, and then a conductive region 22 is formed within the lined void 76. Figure 37 The level 16 of

[0099] Referring to Figure 38 , the first material 60 ( Figure 37 ) is removed to form a second void 82. The material 94 is exposed within the second void 82.

[0100] Referring to Figure 39 , the material 94 ( Figure 38 ) is removed to extend the void 82.

[0101] Referring to Figure 40 , the void 82 extends through the charge blocking material 34 and then through the charge storage material 38. The extended void 82 divides the charge blocking material 34 into vertically spaced linear segments 36 and divides the charge storage material into vertically spaced linear segments 40.

[0102] Figure 40A Shows a process stage that can replace Figure 40 The process stage of. By similar to the above referring to Figure 15The described process removes exposed portions of the high-k dielectric material 28 along the upper surface 77 and the lower surface 81 of the conductive region 22 such that the high-k dielectric material 28 is formed into vertically extending linear segments 88.

[0103] Reference Figure 41 , shows the structure 10b at a process stage subsequent to the process stage of Figure 40 . Insulating material 56 is formed within the void 82 ( Figure 40 ). Figure 41 The assembly 10b of Figure 19 includes NAND memory cells 52, similar to the NAND memory cells described above with reference to

[0104] Although the void 82 ( Figure 41 ) is shown as being completely filled with insulating material 56 at the process stage of Figure 40 , in other embodiments, the void may be only partially filled to form a configuration similar to the configuration described above with reference to Figure 20 .

[0105] Reference Figure 41A , shows the structure 10b at a process stage subsequent to the process stage of Figure 40A . Insulating material 56 is formed within the void 82 ( Figure 40A ). Figure 41A The assembly 10b of Figure 19 includes NAND memory cells 52, similar to the NAND memory cells described above with reference to Figure 19 . Compared to the substantially flat configuration of such segments at the above process stage of Figure 41 , the segment 40 of the charge storage material 38 has a rounded configuration at the process stage of

[0106] Although the void 82 ( Figure 41A ) is shown as being completely filled with insulating material 56 at the process stage of Figure 40A , in other embodiments, the void may be only partially filled to form a configuration similar to the configuration described above with reference to Figure 20 .

[0107] In operation, the charge storage material 38 may be configured to store information in the memory cells 52 of the various embodiments described herein. The value of the information stored in an individual memory cell (where the term "value" represents one or more bits) may be based on the amount of charge (e.g., the number of electrons) stored in the charge storage region of the memory cell. The amount of charge within an individual charge storage region may be controlled (e.g., increased or decreased) based at least in part on the value of the voltage applied to the associated gate 54 and / or based on the value of the voltage applied to the channel material 44.

[0108] The tunneling material 42 forms a tunneling region of the memory cell 52. Such a tunneling region can be configured to allow the desired migration (e.g., transport) of charges (e.g., electrons) between the charge storage material 38 and the channel material 44. The tunneling region can be configured (i.e., designed) to achieve selected criteria, such as but not limited to the equivalent oxide thickness (EOT). The EOT quantifies the electrical properties (e.g., capacitance) of the tunneling region in terms of a representative physical thickness. For example, the EOT can be defined as the thickness of a theoretical silicon dioxide layer that would have the same capacitance density as a given dielectric, neglecting leakage current and reliability considerations.

[0109] The charge blocking material 34 can provide a mechanism for blocking the flow of charges from the charge storage material 38 to the associated gate 54.

[0110] The dielectric barrier material (high-k material) 28 can be used to inhibit the back tunneling of charge carriers from the gate 54 towards the charge storage material 38. In some embodiments, the dielectric barrier material 28 can be considered to form a dielectric barrier region within the memory cell 52.

[0111] The components and structures discussed above can be used within an integrated circuit (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and can be incorporated into an electronic system. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and specialized modules, and can include multi-layer, multi-chip modules. The electronic system can be any one of a wide range of systems: such as cameras, wireless devices, displays, chip sets, set-top boxes, gaming, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0112] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method known now or to be developed, the methods including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0113] The terms "dielectric" and "insulating" can be used to describe materials having insulating electrical properties. The terms are considered synonymous in the present disclosure. The use of the term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases can provide a variation in language within the present disclosure to simplify the underlying basis within the appended claims, rather than to indicate any significant chemical or electrical differences.

[0114] The terms "electrically connected" and "electrically coupled" can both be used in the present disclosure. The terms are considered synonymous. The use of one term in some cases and the other term in other cases may be to provide a variation in language within the present disclosure to simplify the underlying basis within the accompanying claims.

[0115] The specific orientations of the various embodiments in the figures are for illustrative purposes only, and in some applications, the embodiments may be rotated relative to the shown orientations. The description provided herein and the appended claims relate to any structure having the described relationships between the various features, whether the structure is in the specific orientation of the figures or rotated relative to such orientation.

[0116] Unless otherwise indicated, the cross-sectional views illustrated in the accompanying drawings show only the features in the plane of the cross-section and do not show the material behind the plane of the cross-section, in order to simplify the drawings.

[0117] When a structure is referred to above as being "on", "adjacent" or "against" another structure, the structure may be directly on the other structure or there may also be intervening structures. In contrast, when a structure is referred to as being "directly on", "directly adjacent" or "directly against" another structure, there are no intervening structures. The terms "directly below", "directly above", etc. do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate vertical alignment.

[0118] A structure (e.g., a layer, material, etc.) may be referred to as "vertically extending" to indicate that the structure generally extends upward from a bottom substrate (e.g., a substrate). A vertically extending structure may or may not extend substantially orthogonally relative to the upper surface of the substrate.

[0119] Some embodiments include an integrated structure having a vertically stacked arrangement of alternating insulating layers and conductive layers. A channel material extends vertically through the stack. The conductive layers have a front surface facing the channel material and upper and lower surfaces extending rearward from the front surface. A high-k dielectric material is arranged as a first section of the vertical stack. The high-k dielectric material is along the front surface of the conductive layer and not along the upper and lower surfaces of the conductive layer. A charge blocking material is arranged as a second section of the vertical stack. The second section is adjacent to the first section. A charge storage material is arranged as a third section of the vertical stack. The third section is adjacent to the second section. A gate dielectric material is adjacent to the charge storage material and between the charge storage material and the channel material.

[0120] Some embodiments include a vertically stacked NAND memory array having alternating insulating levels and conductive levels. The conductive levels include control gate regions. A high-k dielectric material is adjacent to the control gate regions and is configured as an arrangement of first vertically extending linear segments that are vertically spaced apart from each other. A charge blocking material is adjacent to the high-k dielectric material and is configured as an arrangement of second vertically extending linear segments that are vertically spaced apart from each other. A charge storage material is adjacent to the charge blocking material and is configured as an arrangement of third vertically extending linear segments that are vertically spaced apart from each other. A gate dielectric material is adjacent to the charge storage material. A channel material extends vertically along the stack and is adjacent to the gate dielectric material.

[0121] Some embodiments include a method of forming an integrated structure. A vertical stack is formed to include alternating first and second levels. The first level includes a first material and the second level includes a second material. An opening is formed to extend through the stack. The opening has peripheral sidewalls. A charge blocking material is formed adjacent to the peripheral sidewalls. A charge storage material is formed adjacent to the charge blocking material. A gate dielectric material is formed adjacent to the charge storage material. A channel material is formed adjacent to the gate dielectric material. The second material is removed to leave a first void. A conductive level is formed within the first void. The conductive level has a front end with a front surface. The front surface faces the charge blocking material. A high-k dielectric material is formed to be between the front surface and the charge blocking material. The high-k dielectric material is configured as first segments that are vertically spaced apart from each other, where the first segments are along the front surface of the conductive level and do not surround the front end of the conductive level. The first material is removed to leave a second void. The second void is extended through the charge storage material to divide the charge storage material into vertically spaced apart segments.

[0122] As provided, the subject matter disclosed herein has been described in more or less specific language with respect to structural and method features. However, it should be understood that the claims are not limited to the specific features shown and described, since the components disclosed herein include example embodiments. Accordingly, the claims have the full scope as literally stated and should be interpreted appropriately in accordance with the doctrine of equivalents.

Claims

1. An integrated structure, comprising: A vertical stack of alternating insulating layers and conductive layers; A channel material that vertically extends through the stack; The conductive layer having a front surface facing the channel material, and having an upper surface and a lower surface extending rearward from the front surface; A high-k dielectric material arranged as a first section of the vertical stack; the high-k dielectric material is along the front surface of the conductive layer and not along the upper surface and the lower surface of the conductive layer; A charge blocking material arranged as a second section of the vertical stack; the second section is adjacent to the first section; A charge storage material arranged as a third section of the vertical stack; the third section is adjacent to the second section; A gate dielectric material adjacent to the charge storage material and between the charge storage material and the channel material; And A void that exposes a conductive portion of the conductive layer and extends into the charge blocking material, such that a vertical dimension of the second section of the charge blocking material is greater than a vertical dimension of the first section of the high-k dielectric material.

2. The integrated structure according to claim 1, wherein the front surface has a first vertical dimension; and wherein the first section has a second vertical dimension that is greater than or approximately equal to the first vertical dimension.

3. The integrated structure according to claim 1, wherein the front surface has a first vertical dimension; and wherein the first section has a second vertical dimension that is greater than the first vertical dimension.

4. The integrated structure according to claim 1, wherein: The front surface has a first vertical dimension; The first section has a second vertical dimension; The second section has a third vertical dimension; The second vertical dimension is greater than or approximately equal to the first vertical dimension; and The third vertical dimension is greater than the second vertical dimension.

5. The integrated structure according to claim 4, wherein: The third section has a fourth vertical dimension; and The fourth vertical dimension is greater than or approximately equal to the third vertical dimension.

6. The integrated structure according to claim 1, wherein the high-k dielectric material comprises one or more of aluminum oxide, hafnium oxide, hafnium silicate, zirconium oxide, and zirconium silicate.

7. The integrated structure according to claim 1, wherein each of the third sections has a substantially flat configuration.

8. The integrated structure according to claim 1, wherein each of the third sections has a rounded configuration.

9. The integrated structure according to claim 1, wherein the conductive layer comprises two or more conductive materials.

10. The integrated structure according to claim 9, wherein the high-k dielectric material directly abuts against one of the two or more conductive materials.

11. A NAND memory array, comprising: A vertical stack of alternating insulating layers and conductive layers; The conductive layer comprising a control gate region; A high-k dielectric material adjacent to the control gate region and configured as an arrangement of first vertically extending linear sections that are vertically spaced apart from each other; A charge blocking material, an arrangement of second vertically extending linear segments that are adjacent to the high-k dielectric material and are configured to be vertically spaced apart from each other; A charge storage material, an arrangement of third vertically extending linear segments that are adjacent to the charge blocking material and are configured to be vertically spaced apart from each other; A gate dielectric material, adjacent to the charge storage material; And A channel material, vertically extending along the stack and adjacent to the gate dielectric material, wherein a void extends into the charge blocking material such that a vertical dimension of the second vertically extending linear segments of the charge blocking material is greater than a vertical dimension of the first vertically extending linear segments of the high-k dielectric material.

12. The NAND memory array according to claim 11, wherein the third vertically extending linear segments are at least as long as the second vertically extending linear segments.

13. The NAND memory array according to claim 11, wherein the insulating layer is at least partially filled with an insulating material.

14. The NAND memory array according to claim 13, wherein the insulating layer is only partially filled with the insulating material.

15. The NAND memory array according to claim 13, wherein the insulating layer is completely filled with the insulating material.

16. The NAND memory array according to claim 11, wherein the conductive layer has a certain thickness; and wherein the first vertically extending linear segments have a length approximately equal to the thickness.

17. The NAND memory array according to claim 11, wherein the conductive layer has a certain thickness; and wherein the first vertically extending linear segments have a length greater than the thickness.

18. A method of forming an integrated structure, comprising: Forming a vertical stack of alternating first and second layers; The first layer includes a first material and the second layer includes a second material; Forming an opening extending through the stack, the opening having peripheral sidewalls; Forming a charge blocking material adjacent to the peripheral sidewalls; Forming a charge storage material adjacent to the charge blocking material; Forming a gate dielectric material adjacent to the charge storage material; Forming a channel material adjacent to the gate dielectric material; Removing the second material to leave a first void; Forming a conductive layer within the first void; the conductive layer has a front end with a front surface; The front surface faces the charge blocking material; Forming a high-k dielectric material within the first void to align the first void to be between the front surface and the charge blocking material; the high-k dielectric material is configured as first segments that are vertically spaced apart from each other, wherein the first segments are along the front surface of the conductive layer and do not surround the front end of the conductive layer; Removing portions of the high-k dielectric material above and below the conductive layer; Removing the first material to leave a second void; Forming a strip within the second void to narrow a vertical dimension of the second void; And Extending the second void through the charge storage material to divide the charge storage material into vertically spaced apart segments.

19. The method according to claim 18, comprising forming the high-k dielectric material within the first void to line the first void; wherein the forming of the conductive layer comprises forming a conductive material within the lined first void; wherein the formation of the second void exposes portions of the high-k dielectric material above and below the conductive material; wherein the second void has a vertical thickness; and the method further comprises the following steps in the following order: removing the exposed portions of the high-k dielectric material; forming a strip within the second void to narrow the vertical thickness; extending the second void through the charge blocking material and then through the charge storage material to divide the charge storage material into the vertically spaced-apart sections; and at least partially filling the second void with an insulating material.

20. The method according to claim 18, comprising forming the high-k dielectric material within the first void to line the first void; wherein the forming of the conductive layer comprises forming a conductive material within the lined first void; wherein the formation of the second void exposes portions of the high-k dielectric material above and below the conductive material; wherein the second void has a vertical thickness; and the method further comprises: removing the exposed portions of the high-k dielectric material; forming a sacrificial material within the second void to narrow the vertical thickness; after narrowing the vertical thickness, extending the second void through the charge blocking material and then through the charge storage material to divide the charge storage material into the vertically spaced-apart sections; removing the sacrificial material; and after removing the sacrificial material, at least partially filling the second void with an insulating material.

21. The method according to claim 20, wherein the sacrificial material comprises silicon nitride.

22. The method according to claim 18, comprising: recessing the first tier relative to the second tier to form a cavity along the first tier; filling the cavity with a sacrificial material to form the peripheral sidewalls of the opening to have substantially straight sidewall surfaces; the formation of the charge blocking material comprises forming the charge blocking material along the substantially straight sidewall surfaces; and removing the sacrificial material during the formation of the second void.

23. The method according to claim 22, wherein the charge blocking material has a substantially flat configuration along the substantially straight sidewall surfaces; wherein the charge storage material is formed along the substantially flat configuration; and wherein each of the vertically spaced-apart sections of the charge storage material has a substantially flat configuration.

24. The method according to claim 22, wherein the sacrificial material comprises polysilicon.

25. The method according to claim 18, wherein: the high-k dielectric material is initially formed to vertically extend through the stacked layers; the removal of the first material exposes regions of the high-k dielectric material; and removing at least a portion of the regions.

26. The method according to claim 25, wherein the second void has a vertical thickness, and the method further comprises the following steps in the following order: forming a strip within the second void to narrow the vertical thickness and reduce the amount of the exposed high-k dielectric material; removing the reduced amount of the exposed high-k dielectric material; and at least partially filling the second void with an insulating material.

27. The method according to claim 25, wherein the second void has a vertical thickness, and the method further comprises: forming a sacrificial material within the second void to narrow the vertical thickness and reduce the amount of the exposed high-k dielectric material; removing the reduced amount of the exposed high-k dielectric material; removing the sacrificial material; and after removing the sacrificial material, at least partially filling the second void with an insulating material.

28. The method according to claim 27, wherein the sacrificial material comprises silicon nitride.

29. The method according to claim 18, comprising: recessing the first tier relative to the second tier to form a cavity along the first tier and forming a first undulating sidewall surface of the opening; forming a silicon layer along the first undulating surface; partially oxidizing the silicon layer to form an oxide laterally outside the remaining silicon; the remaining silicon being within the cavity; and removing the oxide to form the peripheral sidewall of the opening to have a second undulating surface extending along the remaining silicon and along the second material of the second tier; wherein the forming of the charge blocking material comprises forming the charge blocking material along the second undulating surface.

30. The method according to claim 29, wherein the charge blocking material has an undulating configuration along the second undulating surface; wherein the charge storage material is formed along the undulating configuration of the charge blocking material; and wherein each of the vertically spaced apart segments of the charge storage material has a rounded configuration.

31. The method according to claim 29, comprising forming the high-k dielectric material within the first void to line the first void; wherein the forming of the conductive tier comprises forming a conductive material within the lined first void; wherein the forming of the second void exposes portions of the high-k dielectric material above and below the conductive material; and the method further comprises removing the exposed portions of the high-k dielectric material.

32. The method according to claim 31, further comprising at least partially filling the second void with an insulating material.

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