Semiconductor structure with dielectric layer

Abstract

A semiconductor component (200) is disclosed, the semiconductor component having at least one dielectric layer (230) and at least two electrodes (201, 202), wherein at least a first defect type and a second defect type different from the first defect type are present in the dielectric layer. The different defect types (212, 215, 217) accumulate on one of the two electrodes within characteristic times τ1 and τ2 depending on an operating voltage applied between the electrodes and a current main operating temperature and produce associated maximum barrier height changes δΦ1 and δΦ2 on the electrode, wherein τ1<τ2 and δΦ1<δΦ2 apply. PZT layers sputtered at less than 500° C. and doped with nickel are preferred, for example for piezoelectric actuators.

Description

Technical Field

[0001] The invention relates to a semiconductor structural element. Background Art

[0002] In "Improved reliability predictions in high permittivity dielectric oxide capacitors under high de electric fields with oxygen vacancy induced electromigration" by CA Randall, R. Maier, W. Qu, K. Kobayashi, K. Morita, Y. Mizuno, N. Inoue and T. Oguni in "Journal of Applied Physics" (113, 014101 (2013)), the jump of defect types present in the dielectric layer (for example, oxygen defects) is described as the cause of breakdown in the dielectric layer. Here, the central model parameters are explained physically, but are obtained empirically by fitting with the stop time (Ausfallzeit) under the assumption that there is only one active defect type. There is no description of how these parameters are more accurately associated with the material. Here, complex stop mechanisms are not completely or not mapped at all, in which case there are multiple defect types in the semiconductor layer. The service life prediction described there is only applicable if, under the current load conditions with a certain temperature and a certain electrical field, one defect type predominates and only leads to failure due to the accumulation of this defect type on the boundary layer.

[0003] In "Highly accelerated lifetime testing of potassium sodium niobate thin films" by Wanlin Zhu, Betul Akkopru-Agkun and Susan Trolier-McKinstry in "Journal of Applied Physics" (111, 212903 (2017)), typical failure frequencies over operating time for various operating conditions were further determined. It can be seen from this that the failure mechanisms in the material vary under these test operating conditions or even under specific operating conditions in a group of samples. However, in addition, no connection with physical, electrical or chemical processes in the material can be drawn based on the empirical model.

[0004] The object of the present invention is to optimize the service life of a semiconductor component having more than one active defect type as a function of a set main operating voltage and a main operating temperature of the semiconductor component. Summary of the invention

[0005] In order to achieve this object, a semiconductor component according to the invention is proposed. This semiconductor component is manufactured on a silicon substrate by means of thin-film technology and can be used, for example, as a piezoelectric actuator in a MEMS component, such as a micromirror. In this case, the semiconductor component has at least one dielectric layer. In addition, the semiconductor component has at least one first and second electrode, via which a main operating voltage is applied to the dielectric layer. Depending on the specifications of the semiconductor component, the main operating voltage is the maximum potential difference permitted between the two electrodes of the semiconductor component in active operation. There are also at least two different defect types in the dielectric layer. These defect types can be defects (such as oxygen or lead defects), lattice defects caused by occupied interstitial positions (for example, due to hydrogen), Frenkel defects, but also substitutional defects (for example, due to intentionally or unintentionally introduced foreign atoms). These defect types differ from each other, for example, in their charge number. The first defect type is assigned a first charge N q,1 and the first true activation energy E related to materials and defects A,0,1 The second defect type is assigned a second charge N q,2 and the second true activation energy E A,0,2 . At least two different defect types accumulate on the boundary layer of the two electrodes within characteristic times τ1 and τ2, depending on the main operating voltage applied between the first and second electrodes and the current main operating temperature, and produce maximum barrier height changes δΦ1 and δΦ2 on these electrodes. Depending on the specifications of the semiconductor component, the main operating temperature is the maximum temperature allowed in active operation. τ1 and δΦ1 are assigned to the first defect type, and τ2 and δΦ2 are assigned to the second defect type. The higher the maximum barrier height changes δΦ1 and δΦ2 and the smaller τ1 and τ2 of the corresponding defect type, the greater the critical barrier height change ΔΦ on the boundary layer between the dielectric layer and the electrode. krit + / -The faster it is reached and the faster the dielectric breakdown occurs. In the semiconductor structure element according to the invention, it applies that τ2 is greater than τ1. This means that, compared to the first defect type, the second defect type essentially takes a longer time to move in the dielectric layer towards the electrode and accumulate on the boundary surface of the electrode. However, it also applies that δΦ1<δΦ2 and therefore the maximum barrier height change δΦ2 caused by the second defect type is greater than the maximum barrier height change δΦ1 caused by the first defect type. Therefore, the defect type that has a relatively low influence on the electrical breakdown of the dielectric layer reaches the boundary layer first. The effect that results from this is that the critical barrier height change ΔΦ of the electrode is reached later in time. krit + / - , and thus achieve a longer service life under the operating conditions for which the semiconductor component is designed.

[0006] For example, during the deposition of the dielectric layer, the maximum barrier height variation δΦ i can be influenced by the choice of the starting material. For example, in the case of a PZT layer, the lead, zirconium and / or titanium deficiency or excess can be set by the composition (Zusammensetzung) in the starting material. This means that in the case of sputtering deposition, the choice of the target material can be important, and in the case of sol deposition, the choice of the precursor sol can be important. Thus, for example, the δΦ associated with a lead defect i can be reduced by increasing the lead content in the target or precursor sol above the stoichiometric composition. In contrast, for example, the δΦ associated with lead excess i This can be reduced by reducing the lead content in the target or precursor sol.

[0007] In addition, the maximum barrier height variation δΦ i can be varied, for example, by process parameters during deposition. Thus, for example, higher temperatures during the sputtering of PZT can lead to outgassing of lead, which leads to a reduction in the lead content of the layer. Thus, δΦ associated with lead defects i It can be reduced by lowering the process temperature during PZT sputtering.

[0008] The process gases involved can also be used to influence the defect type. For example, oxygen defects are a known defect type in PZT layers. Furthermore, the number of oxygen defects present in the material can be influenced by varying the oxygen partial pressure during the sputtering deposition of PZT. Thus, for example, δΦ associated with oxygen defects i It can be reduced by increasing the oxygen flow.

[0009] Subsequent processes are usually required for the passivation and contacting of semiconductor components. In addition, subsequent processes are usually required for the production of other components on the same substrate. These subsequent processes can have a very large impact on the electrical service life of semiconductor components. If hydrogen in subsequent processes penetrates into the lead oxide structure of PZT, oxygen can reduce the lead oxide. This produces oxygen defects together with H2O or OH sites for gaseous precipitation, or mobile hydrogen ions in the structure. In subsequent processes, such as the deposition of passivation in a hydrogen-containing plasma process, the reduction in the hydrogen content leads to a decrease in the δΦ associated with the oxygen defects or hydrogen ions. i In such a process, for example, the hydrogen content can be reduced by using precursors with a lower hydrogen content, for example, using N2 as the nitrogen source instead of NH3 in the deposition of PECVD-SiN passivation. Another possibility to reduce hydrogen in the deposition of PECVD passivation is, for example, to reduce the gas flow of hydrogen-containing precursors in order to achieve a reduction in the δΦ associated with oxygen defects or hydrogen ions. i .

[0010] By suitable selection of the subsequent processes and / or also by the hydrogen barrier surrounding the dielectric, the defect quantity and / or the δΦ associated with the oxygen vacancies and / or the hydrogen ions can be influenced. i Surrounding PZT with a hydrogen barrier (e.g. sputtered metal oxides: RuO, TiO, AlOx) also leads to a δΦ associated with oxygen vacancies and / or hydrogen ions. i Another possibility for reducing the material damage caused by hydrogen is to reduce the temperature and / or the duration of the temperature step in the subsequent process in order to provide less energy for the reaction with the dielectric layer. This leads to a δΦ associated with the oxygen vacancies or hydrogen ions. i reduction.

[0011] In another example, where oxygen defects are known to dominate in the dielectric material, the temperature step can be set in an oxygen atmosphere. Subsequent introduction of oxygen into the structure with oxygen defects results in a δΦ associated with the oxygen defects. i reduction.

[0012] For example, a criterion can be achieved according to which τ1<τ2 and δΦ1<δΦ2 apply by doping the dielectric layer with at least one further defect type in such a way that δΦ1<δΦ2 applies for the maximum barrier height change at the contact between the dielectric layer and the electrode. The energy structure inside the material can thus be changed. Thus, for example, for an existing interfering defect type a with a relatively small τ1 and a large δΦ1, new deeper local defect centers that did not previously exist can be generated, i.e. with a deeper local potential energy minimum. As a result, the mobility of the interfering defect type a can be reduced. In this case, the introduction of a further defect type may well lead to a further large maximum barrier height drop of δΦ3. Preferably, however, such a drop for the corresponding main operating state occurs only at a point in time after the electrical failure of the dielectric layer at the time t krit The reason for this is that the other defect type in question has such a large characteristic time constant τ3 that it cannot accumulate in the boundary layer of the electrode until failure of the component.

[0013] Defects can also be introduced unintentionally in the starting material through contamination, which can be reduced by increasing the purity of the starting material, such as the target in sputtering or the precursor sol in the sol-gel method. Reducing foreign matter (e.g., iron, chlorine) in the construction of the dielectric layer can therefore reduce the δΦ associated with these defects. i .

[0014] In the case of field-activated defects that dominate over thermally activated defects, increasing the thickness of the dielectric layer is another possibility to change the order in the defect configuration. Increasing the thickness of the dielectric layer, for example, especially in the case of piezoelectric actuators with PZT, offers the possibility of increasing the service life at a constant actuator force, since a small electric field increases the time constant τ of all the i defect types involved. i .

[0015] The semiconductor component according to the invention exhibits a leakage current density J over the load period until dielectric failure. TED The time curve of this is obtained by the equation according to the thermionic emission diffusion theory of Crowell and Sze

[0016]

[0017] Here, q represents the unit charge, N c represents the effective density of states in the conduction band, v R represents the effective recombination velocity, v D represents the effective diffusion velocity, φ B eff represents the effective Schottky barrier, k Brepresents the Boltzmann constant, T represents the ambient temperature, and U represents the potential difference across the dielectric layer. In this context, U means the main operating voltage applied to the two electrodes of the semiconductor component.

[0018] The time curve of the leakage current density is given by the change of the effective Schottky barrier φ B eff (t). This change or the Schottky barrier φ B eff (t) characterizes the influence of two boundary layers on the leakage current density, which are located between the two electrodes and the dielectric layer. The effective Schottky barrier is hereinafter referred to as φ(t) and contains all components of the semiconductor-electrode material transition, the changes due to the applied main operating voltage and the changes due to the accumulation of defects. The logarithm of the leakage current density simplifies equation (1) to a time constant K and a term that is variable in time and reflects the processes inside the material caused by the movement of all movable defects contained in the material:

[0019]

[0020] The term defects also includes structural changes in the design.

[0021] As the electrode approaches, the displacement of the defects leads to an accumulation of defects in the dielectric layer, which results in a change in the effective barrier height. Solving Equation 2.1 for φ yields

[0022] Φ(t)=[ln(K)-ln(J TED (t))]k B T (2.2)

[0023] This temporal profile of the effective barrier height due to defect accumulation is obtained by

[0024]

[0025] Here, in general, the accumulation and the associated change in the effective Schottky barrier occur at the two boundary layers φ + (t) and φ -(t). Here, the superscripts "+" and "-" respectively mark the changes on the boundary layer, which characterize the transition of minority carriers and majority carriers into the dielectric layer. The boundary layer has an initial barrier height φ0 and undergoes a barrier height change ΔΦi caused by defect type i. Due to the necessary charge neutrality, there must always be defect pairs or defect accumulations. This means that when a defect with a negative charge appears, there are also defects with a positive charge in the material. Their corresponding influences are marked by superscripts + and -. Individual defects move in opposite directions according to their charge in the applied electric field of the main operating voltage. Defects with a positive charge migrate to the electrode with a negative potential and accumulate in the dielectric layer near it. Defects with a negative charge move to the electrode with a positive potential in order to accumulate near it again.

[0026] The change in barrier height Δφ caused by defect type i i is characterized by its maximum height δφ i and the characteristic time constant τ i , the time constant in which the barrier height changes most strongly:

[0027]

[0028] Here, generally speaking, δφ i is the number of defects Z i function of , but additionally depends on the type of boundary layer. The influence of the number of defects cannot be generalized, since the accumulation of a single layer can already produce a significant barrier height change Δφ i Therefore, for the material, only Z i >0 is decisive. In the above formula, the term represents an approximation for the statistical accumulation of a given defect distribution in a material. Here, the maximum positive and negative heights of the potential barrier vary δφ + and δφ - and the associated time constant τ i + and τ i - have different sizes because different defects and, as is known, different boundary layers are involved. This together with equation (3.2) leads to

[0029]

[0030] or for the temporally variable part of the potential barrier variation resulting in

[0031]

[0032] Time constant τ + / -is defined by the mobility of the defect in the dielectric layer and the path it has to take in this layer. In order to move inside the dielectric layer, defect type i must travel the distance d from the center of gravity of its distribution to the boundary layer. i . With speed v i Together, the characteristic time constant for the accumulation process of defect type i is generated

[0033]

[0034] The semiconductor component according to the invention is characterized in that the defects are displaced by jumping in the applied electric field of the main operating voltage. Defect type i is located along a line with an average effective spacing a i The local defect state moves. This leads to a jump velocity v i , which is described by the known variable range hopping method:

[0035]

[0036] Here, C 0,i (a i ) represents a function that shows the influence of the local defect distribution. Here, as is common in variable range jumps, the jump test frequency ν i It refers to the frequency with which the defect encounters the existing potential barrier. In addition, the defect jump probability overlaps with the wave function of the dihydrogen local defect The defect is proportional to the distance a between the local defect states. i has a decay length α.

[0037] Here, C 0,i (a i ) represents a function showing the influence of local defect distribution. The jump probability with increasing operating temperature is calculated by having a real activation energy E related to the material and defects. A,o,i Here, the real activation energy E A,o,i Refers to the activation energy that is independent of the operating voltage and operating temperature. With increasing main operating temperature and simultaneously decreasing main operating voltage, the dominant factor is the defect type with large real activation energy and low charge. This means that under these operating conditions, defect types with large real activation energy and low charge contribute to the electrical failure of semiconductor components. The hyperbolic sine function describes the directional reduction of the energy barrier during the jump process, which contains the charge N associated with the defect i. q,i , average local defect center distance a i The product of the voltage U and the electric field E. The electric field E is generated by the applied main operating voltage U and the thickness d of the dielectric layer. The term sinh(N q,i a i E / (kB T)) is influenced by increasing the main operating voltage and decreasing the main operating temperature. In this case, defect types with a high charge number and at the same time a low actual activation energy contribute to the electrical failure of the semiconductor component.

[0038] In a semiconductor component, n defect types contained in a dielectric layer move through local defect states with the same average spacing a0. Therefore, the following applies:

[0039] a1=a2...=a n =a0 (8)

[0040] This spacing of local defect states enables the determination of the local defect states from the leakage current measurement data J with the knowledge of the physical modeling described previously. TED The mean effective spacing a0 is the key material property for dielectric failure under temperature and voltage load. This material property is independent of the operating voltage and operating temperature and can be influenced by the manufacturing process.

[0041] By understanding the previously described physical model, for the i defect types involved, the leakage current measurement data J can be TED Determine the charge N q,i and the true activation energy E A,0,i In addition, the potential barrier drop Δφ can be calculated for the operating state i The time curve of the potential barrier drop Δφ i By the characteristic time constant τ i (In this time constant, the barrier height changes Δφ i The most intense change) and its maximum barrier height decrease δφ i Description. In understanding the charge N q,i and the true activation energy E A,0,i In the case of , the defect type can be identified in different operating states and the defect type is assigned to its different impact Δφ according to the operating state. i Therefore, for semiconductor components, operating states can be identified in which a long service life of the semiconductor components can be achieved. This is characterized by having a failure time t krit The time constant τ i The faster defect type has a comparably smaller maximum barrier height drop δφ i .

[0042] In semiconductor components, there is a critical barrier height change ΔΦ for both boundary layers krit + / - If locally at time t kritReaching or exceeding one of these critical barrier height changes ΔΦ krit + / - , then dielectric breakdown occurs locally. This means that when φ is reached krit + When , breakdown occurs via tunneling minority carriers (case 1):

[0043] φ krit + =φ0 + +Σ i Δφ i + (t krit )=φ0 + +Δφ krit + Among them, Δφ krit + =∑ i Δφ i + (t krit ) (9.1)

[0044] On the contrary, when reaching φ krit - When , breakdown occurs via tunneling majority carriers (case 2):

[0045] φ krit - =φ0 - +∑ i Δφ i - (t krit )=φ0-+Δφ krit - Among them, Δφ krit - =∑ i Δφ i - (t krit ) (9.2)

[0046] At local krit When the leakage current density J increases locally, the semiconductor structure element is damaged locally. TED In the curve of krit , can either be achieved by a short rise followed by an immediate return to the J before the rise TED This is detected by a jump in the first case, or by a permanent jump. In the first case, the conduction path itself is thermally damaged. In the second case, the supplied electrical power is not sufficient to completely damage the conduction path. kritAfterwards, a semiconductor component remains which is locally damaged in a limited area. krit As the load increases, more and more local dielectric breakdowns occur, which ultimately lead to complete destruction of the semiconductor component. The first local breakdown is therefore an important and relevant measure for the service life of the semiconductor component.

[0047] Therefore, with the help of the physical description of the barrier height change (5) for the hopping transport via n defect types (6) and (7), the charge N can be determined from the time curve of the leakage current density (1). q,i , true activation energy E A,0,i , the height of the maximum barrier change δφ i and the characteristic time constant τ i If such measurements are carried out before and after changes in the production process, the semiconductor component can be improved in a targeted manner.

[0048] For this purpose, firstly, the temperature until dielectric breakdown at time t is measured on the semiconductor component at at least two main operating voltages U1 and U2 and at least two main operating temperatures T1 and T2. krit Leakage current curve J TED Then the equations (2.2) and (5) described above are treated equivalently and then by numerical fitting and then by J TED The time curve of the barrier height change Δφ and the time curve of the single parameter δφ are obtained by i and τ i With the help of (9.1) and (9.2), we also get the critical barrier drop Δφ according to the main operating voltage and the main operating temperature krit .

[0049] According to the formulas (6), (7) and (8) described above, τ is obtained according to the electric field E and the main operating temperature. i :

[0050]

[0051] From the τ thus determined for at least two main operating temperatures T1 and T2 and at least two main operating voltages U1=E1 / d and U2=E2 / d i , the parameter N can be determined by mathematical fitting from equation (10.1) when there are n>1 defects q,i 、E a,0,i And the parameter a0. The measured J TED The curves are subject to manufacturing fluctuations and tolerances caused by the measurement technique used. Therefore, the material properties a0, C 0,i (a0), Nq,i and A,0,i The accuracy of can be improved by increasing the number of samples and also by additional measurement data at more than two voltages and / or more than two temperatures.

[0052] After changing the process conditions, repeat the determination of δφ i and τ i And here the parameter N q,i and E a,0,i It is uniquely and clearly assigned to the defect type. This shows the physical influence of the process change on the i defect in question.

[0053] Preferably, at least one further third defect type is present in the dielectric layer. In this case, the third defect type is designed to accumulate on one of the two electrodes within a characteristic time τ3 as a function of the main operating voltage applied between the first and second electrodes and the current main operating temperature and to produce a maximum barrier height change δΦ3 on said electrode. In this case, τ1<τ3<τ3 applies, wherein the order of the maximum barrier height change differs from the order δΦ1>δΦ2>δΦ3. This means, for example, that δΦ3>δΦ2>δΦ1 or δΦ2>δΦ1>δΦ3 applies. Dielectric layers in which more than only two different defect types are present are increasingly common. In the case of a PZT layer, for example, there is an at least local excess or deficiency of Pb, Ti and Zr atoms in the dielectric layer. In addition, in practice, operating states occur in which more than two defect types provide a significant and relevant contribution to the electrical failure of the dielectric layer.

[0054] The dielectric layer is preferably designed as a polycrystalline high-k oxide dielectric and in particular as a PZT layer (PZT=Pb[Zr x Ti 1-x ]O3), doped PZT layer (Pb[Zr x Ti 1-x-y ]O3Ni y ), KNN layer (KNN = [K x Na 1-x ]NbO3), HfO2, ZrO2 or SrTiO3.

[0055] Preferably, the dielectric layer is designed as a sputtered PZT layer. In this case, the so-called target material is deposited on the substrate in a plasma. For example, PZT is used as the target material. Preferably, in this context, the sputtered PZT layer has a deposition temperature of less than 500° C. In the case of such a dielectric layer, the following effect can be demonstrated: depending on the selected main operating voltage and main operating temperature, more than two defect types actively contribute to the dielectric failure.

[0056] Preferably, the sputtered PZT layer has Pb x (Zr 0.52 Ti 0.48 )O3 composition. Here, for x, the following applies: 1.2≤x≤1.3, so that the composition can be composed, for example, of Pb 1.2 (Zr 0.52 Ti 0.48 )O3 or Pb 1.3 (Zr 0.52 Ti 0.48 )O3 composition. Alternatively, the sputtered PZT layer of the semiconductor structure has a nickel content of between 0.1 and 1 atomic percent. Preferably, additional defects can also be introduced into the high-k dielectric by doping in order to influence the change δΦ of the maximum barrier height and the time constant τ. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1a The graphs of leakage current measurements are shown for five different dielectric layers.

[0058] Figure 1b The time curve of the effective barrier height resulting from leakage current measurements and a breakdown of the contribution to the defect types present are shown.

[0059] Figure 2a The maximum barrier height change and the characteristic time constant of three exemplary embodiments are shown for an exemplary operating state of 175° C. / −2.5 V.

[0060] Figure 2b The maximum barrier height variation and characteristic time constant for one embodiment are shown under two exemplary operating conditions of 175°C / -2.5V and 100°C / -10V.

[0061] Figure 2c The maximum barrier height change and the characteristic time constant of two exemplary embodiments are shown for an exemplary operating state of 175° C. / −2.5 V.

[0062] Figure 2d The maximum barrier height change and the characteristic time constant of two exemplary embodiments are shown for an exemplary operating state of 175° C. / −2.5 V.

[0063] Figure 2e The maximum barrier height change and the characteristic time constant of two exemplary embodiments are shown for the exemplary operating state 100° C. / −10 V.

[0064] Figures 3a to 3d Schematic representation of the movement of different defect types in a dielectric layer along local defect states with an average effective spacing a0. DETAILED DESCRIPTION

[0065] Figure 1a A curve 14 is shown for leakage current measurement of a dielectric layer of a semiconductor structure element, which will be referred to as Example 1 in the following text. In this case, the time is plotted logarithmically in seconds on the X-axis 12 and the leakage current density is plotted logarithmically in amperes per square centimeter on the Y-axis 10. Example 1, which is provided for leakage current measurement, has a silicon substrate having a dielectric passivation layer and a first electrode deposited thereon. This first electrode has a double layer made of PVD platinum with a thickness of 110 nm, which is covered by a conductive 100 nm lanthanum nickel oxide buffer layer (referred to as LNO layer in the following text). The LNO layer is likewise applied by PVD. The dielectric layer located on the first electrode has a thickness of 1 μm and is deposited in an RF-PVD process at a temperature of 480° C. and Pb 1.3 (Zr 0.52 Ti 0.48 )O3. The remaining process parameters of the deposition described above are selected so that the dielectric layer grows polycrystalline and preferably with a (100) c-axis orientation. The second electrode of the semiconductor element (a 110 nm thick platinum electrode) is deposited on the dielectric layer by PVD. The semiconductor structure element according to Example 1 is not subjected to any thermal post-treatment after passivation and electrical contacting.

[0066] also, Figure 1a A curve 16 shows a leakage current measurement of a dielectric layer of another semiconductor component, which is referred to below as Example 2.

[0067] The production of Example 2 was carried out in a similar manner to Example 1, but the structural element was subjected to a thermal post-treatment after the electrical contacting. This was carried out at 450° C. in a nitrogen atmosphere at 60 mbar for 40 minutes.

[0068] also, Figure 1a The curve 18 shows a leakage current measurement of the dielectric layer of another semiconductor component, which is referred to below as Example 3. The production of Example 3 was carried out similarly to Example 1, but the component was subjected to a thermal post-treatment after the electrical contacting. This was carried out at 500° C. in a nitrogen atmosphere of 60 mbar for 40 minutes.

[0069] also, Figure 1a The graph 20 shows the leakage current measurement of the dielectric layer of another semiconductor component, which is referred to below as Example 4. The production of Example 4 was carried out similarly to Example 1, but the deposition of the dielectric layer with Pb 1.3 (Zr 0.52 Ti 0.48 )O3 target dielectric layer.

[0070] also, Figure 1a The graph 22 shows the leakage current measurement of the dielectric layer of another semiconductor component, which is referred to below as Example 5. The production of Example 5 is carried out similarly to Example 1, but the deposition of the dielectric layer with Pb 1.3 (Zr 0.52 Ti 0.48 )O3Ni 0.005 The target consists of a dielectric layer.

[0071] Before measuring the leakage current curves, all described examples 1, 2, 3, 4 and 5 were covered with a passivation layer and electrically contacted with an aluminum conductor circuit.

[0072] Four of the five exemplary embodiments were measured up to the respective dielectric breakdown 15, 17, 19 and 24. As can be seen here, depending on the production and composition of the dielectric layer, very different leakage current curves 14, 16, 18, 20 and 22 with different breakdown times 17, 15, 19 and 24 result.

[0073] Figure 1b An example is shown based on Figure 1a The model parameters are extracted from the leakage current curve 16 measured on the embodiment 2. Here again, the time is plotted logarithmically in seconds on the X-axis 32 and the barrier height change Δφ is plotted logarithmically in electron volts on the Y-axis 30. The curve 38 shows the time-dependent curve of the barrier height change Δφ(t) starting from the initial barrier height φ0.

[0074] This curve 38 of the barrier height variation Δφ(t) is obtained by the following formula (see formula 2.2 above):

[0075] Φ(t)=[ln(k)-ln(J TED (t))]]k B T

[0076] The ascertained time profile of the mean effective barrier height φ(t) is then numerically matched to the following formula (see above formula 3.2):

[0077]

[0078] This numerical fit yields different Δφ values ​​for the curve describing Δφ(t): i + / - Therefore, in the case shown, Δφ(t) 38 is given by Δφ a - (t)39 curve, Δφ b - (t)40 curve and Δφ c- The curve of (t)42 together with the curve Σ i Δφ i + 36 described. According to the following formula (see formula 5.1 above)

[0079]

[0080] Then we can find different τ i + / - and δφ i + / - In this case, the barrier height change Δφ for the majority carriers i - 39, 40 and 42, the characteristic time constant τ can be obtained a , τ b and τ c These characteristic time constants are Figure 1b 47a, 47b and 47c are respectively marked in FIG. 4 and represent the time points at which the corresponding barrier height change changes most strongly. i - The maximum barrier of 39 and 40 decreases by δφ i - For example, they are marked with 50 and 51. The barrier height change Δφ for minority carriers i + They are not explicitly shown separately in order to improve the overview. Only the sum curve Σ for the minority carriers is shown i Δφ i + 36 and each time constant τ d , τ e and τ f 49a, 49b and 49c. In this case, the corresponding characteristic time constants are assigned to the defect types a, b, c, d, e and f present in the layer. Accordingly, six different defect types are present in the dielectric layer.

[0081] exist Figure 1b In the case shown above, the dielectric breakdown 47 of the dielectric layer occurs by tunneling majority carriers according to the following formula (see formula 9.2 above):

[0082] φ krit -=φ0-+∑ i Δφ i -(t krit )=φ0-+Δφ krit - Among them, Δφ krit - =∑i Δφ i - (t krit )

[0083] Therefore, Δφ a - (t)39, Δφ b - (t)40 and Δφ c - (t)42 is added to the previously obtained curve, and the barrier height changes Σ according to the curve i Δφ i - 44. Here, if at time t krit 48 The critical barrier height change Δφ for majority carriers to reach the dielectric layer krit - 52, local breakdown of the layer occurs due to the presence of different defect types a, b and c, which accumulate on the boundary layer between the dielectric layer and the electrode.

[0084] Figure 2a The barrier height variation Δφ(t) for the three embodiments 1, 2 and 3 is shown. ± The measured curve has a corresponding characteristic time constant τ at a main operating temperature of 175°C and a main operating voltage of -2.5V. i + / - and the maximum barrier height variation δφ i + / - Here, the time is plotted in logarithmic form in seconds on the X-axis 62 and the critical barrier height change Δφ divided by the corresponding embodiment 1, 2 and 3 is plotted in unitless form on the Y-axis 60. krit - The barrier height changes.

[0085] Here, Δφ(t) for Examples 3, 2, and 1 is shown. - Curves 63, 64, 65 and Δφ(t) of Examples 3, 2 and 1 + The associated curves 66, 67, 68. The electrical failure of the dielectric layer of the exemplary embodiment occurs at the associated points in time 94, 96 and 98, at which a critical barrier height drop is reached.

[0086] The defect structure used in Example 1 consists of defect types a, b, c, d, e and f and their associated time constants τ a 72a, τ b 72b, τ c 72c, τ d 90a, τ e70b and τ f 70c composition. Different defect types cause the maximum barrier height to decrease δφ b - 72c, δφ c - 73c, δφ d + 91a, δφ e + 71b and δφ f + 71c.

[0087] The defect structure used in Example 2 consists of defect types a, b, c, d, e and f and their associated time constants τ a 82a, τ b 82b, τ c 82c, τ d 80a, τ e 80b and τ f 80c composition. Here, different defect types are also assigned the maximum barrier height reduction δφ caused a - 83a, δφ b - 83c, δφ c - 83c, δφ d + 81a, δφ e + 81b and δφ f + 81c.

[0088] The defect structure used in Example 3 consists of defect types a, b, c, d, e and f and their associated time constants τ a 92a, τ b 92b, τ c 92c, τ d 70a, τ e 90b and τ f 90c composition. Different defect types are again assigned the maximum barrier height drop δφ caused by a - 93a, δφ b - 93c, δφ c - 93c, δφ d + 71a, δφ e + 91b and δφ f +91c.

[0089] For different defect types, the true activation energy E can be obtained by mathematically fitting the model described above and the following equation (see Equation 10.1 above): A,0,i and charge N q,i

[0090]

[0091] For defect type a, the true activation energy is 0.92 eV at a charge of 1e. For defect type b, the true activation energy is 0.95 eV at a charge of 3e. For defect type c, the true activation energy is 0.855 eV at a charge of 4e. For defect type d, the true activation energy is <0.8 eV at a charge of le. For defect type e, the true activation energy is 1.04 eV at a charge of 2e. For defect type f, the true activation energy is 1.22 eV at a charge of 2e. Thus, for example, within the dielectric layer, defect type a can be physically associated with hydrogen and / or OH groups and defect type e with oxygen defects and / or lead. Due to the different manufacture of Examples 1, 2 and 3, the maximum barrier heights of defect types a and e decrease by δφ a - and δφ e - Under the exemplary main operating conditions selected here, the following applies to the semiconductor components in Examples 1 and 2: a <τ b and δφ a - <δφ b - Due to the relatively large barrier drop 93a of Example 3 at a relatively early time point 92a, the barrier curve 63 of Example 3 is affected. This results in a failure time point t krit 94 and 96 compared at time point t krit 98, an earlier electrical failure in time. In order to achieve a longer service life of the semiconductor component, the barrier drop that occurs early should be small. For Examples 1 and 2, it is further shown that the applicable a <τ b <τ c and δφ a - <δφ b - <δφ c - .

[0092] Figure 2b shows that the characteristic time constant τ i + / - and the maximum barrier height variation δφ i + / - The change of barrier height Δφ(t) under two different operating conditions ± Here, time is plotted logarithmically in seconds on the X-axis 62 and the change in barrier height Δφ divided by the critical potential is plotted in a unitless manner on the Y-axis 60 . krit - The barrier height changes.

[0093] This results in the curve Δφ(t) for a main operating temperature of 175°C and a main operating voltage of -2.5 V: - 64 (hereinafter referred to as operating condition a) and the curve Δφ(t) for a main operating temperature of 100°C and a main operating voltage of -10V - 110 (hereinafter referred to as operating state b). The associated curve Δφ(t) for operating state a is also shown. + 67 and the curve Δφ(t) for operating state b + 100.

[0094] For operating states a and b, electrical failure of the dielectric layer occurs at time points 96 and 97, respectively. The defect structure for Example 2 in operating state a consists of active defect types a, b, c, d, e and f and their associated time constants τ until electrical failure. a 82a, τ b 82b, τ c 82c, τ d 80a, τ e 80b and τ f 80c and the maximum barrier height drop δφ caused by these defect types a - 83a, δφ b - 83b, δφ c - 83c, δφ d + 81a, δφ e + 81b and δφ f + 81c structure.

[0095] The defect structure for example 2 in operating state b consists of active defect types a, b, d and e and their associated time constants τ until electrical failure. a 170a, τ b170b, τ d 101a and τ e 101b and the maximum barrier height reduction δφ caused by these defect types a - 171a, δφ b - 171b, δφ d + 102b and δφ e + 102b structure.

[0096] It can be seen that the defect structure in the semiconductor structure and the defect effective up to the electrical breakdown position depend on the selected operating conditions. The time shift 106 is a function of the main operating temperature and the term in equation (10.1) The change in the maximum barrier height drop 105 is caused by the change in the main operating voltage and the associated change Δφ(t) ± caused by.

[0097] For Example 2, the operating condition a is: τ a <τ b <τ c and δφ a - <δφ b - <δφ c - and τ d <τ e <τ f and δφ d + <δφ e + <δφ f + In addition, for Example 2, the following applies to operating condition b: a <τ b and δφ a - <δφ b - and τ d <τ e and δφ d + <δφ e + .

[0098] Figure 2c The time constant τ is shown for the case where the main operating temperature is 175°C and the main operating voltage is -2.5V. i + / - and the maximum barrier height variation δφi + / - The barrier height variation Δφ(t) of the two embodiments 2 and 4 ± Here, time is plotted logarithmically in seconds on the X-axis 62 and the critical barrier height change Δφ of Example 2 is plotted in a unitless manner on the Y-axis 60. krit - The barrier height change of Example 4 is normalized so that the maximum barrier height change δφ a - 132a and δφ a - Same as 83a.

[0099] Here, the curve Δφ(t) of Example 2 is shown. - 64 and the curve Δφ(t) of Example 4 - 130. The curve Δφ(t) of Example 2 is also shown. + 67 and the curve Δφ(t) of Example 4 + 120. The electrical failure of the dielectric layer of Example 2 occurs at the point in time 96 when the critical barrier height drop is reached. Example 4 could not be loaded to failure during the test period, and therefore the curve 130 did not reach the value -1.

[0100] Here, the defect structure used in Example 2 consists of defect types a, c, d, e and f and their associated time constants τ a 82a, τ b 82b, τ c 82c, τ d 80a, τ e 80b and τ f 80c and the maximum barrier height drop δφ caused by these defect types a - 83a, δφ b - 83b, δφ c - 83c, δφ d + 81a, δφ e + 81b and δφ f + 81c structure.

[0101] The defect structure used in Example 4 consists of defect types a, c, d and e and their associated time constants τ a 131a, τ c 131c, τ d 121a and τ e121b and the maximum barrier height drop δφ caused by these defect types a - 132a, δφ c - 132c and δφ d + 122a structure.

[0102] For defect type a, the true activation energy is 0.92 eV when the charge is le. For defect type b, the true activation energy is 0.95 eV when the charge is 3e. For defect type c, the true activation energy is 0.855 eV when the charge is 4e. For defect type d, the true activation energy is <0.8 eV when the charge is le. For defect type e, the true activation energy is 1.04 eV when the charge is 2e. For defect type f, the true activation energy is 1.22 eV when the charge is 2e. Due to the reduction in the lead content in the sputtered PZT layer of Example 4, the maximum barrier height of lead-related defect types b, c and f decreases by δφ compared to Example 2. b - ,δφ c - and δφ f + This reduction is indicated by 115, for example, for δφ c - 132b. The maximum barrier height decreases by δφ b - and δφ f + is so small that it is no longer recognizable due to the numerical fit to the model. Since for defect type b τ a <τ b <τ c , it can be deduced that τ b <τ c and δφ b - <<δφ c - Applicable.

[0103] Figure 2d The time constant τ is shown for the case where the main operating temperature is 175°C and the main operating voltage is -2.5V. i + / - and the maximum barrier height variation δφ i + / - The barrier height variation Δφ(t) of the two embodiments 2 and 5 ±Here, the time is plotted logarithmically in seconds on the X-axis 62 and the change Δφ of the critical barrier height of the corresponding embodiment 2 and 5 is plotted on the Y-axis 60 in a unitless manner. krit - The barrier height changes.

[0104] Here, the curve Δφ(t) of Example 2 is shown. - 64 and the curve Δφ(t) of Example 5 - 150. The corresponding curve Δφ(t) of Example 2 is also shown. + 67 and the curve Δφ(t) of Example 5 + 140. The electrical failure of the dielectric layer of Example 2 occurs at time point 96 and in the case of Example 5 at time point 99.

[0105] Here, the defect structure used in Example 2 consists of defect types a, b, c, d, e and f and their associated time constants τ a 82a, τ b 82b, τ c 82c, τ d 80a, τ e 80b and τ f 80c and the maximum barrier height drop δφ caused by these defect types a - 83a, δφ b - 83b, δφ c - 83c, δφ d + 81a, δφ e + 81b and δφ f + 81c structure.

[0106] The defect structure used in Example 5 consists of defect types a, b and d and their associated time constants τ a 148a, τ b 148b and τ d 145a and the maximum barrier height drop δφ caused by these defect types a - 149a, δφ b - 149b and δφ d + 146a structure.

[0107] For defect type a, the true activation energy is 0.92 eV at a charge of le. For defect type b, the true activation energy is 0.95 eV at a charge of 3e. For defect type c, the true activation energy is 0.855 eV at a charge of 4e. For defect type d, the true activation energy is <0.8 eV at a charge of le. For defect type e, the true activation energy is 1.04 eV at a charge of 2e. For defect type f, the true activation energy is 1.22 eV at a charge of 2e. Due to the additional nickel content in the sputtered PZT layer of Example 5, the maximum barrier height decreases by δφ a - and δφ b - may be significantly affected. In addition, the maximum barrier height decreases by δφ e + and δφ f + It may be reduced to such an extent that it is no longer identifiable due to the numerical fit to the model. For Example 5, for the operating conditions 175° C. and −2.5 V, it applies that: τ a <τ b and δφ a - <<δφ b - .

[0108] Figure 2e It is shown that when the main operating temperature is 100°C and the main operating voltage is -10V, the corresponding characteristic time constant τ i + / - and the maximum barrier height variation δφ i + / - The barrier height variation Δφ(t) for both Examples 2 and 5 is ± Here, the time is plotted logarithmically in seconds on the X-axis 155 and the change in barrier height Δφ divided by the critical value of the corresponding embodiment 2 and 5 is plotted unitlessly on the Y-axis 156. krit - The barrier height changes.

[0109] Here, the curve Δφ(t) of Example 2 is shown. - 110 and the curve Δφ(t) of Example 5 - 169. The curve Δφ(t) corresponding to Example 2 is also shown. + 100 and the curve Δφ(t) of Example 5 + 165. The electrical failure of the dielectric layer of Example 2 occurs at time point 96c and the electrical failure of the dielectric layer of Example 5 occurs at time point 96d.

[0110] Here, the defect structure used in Example 2 consists of defect types a, b, d and e and their associated time constants τ a 170a, τ b 170b, τ d 161a and τ e 161b and the maximum barrier height drop δφ caused by these defect types a - 171a, δφ b - 171b, δφ d + 162a and δφ e + 162b structure.

[0111] The defect structure used in Example 5 consists of defect types a and d and their associated time constants τ a 175a and τ d 158a and the maximum barrier height drop δφ caused by these defect types a - 176a and δφ d + 159a structure.

[0112] For defect type a, the actual activation energy is 0.92 eV at a charge of le. For defect type b, the actual activation energy is 0.95 eV at a charge of 3e. For defect type d, the actual activation energy is <0.8 eV at a charge of le. For defect type e, the actual activation energy is 1.04 eV at a charge of 2e. Due to the additional nickel content in the sputtered PZT layer of Example 5, the maximum barrier height decreases by δφ a - 176a may be significantly affected. In addition, the maximum barrier height decreases by δφ e + It may be reduced to such an extent that it is no longer recognizable due to the numerical fit to the model.

[0113] For Example 2, for operating conditions 100°C and -10V, it applies that: τ a <τ b and δφ a - <<δφ b - , and τ d <τ e and δφ d + <δφ d + .

[0114] Figure 3a The semiconductor structure element 200 at a first time point t0 is schematically shown. Here, the semiconductor structure element 200 includes a dielectric layer 230 with a layer thickness 208. For example, the dielectric layer 230 can be a PZT layer. In addition, the semiconductor structure element 200 has a first electrode 202 and a second electrode 201 arranged opposite each other. A boundary layer 203 or 204 is also arranged between the corresponding electrode 201 or 202 and the dielectric layer 230. There are different defect types in the dielectric layer 230, which are exemplarily marked as defect type 212 with a single positive charge 214 and defect types 215 and 217 with a single negative charge 216. The superscripts + and - here respectively mark the number of charge carriers of the corresponding defect type. Due to the necessary charge neutrality in the dielectric layer 230, there are defect pairs or defect accumulations. This means that when defects 215 and 217 with negative charges appear, there are also defects 212 with positive charges in the material. Different defect types 212, 215 and 217 are arranged in local impurities 235 on. Figure 3a At the first time t0 shown above, no voltage and therefore no electric field is applied between the electrodes 201 and 202 .

[0115] Figure 3b The semiconductor device 200 is shown at a second time point t1 after the first time point t0. At this time point t1, a voltage is applied between the first electrode 202 and the second electrode 201, and an electric field 220 is thus generated in the dielectric layer 230. The different defect types 212, 215 and 217 now move along the local defect state 235 depending on the main operating voltage applied between the first electrode 202 and the second electrode 201 and the current main operating temperature. This state of movement of the defect types 212, 215 and 217 is also called jumping. Each defect type moves towards the corresponding electrode at a different speed. The corresponding time is called the characteristic time τ as follows i : The defect type requires the corresponding time to move from the initial position to the corresponding boundary layer assigned to the electrode after the main operating voltage is applied. The local defect states 235 each have the same average effective distance a0 210. The defect type 212 with a positive charge 214 migrates to the electrode with a negative potential (in this case, the first electrode 202) and accumulates in the boundary layer 203 there. Conversely, the defect types 215 and 217 with a negative charge 216 move to the electrode with a positive potential (in this case, the second electrode 201) in order to accumulate in the boundary layer 204 there. Leakage current J TEDThe charge carriers that want to reach from one electrode to the other must overcome the Schottky barriers φ(t), which are affected by the boundary layers 203 and 204. These barriers have an initial barrier height φ0 and undergo a barrier height variation Δφ due to the defect types that accumulate there. i , which in the further time course leads to a maximum barrier height change δΦ i The defect types produce different barrier height changes Δφ i .

[0116] Figure 3c The semiconductor component 200 is shown at a third time t2 after the second time. In this case, most of the different defect types 212, 215 and 217 have accumulated on the boundary layers 202 and 203 of the dielectric layer 230 and caused a barrier height change Δφ there. i At a fourth time point t3 after the third time point, a critical barrier height φ is reached on one of the boundary layers 202 or 203. krit As in Figure 3d As can be seen in FIG. 2 , a local dielectric breakdown 225 of the dielectric layer 230 now occurs. krit Afterwards, a semiconductor component 200 remains which is locally damaged on a limited surface. krit As the load increases, more and more local dielectric breakdowns 225 occur, which eventually lead to complete destruction of the semiconductor structure 200.

Claims

1. A semiconductor structure element (200), the semiconductor structure element comprising at least one dielectric layer (230), and at least one first electrode (202) and a second electrode (201), in, At least a first defect type and a second defect type different from the first defect type exist in the dielectric layer (230), wherein at least two different defect types (212, 215, 217) accumulate on one of the two electrodes (201, 202) within characteristic times τ1 and τ2 according to a main operating voltage applied between the first electrode (202) and the second electrode (201) and a current main operating temperature, and produce maximum barrier height changes δΦ1 and δΦ2 on the electrodes (201, 202), wherein τ1 and δΦ1 are assigned to the first defect type and τ2 and δΦ2 are assigned to the second defect type, Therein, τ1<τ2 and δΦ1<δΦ2 apply.

2. The semiconductor structure (200) according to claim 1, characterized in that At least one further third defect type is present in the dielectric layer (230), wherein the third defect type accumulates on one of the two electrodes (201, 202) within a characteristic time τ3 as a function of the main operating voltage applied between the first electrode (202) and the second electrode (201) and the current main operating temperature and produces a maximum barrier height change δΦ3 on the electrode (201, 202), wherein τ1<τ2<τ3 applies, and wherein the order of the barrier height changes differs from the order δΦ1>δΦ2>δΦ3.

3. The semiconductor structure (200) according to any one of claims 1 or 2, characterized in that The dielectric layer (230) is constructed as a polycrystalline oxide high-k dielectric.

4. The semiconductor structure (200) according to claim 3, characterized in that The dielectric layer (230) is configured as a PZT layer or a KNN layer.

5. The semiconductor structure (200) according to any one of claims 1 or 2, characterized in that The dielectric layer (230) is configured as a sputtered PZT layer.

6. The semiconductor structure (200) according to claim 5, characterized in that The sputtered PZT layer has a PZT deposition temperature below 500°C.

7. The semiconductor structure (200) according to claim 5, characterized in that The sputtered PZT layer has Pb x (Zr 0.52 Ti 0.48 )O3 composition, wherein 1.2≤x≤1.3 is applicable.

8. The semiconductor structure (200) according to claim 5, characterized in that The sputtered PZT layer has a nickel content between 0.1 and 1 atomic percent.

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