Semiconductor device

Abstract

A semiconductor device is provided to suppress the reduction in the dielectric strength of a dielectric film (deterioration in the withstand voltage of the dielectric film). The semiconductor device includes a semiconductor substrate having a first main surface and a second main surface opposed to each other, a dielectric film disposed on a portion of the first main surface, a first electrode layer disposed on a portion of the dielectric film, and a protective layer continuously covering a first outer peripheral end of the dielectric film from an end of the first electrode layer to a first outer peripheral end of the dielectric film. The dielectric film has an electrode layer placement portion on which the first electrode layer is disposed, and a protective layer covering portion covered by the protective layer. The thickness of the first outer peripheral end of the protective layer covering portion of the dielectric film is smaller than the thickness of the electrode layer placement portion of the dielectric film. The protective layer has a first protective layer continuously covering a second outer peripheral end of the first electrode layer and at least a portion of the protective layer covering portion, and a second protective layer disposed on the first protective layer. The first protective layer has a lower relative permittivity than the second protective layer. The second protective layer has higher moisture resistance than the first protective layer.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] Conventionally, the capacitor structure described in Japanese Patent Application Publication No. 2019-33154 (Patent Document 1) is used as a capacitor structure in semiconductor devices. This capacitor structure is disposed on an insulating film of a substrate. The capacitor structure includes a second electrode layer partially disposed on the insulating film, an interlayer insulating film (dielectric film) covering the second electrode layer, a metal film partially disposed on the interlayer insulating film, a first electrode layer disposed on the metal film, and a protective insulating film (protective layer) continuously covering the insulating film from the end of the first electrode layer.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2019-33154

[0004] In recent years, with the increasing opportunities to apply high voltages to semiconductor devices, the requirements for high voltage withstand capability (high insulation breakdown strength) have increased. However, it is not easy to achieve high moisture resistance and high insulation breakdown strength under such high voltages. Summary of the Invention

[0005] Therefore, the purpose of this disclosure is to provide a semiconductor device with high moisture resistance and high insulation breakdown strength.

[0006] The inventors, through dedicated research to solve the aforementioned problems, have obtained the following insights. First, they confirmed that to achieve higher moisture resistance, a first electrode layer can be formed at the center of a dielectric film disposed on a portion of a semiconductor substrate, and the thickness of the dielectric film located outside the first electrode layer can be reduced. However, it is known that if the thickness of the dielectric film located outside the first electrode layer is reduced, for example, the withstand voltage between the second outer peripheral end of the first electrode layer and the first main surface of the semiconductor substrate decreases. Therefore, further research has clarified that by comprising a first protective layer with a relatively low permittivity (thus exhibiting higher insulation breakdown strength) and a second protective layer with higher moisture resistance than the first protective layer, both high moisture resistance and high insulation breakdown strength can be achieved. Based on the above insights obtained independently by the inventors, this disclosure includes the following aspects.

[0007] To address the aforementioned issues, a semiconductor device according to one aspect of this disclosure includes:

[0008] A semiconductor substrate having a first main surface and a second main surface that are opposite to each other;

[0009] A dielectric film is disposed on a portion of the aforementioned first main surface;

[0010] A first electrode layer is disposed on a portion of the aforementioned dielectric film; and

[0011] A protective layer continuously covers the dielectric film from the end of the first electrode layer to the first outer peripheral end.

[0012] The dielectric film described above has an electrode layer configuration portion on which the first electrode layer is disposed, and a protective layer covering portion covered by the protective layer.

[0013] The thickness of the first outer peripheral end of the protective layer covering portion of the dielectric film is smaller than the thickness of the electrode layer arrangement portion of the dielectric film.

[0014] The aforementioned protective layer has a first protective layer that continuously covers the second outer peripheral end of the first protective layer and at least a portion of the protective layer coverage, and a second protective layer disposed on the first protective layer.

[0015] The first protective layer has a lower relative permittivity than the second protective layer.

[0016] The second protective layer has higher moisture resistance than the first protective layer.

[0017] According to the above method, the protective layer comprises a first protective layer having a lower relative permittivity than the second protective layer, and a second protective layer disposed on the first protective layer and having higher moisture resistance than the first protective layer. Thus, the protective layer has multiple layers with different functions (higher dielectric strength and moisture resistance). Therefore, the semiconductor device possesses both moisture resistance and voltage withstand capability. More specifically, the thickness of the first outer peripheral end of the protective layer covering portion of the dielectric film is smaller than the thickness of the electrode layer placement portion of the dielectric film. This allows the dielectric film to have at least a thin film region with a relatively thin protective layer covering portion at the first outer peripheral end, thereby reducing the step difference of the step portion of the second protective layer disposed at the end (protective layer covering portion) of the dielectric film. Reducing the step difference of the step portion decreases the deformation of the second protective layer, thereby reducing the internal stress generated within the second protective layer around the end of the dielectric film. As a result, the second protective layer around the end of the dielectric film can suppress the formation of cracks. Therefore, the above method can prevent moisture from penetrating the dielectric film through cracks, suppressing the reduction of the dielectric film's voltage withstand capability (reduction of dielectric strength). By making the protective layer covering portion of the dielectric film a thin film region, as described above, the decrease in withstand voltage near the end of the dielectric film caused by cracks can be suppressed. On the other hand, since the thickness of the dielectric film is reduced in the thin film region, the withstand voltage between the second outer peripheral end of the first electrode layer and the first main surface of the semiconductor substrate decreases. In contrast, by providing a first protective layer with a lower relative permittivity than the second protective layer and covering the second outer peripheral end of the first electrode layer, the decrease in withstand voltage between the second outer peripheral end of the first electrode layer and the first main surface of the semiconductor substrate can be suppressed. Furthermore, a protective layer with a lower relative permittivity can have a higher insulation breakdown strength. Since the first protective layer has a lower relative permittivity (higher insulation breakdown strength), insulation breakdown between the end of the first electrode layer and the first main surface of the semiconductor substrate can be effectively suppressed, and insulation breakdown of the dielectric film can be suppressed. Based on the above, the semiconductor device of the above method has both moisture resistance and voltage withstand capability.

[0018] In another aspect of semiconductor devices,

[0019] The first protective layer extends continuously from the end of the first electrode layer to at least a portion of the protective layer coverage area.

[0020] According to the above method, the first protective layer continuously covers at least a portion of the dielectric film from the end of the first electrode layer. In other words, the first protective layer has a lower relative permittivity than the second protective layer, and the area covered by the first protective layer of the first electrode layer is increased. Therefore, it is possible to more effectively suppress the insulation breakdown of the dielectric film between the end of the first electrode layer and the first main surface of the semiconductor substrate.

[0021] In another aspect of semiconductor devices,

[0022] The first protective layer extends continuously from the second outer peripheral end of the first electrode layer to the first outer peripheral end of the protective layer covering portion.

[0023] According to the above method, the first protective layer continuously covers the first electrode layer from the second outer peripheral end to the first outer peripheral end of the protective layer coverage portion, thereby increasing the area of ​​the first protective layer covering the first electrode layer. Therefore, it is possible to more effectively suppress the insulation breakdown of the dielectric film between the end of the first electrode layer and the first main surface of the semiconductor substrate.

[0024] In another embodiment of the semiconductor device, the semiconductor device further includes a first metal film disposed between the first protective layer and the second protective layer and covering the first protective layer.

[0025] According to the above method, the semiconductor device further includes a first metal film. The first metal film is disposed between the first protective layer and the second protective layer, and covers the first protective layer. The first metal film is made of metal, so it is not easily permeable by moisture. Therefore, even if a crack occurs in the second protective layer, moisture is prevented from seeping into the dielectric film through the crack. Therefore, the above method can more effectively suppress the insulation breakdown of the dielectric film between the end of the first electrode layer and the first main surface of the semiconductor substrate. Furthermore, the first metal film is disposed between the first protective layer and the second protective layer. Therefore, the surface distance of the protective layer is increased, and the generation of surface discharge on the surface of the protective layer can be more effectively suppressed.

[0026] In another embodiment of the semiconductor device, the first protective layer is covered by the second protective layer and the first metal film.

[0027] According to the above method, the first protective layer is covered by the second protective layer and the first metal film. Therefore, the entire area outside the first protective layer is protected by the second protective layer and the first metal film, which have relatively high moisture resistance. Thus, the above method can prevent external moisture from penetrating into the dielectric film through the first protective layer, and can more effectively suppress the insulation damage of the dielectric film.

[0028] In another aspect of semiconductor devices,

[0029] The aforementioned first protective layer has a stepped portion including one or more corners.

[0030] The first metal film described above covers at least one of the aforementioned corners.

[0031] According to the above method, the first protective layer has a stepped portion including one or more corners. Therefore, internal stress is easily generated in the second protective layer around the corners. As a result, cracks may occur in the second protective layer. However, in the above method, the first metal film has relatively high moisture resistance and covers at least one corner of the first protective layer, thus preventing moisture from penetrating into the dielectric film through cracks. Therefore, the above method suppresses the insulation damage of the dielectric film.

[0032] In another aspect of semiconductor devices,

[0033] The first metal film is configured to span the electrode layer configuration portion and the protective layer coverage portion.

[0034] According to the above method, by configuring the first metal film to span the electrode layer configuration portion and the protective layer coverage portion, it is possible to effectively prevent moisture from penetrating the first protective layer.

[0035] In another aspect of semiconductor devices,

[0036] The first metal film is disposed inside the boundary between the electrode layer configuration portion and the protective layer coverage portion.

[0037] According to the above method, by covering at least one corner of the first protective layer with the first metal film and positioning it inside the boundary between the electrode layer configuration portion and the protective layer coverage portion, it is possible to effectively prevent moisture intrusion into the first protective layer and effectively prevent the generation of surface discharge on the surface of the protective layer.

[0038] In another aspect of semiconductor devices,

[0039] The first electrode layer has the aforementioned end portion and central portion covered by the aforementioned first protective layer.

[0040] The first metal film is electrically connected to the first electrode layer and is exposed at the central portion of the first electrode layer.

[0041] According to the above method, the first metal film is further disposed on the central portion of the first electrode layer. Therefore, the first metal film provides moisture-resistant protection to the first protective layer, suppressing insulation damage to the dielectric film. Furthermore, the first metal film is disposed exposed on the central portion of the first electrode layer. Therefore, in addition to its function of suppressing insulation damage to the dielectric film, the first metal film also functions as an external connection electrode.

[0042] In addition, according to one method of semiconductor devices,

[0043] The third outer peripheral end of the first protective layer is covered by the second protective layer.

[0044] The first metal film continuously covers the first protective layer except for the third outer peripheral end.

[0045] The thickness of the first protective layer is the same as or greater than the thickness of the electrode layer arrangement portion of the dielectric film.

[0046] According to the above method, the thickness of the first protective layer is the same as or greater than the thickness of the electrode layer of the dielectric film. In this case, the first protective layer functions as a stress-relieving layer, suppressing the peeling and cracking of the second protective layer caused by stress. Therefore, this method further prevents moisture from seeping into the dielectric film through cracks, further suppressing the reduction in the dielectric strength of the dielectric film. Furthermore, a first metal film is disposed between the first and second protective layers and continuously covers the first protective layer except for the second outer peripheral end. The first protective layer is double-covered by the first metal film and the second protective layer, which have relatively high moisture resistance. This prevents moisture from seeping into the first protective layer and further into the protective layer covering portion of the dielectric film. In this method, the reduction in the dielectric strength of the dielectric film can be further suppressed. Moreover, since the first metal film is disposed between the first and second protective layers, the surface distance of the protective layer is increased, suppressing surface discharge on the protective layer surface.

[0047] In addition, according to one method of semiconductor devices,

[0048] Semiconductor devices also have a second metal film.

[0049] The second metal film covers the third outer peripheral end of the first protective layer and is separated from the first metal film through an opening.

[0050] According to the above method, a second metal film is also included, which covers the third outer peripheral end of the first protective layer and is separated from the first metal film through an opening. In other words, the first and second metal films continuously cover the first protective layer except for the opening. Furthermore, the second protective layer covers the first and second metal films and the first protective layer. Thus, the first protective layer is doubly covered by the first and second metal films, which have relatively high moisture resistance, and the second protective layer. This prevents moisture from penetrating the first protective layer and further penetrating the protective layer covering portion of the dielectric film. The above method can further suppress the insulation breakdown of the dielectric film. In addition, compared with the case where the first metal film continuously covers the portion of the first protective layer except for the third outer peripheral end, the above method can, for example, effectively prevent the peeling of the third outer peripheral end of the first protective layer.

[0051] In addition, according to one method of semiconductor devices,

[0052] The semiconductor device further includes a diffusion prevention film disposed between the first electrode layer and the first metal film.

[0053] According to the above method, a diffusion prevention film is disposed between the first electrode layer and the first metal film. In other words, the first electrode layer and the first metal film do not contact each other, thus preventing the components constituting the first electrode layer from diffusing into the first metal film. As a result, the semiconductor device can operate stably.

[0054] In addition, according to one method of semiconductor devices,

[0055] The first electrode layer mentioned above is made of polycrystalline silicon.

[0056] The aforementioned diffusion-preventing film is composed of an Al-Si alloy.

[0057] The first metal film mentioned above is composed of Al.

[0058] In this manner, diffusion of polycrystalline silicon (more specifically, Si in polycrystalline silicon) constituting the first electrode layer into Al constituting the first metal film is prevented. As a result, the semiconductor device can operate stably.

[0059] In another aspect of semiconductor devices,

[0060] The resistivity of the aforementioned semiconductor substrate is between 0.001 Ωcm and 100 Ωcm.

[0061] According to the above method, it is possible to fabricate a CR element that functions as a resistor on a semiconductor substrate.

[0062] In another aspect of semiconductor devices,

[0063] The first protective layer mentioned above is an oxide.

[0064] The second protective layer mentioned above is a nitride.

[0065] According to the above method, the first protective layer is an oxide, and the second protective layer is a nitride. Therefore, the first protective layer has relatively high insulation breaking strength, and the second protective layer has relatively high moisture resistance. Thus, the above method combines excellent insulation breaking strength and excellent moisture resistance.

[0066] In another aspect of semiconductor devices,

[0067] The aforementioned first protective layer is composed of oxides, the main component of the semiconductor substrate.

[0068] The aforementioned second protective layer is composed of nitrides, the main component of the semiconductor substrate.

[0069] According to the above method, the first and second protective layers are respectively composed of oxides and nitrides, which are the main components of the semiconductor substrate. Therefore, the adhesion between the first and second protective layers and the first main surface of the semiconductor substrate is improved.

[0070] In another aspect of semiconductor devices,

[0071] The semiconductor substrate has a channel on the first main surface of the electrode layer configuration portion where the dielectric film is disposed.

[0072] The electrode layer of the dielectric film is continuously disposed on the first main surface to form a recess covering the inner surface of the channel.

[0073] The first electrode layer described above has an entry portion that enters the recess described above.

[0074] Semiconductor devices have a channel structure, so the area of ​​the interface between the dielectric film and the first electrode layer is increased compared to semiconductor devices without a channel structure. As a result, the capacitance of the semiconductor device can be increased.

[0075] According to one aspect of this disclosure, a semiconductor device with high moisture resistance and high insulation breakdown strength can be provided. Attached Figure Description

[0076] Figure 1 This is a cross-sectional view showing a first embodiment of a semiconductor device.

[0077] Figure 2 yes Figure 1 Enlarged view of part A.

[0078] Figure 3A This is an explanatory diagram illustrating the manufacturing method of a semiconductor device.

[0079] Figure 3B This is an explanatory diagram illustrating the manufacturing method of a semiconductor device.

[0080] Figure 3C This is an explanatory diagram illustrating the manufacturing method of a semiconductor device.

[0081] Figure 3D This is an explanatory diagram illustrating the manufacturing method of a semiconductor device.

[0082] Figure 3E This is an explanatory diagram illustrating the manufacturing method of a semiconductor device.

[0083] Figure 3F This is an explanatory diagram illustrating the manufacturing method of a semiconductor device.

[0084] Figure 4 This is a partially enlarged cross-sectional view showing a second embodiment of the semiconductor device.

[0085] Figure 5 This is a partially enlarged cross-sectional view showing a third embodiment of the semiconductor device.

[0086] Figure 6 This is a partially enlarged cross-sectional view showing a fourth embodiment of the semiconductor device.

[0087] Figure 7 This is a partially enlarged cross-sectional view showing the fifth embodiment of the semiconductor device.

[0088] Figure 8 This is a partially enlarged cross-sectional view showing the sixth embodiment of the semiconductor device.

[0089] Figure 9 This is a partially enlarged cross-sectional view showing the seventh embodiment of the semiconductor device.

[0090] Figure 10 This is a partially enlarged cross-sectional view showing the eighth embodiment of the semiconductor device.

[0091] Figure 11 This is a cross-sectional view showing the ninth embodiment of the semiconductor device.

[0092] Figure 12 yes Figure 11 Enlarged view of part B.

[0093] Figure 13A This is an explanatory diagram illustrating the manufacturing method of a semiconductor device.

[0094] Figure 13B This is an explanatory diagram illustrating the manufacturing method of a semiconductor device.

[0095] Figure 13C This is an explanatory diagram illustrating the manufacturing method of a semiconductor device.

[0096] Figure 13D This is an explanatory diagram illustrating the manufacturing method of a semiconductor device.

[0097] Figure 13E This is an explanatory diagram illustrating the manufacturing method of a semiconductor device.

[0098] Figure 13F This is an explanatory diagram illustrating the manufacturing method of a semiconductor device.

[0099] Figure 13G This is an explanatory diagram illustrating the manufacturing method of a semiconductor device. Detailed Implementation

[0100] Hereinafter, a semiconductor device as one embodiment of the present disclosure will be described in detail with reference to the illustrated embodiments. Furthermore, the accompanying drawings contain partially schematic diagrams and do not necessarily reflect actual dimensions or ratios. Additionally, the dimensions (more specifically, thickness, length, and width, etc.) of the constituent elements within the semiconductor device are determined based on SEM images obtained by a scanning electron microscope.

[0101] <First Implementation>

[0102] [constitute]

[0103] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present disclosure. Figure 2 yes Figure 1 An enlarged view of part A. (See image below.) Figure 1 as well as Figure 2 As shown, the semiconductor device 1 includes a semiconductor substrate 10 having a first main surface 11 and a second main surface 12 facing each other, a dielectric film 20 disposed on a portion of the first main surface 11, a first electrode layer 30 disposed on a portion of the dielectric film 20 (opposite to the first main surface 11), and a protective layer 90 continuously covering the first electrode layer 30 from its end 32 to a first outer peripheral end 26a of the dielectric film 20. The dielectric film 20 has an electrode layer placement portion 21 on which the first electrode layer 30 is disposed, and a protective layer covering portion 22 covered by the protective layer 90.

[0104] Furthermore, in the figure, the direction parallel to the thickness of semiconductor device 1 is designated as the Z direction, the positive Z direction is designated as the upper side, and the negative Z direction is designated as the lower side. On a plane orthogonal to the Z direction of semiconductor device 1, the direction parallel to the plane of the paper on which the figure is shown is designated as the X direction, and the direction orthogonal to the plane of the paper on which the figure is shown is designated as the Y direction. The X direction, Y direction, and Z direction are orthogonal to each other.

[0105] In this specification, the first outer peripheral end 26a of the protective layer cover 22 refers to the end of the outer periphery of the protective layer cover 22 when viewed from the Z direction. Furthermore, the second outer peripheral end 33 of the first electrode layer 30, described later, refers to the end of the outer periphery of the first electrode layer 30 when viewed from the Z direction.

[0106] The protective layer 90 has a first protective layer 50 covering at least a portion of the second outer peripheral end 33 of the first electrode layer 30 and the protective layer cover portion 22, and a second protective layer 70 disposed on the first protective layer 50. The first protective layer 50 has a lower relative permittivity than the second protective layer 70. Generally, a protective layer with a lower relative permittivity has a higher dielectric strength. The second protective layer 70 has higher moisture resistance than the first protective layer 50. In other words, the protective layer 90 has a first protective layer 50 with higher dielectric strength (voltage withstand capability, electrical insulation) and a second protective layer 70 with higher moisture resistance. Thus, the protective layer 90 has multiple layers with different functions (dielectric strength and moisture resistance). Therefore, the protective layer 90 has functions separately for each layer, so the protective layer 90 has both dielectric strength and moisture resistance even at high voltages. On the other hand, unlike the present invention, when the protective layer is composed of a single layer, it is difficult for the protective layer to adequately satisfy both dielectric strength and moisture resistance at high voltages. When the protective layer is a single layer made of a single material, there may be a trade-off between insulation breaking strength and moisture resistance. This is because, even if a material has excellent insulation breaking strength and moisture resistance, it may not be able to fully satisfy both properties.

[0107] Furthermore, the thickness of the first outer peripheral end 26a of the protective layer covering portion 22 of the dielectric film 20 is smaller than the thickness of the electrode layer placement portion 21 of the dielectric film 20. In other words, the protective layer covering portion 22 of the dielectric film 20 is understood to be a thinner thin film region at least at the first outer peripheral end 26a compared to the electrode layer placement portion 21. Here, the surface shape of the protective layer 90 stacked thereon can be determined based on the surface shape of the dielectric film 20 disposed below the protective layer 90. Therefore, by making the protective layer covering portion 22 of the dielectric film 20 a thin film region, compared to the case where the thickness of the protective layer covering portion is the same as the thickness of the electrode layer placement portion, the step difference (more specifically, the length Lb of the second side surface 74b described later) of the step portion 71 of the second protective layer 70 corresponding to the first outer peripheral end 26a of the dielectric film 20 is reduced. As a result, crack formation can be suppressed near the corner of the step portion 71 of the second protective layer 70 corresponding to the first outer peripheral end 26a of the dielectric film 20 (more specifically, the second corner portion 75b described later).

[0108] More specifically, the thickness Tb of the first outer peripheral end 26a of the protective layer cover portion 22 of the dielectric film 20 is ΔT smaller (=Ta-Tb) than the thickness Ta of the electrode layer arrangement portion 21 of the dielectric film 20 (which can be understood as the thickness of the first outer peripheral end 26a of the protective layer cover portion 22 when the protective layer cover portion 22 is not a thin film region, and more specifically, the thickness of the protective layer cover portion 22 of the dielectric film 20 is the same as the thickness of the electrode layer arrangement portion 21). In other words, the protective layer cover portion 22 has an upper surface 24 that is at least ΔT smaller than that of the first outer peripheral end 26a compared to the case where it is not a thin film region.

[0109] The surface shape of the second protective layer 70 can be determined by the surface shape of the protective layer cover portion 22 of the dielectric film 20 below the second protective layer 70, so it corresponds to and is approximately the same as the surface shape of the protective layer cover portion 22 of the dielectric film 20. Therefore, the second upper surface 73b of the second protective layer 70 is at least ΔT lower at the first outer peripheral end 26a compared to the case where the protective layer cover portion 22 of the dielectric film 20 is not a thin film region.

[0110] In other words, the length Lb of the second side surface 74b of the second protective layer 70 corresponds to the aforementioned Tb, and the length La of the second side surface 74b when the protective layer covering portion 22 of the dielectric film 20 is not a thin film region corresponds to the aforementioned Ta. Therefore, Lb is ΔT shorter than La. (Furthermore, in...) Figure 2 In the diagram, the thickness of La is shown to be the same as that of the first electrode layer 30; in other words, the thickness of the electrode layer arrangement portion 21 is shown to be the same as that of the first electrode layer 30 (but this embodiment is not limited to this). It can be understood that the second step difference of the second side surface 74b between the second upper surface 73b and the third upper surface 73c, which descends one step from the second upper surface 73b, is smaller than in the case where the protective layer covering portion 22 of the dielectric film 20 is not entirely a thin film region. As a result, the proportion of the second step difference in the step portion 71 of the second protective layer 70 is reduced. Due to the reduction in the proportion of the second step difference on the step portion 71, the internal stress generated within the second protective layer 70 around the second corner 75b corresponding to the corner 27 of the protective layer covering portion 22 is reduced.

[0111] Therefore, by shortening the length Lb of the second side surface 74b in the second protective layer 70 surrounding the second corner 75b, which is formed by the second upper surface 73b and the second side surface 74b of the second protective layer 70, the internal stress generated within the second protective layer 70 around the second corner 75b can be reduced. This allows the second protective layer 70 around the second corner 75b to suppress crack formation. Furthermore, the second protective layer 70 around the corner 27 (corresponding to the second corner 75b) can also suppress crack formation.

[0112] In the second protective layer 70, cracks arise at the step portion 71, and more specifically, near corners where stress tends to concentrate (first corner 75a, second corner 75b, and third corner 75c in the illustration), representing a tendency to originate from corners. Among these cracks in the second protective layer 70, moisture (more specifically, atmospheric moisture) can easily penetrate the dielectric film 20 via cracks arising near the corner (second corner 75b in the illustration) corresponding to the first outer peripheral end 26a of the dielectric film 20. In other words, if the generation of cracks near the corner (second corner 75b) of the step portion 71 of the second protective layer 70 corresponding to the first outer peripheral end 26a of the dielectric film 20 can be suppressed, the penetration of moisture into the dielectric film 20 can be effectively prevented, and thus, the breakdown voltage of the dielectric film 20 can be effectively suppressed.

[0113] According to the semiconductor device 1 of this embodiment, as described above, crack formation can be suppressed near the corner (second corner 75b) of the step portion 71 of the second protective layer 70 corresponding to the first outer peripheral end 26a of the dielectric film 20. Therefore, the semiconductor device 1 can prevent moisture (more specifically, atmospheric moisture) from penetrating into the dielectric film 20 through cracks in the second protective layer 70. Thus, in this embodiment, the reduction in the insulating strength of the dielectric film 20 (deterioration of the dielectric film's withstand voltage) is suppressed.

[0114] Furthermore, the first protective layer 50 has a lower relative permittivity than the second protective layer 70, and consequently, a higher insulation breakdown strength than the second protective layer 70, and continuously covers at least a portion of the second outer peripheral end 33 of the first electrode layer 30 and the protective layer cover portion 22. Therefore, insulation breakdown between the second outer peripheral end 33 of the first electrode layer 30 and the first main surface 11 of the semiconductor substrate 10 can be suppressed, and the decrease in the insulation breakdown strength of the dielectric film 20 can be suppressed.

[0115] (Semiconductor devices)

[0116] As described above, the semiconductor device 1 can suppress the decrease in the insulation strength of the dielectric film 20, so it can operate even when a high voltage of 100V or more (more specifically, a higher voltage of 600V or more) is applied. In other words, the semiconductor device 1 has the voltage withstand capability to withstand rated voltages of 100V or more, and even rated voltages of 600V or more.

[0117] Semiconductor device 1 is, for example, a capacitor. Semiconductor device 1 is used, for example, as a decoupling capacitor (bypass capacitor) in high-frequency digital circuits, in electronic devices such as personal computers, DVD players, digital cameras, TVs, mobile phones, automotive electronics, medical, industrial, and communication equipment. However, the application of semiconductor device 1 is not limited to this; for example, it can also be used in filter circuits, rectifier smoothing circuits, etc.

[0118] The semiconductor device 1 may also include a second electrode layer 40 disposed on the second main surface 12 of the semiconductor substrate 10. In the illustrated embodiment, the first electrode layer 30 and the second electrode layer 40, which function as external connection electrodes, are arranged to face each other via the semiconductor substrate 10. Furthermore, the semiconductor device 1 may also include external connection electrodes electrically connected to the first electrode layer 30 and the second electrode layer 40, respectively. In the semiconductor device 1, the first electrode layer 30 and the second electrode layer 40 (or, if present, external connection electrodes) can be electrically connected to wiring on a circuit board (not shown) via wires or solder bumps.

[0119] However, the second electrode layer 40 can also be disposed between the semiconductor substrate 10 and the dielectric film 20. In this case, the first electrode layer 30, which functions as an external connection electrode, and the external connection electrode electrically connected to the second electrode layer 40 can also be configured to be separated from each other on the same XY plane.

[0120] (Semiconductor substrate)

[0121] The semiconductor substrate 10 has a first main surface 11 and a second main surface 12 that are opposite to each other. For example... Figure 1 As shown, the cross-sectional shape of the semiconductor substrate 10 is approximately rectangular.

[0122] The semiconductor substrate 10 can be made of any material, such as silicon (Si), SiC, or GaN. The semiconductor substrate 10 can be doped with impurities (dopants) to adjust conductivity, etc. The dopant (donor) that supplies electrons is, for example, a group 15 element (more specifically, phosphorus, etc.). The dopant (acceptor) that supplies holes is a group 13 element (more specifically, boron, etc.). The semiconductor substrate 10 can also be an n-type semiconductor substrate or a p-type semiconductor substrate. The resistivity of the semiconductor substrate 10 is, for example, 0.001 Ωcm to 100 Ωcm. If the resistivity of the semiconductor substrate 10 is within the above range, then by means of the semiconductor device 1, a CR element (capacitor-resistor composite element) that functions as a resistor can be fabricated using the semiconductor substrate 10.

[0123] The thickness of the semiconductor substrate 10 is, for example, 100 μm to 700 μm.

[0124] Furthermore, in this specification, thickness refers to the length in the Z direction.

[0125] (Dielectric film)

[0126] The dielectric film 20 is disposed on a portion of the first main surface 11. The dielectric film 20 has an electrode layer placement portion 21 disposed on the first electrode layer 30 and a protective layer covering portion 22 covered by the protective layer 90 (the second protective layer 70 and the first protective layer 50).

[0127] The electrode layer arrangement section 21 of the dielectric film 20 mainly adjusts the capacitance. The protective layer covering section 22 of the dielectric film 20 mainly ensures the electrical insulation between the semiconductor substrate 10 and the first electrode layer 30.

[0128] The dielectric film 20 is made of, for example, a Si-based material (more specifically, silicon oxide (SiO2)). The dielectric film 20 is preferably made of silicon oxide. If the dielectric film 20 is made of silicon oxide, the capacitance of the semiconductor device 1 can be increased.

[0129] The thickness Tb of the first outer peripheral end 26a of the protective layer covering portion 22 of the dielectric film 20 is smaller than the thickness Ta of the electrode layer arrangement portion 21 of the dielectric film 20. The thickness Ta of the electrode layer arrangement portion 21 of the dielectric film 20 is, for example, 0.1 μm to 3 μm.

[0130] like Figure 1 as well as Figure 2 As shown, the cross-sectional shape of the protective layer covering portion 22 of the dielectric film 20 can be, for example, approximately rectangular. In other words, in Figure 1 as well as Figure 2 In the configuration shown, the dielectric film 20 has a thin film region throughout the protective layer cover portion 22. However, in this invention, as long as the thickness of the first outer peripheral end 26a of the protective layer cover portion 22 is smaller than the thickness of the electrode layer arrangement portion 21, the protective layer cover portion 22 can also have a cross-sectional shape that gradually (e.g., continuously or in a stepped manner) thins from the electrode layer arrangement portion 21 side toward the first outer peripheral end 26a. More specifically, the minimum thickness of the electrode layer arrangement portion 21 is greater than or equal to the maximum thickness of the protective layer cover portion 22. For example, the thickness of the first outer peripheral end 26a of the protective layer cover portion 22 can actually be 0. As will be described later in the manufacturing method of the semiconductor device 1, the protective layer cover portion 22 (thin film region) of the dielectric film 20 can be formed, for example, by overetching. If the upper surface 24 of the protective layer cover portion 22 of the dielectric film 20 is formed by overetching, it becomes rougher compared to the case formed by methods other than overetching. Therefore, the contact area between the upper surface 24 of the protective layer covering portion 22 of the dielectric film 20 and the protective layer 90 is increased, and the adhesion between them is improved.

[0131] The width (length of the upper surface 24) of the protective layer cover portion 22 of the dielectric film 20 is, for example, 30 μm or less. If the length of the protective layer cover portion 22 of the dielectric film 20 is 30 μm or less, the insulation between the end face (second outer peripheral end 33) of the first electrode layer 30 and the first main surface 11 is improved. The width of the protective layer cover portion 22 is greater than the thickness of the protective layer cover portion 22.

[0132] (First electrode layer)

[0133] The first electrode layer 30 and the second electrode layer 40 form an electric field. The first electrode layer 30 is disposed on the electrode layer placement portion 21, which is part of the dielectric film 20. The first electrode layer 30 is positioned opposite the second electrode layer 40, separated by the dielectric film 20 and the semiconductor substrate 10. The first electrode layer 30 has an end portion 32 covered by a protective layer 90 and a central portion 31. The central portion 31 is exposed and is not covered by the protective layer 90, so it also functions as an external connection electrode. For example, the first electrode layer 30 can be electrically connected to the circuit board via wires or solder bumps.

[0134] The first electrode layer 30 is made of, for example, metals and other conductive materials (more specifically, conductive resins and polycrystalline silicon). Metals include, for example, Mo (molybdenum), Al (aluminum), Au (gold), W (tungsten), Pt (platinum), and Ti (titanium), and alloys of these metals. The first electrode layer 30 can have multiple layers composed of these metals. Furthermore, from the viewpoint of improving conductivity and moisture resistance, the material of the first electrode layer 30 is preferably metal and polycrystalline silicon, more preferably Al and polycrystalline silicon. That is, the first electrode layer 30 is preferably made of polycrystalline silicon or Al. Improving the moisture resistance of the first electrode layer 30, for example, means preventing moisture from penetrating the dielectric film 20 through the first electrode layer 30 made of polycrystalline silicon or Al, thereby suppressing the decrease in insulation strength.

[0135] (Second electrode layer)

[0136] The second electrode layer 40 can be disposed on the second main surface 12 of the semiconductor substrate 10. Since its lower surface is exposed, the second electrode layer 40 also functions as an external connection electrode. For example, the second electrode layer 40 can be electrically connected to the circuit board via wires or solder bumps. The material of the second electrode layer 40 is, for example, metal and other conductive materials (more specifically, conductive resin and polycrystalline silicon). Metals include, for example, Mo (molybdenum), Al (aluminum), Au (gold), W (tungsten), Pt (platinum), Ni (nickel), and Ti (titanium), and alloys of these metals. The second electrode layer 40 can also be a multilayer metal film. The multilayer metal film can have multiple layers composed of these metals. For example, a second electrode layer composed of a Ti layer, a Ni layer, and an Au layer. Furthermore, the second electrode layer 40 can also be disposed between the semiconductor substrate 10 and the dielectric film 20.

[0137] (protective layer)

[0138] The protective layer 90 continuously covers the first electrode layer 30 from its end 32 to the first outer peripheral end 26a of the dielectric film 20. In other words, the protective layer 90 continuously and uninterruptedly covers the end 32 of the first electrode layer 30, the protective layer cover portion 22 of the dielectric film 20, and a portion of the first main surface 11 of the semiconductor substrate 10, from the end 32 of the first electrode layer 30 to the first outer peripheral end 26a of the dielectric film 20. The protective layer 90 has a first protective layer 50 and a second protective layer 70 disposed on the first protective layer 50.

[0139] (First protective layer)

[0140] The first protective layer 50 continuously and uninterruptedly covers the second outer peripheral end 33 of the first electrode layer 30, the fourth outer peripheral end 26b of the dielectric film 20, and a portion of the upper surface 24 of the protective layer cover portion 22 of the dielectric film 20. In other words, the first protective layer 50 continuously covers at least a portion of the second outer peripheral end 33 of the first electrode layer 30 and the protective layer cover portion 22 of the dielectric film 20. Thus, by providing a first protective layer 50 with high insulation breakdown strength in the space between the second outer peripheral end 33 of the first electrode layer 30 and the upper surface 24 of the protective layer cover portion 22 of the dielectric film 20, short-circuit discharges such as short circuits between the second outer peripheral end 33 of the first electrode layer 30 and the first main surface 11 of the semiconductor substrate 10 can be prevented. Therefore, in this embodiment, the insulation breakdown strength of the semiconductor device 1 is improved.

[0141] The thickness of the first protective layer 50 is, for example, 0.1 μm to 3 μm. If the thickness of the first protective layer 50 is 0.1 μm to 3 μm, the generation of discharge between the first main surface 11 of the semiconductor substrate 10 and the first electrode layer 30 can be further suppressed, thereby improving the insulation breakdown strength of the semiconductor device 1. The thickness of the first protective layer 50 can be the same as or greater than the thickness of the electrode layer arrangement portion 21 of the dielectric film 20.

[0142] The first protective layer 50 has a lower relative permittivity than the second protective layer 70, and preferably has the same or lower relative permittivity as the dielectric film 20. The relative permittivity can be measured according to JIS C2138. The lower the relative permittivity, the higher the insulation breakdown strength. The material of such a first protective layer 50 is, for example, a material with a low relative permittivity. Among these materials, the material of the first protective layer 50 is also preferably an oxide, which is the oxide of the main component of the semiconductor substrate 10 (more specifically, silicon oxide (SiO2)). In other words, the first protective layer 50 is preferably made of a material with a low relative permittivity, more preferably of an oxide, and even more preferably of an oxide of the main component of the semiconductor substrate 10 (more specifically, silicon oxide (SiO2)). If the first protective layer 50 is made of an oxide, the insulation breakdown strength of the semiconductor device 1 is improved.

[0143] (Second protective layer)

[0144] The second protective layer 70 continuously and uninterruptedly covers the end 32 of the first electrode layer 30, the upper surface 53 and side surface 54 of the first protective layer 50, the upper surface 24 and first outer peripheral end 26a of the protective layer cover portion 22 of the dielectric film 20, and a portion of the first main surface 11 of the semiconductor substrate 10. In other words, the second protective layer 70 continuously covers from the end 32 of the first electrode layer 30 to a portion of the first main surface 11 of the semiconductor substrate 10. The second protective layer 70 primarily protects the protective layer cover portion 22. The second protective layer 70 prevents moisture from penetrating the protective layer cover portion 22. In addition, the second protective layer 70 suppresses surface discharge (and, depending on the situation, air discharge) between the exposed portion of the first electrode layer 30 (or, if present, the external connection electrode) and the exposed portion of the semiconductor substrate 10 (more specifically, the first main surface 11).

[0145] The second protective layer 70 has a stepped portion 71 whose upper surface 73 (first to third upper surfaces 73a to 73c) decreases in a stepped manner. The stepped portion 71 of the second protective layer 70 is configured to have a corner portion 75 formed by the upper surface 73 and the side surface 74, and more specifically, it is configured to have three pairs of first to third corner portions 75a to 75c formed by the first to third upper surfaces 73a to 73c and the first to third side surfaces 74a to 74c. In the illustrated embodiment, the stepped portion 71 on the surface of the second protective layer 70 has a first upper surface 73a and a first side surface 74a forming the first corner portion 75a, a second upper surface 73b and a second side surface 74b forming the second corner portion 75b, and a third upper surface 73c and a third side surface 74c forming the third corner portion 75c. In other words, the stepped portion 71 has a first step difference between the first upper surface 73a and the second upper surface 73b (corresponding to the first side surface 74a), a second step difference between the second upper surface 73b and the third upper surface 73c (corresponding to the second side surface 74b), and a third step difference between the third upper surface 73c and the first main surface 11 (corresponding to the third side surface 74c), which are formed in a stepped manner on the surface of the second protective layer 70 and descend sequentially.

[0146] For each step difference, the shape of the upper surface and side surface constituting the step difference, and the corner formed by the upper surface and side surface, is not limited to the manner shown in the figure (cross-sectional shape). Multiple upper surfaces can be parallel to each other (parallel straight lines in cross-section), but are not limited to this; they can also be actually inclined, curved, or have irregularities. Similarly, multiple side surfaces can also be parallel to each other, but are not limited to this; they can also be actually inclined, curved, or have irregularities. Pairs of upper surfaces and side surfaces forming any corner can be connected approximately perpendicularly (approximately 90°) or at angles other than approximately perpendicular (approximately 90°). While multiple corners can all be approximately right angles (approximately 90°), this is not limited to this; they can also actually have rounded corners or be partially lacking. Furthermore, in this specification, "approximately perpendicular (approximately 90°)" and "approximately right angle (approximately 90°)" are not limited to 90°; considering the range of actual deviations, angles near 90° are also included. An angle “approximately vertical (about 90°) or beyond” can be any appropriate angle that is outside the range of realistic deviations.

[0147] The thickness of the second protective layer 70 is, for example, 0.1 μm to 3 μm. If the thickness of the second protective layer 70 is 0.1 μm to 3 μm, the moisture resistance of the second protective layer 70 is improved, further preventing moisture from reaching the protective layer cover portion 22. Here, the thickness of the second protective layer 70 is not the thickness around the corner portion 55, but rather, for example, the Z-direction length between the first upper surface 73a of the second protective layer 70 and the upper surface of the first electrode layer 30, the Z-direction length between the second upper surface 73b of the second protective layer 70 and the upper surface 24 of the protective layer cover portion 22 of the dielectric film 20, and the Z-direction length between the third upper surface 73c of the second protective layer 70 and the first main surface 11 of the semiconductor substrate 10. The thickness of the second protective layer 70 can be the same as or greater than the thickness of the electrode layer arrangement portion 21 of the dielectric film 20.

[0148] The second protective layer 70 has higher moisture resistance than the first protective layer 50, and preferably higher moisture resistance than the dielectric film 20. Although various methods for measuring moisture resistance are known, these moisture resistances can be evaluated relatively by using the same methods to evaluate the second protective layer 70, the first protective layer 50, and the dielectric film 20 under the same conditions. The material of the second protective layer 70 is selected from materials with higher moisture resistance than the first protective layer 50. Such a material for the second protective layer 70 is, for example, a nitride, preferably a nitride (more specifically, silicon nitride (SiN)) that is the main component of the semiconductor substrate 10, as described later. In other words, the second protective layer 70 is preferably composed of a nitride, and more preferably of a nitride (more specifically, silicon oxide) that is the main component of the semiconductor substrate 10. If the second protective layer 70 is made of nitride, then the dielectric film 20 is disposed on the first main surface 11 of the semiconductor substrate 10, the upper surface of the electrode layer placement portion 21 is covered by the first electrode layer 30, a portion of the protective layer covering portion 22 is indirectly covered by the second protective layer 70 via the end 32 of the first electrode layer 30 and the first protective layer 50, and the remaining portion of the protective layer covering portion 22 is directly covered by the second protective layer 70. Therefore, the outer surface of the dielectric film 20 is covered by a material with higher moisture resistance than the dielectric film 20. As a result, by suppressing moisture penetration into the dielectric film 20, the moisture resistance of the semiconductor device 1 is improved.

[0149] [Semiconductor device manufacturing method]

[0150] Next, an example of a method for manufacturing semiconductor device 1 will be described.

[0151] The method for manufacturing semiconductor device 1 includes:

[0152] A dielectric film 20 is formed on a portion of the first main surface 11 of the semiconductor substrate 10 (more specifically, referring to...). Figures 1-2The dielectric film formation process of the precursor of the dielectric film 20 (including the electrode layer arrangement portion 21 and the portion that becomes the protective layer covering portion 22 later);

[0153] A first electrode layer forming process in which a first electrode layer 30 is formed on a portion of the dielectric film 20, and a portion of the dielectric film 20 is removed to form a protective layer covering portion 22 (thin film region) (thereby forming a dielectric film 20 having an electrode layer arrangement portion 21 and a protective layer covering portion 22).

[0154] The first protective layer forming process forms a first protective layer 50 that continuously covers the second outer peripheral end 33 of the first electrode layer 30 and the fourth outer peripheral end 26b of the dielectric film 20;

[0155] A second protective layer forming process is performed to form a second protective layer 70 that continuously covers the first main surface 11 from the end 32 of the first electrode layer 30; and

[0156] The second electrode layer formation process for forming a second electrode layer 40 on the second main surface 12 of the semiconductor substrate 10.

[0157] The manufacturing method of semiconductor device 1 can further include a dicing process, which monolithically divides the structure (mother integrated circuit) having multiple semiconductor device structures obtained above into a single piece through dicing.

[0158] Specifically, refer to Figures 3A to 3F An example of a method for manufacturing semiconductor device 1 will be described. Figures 3A to 3F This diagram illustrates a method for manufacturing semiconductor device 1. The method for manufacturing semiconductor device 1 includes a dielectric film formation step, a first electrode layer formation step, a first protective layer formation step, a second protective layer formation step, a second electrode layer formation step, and a dicing step. Furthermore, a parent integrated circuit incorporating semiconductor device 1 is manufactured from the dielectric film formation step to the second electrode layer formation step; however, for ease of explanation, the manufacturing method is described focusing on a single semiconductor device 1.

[0159] (Dielectric film formation process)

[0160] like Figure 3A As shown, in the dielectric film formation process, a dielectric film 20 is formed on a portion of the first main surface 11 of the semiconductor substrate 10. In the dielectric film formation process, for example, the dielectric film 20 is formed on the first main surface 11 of the semiconductor substrate 10, and the dielectric film 20 is patterned. Specifically, a silicon substrate is prepared as the semiconductor substrate 10. Using a chemical vapor deposition (CVD) method, a SiO2 dielectric film 20 is formed on the first main surface 11 of the semiconductor substrate 10, for example, with a thickness of 0.1 to 3 μm.

[0161] Next, the dielectric film 20 formed on the first main surface 11 of the semiconductor substrate 10 is patterned using photolithography and dry etching. For example, in photolithography, a liquid resist is spin-coated to form a photoresist film on the dielectric film 20. The photoresist film is exposed via a mask corresponding to the predetermined pattern. The exposed photoresist film is then developed. In dry etching, for example, reactive ion etching (RIE) is used to selectively remove the dielectric film 20 not covered by the photoresist film. Thereafter, the photoresist film is removed. Thus, a dielectric film 20 with a predetermined pattern is formed on the first main surface 11 of the semiconductor substrate 10 (more specifically, referring to...). Figures 1-2 The aforementioned precursor of dielectric film 20 includes an electrode layer configuration portion 21 and a portion that subsequently becomes a protective layer covering portion 22.

[0162] (First electrode layer formation process)

[0163] In the first electrode layer formation process, such as Figure 3B as well as Figure 3C As shown, a first electrode layer 30 is formed on a portion of the dielectric film 20, and a protective layer cover 22 (thin film region) is formed by removing a portion of the dielectric film 20. In the first electrode layer formation process, for example, the first electrode layer 30 is formed on the first main surface 11 of the semiconductor substrate 10 on which the dielectric film 20 is disposed, and the first electrode layer 30 is patterned. Specifically, as... Figure 3B As shown, a first electrode layer 30 of Al is formed on the first main surface 11 of a semiconductor substrate 10 on which the dielectric film 20 is disposed using sputtering or vacuum evaporation, for example, with a thickness of 0.1 to 3 μm.

[0164] Next, the first electrode layer 30 is patterned using photolithography and dry etching. Specifically, as shown... Figure 3B As shown, a mask layer (more specifically, a photoresist layer) 80 is patterned and formed in the first electrode layer 30. Next, as... Figure 3C As shown, the first electrode layer 30 is patterned. During the patterning of the first electrode layer 30, unwanted portions of the first electrode layer 30 that do not form the desired pattern are removed. Furthermore, a portion of the dielectric film 20 is also removed by over-etching. Next, the mask layer 80 is removed. Thus, a first electrode layer 30 with a predetermined pattern is formed, and a protective layer cover portion 22 (thin film region) of the dielectric film 20 is formed.

[0165] Since the upper surface 24 of the protective layer cover 22 of the dielectric film 20 is formed by etching, it becomes rougher compared to the case where no etching is performed. If the upper surface 24 becomes rougher, the contact area between the upper surface 24 and the first and second protective layers 50 and 70 formed in the subsequent first and second protective layer forming processes increases, and the adhesion between the protective layer cover 22 of the dielectric film 20 and the first and second protective layers 50 and 70 is improved.

[0166] (First protective layer formation process)

[0167] In the first protective layer forming process, such as Figure 3D As shown, a first protective layer 50 is formed that continuously covers the second outer peripheral end 33 of the first electrode layer 30 and the fourth outer peripheral end 26b of the dielectric film 20. Specifically, the first protective layer 50 is formed using a CVD method, for example, SiO2, and patterned using photolithography and dry etching. The first protective layer 50 is formed as described above. Furthermore, the first protective layer 50 is formed to have a thickness of 0.1–3 μm. Thus, the first protective layer 50 is formed.

[0168] (Second protective layer formation process)

[0169] In the second protective layer forming process, such as Figure 3E As shown, a second protective layer 70 is formed, continuously covering the first main surface 11 of the semiconductor substrate 10 from the end 32 of the first electrode layer 30. Specifically, the second protective layer 70 is formed using a CVD method, for example, using SiN, and patterned using photolithography and wet etching. The second protective layer 70 is formed as described above. Furthermore, the second protective layer 70 is formed to have a thickness of 0.1 to 3 μm. Thus, the second protective layer 70 is formed.

[0170] (Second electrode layer formation process)

[0171] In the second electrode layer formation process, such as Figure 3F As shown, a second electrode layer 40 is formed on the second main surface 12 of the semiconductor substrate 10. Specifically, in the second electrode layer formation process, a Ti layer, a Ni layer, and an Au layer are sequentially formed on the second main surface 12 of the semiconductor substrate 10, for example, using sputtering and vacuum evaporation. This forms a multilayer metal film consisting of three layers. The resulting multilayer metal film forms the second electrode layer 40, which consists of three layers—Ti, Ni, and Au—sequentially stacked from the semiconductor substrate 10 side. This results in a master layer stack. Alternatively, in the second electrode layer formation process, the second main surface 12 can be ground or polished before the second electrode layer 40 is formed.

[0172] (Cutting process)

[0173] In the dicing process, the master laminate is diced to form a single semiconductor device 1.

[0174] <Second Implementation>

[0175] [constitute]

[0176] Figure 4 This is an enlarged cross-sectional view schematically showing a semiconductor device 1A according to the second embodiment. The second embodiment is a variation of the first embodiment, differing from the first embodiment in the placement of the first protective layer. This difference in configuration will be described below. Furthermore, in the second embodiment, reference numerals that are the same as those in the first embodiment are those that are the same as those in the first embodiment, so their description is omitted.

[0177] like Figure 4 As shown, in the semiconductor device 1A of the second embodiment, the first protective layer 50A continuously covers at least a portion of the protective layer coverage portion 22 of the dielectric film 20 from the end 32 of the first electrode layer 30. In other words, the first protective layer 50A continuously covers the end 32 and the second outer peripheral end 33 of the first electrode layer 30, and the first outer peripheral end 26a and a portion of the upper surface 24 of the dielectric film 20 without interruption. Thus, the first protective layer 50A further covers the end 32 of the first electrode layer 30. In other words, the first protective layer 50A has a lower relative permittivity than the second protective layer 70A, and the surface distance of the protective layer 90 between the first electrode layer 30 and the semiconductor substrate 10, more specifically, the distance between the exposed portion of the first electrode layer 30 (the portion not covered by the second protective layer 70A) and the exposed portion of the semiconductor substrate 10 (the portion of the first main surface not covered by the second protective layer 70A) of the second protective layer 70A (representatively, the shortest distance between them), is increased due to the presence of the first protective layer 50A at the end 32 of the first electrode layer 30. Therefore, surface discharge can be suppressed, and the voltage withstand capability between the first electrode layer 30 and the semiconductor substrate 10 can be improved.

[0178] The second protective layer 70A continuously covers the first main surface 11 of the semiconductor substrate 10 from the end 32 of the first electrode layer 30. More specifically, the second protective layer 70A continuously covers the end 32 of the first electrode layer 30, the second side surface 54b (inner peripheral end) of the first protective layer 50A, the first upper surface 53a and the first side surface 54a, and the upper surface 24 and the first outer peripheral end 26a of the dielectric film 20 without interruption.

[0179] [Manufacturing method of semiconductor device 1A]

[0180] The manufacturing method of semiconductor device 1A is the same as that of semiconductor device 1 in the first embodiment, except that the pattern of the first protective layer in the first protective layer formation process is changed and the pattern of the second protective layer in the second protective layer formation process is changed as needed.

[0181] <Third Implementation Method>

[0182] [constitute]

[0183] Figure 5 This is an enlarged cross-sectional view schematically showing a cross-section of the semiconductor device 1B according to the third embodiment. The third embodiment is a variation of the second embodiment, differing from the second embodiment in the placement of the first protective layer. This difference in configuration will be described below. Furthermore, in the third embodiment, reference numerals that are the same as those in the first and second embodiments are the same as those in the first embodiment, so their description is omitted.

[0184] like Figure 5 As shown, in the semiconductor device 1B of the third embodiment, the first protective layer 50B continuously covers from the end 32 of the first electrode layer 30 to the first outer peripheral end 26a of the protective layer cover portion 22 of the dielectric film 20. In other words, the first protective layer 50B continuously covers the end 32 and the second outer peripheral end 33 of the first electrode layer 30, the fourth outer peripheral end 26b of the dielectric film 20, the upper surface 24 and the first outer peripheral end 26a, and a portion of the first main surface 11 of the semiconductor substrate 10 without interruption. In this way, the first protective layer 50B covers the first outer peripheral end 26a of the protective layer cover portion 22 of the dielectric film 20, thereby increasing the area of ​​the first protective layer 50B covering the first electrode layer 30. Therefore, it is possible to further suppress the insulation breakdown between the second outer peripheral end 33 of the first electrode layer 30 and the first main surface 11 of the semiconductor substrate 10, and further suppress the decrease in the insulation breakdown strength of the dielectric film 20.

[0185] The first protective layer 50B has a stepped portion 51 whose upper surface (first to third upper surfaces 53a to 53c) is stepped down. The stepped portion 51 of the first protective layer 50B is configured to have first to third corner portions 55a to 55c formed by three pairs of first to third upper surfaces 53a to 53c and first to third side surfaces 54a to 54c, and a fourth corner portion 55d formed by a pair of first upper surface 53a and fourth side surfaces. In the illustrated embodiment, the stepped portion 51 on the surface of the first protective layer 50B has a first upper surface 53a and a first side surface 54a forming the first corner portion 55a, a second upper surface 53b and a second side surface 54b forming the second corner portion 55b, a third upper surface 53c and a third side surface 54c forming the third corner portion 55c, and a fourth side surface (inner peripheral end) 54d forming the fourth corner portion 55d on the inner edge of the first upper surface 53a. In other words, the stepped portion 51 has a first step difference between the first upper surface 53a and the second upper surface 53b (corresponding to the first side surface 54a), a second step difference between the second upper surface 53b and the third upper surface 53c (corresponding to the second side surface 54b), and a third step difference between the third upper surface 53c and the first main surface 11 (corresponding to the third side surface 54c), which are formed in a stepped manner on the surface of the first protective layer 50B and descend sequentially.

[0186] For each step difference, the shape of the upper surface and side surface constituting the step difference, and the corner formed by the upper surface and side surface, is not limited to the manner shown in the figure (cross-sectional shape). The above description can also be applied to the step difference in Embodiment 1.

[0187] The second protective layer 70B continuously covers the first protective layer 50B from its fourth side surface 54d (inner peripheral end) to its third side surface 54c. In other words, the second protective layer 70B continuously and without interruption covers a portion of the upper surface of the first electrode layer 30, the first to third upper surfaces 53a to 53c of the first protective layer 50B, the first to fourth side surfaces 54a to 54d, and a portion of the first main surface 11 of the semiconductor substrate 10.

[0188] [Manufacturing method of semiconductor device 1B]

[0189] The manufacturing method of semiconductor device 1B is the same as that of semiconductor device 1 in the first embodiment, except that the pattern of the first protective layer in the first protective layer formation process is changed and the pattern of the second protective layer in the second protective layer formation process is changed as needed.

[0190] <Fourth Implementation>

[0191] [constitute]

[0192] Figure 6This is an enlarged cross-sectional view schematically showing a cross-section of the semiconductor device 1C according to the fourth embodiment. The fourth embodiment is a variation of the third embodiment, differing from the third embodiment in that it further includes a first metal film. This difference in configuration will be described below. Furthermore, in the fourth embodiment, the reference numerals that are the same as those in the first to third embodiments are the same as those in the first embodiment, so their description is omitted.

[0193] like Figure 6 As shown, the semiconductor device 1C of the fourth embodiment further includes a first metal film 60. The first metal film 60 is disposed between the first protective layer 50B and the second protective layer 70C. The first metal film 60 covers at least a portion of the first protective layer 50B. Specifically, the first metal film 60 continuously covers the first upper surface 53a, the first corner 55a, and the first side surface 54a of the first protective layer 50B. In other words, the first metal film 60 is formed to be in contact with the inner peripheral surface near the first step difference of the second protective layer 70C. The first metal film 60 is made of metal and has low moisture permeability, so it is not easy for moisture to pass through, and its moisture resistance is higher than that of the first protective layer 50B. Therefore, even if cracks occur in the second protective layer 70C, especially around the first corner 75a of the second protective layer 70C and the corner 65 of the first metal film 60, moisture is prevented from penetrating into the dielectric film 20 through the cracks. Therefore, insulation breakdown between the end of the first electrode layer 30 and the first main surface 11 of the semiconductor substrate 10 can be further suppressed, and the reduction in the insulation breakdown strength of the dielectric film 20 can be further suppressed. In addition, since the first metal film 60 is disposed between the first protective layer 50B and the second protective layer 70C, the surface distance of the protective layer 90, more specifically, the distance between the exposed portion of the first electrode layer 30 (the portion not covered by the second protective layer 70C) and the exposed portion of the semiconductor substrate 10 (the portion of the first main surface 11 not covered by the second protective layer 70C) of the second protective layer 70C (representatively, the shortest distance between them) increases, thereby suppressing surface discharge on the surface of the protective layer 90.

[0194] The first protective layer 50B has a stepped portion 51 including one or more corners, and the first metal film 60 covers at least one corner of the first protective layer 50B. Specifically, the first metal film 60 continuously covers the first upper surface 53a, the first corner 55a, and the first side surface 54a of the first protective layer 50B. Preferably, the first metal film 60 covers any one of the multiple corners (first to fourth corners 55a, 55b, 55c, 55d) of the first protective layer 50B, and more preferably covers two or more of the multiple corners (first to fourth corners 55a, 55b, 55c, 55d). This is because when the second protective layer 70C has a stepped portion 71, cracks are easily generated around the corners 75a, 75b, 75c on the outer periphery of the second protective layer 70C, and around the corners on the inner periphery (more specifically, the portions that connect with the corner 65 of the first metal film 60 and the portions that connect with the corners 55b, 55c of the first protective layer). In particular, the first metal film 60 is preferably configured to span the electrode layer configuration portion 21 and the protective layer covering portion 22 of the dielectric film 20. More specifically, since the protective layer covering portion 22 of the dielectric film 20 is a thin film region, the first step difference formed by the first upper surface 53a and the second upper surface 53b descending one step from the first upper surface 53a is increased. Therefore, the first metal film 60 preferably covers the first corner 55a among the multiple corners (first to fourth corners 55a, 55b, 55c, 55d) of the first protective layer 50B. The first metal film 60 is made of metal, so it has excellent moisture resistance. Therefore, even if cracks occur around the corners 75a, 75b, 75c on the outer periphery of the second protective layer 70C, as well as at the inner periphery, moisture is prevented from penetrating into the first protective layer 50B through the first metal film 60.

[0195] The first protective layer 50B is covered by the second protective layer 70C and the first metal film 60. Therefore, the entire outer surface of the first protective layer 50B is protected against moisture by the second protective layer 70C and the first metal film 60, which have relatively high moisture resistance. This prevents external moisture from penetrating the dielectric film 20 through the first protective layer 50B, further suppressing the reduction in the insulation strength of the dielectric film 20.

[0196] The thickness of the first metal film 60 is, for example, 0.1 μm to 3 μm. If the thickness of the first metal film 60 is 0.1 μm to 3 μm, it can prevent moisture from penetrating into the dielectric film 20, thereby improving the moisture resistance of the semiconductor device 1C.

[0197] From the viewpoint of improving the moisture resistance of the first metal film 60, the material of the first metal film 60 is, for example, a metal (more specifically, Al, etc.). Among these metals, Al is also preferred as the material of the first metal film 60. In other words, the first protective layer 50B is preferably composed of Al.

[0198] [Manufacturing method of semiconductor device 1C]

[0199] The manufacturing method of semiconductor device 1C is the same as that of semiconductor device 1B in the third embodiment, except that it includes a first metal film formation step after the first protective layer formation step and before the second protective layer formation step. A metal film can be formed on the exposed surface of a semiconductor substrate on which the dielectric film, the first electrode layer, and the first protective layer are formed using sputtering or vacuum evaporation. Next, the metal film is patterned into a first metal film 60 using photolithography and dry etching to perform the first metal film formation step.

[0200] <Fifth Implementation>

[0201] [constitute]

[0202] Figure 7 This is an enlarged cross-sectional view schematically showing a cross-section of the semiconductor device 1D according to the fifth embodiment. The fifth embodiment is a variation of the fourth embodiment, differing from the fourth embodiment in the placement of the first metal film. This difference in configuration will be described below. Furthermore, in the fifth embodiment, reference numerals that are the same as those in the first to fourth embodiments are those that are the same as those in the first to fourth embodiments, so their description is omitted.

[0203] like Figure 7 As shown, in the semiconductor device 1D of the fifth embodiment, the first electrode layer 30 has an end portion 32 covered by the first protective layer 50B and a central portion 31. A first metal film 60D is disposed on the first upper surface 53a of the first protective layer 50B. The first metal film 60D is positioned to expose the central portion 31 of the first electrode layer 30 and is electrically connected to the first electrode layer 30. Therefore, in addition to suppressing the insulation breakdown of the dielectric film 20, the first metal film 60D also functions as an external connection electrode.

[0204] In the illustrated cross-section, the first metal film 60D continuously covers the first protective layer 50B and the central portion 31 of the first electrode layer 30 from the first upper surface 53a of one first protective layer 50B to the first upper surface 53a of the other first protective layer 50B. The first metal film 60D has a central portion 61D covering the central portion 31 of the first electrode layer 30 and an end portion 62D covering the first protective layer 50B. The first metal film 60D covers a corner portion 55d of the first protective layer 50B.

[0205] The second protective layer 70D continuously covers the first protective layer 50B and the end 62D of the first metal film 60D from the side 64d to the third side 54c of the first protective layer 50B. In other words, the second protective layer 70D covers a portion of the central portion 61D of the first metal film 60D, the end 62D, and the first protective layer 50B. The first metal film 60D is disposed inside the boundary between the electrode layer arrangement portion 21 and the protective layer covering portion 22 of the dielectric film 20 (in other words, it is separated towards the central portion 31 of the first electrode layer 30). Since the first metal film 60D covers the corner 55d of the first protective layer 50B and is disposed inside the boundary between the electrode layer arrangement portion 21 and the protective layer covering portion 22, it can effectively prevent moisture from penetrating the first protective layer 50B. Furthermore, as a result, the surface distance of the second protective layer 70D, more specifically, the distance between the exposed portion of the first metal film 60D (the portion of the central portion 61D not covered by the second protective layer 70D) and the exposed portion of the semiconductor substrate 10 (the portion of the first main surface not covered by the second protective layer 70D) (representing the shortest distance between them) is increased, which can effectively prevent the generation of surface discharge on the protective layer surface.

[0206] [Manufacturing Method of Semiconductor Device 1D]

[0207] The manufacturing method of semiconductor device 1D is the same as that of semiconductor device 1C in the fourth embodiment, except that the pattern of the first metal film in the first metal film formation process and the pattern of the second protective layer in the second protective layer formation process are changed.

[0208] <Sixth Implementation Method>

[0209] [constitute]

[0210] Figure 8 This is an enlarged cross-sectional view schematically showing a cross-section of the semiconductor device 1E according to the sixth embodiment. The sixth embodiment is a variation of the fifth embodiment, differing from the fifth embodiment in the arrangement position of the first metal film 60E. This difference in configuration will be described below. Furthermore, in the sixth embodiment, reference numerals that are the same as those in the first to fifth embodiments correspond to configurations that are the same as those in the first to fifth embodiments, so their description is omitted.

[0211] like Figure 8As shown, in the semiconductor device 1E of the sixth embodiment, the third outer peripheral end (third side surface 54c) of the first protective layer 50B is covered by the second protective layer 70E. The first metal film 60E continuously covers the central portion 31 of the first electrode layer 30 and the first protective layer 50B except for the third outer peripheral end. In other words, in the illustrated cross-section, the first metal film 60E continuously covers the third upper surface 53c of one first protective layer 50B to the third upper surface 53c of the other first protective layer 50B. The thickness of the first protective layer 50B is the same as or greater than the thickness of the electrode layer arrangement portion 21 of the dielectric film 20.

[0212] Therefore, the first protective layer 50B functions as a stress-relieving layer, suppressing the peeling and cracking of the second protective layer 70E caused by stress. This further prevents moisture from penetrating into the dielectric film 20 through cracks, and further suppresses the reduction in the insulating strength of the dielectric film 20.

[0213] Furthermore, a first metal film 60E is disposed between the first protective layer 50B and the second protective layer 70E, continuously covering the first protective layer 50B except for its third outer peripheral end. The first protective layer 50B is doubly covered by the first metal film 60E and the second protective layer 70E, both of which have high moisture resistance. This prevents moisture from penetrating the first protective layer 50B and further penetrating the protective layer coverage portion 22 of the dielectric film 20, thereby further suppressing the reduction in the insulation breakdown strength of the dielectric film 20.

[0214] Furthermore, the first metal film 60E continuously covers the first protective layer 50B except for the third outer peripheral end of the first protective layer 50B. Therefore, even if a crack occurs in the second protective layer 70B, moisture is prevented from penetrating into the protective layer coverage portion 22 of the dielectric film 20.

[0215] The fifth peripheral end (corresponding to side surface 642) of the first metal film 60E is configured to be separated from the first main surface 11. Therefore, the fifth peripheral end of the first metal film 60E is not electrically connected to the first main surface 11. In other words, the first electrode layer 30 is electrically insulated from the semiconductor substrate 10.

[0216] The second protective layer 70E continuously covers the first protective layer 50B and the first metal film 60E from the side 642 of the first metal film 60E to the third side 54c of the first protective layer 50B.

[0217] [Manufacturing method of semiconductor device 1E]

[0218] The manufacturing method of semiconductor device 1E is the same as that of semiconductor device 1D in the fifth embodiment, except that the pattern of the first metal film in the first metal film formation process and the pattern of the second protective layer in the second protective layer formation process are changed.

[0219] <Seventh Implementation>

[0220] [constitute]

[0221] Figure 9 This is an enlarged cross-sectional view schematically showing a cross-section of the semiconductor device 1F according to the seventh embodiment. The seventh embodiment is a variation of the fifth embodiment, differing from the fifth embodiment in the placement position of the first metal film 60F and the further inclusion of a second metal film 63. This difference in configuration will be described below. Furthermore, in the seventh embodiment, reference numerals that are the same as in the first to fifth embodiments indicate configurations that are the same as in the first to fifth embodiments, so their description is omitted.

[0222] like Figure 9 As shown, the semiconductor device 1F of the seventh embodiment further includes a second metal film 63. The second metal film 63 covers the third outer peripheral end (corresponding to the third side surface 54c) of the first protective layer 50B and is separated from the first metal film 60F through an opening 64. The opening 64 is configured such that the second upper surface 53b of the first protective layer 50B contacts the second protective layer 70F. In other words, the first metal film 60F and the second metal film 63 continuously cover the first protective layer 50B except for the opening 64, covering the first to fourth corner portions 55a, 55b, 55c, and 55d of the first protective layer 50B. Furthermore, the second protective layer 70F covers the first metal film 60F, the second metal film 63, and the first protective layer 50B. Thus, the first protective layer 50B is doubly covered by the first metal film 60F, the second metal film 63, and the second protective layer 70F, which have high moisture resistance. Therefore, even if moisture seeps in through the second protective layer 70F, it can prevent it from seeping into the protective layer covering portion 22 of the dielectric film 20, further suppressing the insulation damage of the dielectric film 20.

[0223] Furthermore, unlike the sixth embodiment where the first protective layer 50B is continuously covered by the first metal film 60E except for the third outer peripheral end, this embodiment covers only the third outer peripheral end of the first protective layer 50B. Therefore, for example, peeling of the third outer peripheral end of the first protective layer 50B can be effectively prevented.

[0224] The second metal film 63 is separated from the first metal film 60F through the opening 64. Therefore, the second metal film 63 is not electrically connected to the first metal film 60F. In other words, the first electrode layer 30 is electrically insulated from the semiconductor substrate 10. Furthermore, although the opening 64 is provided on the second upper surface 53b of the first protective layer 50B, it is not limited thereto. The opening 64 may also be provided on the first upper surface 53a and / or the third upper surface 53c of the first protective layer 50B. Preferably, the opening 64 is provided on the first to third upper surfaces 53a, 53b, and 53c, and the first metal film 60F and the second metal film 63 cover the entire first to fourth corner portions 55a, 55b, 55c, and 55d of the first protective layer 50B.

[0225] When viewing the semiconductor device 1F from the Z direction, the opening 64 is disposed on the inner side (on the electrode layer arrangement portion 21 side of the dielectric film 20) compared to the first outer peripheral end 26a of the protective layer covering portion 22 of the dielectric film 20.

[0226] [Manufacturing method of semiconductor device 1F]

[0227] The manufacturing method of semiconductor device 1F is the same as that of semiconductor device 1D in the fifth embodiment, except that the pattern of the first metal film in the first metal film formation step and the pattern of the second protective layer in the second protective layer formation step are changed. The second metal film 63 can be formed simultaneously with the first metal film 60F in the first metal film formation step.

[0228] <Eighth Implementation Method>

[0229] [constitute]

[0230] Figure 10 This is an enlarged cross-sectional view schematically showing a cross-section of the semiconductor device 1G according to the eighth embodiment. The eighth embodiment is a variation of the fifth embodiment, differing from the fifth embodiment in that it further includes a diffusion-preventing film 100. This difference in configuration will be described below. Furthermore, in the eighth embodiment, the same reference numerals as in the first to fifth embodiments refer to configurations that are the same as in the first to fifth embodiments, so their description is omitted.

[0231] like Figure 10As shown, in the semiconductor device 1G of the eighth embodiment, a diffusion prevention film 100 is disposed between the first electrode layer 30 and the first metal film 60G. The first electrode layer 30 and the first metal film 60G are not in contact, thus preventing the diffusion of components constituting the first electrode layer 30 into the first metal film 60G. Therefore, the semiconductor device 1G can operate stably. For example, when the first electrode layer 30 is made of polysilicon, the first metal film 60G is made of Al, and the diffusion prevention film 100 is made of an Al-Si alloy, the diffusion prevention film 100 can prevent the diffusion of components constituting the first electrode layer 30, i.e., polysilicon, into the first metal film 60G.

[0232] A diffusion-preventing film 100 is disposed on a portion of the first electrode layer 30. A first protective layer 50G continuously covers the end 101 of the diffusion-preventing film 100, a portion of the first electrode layer 30, and the protective layer cover 22 from the end 101 of the diffusion-preventing film 100 to the first outer peripheral end 26a of the protective layer cover 22 of the dielectric film 20. A first metal film 60G covers the inner peripheral end (corresponding to the fifth side surface 54e) of the first protective layer 50G and the central portion 102 of the diffusion-preventing film 100.

[0233] [Manufacturing Method of Semiconductor Device 1G]

[0234] The manufacturing method of semiconductor device 1G is the same as that of semiconductor device 1D in the fifth embodiment, except that it further includes a diffusion prevention film formation step after the first electrode layer formation step and before the first protective layer formation step.

[0235] (Diffusion prevention film formation process)

[0236] In the diffusion prevention film formation process, a diffusion prevention film 100 is formed at the central portion 31 of the first electrode layer 30. In this process, for example, the diffusion prevention film 100 is formed on a semiconductor substrate 10 on which the first electrode layer 30 is disposed, and the diffusion prevention film 100 is patterned. Specifically, using sputtering or vapor deposition, an Al-Si alloy diffusion prevention film 100 is formed on the semiconductor substrate 10 on which the first electrode layer 30 is disposed, for example, to a thickness of 0.1 to 3 μm. Next, the diffusion prevention film 100 is patterned using photolithography and dry etching.

[0237] (First protective layer formation process)

[0238] In the first protective layer forming process, a first protective layer 50G is formed that continuously covers the end 101 of the diffusion prevention film 100, a portion of the first electrode layer 30, and the protective layer cover portion 22.

[0239] (First metal film formation process)

[0240] In the first metal film forming process, a first metal film 60G is formed covering the inner peripheral end (corresponding to the fifth side surface 54e) of the first protective layer 50G and the central portion 102 of the diffusion prevention film 100.

[0241] <Ninth Implementation Method>

[0242] [constitute]

[0243] Figure 11 This is a schematic cross-sectional view of the semiconductor device 1H according to the ninth embodiment. The ninth embodiment is a variation of the fourth embodiment, differing from the fourth embodiment in that it has a channel structure (groove structure). This difference in configuration will be described below. Furthermore, in the ninth embodiment, the same reference numerals as in the first to fourth embodiments are the same as in the fourth embodiment, so their description is omitted.

[0244] like Figure 11 As shown, in the semiconductor device 1H of the ninth embodiment, the semiconductor substrate 10H has a channel (groove) 13 on the first main surface 11H of the electrode layer placement portion 21H where the dielectric film 20H is disposed. The electrode layer placement portion 21H of the dielectric film 20H is disposed on the first main surface 11H including the inner surface of the channel 13, so as to form a recess 25 covering the inner surface of the channel 13. The first electrode layer 30H has an entry portion 36 that enters the recess 25.

[0245] The semiconductor device 1H has a channel structure 14, so compared with a semiconductor device without a channel structure 14, the area of ​​the interface formed by the dielectric film 20H and the first electrode layer 30H is increased. As a result, the semiconductor device 1H can increase the capacitance.

[0246] The electrode layer arrangement portion 21H of the dielectric film 20H has a recess 25 covering the inner surface of the channel 13. The first electrode layer 30H has a planar portion 35 and an entry portion 36. The entry portion 36 extends from the planar portion 35 in the reverse Z direction and fills the recess 25. The first electrode layer 30H has a comb shape.

[0247] like Figure 11 As shown, the shape of the entry part 36 (the cross-sectional shape on the ZX plane) is a rectangular shape extending in the opposite Z direction. In addition, the shape of the entry part 36 (the cross-sectional shape on the XY plane) is, for example, a polygon (more specifically, a quadrilateral, a pentagon, and a hexagon, etc.) and a circle.

[0248] The shape of the entry part 36 (the cross-sectional shape on the ZX plane) is such that its lower end has a bottom surface. The shape of the bottom surface is, for example, a polygon (more specifically, a quadrilateral, a pentagon, and a hexagon, etc.) and a circle. In addition, the shape of the entry part 36 (the cross-sectional shape on the ZX plane) is not limited to the shape of its lower end having a bottom surface; for example, it can also be a semi-circular arc.

[0249] The entry portion 36 may have a taper (inclination) added to its side (inner surface). In other words, the entry portion 36 may also have a shape in which the width (length in the X direction) increases or decreases from its lower end toward the first main surface 11H. The recess 25 may also have a taper added to its outer and inner sides.

[0250] The recess 25 and the entry portion 36 are arranged along the X direction. For example, when viewed from a direction perpendicular to the first main surface 11H, the recess 25 and the entry portion 36 are arranged in a matrix shape.

[0251] The density of the recesses 25 and the inlets 36 (the number of channels 13 per unit area of ​​the first main surface 11H) is, for example, 15,000 / mm². 2 about.

[0252] Figure 12 yes Figure 11 Enlarged view of part B. (See image below.) Figure 12 As shown, the length D of the recess 25 is, for example, 10 μm to 50 μm. The width W2 of the recess 25 in the X direction is, for example, about 5 μm. The aspect ratio of the recess 25 (the ratio of the length D in the Z direction to the width W2 in the X direction) is, for example, 2 to 10. The distance W3 between the recesses 25 in the X direction is, for example, 3 μm. The distance W1 from the first outer peripheral end 26 of the dielectric film 20H to the end of the channel structure 14 is, for example, 50 to 200 μm.

[0253] The density, shape, and length D of the recess 25 can be adjusted appropriately according to the desired capacitance.

[0254] Furthermore, in the ninth embodiment, the thickness of the dielectric film 20H refers to the thickness of the dielectric film 20H in the Z direction covering the first main surface 11H where the channel 13 is not formed.

[0255] [Manufacturing method of semiconductor device 1H]

[0256] The manufacturing method of semiconductor device 1H further includes a channel formation step before the dielectric film formation step in the manufacturing method of semiconductor device 1. That is...

[0257] The method for manufacturing semiconductor device 1H includes:

[0258] The channel forming process in which the channel 13 is formed on the first main surface 11H of the semiconductor substrate 10H;

[0259] On the first main surface 11H, the dielectric film 20H (more specifically, referring to...) Figures 11-12 The aforementioned dielectric film 20H precursor (including the electrode layer arrangement portion 21H and the portion that becomes the protective layer covering portion 22 later) is formed into a dielectric film forming process that covers the inner surface of the channel 13 to form a recess 25.

[0260] The first electrode layer forming process involves forming the first electrode layer 30H in the dielectric film 20H to form the entry portion 36 that enters the recess 25, and removing a portion of the dielectric film 20H to form the protective layer covering portion 22 (thin film region) (thereby forming the dielectric film 20H having the electrode layer arrangement portion 21H and the protective layer covering portion 22).

[0261] A first protective layer forming process is used to form a first protective layer 50B that continuously covers the first main surface 11H of the semiconductor substrate 10H from the end 32 of the first electrode layer 30H to the first main surface 11H of the semiconductor substrate 10H.

[0262] A first metal film forming process for forming a first metal film 60 covering a portion of the first protective layer 50B;

[0263] A second protective layer forming process that continuously covers at least a portion of the first protective layer 50B and the first metal film 60; and

[0264] The second electrode layer formation process is used to form the second electrode layer 40 on the second main surface 12 of the semiconductor substrate 10H.

[0265] The manufacturing method of semiconductor device 1H can further include a dicing process, which monolithically divides the structure (mother integrated circuit) having multiple semiconductor device structures obtained above into a single piece through dicing.

[0266] Specifically, refer to Figures 13A to 13G An example of a method for manufacturing a semiconductor device 1H will be described. Figures 13A to 13G This diagram illustrates a method for manufacturing a semiconductor device 1H. The method for manufacturing the semiconductor device 1H includes a channel formation process, a dielectric film formation process, a first electrode layer formation process, a first protective layer formation process, a first metal film formation process, a second protective layer formation process, a second electrode layer formation process, and a dicing process. Furthermore, although a parent integrated circuit comprising the semiconductor device 1H is fabricated from the channel formation process to the second electrode layer formation process, for ease of explanation, the manufacturing method is described focusing on a single semiconductor device 1H.

[0267] (Trench formation process)

[0268] In the channel forming process, such as Figure 13A As shown, a channel 13 is formed on the first main surface 11H of the semiconductor substrate 10H. The channel formation process first prepares a silicon substrate as the semiconductor substrate 10H. Next, for example using a Bosch process, the first main surface 11H of the semiconductor substrate 10H is deeply etched (depth RIE (reactive ion etching)) so that the distance W2 between adjacent channels 13 is 3 μm and the depth of the channel 13 is 5 μm. Thus, multiple channels 13 are formed on the first main surface 11H.

[0269] A planarization process may also be included after the channel formation process. In the planarization process, for example, CMP (Chemical Mechanical Polishing) is used to planarize the first main surface 11H of the semiconductor substrate 10H where the channel 13 is formed. As a result, unwanted components of the semiconductor substrate 10H are removed from the channel pattern, giving the semiconductor substrate 10H a uniform thickness, thus enabling the formation of the desired layer configuration.

[0270] (Dielectric film formation process)

[0271] In the dielectric film formation process, such as Figure 13B As shown, a dielectric film 20H is formed on the first main surface 11H to cover the recess 25 formed on the inner surface of the channel 13. In the dielectric film formation process, for example, a dielectric film 20H is formed on the first main surface 11H of the semiconductor substrate 10H, and the dielectric film 20H is patterned. Using a CVD method, a SiO2 dielectric film 20H is formed on the first main surface 11H of the semiconductor substrate 10H, for example, to a thickness of 0.1 to 3 μm. Thus, a dielectric film 20H covering the recess 25 formed on the inner surface of the channel 13 is formed.

[0272] Next, the dielectric film 20H formed on the first main surface 11H of the semiconductor substrate 10H is patterned using the same photolithography and dry etching methods as described in the dielectric film formation step of the semiconductor device 1 manufacturing method of the first embodiment. Thus, a dielectric film 20H with a predetermined pattern is formed on the first main surface 11H of the semiconductor substrate 10H (more specifically, referring to…). Figures 11-12 The aforementioned precursor of dielectric film 20H includes an electrode layer configuration portion 21H and a portion that subsequently becomes a protective layer covering portion 22.

[0273] (First electrode layer formation process)

[0274] In the first electrode layer formation process, such as Figure 13CAs shown, the first electrode layer 30H is formed on the dielectric film 20H to form an entry portion 36 that enters the recess 25, and a portion of the dielectric film 20H is removed to form a protective layer covering portion 22 (thin film region). In the first electrode layer formation process, for example, the first electrode layer 30H is formed on the first main surface 11H of the semiconductor substrate 10H on which the dielectric film 20H is disposed, and the first electrode layer 30H is patterned. Specifically, using sputtering or vacuum evaporation, the first electrode layer 30H of Al is formed on the first main surface 11H of the semiconductor substrate 10H on which the dielectric film 20H is disposed to a thickness of 0.1 to 3 μm. Thus, a first electrode layer 30H having a planar portion 35 and an entry portion 36 extending from the planar portion 35 in the reverse Z direction is formed. In other words, a channel structure is formed.

[0275] Next, the first electrode layer 30H is patterned using photolithography and dry etching. During the patterning of the first electrode layer 30H, a portion of the dielectric film 20H is also removed by over-etching. Thus, a first electrode layer 30H with a predetermined pattern is formed, and a protective layer cover portion 22 (thin film region) of the dielectric film 20H is formed.

[0276] (First protective layer formation process ~ cutting process)

[0277] like Figures 13D to 13G As shown, the semiconductor device 1H is manufactured through the same first protective layer formation process and dicing process as the first protective layer formation process and dicing process in the fourth embodiment.

[0278] Furthermore, the manufacturing conditions described in the first to ninth embodiments are not limited as long as they enable the protective layer covering portion of the dielectric film to be formed such that the step difference at the first outer peripheral end of the protective layer covering portion of the dielectric film in the semiconductor device is smaller than the thickness of the electrode layer arrangement portion of the dielectric film.

[0279] This disclosure is not limited to the first to ninth embodiments, and can be implemented in various ways as long as the spirit of this disclosure is not changed. Furthermore, the configurations shown in the first to ninth embodiments are examples and are not particularly limiting; various modifications can be made without actually departing from the effects of this disclosure. For example, the items described in the first to ninth embodiments can be appropriately combined.

[0280] The semiconductor device of the present invention has a capacitor structure by adding a second electrode layer; in other words, it functions as a capacitor. The semiconductor device of the present invention can be widely used in various applications; for example, it can be mounted on various electronic circuit boards as an electronic component containing a capacitor, utilizing both the first and second electrode layers.

[0281] This application claims priority to Japan Patent Application No. 2019-171533, filed on September 20, 2019, the entire contents of which are incorporated herein by reference.

[0282] Explanation of reference numerals in the attached figures

[0283] 1, 1A, 1B, 1C, 1E, 1F, 1G, 1H… Semiconductor device; 10, 10H… Semiconductor substrate; 11, 11H… First main surface; 12… Second main surface; 13… Channel; 20, 20H… Dielectric film; 21, 21H… Electrode layer arrangement portion of dielectric film; 22… Protective layer covering portion of dielectric film; 25… Recess of dielectric film; 26a… First outer peripheral end of dielectric film; 30, 30H… First electrode layer; 31… Central portion of first electrode layer; 32… End of first electrode layer; 3 3…Second outer peripheral end of the first electrode layer, 36…Entry portion, 50, 50A, 50B, 50G…First protective layer, 51…Step portion, 60, 60D, 60E, 60F, 60G…First metal film, 63…Second metal film, 70, 70A, 70B, 70C, 70D, 70E, 70F, 70G…Second protective layer, 71…Step portion, 100…Diffusion prevention film, Ta…Thickness of the electrode layer arrangement portion of the dielectric film, Tb…Thickness of the outer peripheral end of the protective layer covering portion of the dielectric film.

Claims

1. A semiconductor device, wherein, have: A semiconductor substrate having a first main surface and a second main surface that are opposite to each other; A dielectric film is disposed on a portion of the aforementioned first main surface; A first electrode layer is disposed on a portion of the aforementioned dielectric film; and A protective layer continuously covers the dielectric film from the end of the first electrode layer to the first outer peripheral end. The dielectric film described above has an electrode layer configuration portion on which the first electrode layer is disposed, and a protective layer covering portion covered by the protective layer. The thickness of the first outer peripheral end of the protective layer covering portion of the dielectric film is smaller than the thickness of the electrode layer arrangement portion of the dielectric film. The aforementioned protective layer has a first protective layer and a second protective layer disposed on the first protective layer, wherein the first protective layer continuously covers the second outer peripheral end of the first electrode layer and at least a portion of the protective layer coverage area. The first protective layer has a lower relative permittivity than the second protective layer. The second protective layer has higher moisture resistance than the first protective layer.

2. The semiconductor device according to claim 1, wherein, The first protective layer extends continuously from the end of the first electrode layer to at least a portion of the protective layer coverage area.

3. The semiconductor device according to claim 1 or 2, wherein, The first protective layer extends continuously from the second outer peripheral end of the first electrode layer to the first outer peripheral end of the protective layer covering portion.

4. The semiconductor device according to claim 1 or 2, wherein, It also includes a first metal film disposed between the first protective layer and the second protective layer, and covering at least a portion of the first protective layer.

5. The semiconductor device according to claim 4, wherein, The first protective layer is covered by the second protective layer and the first metal film.

6. The semiconductor device according to claim 4, wherein, The aforementioned first protective layer has a stepped portion including one or more corners. The first metal film described above covers at least one of the aforementioned corners.

7. The semiconductor device according to claim 6, wherein, The first metal film is configured to span the electrode layer configuration portion and the protective layer coverage portion.

8. The semiconductor device according to claim 6, wherein, The first metal film is disposed inside the boundary between the electrode layer configuration portion and the protective layer coverage portion.

9. The semiconductor device according to claim 4, wherein, The first electrode layer has the aforementioned end portion and central portion covered by the aforementioned first protective layer. The first metal film is electrically connected to the first electrode layer and is exposed at the central portion of the first electrode layer.

10. The semiconductor device according to claim 4, wherein, The third outer peripheral end of the first protective layer is covered by the second protective layer. The first metal film continuously covers the first protective layer except for the third outer peripheral end. The thickness of the first protective layer is the same as or greater than the thickness of the electrode layer arrangement portion of the dielectric film.

11. The semiconductor device according to claim 4, wherein, It also has a second metal film. The second metal film covers the third outer peripheral end of the first protective layer and is separated from the first metal film through an opening.

12. The semiconductor device according to claim 4, wherein, It also includes a diffusion prevention film disposed between the first electrode layer and the first metal film.

13. The semiconductor device according to claim 12, wherein, The first electrode layer mentioned above is made of polycrystalline silicon. The aforementioned diffusion-preventing film is composed of an Al-Si alloy. The first metal film mentioned above is composed of Al.

14. The semiconductor device according to claim 1 or 2, wherein, The resistivity of the aforementioned semiconductor substrate is between 0.001 Ωcm and 100 Ωcm.

15. The semiconductor device according to claim 1 or 2, wherein, The first protective layer mentioned above is an oxide. The second protective layer mentioned above is a nitride.

16. The semiconductor device according to claim 1 or 2, wherein, The first protective layer is composed of oxide, the main component of the semiconductor substrate. The second protective layer is composed of nitrides, the main component of the semiconductor substrate.

17. The semiconductor device according to claim 1 or 2, wherein, The semiconductor substrate has a channel on the first main surface of the electrode layer configuration portion where the dielectric film is disposed. The electrode layer of the dielectric film is continuously disposed on the first main surface to form a recess covering the inner surface of the channel. The first electrode layer described above has an entry portion that enters the recess described above.

Images