Capacitor bank structure, semiconductor packaging structure and manufacturing method thereof

Abstract

The invention relates to a capacitor bank structure, a semiconductor package structure and a manufacturing method thereof. A capacitor bank structure includes: a capacitor including a plurality of first electrodes and a plurality of second electrodes opposite the plurality of first electrodes; a plurality of conductive pads electrically connected to the capacitor; a first protective material covering sidewalls of the capacitor and the plurality of conductive pads; and a second protective material covering the first protective material and a sidewall of the first electrode, in which a material of the first protective material is different from a material of the second protective material.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of the invention patent application filed on June 21, 2019, with application number 201910543682.3 and entitled "Capacitor Bank Structure, Semiconductor Packaging Structure and Manufacturing Method Thereof".

[0003] Cross-references to related applications

[0004] This application claims the benefit and priority of U.S. Provisional Application No. 62 / 688,927, filed on June 22, 2018, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0005] The present invention relates to capacitor bank structures and semiconductor package structures comprising at least one capacitor, as well as methods for manufacturing the same. Background Technology

[0006] With advancements in microelectronics technology, semiconductor devices are becoming increasingly smaller, leading to lower operating voltages for overall electronic systems. This makes voltage stability a critical issue. To achieve voltage stability, more electronic components (such as decoupling capacitors) should be integrated at the power supply of the electronic system. Besides providing a more stable power output, decoupling capacitors effectively reduce noise from electronic components coupled to the power supply, indirectly reducing the impact of noise on other electronic devices and suppressing unwanted radiation. In other words, they effectively suppress voltage surges when the electronic system is powered off and suppress voltage drops when the system is powered on. Summary of the Invention

[0007] In some embodiments, a capacitor bank structure includes a plurality of capacitors, a protective material, a first dielectric layer, and a plurality of first pillars. The capacitors are arranged side-by-side. Each of the capacitors has a first surface and a second surface opposite the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protective material covers the capacitors, the sidewalls of the first electrodes, and the sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitors and a second surface corresponding to the second surface of the capacitors. The first dielectric layer is disposed on the first surface of the protective material and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

[0008] In some embodiments, a semiconductor package structure includes a conductive structure, a semiconductor device, at least one capacitor, an encapsulation, and a plurality of external pillars. The conductive structure has a top surface and a bottom surface opposite the top surface. The semiconductor device is electrically connected to the top surface of the conductive structure. The capacitor is disposed between the semiconductor device and the top surface of the conductive structure. The capacitor has a first surface and a second surface opposite the first surface, and includes a plurality of first electrodes disposed adjacent to its first surface for electrical connection to the conductive structure and a plurality of second electrodes disposed adjacent to its second surface for electrical connection to the semiconductor device. The encapsulation covers the semiconductor device and the conductive structure. The external pillars are disposed around the semiconductor device and extend through the encapsulation.

[0009] In some embodiments, a method for manufacturing a semiconductor package structure includes: (a) providing at least one capacitor, an encapsulation, and a plurality of external pillars on a semiconductor device, wherein the capacitor has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes disposed adjacent to its first surface and a plurality of second electrodes disposed adjacent to its second surface for electrical connection to the semiconductor device; the encapsulation covers the semiconductor device; and the external pillars extend through the encapsulation; and (b) forming a conductive structure on the at least one capacitor, the encapsulation, and the external pillars, wherein the first electrodes of the capacitor are electrically connected to the conductive structure, and the at least one capacitor is disposed between the semiconductor device and the conductive structure. Attached Figure Description

[0010] When read in conjunction with the accompanying drawings, aspects of some embodiments of the invention will be readily understood from the following detailed description. It should be noted that the various structures may not necessarily be drawn to scale, and for clarity of explanation, the dimensions of the various structures may be arbitrarily increased or decreased.

[0011] Figure 1 A cross-sectional view illustrating the capacitor bank structure according to some embodiments of the present invention is provided.

[0012] Figure 2 A cross-sectional view illustrating the capacitor bank structure according to some embodiments of the present invention is provided.

[0013] Figure 3 A cross-sectional view illustrating the capacitor bank structure according to some embodiments of the present invention is provided.

[0014] Figure 4 Cross-sectional views illustrating semiconductor package structures according to some embodiments of the present invention are shown.

[0015] Figure 5 Cross-sectional views illustrating semiconductor package structures according to some embodiments of the present invention are shown.

[0016] Figure 6 Cross-sectional views illustrating semiconductor package structures according to some embodiments of the present invention are shown.

[0017] Figure 7 Cross-sectional views illustrating semiconductor package structures according to some embodiments of the present invention are shown.

[0018] Figure 8 Cross-sectional views illustrating semiconductor package structures according to some embodiments of the present invention are shown.

[0019] Figure 9 Cross-sectional views illustrating semiconductor package structures according to some embodiments of the present invention are shown.

[0020] Figure 10 Cross-sectional views illustrating semiconductor package structures according to some embodiments of the present invention are shown.

[0021] Figure 11 Cross-sectional views illustrating semiconductor package structures according to some embodiments of the present invention are shown.

[0022] Figure 12 This describes one or more stages of an example of a method for manufacturing a capacitor bank structure according to some embodiments of the present invention.

[0023] Figure 13 This describes one or more stages of an example of a method for manufacturing a capacitor bank structure according to some embodiments of the present invention.

[0024] Figure 14 This describes one or more stages of an example of a method for manufacturing a capacitor bank structure according to some embodiments of the present invention.

[0025] Figure 15 This describes one or more stages of an example of a method for manufacturing a capacitor bank structure according to some embodiments of the present invention.

[0026] Figure 16 This describes one or more stages of an example of a method for manufacturing a capacitor bank structure according to some embodiments of the present invention.

[0027] Figure 17 This describes one or more stages of an example of a method for manufacturing a capacitor bank structure according to some embodiments of the present invention.

[0028] Figure 18 This describes one or more stages of an example of a method for manufacturing a capacitor bank structure according to some embodiments of the present invention.

[0029] Figure 19 This describes one or more stages of an example of a method for manufacturing a capacitor bank structure according to some embodiments of the present invention.

[0030] Figure 20 This describes one or more stages of an example of a method for manufacturing a capacitor bank structure according to some embodiments of the present invention.

[0031] Figure 21 This describes one or more stages of an example of a method for manufacturing a capacitor bank structure according to some embodiments of the present invention.

[0032] Figure 22 This describes one or more stages of an example of a method for manufacturing a capacitor bank structure according to some embodiments of the present invention.

[0033] Figure 23 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0034] Figure 24 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0035] Figure 25 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0036] Figure 26 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0037] Figure 27 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0038] Figure 28This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0039] Figure 29 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0040] Figure 30 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0041] Figure 31 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0042] Figure 32 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0043] Figure 33 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0044] Figure 34 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0045] Figure 35 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0046] Figure 36 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0047] Figure 37 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0048] Figure 38 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0049] Figure 39 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0050] Figure 40 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0051] Figure 41 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0052] Figure 42 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0053] Figure 43 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0054] Figure 44 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0055] Figure 45 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0056] Figure 46 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0057] Figure 47 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0058] Figure 48 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0059] Figure 49 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0060] Figure 50 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0061] Figure 51 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0062] Figure 52 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0063] Figure 53 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0064] Figure 54 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0065] Figure 55 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0066] Figure 56 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0067] Figure 57 This describes one or more stages of an example of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention. Detailed Implementation

[0068] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. Embodiments of the invention will be readily understood from the detailed description taken in conjunction with the accompanying drawings.

[0069] The following discloses numerous different embodiments or instances providing various features for implementing the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of the invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, references to the formation of a first feature on or on a second feature may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features are formed or disposed between the first and second features such that the first and second features do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0070] In comparative packaging structures, capacitors, such as decoupling capacitors, can be positioned as close as possible to the semiconductor die or hot spot to increase their effectiveness. That is, the capacitor can be mounted on one side of the semiconductor die, on a substrate pad, or embedded in the substrate. These three types are described below. In the first type, the capacitor mounted on the side of the semiconductor die is called a "Die Side Capacitor (DSC)". The capacitor and semiconductor die are mounted side-by-side to the substrate. While DSCs are easy to package, the disadvantages are long current paths and excessive area wastage. In the second type, the capacitor embedded within the substrate is called an "Embedded Capacitor (ECC)". While ECCs offer better performance than DSCs, the substrate housing an ECC is relatively thick. Furthermore, the assembly cost of ECCs can be relatively high. In the third type, the capacitor mounted on a land pad on the bottom surface of the substrate is called a "Land Side Capacitor (LSC)". While LSCs do not have the thickness and cost issues compared to ECCs, LSCs reduce the number of solder balls. In addition, LSC increases the size of the solder balls.

[0071] At least some embodiments of the present invention provide a semiconductor package structure comprising at least one capacitor disposed between a semiconductor device and a conductive structure. This shortens the decoupling loop and increases the ball-mount area on the bottom surface of the conductive structure.

[0072] Figure 1 A cross-sectional view of a capacitor bank structure 1 according to some embodiments of the present invention is shown. The capacitor bank structure 1 may include one or more capacitors 12, protective material 13 (e.g., including a first protective material 13a and a second protective material 13b), a first dielectric layer 14, a plurality of first pillars 15, a plurality of conductive pads 16, a second dielectric layer 17, a third dielectric layer 18, a plurality of second pillars 19, and a plurality of conductive pillars 11.

[0073] Capacitors 12 are arranged side-by-side. Capacitors 12 can be either double-sided decoupling capacitors or single-sided decoupling capacitors. For example... Figure 1As shown, each of the capacitors 12 is a two-sided decoupling capacitor and has a first surface 121 and a second surface 122 opposite to the first surface 121, and includes a plurality of first electrodes 123 and a plurality of second electrodes 124. The first electrodes 123 are disposed adjacent to the first surface 121 of the capacitor 12 for external connection, and the second electrodes 124 are disposed adjacent to the second surface 122 of the capacitor 12 for external connection. That is, both sides of the capacitor 12 (e.g., the first surface 121 and the second surface 122) can be used for electrical connection. Furthermore, the first surface 121 is electrically connected to the second surface 122. Therefore, the first electrodes 123 on the first surface 121 can be electrically connected to the second electrodes 124 on the second surface 122. It should be noted that the number of first electrodes 123 may be equal to or different from the number of second electrodes 124. Additionally, each of the first electrodes 123 has a first surface 1231 and a sidewall 1233, and each of the second electrodes 124 has a sidewall 1243. The thickness of each of the capacitors 12 may be less than 50 μm or less than 30 μm.

[0074] The conductive pad 16 is electrically connected to the second electrode 124 of the capacitor 12. In some embodiments, the conductive pad 16 may be a copper layer and may further include at least one surface-trimmed layer (e.g., a nickel (Ni) layer 161 and a gold (Au) layer 162). The Au layer 162 of the surface-trimmed layer of the conductive pad 16 is connected or bonded to the second electrode 124 of the capacitor 12 via a solder layer 125. Figure 1 As shown, each of the conductive pads 16 has a second surface 164 and a sidewall 163.

[0075] Protective material 13 covers capacitor 12, the sidewall 1233 of the first electrode 123, the sidewall 1243 of the second electrode 124, and the sidewall 163 of the conductive pad 16. For example... Figure 1 As shown, protective material 13 may be located between the first dielectric layer 14 and the second dielectric layer 17. Protective material 13 also has a first surface 131 corresponding to a first surface 121 of capacitor 12 and a second surface 132 corresponding to a second surface 122 of capacitor 12. The first surface 131 of protective material 13 may contact the first dielectric layer 14, and the second surface 132 of protective material 13 may contact the second dielectric layer 17. In some embodiments, protective material 13 may include an underfill and / or a molding compound. Figure 1As shown, the protective material 13 may comprise a first protective material 13a and a second protective material 13b. The first protective material 13a covers the sidewalls 1243 of the capacitor 12 and the second electrode 124, as well as the sidewalls 163 of the conductive pad 16. The second protective material 13b covers the sidewalls 1233 of the first protective material 13b and the first electrode 123. The material of the first protective material 13a may be the same as or different from the material of the second protective material 13b. In some embodiments, the material of the first protective material 13a may be an underfill, and the material of the second protective material 13b may be a molding compound 13b. The first protective material 13a may have a first surface 131a and a second surface 132a opposite to the first surface 131a. The first surface 131a of the first protective material 13a may be substantially coplanar with the first surface 121 of the capacitor 12. The second protective material 13b may have a first surface 131b and a second surface 132b opposite to the first surface 131b. A portion of the second protective material 13b is disposed between the first surface 131a of the first protective material 13a and the first dielectric layer 14. The first surface 131b of the second protective material 13b is the first surface 131 of the protective material 13. The second surface 132b of the second protective material 13b and the second surface 132a of the first protective material 13a constitute the second surface 132 of the protective material 13.

[0076] Conductive supports 11 are positioned around the capacitor 12 and extend through the protective material 13. For example... Figure 1 As shown, conductive struts 11 are disposed around the capacitor 12 and the first protective material 13a of the protective material 13, and extend through the second protective material 13b of the protective material 13. Conductive struts 11 may be disposed between the first dielectric layer 14 and the third dielectric layer 18, and extend through the second dielectric layer 17. Each of the conductive struts 11 has a first surface 111 and a second surface 112 opposite to the first surface 111. Figure 1 As shown, the first surface 1231 of the first electrode 123, the first surface 111 of the conductive pillar 11 and the first surface 131 of the protective material 13 are substantially coplanar with each other.

[0077] A first dielectric layer 14 (e.g., a passivation layer) is disposed on a first surface 131 of the protective material 13 and defines a plurality of openings 141 to expose the first electrode 123 and the conductive pillar 11. The first dielectric layer 14 may comprise or be formed of a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) containing a photoinitiator, or a combination of two or more of these. A first pillar 15 is disposed in the openings 141 of the first dielectric layer 14 and protrudes from the first dielectric layer 14. Therefore, the first pillar 15 contacts the first surface 1231 of the first electrode 123 and the first surface 111 of the conductive pillar 11.

[0078] A second dielectric layer 17 (e.g., a passivation layer) is disposed on the second surface 132 of the protective material 13 and covers the sidewalls 163 of the conductive pad 16 and the sidewalls of the conductive pillar 11. The second dielectric layer 17 has a first surface 171 and a second surface 172 opposite to the first surface 171. Figure 1 As shown, the second surface 164 of the conductive pad 16, the second surface 112 of the conductive pillar 11, and the second surface 172 of the second dielectric layer 17 are substantially coplanar with each other. The second dielectric layer 17 may comprise or be formed of a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) containing a photoinitiator, or a combination of two or more of these.

[0079] A third dielectric layer 18 (e.g., a passivation layer) is disposed on the second dielectric layer 17 and defines a plurality of openings 181 to expose the conductive pad 16 and the conductive pillar 11. The third dielectric layer 18 may comprise or be formed of a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) containing a photoinitiator, or a combination of two or more of these. A second pillar 19 is disposed in the openings 181 of the third dielectric layer 18 and protrudes from the third dielectric layer 18. Therefore, the second pillar 19 contacts the second surface 164 of the conductive pad 16 and the second surface 112 of the conductive pillar 11. Figure 1 As shown, some of the second pillars 19 can be electrically connected to some of the first pillars 15 via the conductive pad 16, Ni layer 161, Au layer 162, solder layer 125, second electrode 124, capacitor 12, and first electrode 123. Additionally, some of the second pillars 19 can be electrically connected to some of the first pillars 15 via the conductive pillar 11.

[0080] Figure 2A cross-sectional view of a capacitor bank structure 1a according to some embodiments of the present invention is shown. Figure 2 The capacitor bank structure 1a can be similar to Figure 1 The capacitor bank structure 1 differs in that the conductive strut 11 is omitted and the protective material 13 can consist of either a first protective material 13a or a second protective material 13b. For example... Figure 2 As shown, the first surface 131a of the first protective material 13a is the first surface 131 of the protective material 13, and the second surface 132a of the first protective material 13a is the second surface 132 of the protective material 13.

[0081] Figure 3 A cross-sectional view of a capacitor bank structure 1b according to some embodiments of the present invention is shown. Figure 3 The capacitor bank structure 1b can be similar to Figure 1 The capacitor bank structure 1 differs in that the conductive support 11 is omitted. For example... Figure 3 As shown, the second surface 132b of the second protective material 13b is disposed on the first surface 131a of the first protective material 13a. The first surface 131b of the second protective material 13b is the first surface 131 of the protective material 13, and the second surface 132a of the first protective material 13a is the second surface 132 of the protective material 13.

[0082] Figure 4 A cross-sectional view of a semiconductor package structure 2 according to some embodiments of the present invention is shown. The semiconductor package structure 2 includes a conductive structure 24, a semiconductor device 25, one or more capacitors 12, an encapsulant 26, multiple outer pillars 27, a top package 3, multiple inner pillars 28, a redistribution circuit structure 29, a wiring structure 4, and multiple solder bumps 37.

[0083] The conductive structure 24 may be a substrate or an interposer, and may have a top surface 241 and a bottom surface 242 opposite to the top surface 241. In some embodiments, the conductive structure 24 may include four dielectric layers 243 (e.g., four passivation layers) and four metal circuit layers 244 electrically connected to each other. The semiconductor device 25 may be a semiconductor logic die, such as a central processing unit (CPU), graphics processing unit (GPU), or application processor (AP), and may be electrically connected to the top surface 241 of the conductive structure 24. Figure 4 As shown, the semiconductor device 25 has a first surface 251 and a second surface 252 opposite to the first surface 241. The first surface 251 of the semiconductor device 25 is electrically connected to the top surface 241 of the conductive structure 24 via a redistribution circuit structure 29, a capacitor bank structure 1a, and an internal support 28. The second surface 252 of the semiconductor device 25 is adhered to the wiring structure 4. The capacitor bank structure 1a may be the same as... Figure 2 The capacitor bank structure 1a may include one or more capacitors 12. Therefore, the capacitor 12 is disposed between the first surface 251 of the semiconductor device 25 and the top surface 241 of the conductive structure 24. A first electrode 123 is electrically connected to the conductive structure 24. A second electrode 124 is electrically connected to the semiconductor device 25 via a solder layer 125, a Ni layer 161, an Au layer 162, a conductive pad 16, a second pillar 19, a conductive pad 281, and a redistribution circuit structure 29. The capacitor 12 is not embedded in the conductive structure 24. The area of ​​the capacitor bank structure 1a, viewed from a top view, is smaller than the area of ​​the semiconductor device 25, viewed from a top view. An internal pillar 28 is disposed outside the capacitor bank structure 1a and electrically connected to the semiconductor device 25 and the conductive structure 24.

[0084] A redistribution circuit structure 29 (e.g., including a first passivation layer 291, a second passivation layer 294, and a redistribution layer (RDL) 293) is disposed between the semiconductor device 25 and the capacitor bank structure 1a (including the capacitor 12). The size of the redistribution circuit structure 29 may be substantially equal to the size of the semiconductor device 25. Internal pillars 28 may stand on the redistribution circuit structure 29. Furthermore, the redistribution layer (RDL) 293 may include a fiducial mark 296. However, in some embodiments, the redistribution circuit structure 29 may be omitted.

[0085] Encapsulation 26 is disposed in the space between wiring structure 4 and conductive structure 24 to cover semiconductor device 25, capacitor bank structure 1a (including capacitor 12), conductive structure 24, internal support 28, and redistribution circuit structure 29. The material of encapsulation 26 may be a molding compound.

[0086] An external support 27 is disposed around the semiconductor device 25 and extends through the encapsulation 26 to electrically connect the wiring structure 4 and the conductive structure 24. The wiring structure 4 is disposed between the encapsulation 26 and the top package 3. The wiring structure 4 includes at least one dielectric layer and at least one circuit layer 40. However, in some embodiments, the wiring structure 4 may be omitted.

[0087] The top package 3 is electrically connected to the external pillars 27 and the semiconductor device 25 via internal solder 35 and wiring structure 4. In one embodiment, the top package 3 includes a top substrate 30, one or more memory dies 32, and a top encapsulation 34. The memory dies 32 may be Synchronous Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Lower Power DDR (LPDDR), or High Bandwidth Memory (HBM). The memory dies 32 are electrically connected to the top substrate 30 via wire bonding. However, the memory dies 32 may also be electrically connected to the top substrate 30 via flip-chip bonding. The top encapsulation 34 covers the multiple memory dies 32 and the top substrate 30. Additionally, an intermediate encapsulation 36 may be included in the space between the top substrate 30 and the wiring structure 4 to cover and protect the internal solder 35. Furthermore, solder bumps 37 are disposed on the second surface 242 of the conductive structure 24 for external connectivity.

[0088] exist Figure 4 In the semiconductor package structure 2 described herein, capacitor 12 is disposed between semiconductor device 25 and conductive structure 24. Therefore, the decoupling loop can be shortened. Furthermore, the ball area of ​​the second surface 242 of conductive structure 24 can be increased because capacitor 12 is not attached to the second surface 242 of conductive structure 24. That is, more solder bumps 37 can be disposed on the second surface 242 of conductive structure 24. In addition, the number of capacitors 12 can be increased. Furthermore, capacitor bank structure 1a is a reconstitution structure, which can reduce the manufacturing time of semiconductor package structure 2 and improve the yield of semiconductor package structure 2.

[0089] Figure 5A cross-sectional view of a semiconductor package structure 2a according to some embodiments of the present invention is shown. Figure 5 The semiconductor packaging structure 2a can be similar to Figure 4 The semiconductor packaging structure 2 differs from the capacitor bank structure 1a in that it is... Figure 1 The capacitor bank structure 1 is replaced, and the internal support 28 is omitted. For example... Figure 5 As shown, the area of ​​the capacitor bank structure 1a, viewed from top view, is approximately equal to the area of ​​the semiconductor device 25, viewed from top view. Therefore, Figure 4 The internal support 28 is not necessary, and the conductive support 11 of the capacitor bank structure 1 is electrically connected to the redistributed circuit structure 29 (or semiconductor device 25) and the conductive structure 24. Additionally, a bottom filler 38 is formed between the capacitor bank structure 1 and the redistributed circuit structure 29 (or semiconductor device 25) to cover and protect the joint structure between them. The area of ​​the bottom filler 38, viewed from the top view, is approximately equal to the area of ​​the semiconductor device 25, viewed from the top view.

[0090] Figure 6 A cross-sectional view of a semiconductor package structure 2b according to some embodiments of the present invention is shown. Figure 6 The semiconductor packaging structure 2b can be similar to Figure 4The semiconductor package structure 2 is described below, with the following differences. An inner pillar 28 is disposed on a first surface 251 of the semiconductor device 25. An intermediate redistribution structure 43 (including a redistribution layer (RDL) 431) is disposed on the encapsulation 26 to electrically connect the inner pillar 28 and the outer pillar 27. A capacitor 12 is disposed on and electrically connected to the redistribution layer (RDL) 431 of the intermediate redistribution structure 43. Each of the capacitors 12b is a double-sided decoupling capacitor and has a first surface 121b and a second surface 122b opposite to the first surface 121b, and includes a plurality of first electrodes 123b and a plurality of second electrodes 124b. The first electrodes 123b are disposed adjacent to the first surface 121b of the capacitor 12b for external connection, and the second electrodes 124b are disposed adjacent to the second surface 122b of the capacitor 12b for external connection. That is, both sides of the capacitor 12b (e.g., the first surface 121b and the second surface 122b) are available for electrical connection. A bottom protective material 42 (e.g., a bottom filler) is disposed on the intermediate redistribution structure 43 to cover and protect the capacitor 12. It should be noted that the area of ​​the bottom protective material 42, viewed from top view, is larger than the area of ​​the semiconductor device 25, viewed from top view. An insulating layer 46 is formed or disposed on the intermediate redistribution structure 43 to cover the bottom protective material 42 and the sidewalls of the first electrode 123b of the capacitor 12b. A conductive structure 24 is disposed on the insulating layer 46 and electrically connected to the first electrode 123b of the capacitor 12b. Additionally, a plurality of external pillars 27' are disposed around the capacitor 12b and the bottom protective material 42 and electrically connect the intermediate redistribution structure 43 and the conductive structure 24.

[0091] Figure 7 A cross-sectional view of a semiconductor packaging structure 2c according to some embodiments of the present invention is shown. Figure 7 The semiconductor packaging structure 2c can be similar to Figure 4 The semiconductor package structure 2 differs in the position of capacitor 12c. For example... Figure 7 As shown, capacitor 12c is embedded in conductive structure 24. Additionally, the thickness of semiconductor device 25c can be approximately equal to the height of external support 27.

[0092] Figure 8 A cross-sectional view of a semiconductor package structure 2d according to some embodiments of the present invention is shown. Figure 8 The 2D semiconductor packaging structure can be similar to Figure 4 The semiconductor package structure 2 differs in the position of capacitor 12d. For example... Figure 8As shown, capacitor 12d is disposed between conductive structure 24 and wiring structure 4. Capacitor 12d is disposed around semiconductor device 25d. That is, capacitor 12d and semiconductor device 25d are disposed side-by-side. The thickness of semiconductor device 25d, the thickness of capacitor 12d, and the height of external support 27 can be substantially equal to each other.

[0093] Figure 9 A cross-sectional view of a semiconductor package structure 2e according to some embodiments of the present invention is shown. The semiconductor package structure 2e includes a photodiode (P-die) 50, an electrical die (E-die) 52, a plurality of capacitors 12e, a plurality of external pillars 27, an encapsulation 26, and a plurality of solder bumps 37. The electrical dies (E-dies), capacitors 12e, and external pillars 27 are electrically connected to the bottom surface of the photodiode (P-die) 50. That is, the electrical dies (E-dies) 52 and capacitors 12e are arranged side-by-side. The external pillars 27 are disposed around the electrical dies (E-dies) 52 and capacitors 12e. The encapsulation 26 covers the bottom surface of the photodiode (P-die) 50, the electrical dies (E-dies) 52, capacitors 12e, and external pillars 27. The external pillars 27 extend through the encapsulation 26 and are exposed from the bottom surface of the encapsulation 26. Solder bumps 37 are placed on the bottom surface of the envelope 26 and electrically connected to the external support 27.

[0094] Figure 10 A cross-sectional view of a semiconductor package structure 2f according to some embodiments of the present invention is shown. The semiconductor package structure 2f includes a conductive structure 24, a capacitor bank structure 1b, a semiconductor device 54, a memory die 56, an encapsulant 26, and a plurality of solder bumps 37. The capacitor bank structure 1b is disposed on or electrically connected to a first surface 241 of the conductive structure 24. The capacitor bank structure 1b may include a plurality of capacitors 12f, bridge dies 58, a plurality of pillars 62, and a protective material 60. The capacitors 12f and bridge dies 58 are disposed side-by-side and covered by the protective material 60. The pillars 62 extend through the protective material 60. The semiconductor device 54 and the memory die 56 are disposed on the capacitor bank structure 1b and electrically connected to the capacitors 12f and the bridge dies 58. Therefore, the capacitor bank structure 1b is disposed between the semiconductor device 54 and the memory die 56 and the conductive structure 24. The semiconductor device 54 is electrically connected to the memory die 56 via the bridge dies 58. Encapsulation 26 covers the first surface 241 of conductive structure 24, capacitor bank structure 1b, semiconductor device 54, and memory die 56. Solder bumps 37 are disposed on the second surface 242 of conductive structure 24.

[0095] Figure 11 A cross-sectional view of a semiconductor packaging structure 2g according to some embodiments of the present invention is shown. Figure 11 The semiconductor packaging structure 2g can be similar to Figure 10 The semiconductor package structure 2f differs in the positions of capacitor 12g and bridge die 58. For example... Figure 11 As shown, the bridge die 58 is embedded in the conductive structure 24, and the capacitor 12g is disposed on or electrically connected to the first surface 241 of the conductive structure 24. The encapsulant 26 covers the first surface 241 of the conductive structure 24, the capacitor 12g, the semiconductor device 54, and the memory die 56.

[0096] Figures 12 to 22 This invention describes a method for manufacturing a capacitor bank structure according to some embodiments of the present invention. In some embodiments, the method is used for manufacturing... Figure 1 The capacitor bank structure 1 is shown. See also... Figure 12 A first support carrier 20 and a second dielectric layer 17 are provided. The second dielectric layer 17 is disposed on the first support carrier 20 and defines a plurality of openings 171.

[0097] See Figure 13 Multiple conductive pads 16 and multiple conductive pillars 11 are formed in openings 171 of the second dielectric layer 17. The conductive pads 16 may include at least one surface-trimming layer (e.g., a Ni layer 161 and an Au layer 62) on their end faces. Figure 13 As shown, each of the conductive pads 16 has a second surface 164 and a sidewall 163.

[0098] See Figure 14 One or more capacitors 12 are electrically connected to a conductive pad 16. The capacitor 12 may be a two-sided decoupling capacitor. The capacitor 12 has a first surface 121 and a second surface 122 opposite to the first surface 121, and includes a plurality of first electrodes 123 and a plurality of second electrodes 124. The first electrodes 123 are disposed adjacent to the first surface 121 of the capacitor 12, and the second electrodes 124 are disposed adjacent to the second surface 122 of the capacitor 12. The second electrodes 124 of the capacitor 12 are connected to a surface trimming layer (e.g., a Ni layer 161 and an Au layer) of the conductive pad 16 via a solder layer 125. Additionally, each of the first electrodes 123 has a first surface 1231 and a sidewall 1233, and each of the second electrodes 124 has a sidewall 1243.

[0099] See Figure 15 and Figure 16 A protective material 13 (e.g., comprising a first protective material 13a and a second protective material 13b) is formed to cover the capacitor 12, the sidewall 1233 of the first electrode 123, the sidewall 1243 of the second electrode 124, and the sidewall 163 of the conductive pad 16. See also Figure 15 A first protective material 13a is formed to cover the sidewalls 1243 of the capacitor 12, the second electrode 124, and the sidewalls 163 of the conductive pad 16. See also Figure 16 A second protective material 13b is formed to cover the sidewalls 1233 of the first protective material 13a and the first electrode 123 and the sidewalls of the conductive pillar 11. The protective material 13 (comprising the first protective material 13a and the second protective material 13b) has a first surface 131 corresponding to the first surface 121 of the capacitor 12 and a second surface 132 corresponding to the second surface 122 of the capacitor 12.

[0100] See Figure 17 The second protective material 13b of the protective material 13 thins from the first surface 131 to expose the first electrode 123 and the conductive pillar 11. Meanwhile, the first surface 1231 of the first electrode 123, the first surface 111 of the conductive pillar 11 and the first surface 131 of the protective material 13 are substantially coplanar with each other.

[0101] See Figure 18 A first dielectric layer 14 is formed on a first surface 131 of the protective material 13. The first dielectric layer 14 defines a plurality of openings 141 to expose the first electrode 123 and the conductive pillar 11.

[0102] See Figure 19 Multiple first pillars 15 are formed in the openings 141 of the first dielectric layer 14. The first pillars 15 contact the first electrode 123 and the conductive pillars 11, and protrude from the first dielectric layer 14.

[0103] See Figure 20 The second support carrier 22 is attached to the first pillar 15 and the first dielectric layer 14 via an adhesive layer 221. Subsequently, the first support carrier 20 is removed.

[0104] See Figure 21 A third dielectric layer 18 is formed on the second dielectric layer 17. The third dielectric layer 18 defines a plurality of openings 181 to expose the conductive pad 16 and the conductive pillar 11.

[0105] See Figure 22 Multiple second pillars 19 are formed in openings 181 of the third dielectric layer 18. The second pillars 19 contact the conductive pads 16 and the conductive pillars 11, and protrude from the third dielectric layer 18. Subsequently, a singulation process is performed, and the second support carrier 22 and adhesive layer 221 are removed to form... Figure 1 1. Multiple capacitor bank structure.

[0106] Figures 23 to 36 This invention describes a method for manufacturing a semiconductor package structure according to some embodiments of the present invention. In some embodiments, the method is used to manufacture... Figure 4 Semiconductor package structure 2 is shown in the figure. See also Figure 23The wafer 5 includes a plurality of semiconductor devices 25. The semiconductor devices 25 may be logic dies, such as a central processing unit (CPU), a graphics processing unit (GPU), or an application processor (AP), and may have a first surface 251 and a second surface 252 opposite to the first surface 251.

[0107] See Figure 24 A first passivation layer 291 is formed on a first surface 251 of the semiconductor device 25 (e.g., the first surface of the wafer 5). The first passivation layer 291 defines a plurality of openings 292.

[0108] See Figure 25 A redistribution layer (RDL) 293 is formed in the opening 292 and on the first passivation layer 291. In some embodiments, the redistribution layer (RDL) 293 may include a reference mark 296.

[0109] See Figure 26 A second passivation layer 294 is formed on the re-laid layer (RDL) 293 and the first passivation layer 291. The second passivation layer 294 defines a plurality of openings 295 to expose portions of the re-laid layer (RDL) 293. At the same time, a re-laid structure 29 (including the first passivation layer 291, the re-laid layer (RDL) 293 and the second passivation layer 294) is formed.

[0110] See Figure 27 Multiple conductive pads 281 and multiple internal pillars 28 are formed in the opening 295 and on the re-fabricated layer (RDL) 293. At least one surface trimming layer may be present on the end face of the conductive pads 281.

[0111] See Figure 28 , Figure 2 The capacitor bank structure 1a is attached to the conductive pad 281. In one embodiment, a second pillar 19 of the capacitor bank structure 1a is connected to a surface trimming layer of the conductive pad 281. Therefore, the capacitor 12 is electrically connected to the semiconductor device 25. An inner pillar 28 is disposed around the capacitor bank structure 1a (containing the capacitor 12). It should be noted that the reference mark 296 of the redistribution layer (RDL) 293 can be used for positioning when the capacitor bank structure 1a is attached to the redistribution structure 29.

[0112] See Figure 29 Multiple assemblies 5a are formed by performing a single-part separation process on the wafer 5.

[0113] See Figure 30 A third support carrier 41 (or a first carrier) is provided. Subsequently, a wiring structure 4 (including at least one dielectric layer and at least one circuit layer 40) is formed on the third support carrier 41 (or the first carrier). Subsequently, a plurality of external pillars 27 are formed or attached to the wiring structure 4.

[0114] See Figure 31 The second surface 252 of the semiconductor device 25 of the assembly 5a is attached (or adhered) to the wiring structure 4 on the third support carrier 41 (or the first carrier). Meanwhile, the external support pillar 27 is disposed around the assembly 5a.

[0115] See Figure 32 An encapsulation 26 is formed to cover the assembly 5a (including the semiconductor device 25 and the capacitor 12) and the external support 27.

[0116] See Figure 33 The encapsulation 26 is thinned from its bottom surface by, for example, grinding. Meanwhile, the bottom surface of the encapsulation 26, the bottom surface of the outer pillar 27, the bottom surface of the inner pillar 28, and the bottom surface of the first pillar 15 are substantially coplanar with each other.

[0117] See Figure 34 A conductive structure 24 is formed or disposed on the encapsulation 26 to electrically connect the outer pillar 27, the first pillar 15, and the inner pillar 28. The conductive structure 24 has a top surface 241 and a bottom surface 242 opposite to the top surface 241. In some embodiments, the conductive structure 24 may include four dielectric layers 243 (e.g., four passivation layers) and four metal circuit layers 244 electrically connected to each other. The first surface 251 of the semiconductor device 25 is electrically connected to the top surface 241 of the conductive structure 24 via a redistribution circuit structure 29, a capacitor bank structure 1a, and the inner pillar 28. The capacitor 12 is not embedded in the conductive structure 24. Subsequently, a plurality of solder bumps 37 are formed on the second surface 242 of the conductive structure 24.

[0118] See Figure 35 The fourth support carrier 45 (or the second carrier) is attached to the second surface 242 of the conductive structure 24 via an adhesive layer 44. Subsequently, the third support carrier 41 (or the first carrier) is removed.

[0119] See Figure 36The top package 3 is electrically connected to the external pillar 27. In one embodiment, the top package 3 is electrically connected to the external pillar 27 and the semiconductor device 25 via internal solder 35 and wiring structure 4. In one embodiment, the top package 3 includes a top substrate 30, one or more memory dies 32, and a top encapsulation 34. The memory dies 32 may be synchronous random access memory (SRAM), dynamic random access memory (DRAM), low power DDR (LPDDR), or high bandwidth memory (HBM). The memory dies 32 are electrically connected to the top substrate 30 via wire bonding. However, the memory dies 32 may be electrically connected to the top substrate 30 via flip-chip bonding. The top encapsulation 34 covers multiple memory dies 32 and the top substrate 30. Additionally, an intermediate encapsulation 36 may be formed or disposed in the space between the top substrate 30 and the wiring structure 4 to cover and protect the internal solder 35. Subsequently, a single-step process is performed, and the fourth support carrier 45 (or the second carrier) and the adhesive layer 44 are removed to form Figure 4 Multiple semiconductor packaging structures 2.

[0120] Figures 37 to 46 This invention describes a method for manufacturing a semiconductor package structure according to some embodiments of the present invention. In some embodiments, the method is used to manufacture... Figure 5 The semiconductor package structure 2a shown in the figure. The initial stage of the illustrated process is the same as or similar to that of the semiconductor package structure 2a. Figures 23 to 26 The stages described in the text. Figure 37 Depicted in Figure 26 The stage following the stage described in the text.

[0121] See Figure 37 Multiple conductive pads 281 are formed in the opening 295 and on the re-laid layer (RDL) 293. A surface trimming layer may be present on the end face of the conductive pads 281.

[0122] See Figure 38 , Figure 1 The capacitor bank structure 1 is attached to the conductive pad 281. In one embodiment, the second pillar 19 and the conductive pillar 11 of the capacitor bank structure 1 are connected to the surface trimming layer of the conductive pad 281. Therefore, the capacitor 12 is electrically connected to the semiconductor device 25. Subsequently, a bottom filler 38 is formed in the space between the capacitor bank structure 1 and the redistributed circuit structure 29 (or the semiconductor device 25) to cover and protect the bonding structure between the capacitor bank structure 1 and the redistributed circuit structure 29 (or the semiconductor device 25).

[0123] See Figure 39 The wafer 5 is processed by a single-part separation process to form multiple assemblies 5b.

[0124] See Figure 40A third support carrier 41 (or a first carrier) is provided. Subsequently, a wiring structure 4 (including at least one dielectric layer and at least one circuit layer 40) is formed on the third support carrier 41 (or the first carrier). Subsequently, a plurality of external pillars 27 are formed or attached to the wiring structure 4.

[0125] See Figure 41 The second surface 252 of the semiconductor device 25 of the assembly 5b is attached (or adhered) to the wiring structure 4 on the third support carrier 41 (or the first carrier). Meanwhile, external pillars 27 are positioned around the assembly 5b.

[0126] See Figure 42 An encapsulation 26 is formed to cover the assembly 5b (containing the semiconductor device 25 and the capacitor 12) and the external support 27.

[0127] See Figure 43 The encapsule 26 is thinned from its bottom surface, for example, by grinding. Meanwhile, the bottom surface of the encapsule 26, the bottom surface of the outer support 27, and the bottom surface of the first support 15 are substantially coplanar with each other.

[0128] See Figure 44 A conductive structure 24 is formed or disposed on the encapsulation 26 to electrically connect the outer pillar 27 and the first pillar 15. The conductive structure 24 has a top surface 241 and a bottom surface 242 opposite to the top surface 241. The first surface 251 of the semiconductor device 25 is electrically connected to the top surface 241 of the conductive structure 24 via a redistribution circuit structure 29 and a capacitor bank structure 1. Subsequently, a plurality of solder bumps 37 are formed on the second surface 242 of the conductive structure 24.

[0129] See Figure 45 The fourth support carrier 45 (or the second carrier) is attached to the second surface 242 of the conductive structure 24 via an adhesive layer 44. Subsequently, the third support carrier 41 (or the first carrier) is removed.

[0130] See Figure 46 The top package 3 is electrically connected to the external pillar 27. In one embodiment, the top package 3 is electrically connected to the external pillar 27 and the semiconductor device 25 via an internal solder 35 and a wiring structure 4. Additionally, an intermediate encapsulant 36 may be formed or disposed in the space between the top substrate 30 and the wiring structure 4 to cover and protect the internal solder 35. Subsequently, a separation process is performed, and the fourth support carrier 45 (or the second carrier) and the adhesive layer 44 are removed to form... Figure 5 Multiple semiconductor packaging structures 2a.

[0131] Figures 47 to 57 This invention describes a method for manufacturing a semiconductor package structure according to some embodiments of the present invention. In some embodiments, the method is used to manufacture... Figure 6 The semiconductor package structure 2b shown. The initial stage of the illustrated process is the same as or similar to that of the semiconductor package structure 2b. Figures 23 to 26 The stages described in the text. Figure 47 Depicted in Figure 26 The stage following the stage described in the text.

[0132] See Figure 47 Multiple external supports 27 are formed on the wiring structure 4.

[0133] See Figure 48 The second surface 252 of the semiconductor device 25 is adhered to the wiring structure 4. External pillars 27 are disposed around the semiconductor device 25. Subsequently, a plurality of internal pillars 28 are formed on the first surface 251 of the semiconductor device 25. In some embodiments, the internal pillars 28 may be formed first on the first surface 251 of the semiconductor device 25; subsequently, the second surface 252 of the semiconductor device 25 is adhered to the wiring structure 4.

[0134] See Figure 49 Encapsulation 26 is formed to cover semiconductor device 25, wiring structure 4, internal support 28 and external support 27.

[0135] See Figure 50 The encapsulation 26 is thinned from its bottom surface, for example, by grinding. Meanwhile, the bottom surface of the encapsulation 26, the bottom surface of the outer support 27, and the bottom surface of the inner support 28 are substantially coplanar with each other.

[0136] See Figure 51 An intermediate re-fabricated structure 43 (including a re-fabricated layer (RDL) 431) is formed or disposed on the encapsulation 26 to electrically connect the outer support 27 and the inner support 28.

[0137] See Figure 52 At least one capacitor 12b is disposed on and electrically connected to the intermediate redistribution structure 43. The second electrode 124b of the capacitor 12b is electrically connected to the redistribution layer (RDL) 431 of the intermediate redistribution structure 43. Thus, the capacitor 12b is electrically connected to the semiconductor device 25 and the outer pillars 27. Subsequently, a bottom protective material 42 (e.g., a bottom filler) is formed or disposed on the intermediate redistribution structure 43 to cover and protect the capacitor 12b. It should be noted that the area of ​​the bottom protective material 42, viewed from top view, is larger than the area of ​​the semiconductor device 25, viewed from top view. Subsequently, a plurality of outer pillars 27' are formed or disposed on the redistribution layer (RDL) 431 of the intermediate redistribution structure 43. The outer pillars 27' are disposed around the capacitor 12b and the bottom filler 42.

[0138] See Figure 53An insulating layer 46 is formed or disposed on the intermediate re-fabricated structure 43 to cover the bottom protective material 42, the sidewall of the first electrode 123b of the capacitor 12b, and the external support 27'.

[0139] See Figure 54 The insulating layer 46 is thinned from its bottom surface, for example, by grinding. Meanwhile, the bottom surface of the insulating layer 46, the bottom surface of the first electrode 124b of the capacitor 12b, and the bottom surface of the outer support 27' are substantially coplanar with each other.

[0140] See Figure 55 The conductive structure 24 is formed or disposed on the insulating layer 46 and electrically connected to the first electrode 123b of the capacitor 12b and the outer pillar 27'. In one embodiment, the conductive structure 24 may include four dielectric layers 243 and four metal circuit layers 244. Subsequently, a plurality of solder bumps 37 are formed on the second surface 242 of the conductive structure 24.

[0141] See Figure 56 The fourth support carrier 45 (or the second carrier) is attached to the second surface 242 of the conductive structure 24 via an adhesive layer 44. Subsequently, the third support carrier 41 (or the first carrier) is removed.

[0142] See Figure 57 The top package 3 is electrically connected to the external pillar 27. In one embodiment, the top package 3 is electrically connected to the external pillar 27 and the semiconductor device 25 via an internal solder 35 and a wiring structure 4. Additionally, an intermediate encapsulant 36 may be formed or disposed in the space between the top substrate 30 and the wiring structure 4 to cover and protect the internal solder 35. Subsequently, a separation process is performed, and the fourth support carrier 45 (or the second carrier) and the adhesive layer 44 are removed to form... Figure 6 Multiple semiconductor packaging structures 2b.

[0143] Unless otherwise stated, spatial descriptions such as "above," "below," "up," "left," "right," "down," "top," "bottom," "vertical," "horizontal," "side," "above," "below," "upper part," "above," "below," etc., indicate relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, the limitation being that the advantages of the embodiments of the invention are that they will not deviate from such arrangements.

[0144] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms can refer to a situation in which the event or situation has clearly occurred or is very close to occurring. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation less than or equal to ±10% of a second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first numerical value can be considered “generally” the same as or equal to the second numerical value. For example, "generally" vertical can refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0145] If the displacement between two surfaces does not exceed 5 µm, 2 µm, 1 µm, or 0.5 µm, then the two surfaces are considered to be coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is not greater than 5 µm, 2 µm, 1 µm, or 0.5 µm, then the surface is considered to be substantially flat.

[0146] As used herein, unless the context clearly indicates otherwise, the singular terms “a” and “the” may include multiple indicators.

[0147] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to transfer electric current. Conductive materials typically indicate those that exhibit very little or no resistance to current flow. One measure of conductivity is Siemens per meter (S / m). Generally, conductive materials are those with a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0148] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0149] While the invention has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations may not necessarily be drawn to scale. Artistic representations in this disclosure may differ from actual devices due to manufacturing methods and limitations. Other embodiments of the invention may exist that are not specifically described. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the invention.

Claims

1. A capacitor bank structure, comprising: A capacitor comprising a plurality of first electrodes and a plurality of second electrodes opposite to the plurality of first electrodes; Multiple conductive pads electrically connected to the capacitor; A first protective material covers the sidewalls of the capacitor and the plurality of conductive pads; as well as A second protective material covers the first protective material and the sidewalls of the first electrode, wherein the material of the first protective material is different from the material of the second protective material.

2. The capacitor bank structure according to claim 1, wherein the side surface of the first protective material and the side surface of the second protective material are not parallel.

3. The capacitor bank structure according to claim 2, wherein the first protective material has a first surface and a second surface opposite to the first surface, the second surface of the first protective material is closer to the plurality of conductive pads than the first surface of the first protective material, and the first protective material tapers along a direction from the second surface toward the first surface.

4. The capacitor bank structure according to claim 3, wherein the second surface of the first protective material contacts the plurality of conductive pads.

5. The capacitor bank structure of claim 3, wherein the plurality of conductive pads are exposed from the second surface of the first protective material.

6. The capacitor bank structure according to claim 1, wherein the second protective material simultaneously covers the plurality of first electrodes and the plurality of second electrodes.

7. The capacitor bank structure according to claim 1, wherein the second protective material simultaneously covers the plurality of first electrodes and the plurality of conductive pads.

8. The capacitor bank structure according to claim 1, wherein the second protective material covers the side of the first protective material.

9. The capacitor bank structure according to claim 1, wherein the surface of the second protective material is flush with the surface of the plurality of first electrodes.

10. The capacitor bank structure according to claim 1, wherein the thickness of the plurality of first electrodes is different from that of the plurality of second electrodes.

11. The semiconductor packaging structure according to claim 1, wherein the thickness of the first protective material is less than the thickness of the second protective material.

12. A semiconductor package structure comprising: A capacitor comprising a plurality of first electrodes and a plurality of second electrodes opposite to the plurality of first electrodes; The circuit structure is redistributed, spaced apart from the capacitor, and electrically connected to the plurality of first electrodes; as well as An encapsulation covering the fabric circuit structure and the capacitor.

13. The semiconductor packaging structure of claim 12, wherein the encapsulant continuously covers the side and top surfaces of the capacitor.

14. The semiconductor packaging structure according to claim 12, further comprising: A conductive structure, wherein the capacitor is located between the redistributed circuit structure and the conductive structure, wherein the conductive structure is electrically connected to the plurality of second electrodes, and wherein the encapsulation covers the conductive structure.

15. The semiconductor package structure of claim 14, wherein the conductive structure is spaced apart from the capacitor.

16. The semiconductor package structure of claim 14, wherein the spacing between the capacitor and the redistributed circuit structure is different from the spacing between the capacitor and the conductive structure.

17. The semiconductor packaging structure according to claim 14, further comprising: A conductive support is arranged side-by-side with the capacitor and positioned between the redistribution circuit structure and the conductive structure, wherein the height of the conductive support is greater than the thickness of the capacitor.

18. The semiconductor packaging structure according to claim 17, further comprising: Multiple conductive pads are disposed between the redistributed circuit structure and the multiple second electrodes to electrically connect the redistributed circuit structure and the multiple second electrodes, wherein the conductive pillars horizontally overlap the multiple first electrodes, the multiple second electrodes and the multiple conductive pads.

19. The semiconductor package structure of claim 18, wherein the top surface of the conductive pillar is flush with the top surface of the plurality of conductive pads.

20. A method for manufacturing a semiconductor package structure, comprising: (a) A semiconductor device is provided with at least one capacitor and a plurality of external pillars, wherein the at least one capacitor has a first surface and a second surface opposite to the first surface, and the external pillars are disposed around the semiconductor device; as well as (b) A conductive structure is formed on the at least one capacitor and the external support, wherein the at least one capacitor is disposed between the semiconductor device and the conductive structure.

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