Method for performing multiple analog-to-digital conversions

Abstract

A method of multiple analog-to-digital conversions by an analog-to-digital convertor (ADC) is provided, comprising: receiving a first ramp reference signal and a second ramp reference signal, the level of the first ramp reference signal varying from an initial level along a slope within each cycle of the first ramp reference signal, the level of the second ramp reference signal following the first ramp reference signal with a given offset from the level of the first ramp reference signal; comparing the second ramp reference signal with an input analog signal; sampling the level of the first ramp reference signal when the second ramp reference signal reaches the analog input signal, resetting the level of the second ramp reference signal to the level sampled from the first ramp reference signal after the sampling; generating a digital signal from the comparison result, wherein the comparison, the sampling and the resetting are performed multiple times within the each cycle of the first ramp reference signal, and the comparison after the resetting is performed using the reset second ramp reference signal.

Description

TECHNICAL FIELD

[0001] The present application relates to an analog-to-digital convertor (ADC), and in particular, to a multiple conversion ADC. The present application also relates to an image sensor for generating a digital image, such as a still image or a moving image, and a device having the image sensor, such as a mobile device or a digital camera. BACKGROUND

[0002] In recent years, mobile devices such as mobile phones, smartphones, wireless communication terminals, tablet devices, or personal computers have a photographing function. Mobile devices or digital cameras are equipped with an image sensor, such as a complementary metal-oxide-semiconductor (CMOS) image sensor or a charge coupled device (CCD) image sensor.

[0003] An image sensor includes a plurality of pixels that output analog signals each of which has a signal level corresponding to an intensity of incident light, and a plurality of ADCs for converting the output analog signals into digital signals.

[0004] A single slope ADC (SS ADC) is a type of ADC. The SS ADC causes a comparator to compare a ramp reference signal having a ramp waveform with an analog signal output from a pixel, and outputs a digital signal according to an output signal of the comparator. In the SS ADC, temporal noise such as quantization and input noise can be reduced, and power consumption can be reduced and a smaller silicon area can be achieved.

[0005] With respect to the SS ADC, U.S. Patent No. 8,816,893 proposes multiple conversion ADCs that convert an analog signal into a digital signal multiple times, and output an average value of the conversion results within each period of a ramp reference signal. By using a multiple conversion process, quantization noise and noise in an analog signal can be effectively reduced.

[0006] A multiple conversion ADC is further described below with reference to FIGS. 10 and 11. FIG. 10 is a schematic circuit diagram for describing an ADC provided by the related art. FIG. 11 is a timing chart for describing a multiple conversion process provided by the related art. The ADC 90 shown in FIG. 10 is an example of a multiple conversion ADC provided by the related art.

[0007] As shown in FIG. 10, an analog signal is fed to a negative (-) input terminal of a comparator through a capacitor CO. A ramp reference signal is fed to a positive (+) input terminal of the comparator through capacitors CI and C2. The ramp reference signal is modified by resetting a level of the ramp reference signal in response to on / off switching of a switch SW1. In FIG. 10, the ramp reference signal after the reset is denoted as "modified ramp reference signal".

[0008] The on / off switching of the switch SW1 is controlled in accordance with a ramp control signal output from a control circuit according to an output of the comparator. For example, when the modified ramp reference signal is equal to or lower than an input pixel signal, the control circuit performs the on / off switching in response to a Hi level signal output from the comparator.

[0009] In the example shown in FIG. 11, the level of the ramp reference signal is reset once in a portion denoted as "large signal sampling", and the waveform of the ramp reference signal is modified to a waveform having two sawtooth waves. In this portion, AD conversion is performed once. In a portion denoted as "small signal sampling", the level of the ramp reference signal is reset five times, and the waveform of the ramp reference signal is modified to a waveform having six sawtooth waves. In this portion, AD conversion is performed six times.

[0010] A conversion counter calculates a number of times of AD conversion performed within each cycle of the ramp reference signal according to an output of the comparator. A summing counter calculates a number of pulses of the master clock when the output of the comparator is at a LO level. An arithmetic operator calculates an average value according to a count value of the summing counter and a count value of the conversion counter. By averaging, quantization noise and input noise can be reduced. However, a conversion rate of the ADC 90 is lower than a conversion rate of a conventional SS ADC that performs single-time AD conversion within each cycle of the ramp reference signal. SUMMARY

[0011] Embodiments provide an ADC, an image sensor, a mobile device or a digital camera, and the like, and a method for multiple analog-digital conversion. The mobile device can be a mobile phone, a smartphone, a wireless communication terminal, a tablet device, a personal computer, and the like, and the mobile device and the digital camera can generate digital image data such as image data or video data.

[0012] A first aspect of embodiments provides a method of performing multiple analog-digital conversion by an ADC. In a first possible implementation form of the first aspect, the method comprises:

[0013] receiving a first ramp reference signal and a second ramp reference signal, a level of the first ramp reference signal varying from an initial level along a slope within each cycle of the first ramp reference signal, the second ramp reference signal following the first ramp reference signal with a given offset from the level of the first ramp reference signal;

[0014] comparing the second ramp reference signal with the input analog signal;

[0015] When the second ramp reference signal reaches the analog input signal, sampling the level of the first ramp reference signal, and after the sampling, resetting the level of the second ramp reference signal to the level sampled from the first ramp reference signal;

[0016] A digital signal is generated according to the comparison result, wherein the comparison, the sampling, and the resetting are performed multiple times within each cycle of the first ramp reference signal, and the comparison after the resetting is performed using the reset second ramp reference signal.

[0017] In a first possible implementation of the first aspect, AD conversion is performed multiple times within a single cycle of the first ramp reference signal, with the level sampled from the first ramp reference signal in the previous AD conversion serving as the starting point for the reset second ramp reference signal. For example, if the level of the ramp reference signal decreases monotonically along the slope, the level of the reset second ramp reference signal decreases from the level sampled from the first ramp reference signal. On the other hand, if the level of the ramp reference signal increases monotonically along the slope, the level of the reset second ramp reference signal increases from the level sampled from the first ramp reference signal. According to this configuration, the amplitude of the second ramp reference signal is reduced by resetting, so that the reset second ramp reference signal can reach the input analog signal in a short time. This configuration reduces the time required for AD conversion, thereby effectively increasing the number of AD conversions without reducing the AD conversion speed. Increasing the number of AD conversions can improve the signal-to-noise ratio of the digital signal and the quality of the output image based on the digital signal.

[0018] A second possible implementation of the first aspect provides the method provided by the first possible implementation of the first aspect, wherein the given offset is determined based on temporal noise in the input analog signal, the first reference signal, and the second reference signal, and input-referenced noise of a comparator that performs the comparison. According to the second possible implementation of the first aspect, the reset can be ensured even in the presence of the temporal noise and the input-referenced noise.

[0019] A third possible implementation of the first aspect provides the method provided by the second possible implementation of the first aspect, wherein the given offset is set to a value greater than all peak-to-peak amplitudes of the temporal noise. According to the third possible implementation of the first aspect, the reset can be ensured when the temporal noise is present in the input analog signal and the first and second reference signals.

[0020] A fourth possible implementation of the first aspect provides the method provided by the second or third possible implementation of the first aspect, wherein the first reference signal is fed to the comparator via a capacitive element, and the second reference signal serves as a clamping voltage for the capacitive element. According to the fourth possible implementation of the first aspect, a level sampled from the first ramp reference signal can be maintained in the capacitive element when the second ramp reference signal reaches the analog input signal.

[0021] A fifth possible implementation of the first aspect provides the method provided by any one of the first to fourth possible implementations of the first aspect, wherein, within each cycle of the first ramp reference signal, the level of the first ramp reference signal decreases from the initial level, and the polarity of the given offset is set to negative. When decreasing signals are used as the first ramp reference signal and the second ramp reference signal, the fifth possible implementation of the first aspect may be preferably applied.

[0022] A sixth possible implementation of the first aspect provides the method provided by any one of the first to fourth possible implementations of the first aspect, wherein, within each cycle of the first ramp reference signal, the level of the first ramp reference signal is increased from the initial level, and the polarity of the given offset is set to positive. When increasing signals are used as the first ramp reference signal and the second ramp reference signal, the sixth possible implementation of the first aspect may be preferably applied.

[0023] A seventh possible implementation of the first aspect provides the method provided by any one of the first to sixth possible implementations of the first aspect, wherein the ADC is connected to other ADCs via a common reference line so as to distribute the first reference signal and the second reference signal to the ADC and the other ADCs, and the generation of the ADC is suspended within a predetermined period after at least one of the ADC and the other ADCs is reset.

[0024] Typically, an image sensor includes multiple ADCs electrically connected to each other via a common ramp reference line to transmit a ramp reference signal. If an on / off switch is performed to reset the ramp reference signal, the on / off switch may generate a transient current. This transient current, due to its parasitic resistance, causes switching noise in the common ramp reference line. This switching noise interferes with the ramp reference signals propagating to other ADCs via the common ramp reference line, acting as crosstalk noise. This crosstalk noise may cause comparison errors in the comparators of the other ADCs, reducing the quality of the digital image ultimately output by the image sensor.

[0025] According to a seventh possible implementation of the first aspect, the generation of the ADC is suspended within the predetermined period after the reset, thereby avoiding comparison errors in the comparison and achieving a high-quality digital image ultimately output from the image sensor.

[0026] An eighth possible implementation of the first aspect provides the method provided by any one of the first to seventh possible implementations of the first aspect, wherein the receiving includes: receiving the second ramp reference signal from a ramp generator, and generating the first ramp reference signal based on the received second ramp reference signal. According to the eighth possible implementation of the first aspect, the first ramp reference signal and the second ramp reference signal may be generated by a single ramp generator.

[0027] A ninth possible implementation of the first aspect provides the method provided by any one of the first to seventh possible implementations of the first aspect, wherein the receiving includes: receiving the first ramp reference signal from a ramp generator, and generating the second ramp reference signal based on the received first ramp reference signal. According to an eighth possible implementation of the first aspect, the first ramp reference signal and the second ramp reference signal may be generated by a single ramp generator.

[0028] A tenth possible implementation of the first aspect provides the method provided by any one of the first to ninth possible implementations of the first aspect, wherein the generating comprises: retaining the comparison result in each AD conversion, averaging the retained comparison results within each cycle of the first ramp reference signal, and determining the digital signal based on the average result. According to the tenth possible implementation of the first aspect, quantization noise and input noise can be reduced by averaging the retained comparison results.

[0029] A second aspect of the embodiment provides an analog-to-digital converter (ADC) that performs multiple analog-to-digital conversions. In a first possible implementation of the second aspect, the ADC includes:

[0030] a receiving circuit configured to receive a first ramp reference signal and a second ramp reference signal, wherein the level of the first ramp reference signal changes along a slope from an initial level in each cycle of the first ramp reference signal, and the level of the second ramp reference signal follows the first ramp reference signal at a given offset from the level of the first ramp reference signal;

[0031] a comparing unit, configured to compare the second ramp reference signal with an input analog signal;

[0032] a reset unit, configured to sample the level of the first ramp reference signal when the second ramp reference signal reaches the analog input signal, and after the sampling, reset the level of the second ramp reference signal to the level sampled from the first ramp reference signal;

[0033] A generating unit is configured to generate a digital signal according to the result of the comparison, wherein the comparison, the sampling, and the resetting are performed multiple times within each cycle of the first ramp reference signal, and the comparison after the reset is performed using the reset second ramp reference signal.

[0034] In a first possible implementation of the second aspect, AD conversion is performed multiple times within a single cycle of the first ramp reference signal, with the level sampled from the first ramp reference signal in the previous AD conversion serving as the starting point for the reset second ramp reference signal. For example, if the level of the ramp reference signal decreases monotonically along the slope, the level of the reset second ramp reference signal decreases from the level sampled from the first ramp reference signal. On the other hand, if the level of the ramp reference signal increases monotonically along the slope, the level of the reset second ramp reference signal increases from the level sampled from the first ramp reference signal. According to this configuration, the amplitude of the second ramp reference signal is reduced by resetting, so that the reset second ramp reference signal can reach the input analog signal in a short time. This configuration reduces the time required for AD conversion, thereby effectively increasing the number of AD conversions without reducing the AD conversion speed. Increasing the number of AD conversions can improve the signal-to-noise ratio of the digital signal and the quality of the output image based on the digital signal.

[0035] A second possible implementation of the second aspect provides the ADC provided by the first possible implementation of the second aspect, wherein the given offset is determined based on temporal noise in the input analog signal, the first reference signal, and the second reference signal, and input-referenced noise of a comparator that performs the comparison. According to the second possible implementation of the second aspect, the reset can be ensured even in the presence of the temporal noise and the input-referenced noise.

[0036] A third possible implementation of the second aspect provides the ADC provided by the second possible implementation of the second aspect, wherein the given offset is set to a value greater than all peak-to-peak amplitudes of the temporal noise. According to the third possible implementation of the second aspect, the reset can be ensured when the temporal noise is present in the input analog signal and the first and second reference signals.

[0037] A fourth possible implementation of the second aspect provides the ADC provided by the second or third possible implementation of the second aspect, wherein the first reference signal is fed to the comparison unit via a capacitive element, and the second reference signal serves as a clamping voltage for the capacitive element. According to the fourth possible implementation of the second aspect, a level sampled from the first ramp reference signal can be maintained in the capacitive element when the second ramp reference signal reaches the analog input signal.

[0038] A fifth possible implementation of the second aspect provides the ADC provided by any one of the first to fourth possible implementations of the second aspect, wherein, within each cycle of the first ramp reference signal, the level of the first ramp reference signal decreases from the initial level, and the polarity of the given offset is set to negative. When decreasing signals are used as the first ramp reference signal and the second ramp reference signal, the fifth possible implementation of the second aspect may be preferably applied.

[0039] A sixth possible implementation of the second aspect provides the ADC provided by any one of the first to fourth possible implementations of the second aspect, wherein, within each cycle of the first ramp reference signal, the level of the first ramp reference signal is increased from the initial level, and the polarity of the given offset is set to positive. When increasing signals are used as the first ramp reference signal and the second ramp reference signal, the sixth possible implementation of the second aspect may be preferably applied.

[0040] A seventh possible implementation of the second aspect provides the ADC provided by any one of the first to sixth possible implementations of the second aspect, wherein the ADC is connected to other ADCs via a common reference line so as to distribute the first reference signal and the second reference signal to the ADC and the other ADCs, and the generation of the ADC is suspended for a predetermined period after at least one of the ADC and the other ADCs is reset. According to the seventh possible implementation of the second aspect, the generation of the ADC is suspended for the predetermined period after the reset, thereby avoiding comparison errors in the comparison and achieving a high-quality digital image ultimately output from the image sensor.

[0041] An eighth possible implementation of the second aspect provides the ADC provided by any one of the first to seventh possible implementations of the second aspect, wherein, during the receiving, the receiving unit receives the second ramp reference signal from a ramp generator and generates the first ramp reference signal based on the received second ramp reference signal. According to the eighth possible implementation of the second aspect, the first ramp reference signal and the second ramp reference signal may be generated by a single ramp generator.

[0042] A ninth possible implementation manner of the second aspect provides the ADC of any one of the first to seventh possible implementation manners of the second aspect, wherein in the receiving, the receiving unit receives the first ramp reference signal from a ramp generator, and generates the second ramp reference signal according to the received first ramp reference signal. According to the eighth possible implementation manner of the second aspect, the first ramp reference signal and the second ramp reference signal can be generated by a single ramp generator.

[0043] A tenth possible implementation manner of the second aspect provides the ADC of any one of the first to ninth possible implementation manners of the second aspect, wherein in the generating, the generating unit retains the comparison result in each AD conversion, averages the retained comparison results in each period of the first ramp reference signal, and determines the digital signal according to the average result. According to the tenth possible implementation manner of the second aspect, quantization noise and input noise can be reduced by averaging the retained results of the comparison.

[0044] A third aspect of the embodiment provides an image sensor, comprising: a plurality of pixels configured to generate analog signals according to intensities of incident light, and analog-to-digital converters (ADCs), each of which is identical to the ADC of any one of the first to tenth possible implementation manners of the second aspect, wherein the ADCs convert the analog signals output from the plurality of pixels into digital signals.

[0045] According to the third aspect, the time required for AD conversion is reduced, and the number of AD conversions can be effectively increased without reducing the AD conversion speed. Increasing the number of AD conversions can improve the signal-to-noise ratio of the digital signal and the quality of the output image based on the digital signal.

[0046] A fourth aspect of the embodiment provides a device equipped with a camera function, the device comprising: an optical system; an image sensor comprising a plurality of pixels configured to generate analog signals according to intensities of incident light passing through the optical system, and analog-to-digital converters (ADCs), each of which is identical to the ADC of any one of the first to tenth possible implementation manners of the second aspect, wherein the ADCs convert the analog signals output from the plurality of pixels into digital signals; and a signal processing circuit configured to generate image data according to the digital signals.

[0047] According to the fourth aspect, the time required for AD conversion is reduced, and the number of AD conversions can be effectively increased without reducing the AD conversion speed. Increasing the number of AD conversions can improve the signal-to-noise ratio of the digital signal and the quality of the output image based on the digital signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a schematic block diagram for describing an apparatus provided by an embodiment of the present invention;

[0049] Figure 2 is a schematic diagram for describing an image sensor provided by an embodiment of the present invention;

[0050] Figure 3 This is a schematic block diagram for describing the functions of an ADC in a multiple AD conversion circuit provided by an embodiment of the present invention;

[0051] Figure 4 is a schematic circuit diagram for describing the structure of a multi-step AD conversion circuit provided by an embodiment of the present invention;

[0052] Figure 5 is a timing diagram for describing the operation of the multiple AD conversion circuit provided by an embodiment of the present invention;

[0053] Figure 6 is a schematic circuit diagram for describing the structure of an ADC in an image sensor provided by a first variation of an embodiment of the present invention;

[0054] Figure 7 is a timing chart for describing the operation of the multi-step AD conversion circuit provided by the first variation of the embodiment of the present invention;

[0055] Figure 8 is a schematic circuit diagram for describing the structure of an ADC in an image sensor provided by a second variation of an embodiment of the present invention;

[0056] Figure 9 is a schematic circuit diagram for further describing the structure of an ADC in an image sensor provided by a second variation of an embodiment of the present invention;

[0057] FIG10 is a schematic circuit diagram for describing an AD converter provided by the related art;

[0058] FIG. 11 is a timing diagram for describing a modification of a RAMP reference signal provided by the related art. DETAILED DESCRIPTION

[0059] The technical solutions of the embodiments are described below with reference to the drawings. It can be understood that the embodiments described below are not all, but only some embodiments related to the present application. It should be noted that those skilled in the art can deduce other embodiments within the scope of the present application without creative labor on the basis of the embodiments described below.

[0060] Figure 1 is a schematic block diagram for describing the apparatus provided by the embodiments of the present application. Figure 1 The apparatus 10 shown is an example of the apparatus provided by the embodiments of the present application.

[0061] The apparatus 10 can be a mobile device with a camera function, a digital camera, etc. The mobile device can be a mobile phone, a smartphone, a wireless communication terminal, a tablet device, a personal computer, etc.

[0062] As shown in Figure 1 The apparatus 10 includes a lens 10a, an image sensor 10b, a processing circuit 10c, and a memory 10d.

[0063] The lens 10a is an optical system that guides incident light to the image sensor 10b. The optical system can include a plurality of optical lenses, and at least one of the plurality of optical lenses can be used for auto focus and / or optical image stabilization. The image sensor 10b performs photoelectric conversion to convert light passing through the lens 10a into an electrical signal, and performs analog-to-digital conversion to convert the electrical signal into a digital signal. The digital signal output from the image sensor 10b is fed to the processing circuit 10c.

[0064] The processing circuit 10c can be at least one processing unit, such as an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), a field-programmable gate array (FPGA), or a general-purpose processor. In some examples, the processing circuit 10c can be implemented by hardware, imaging-specific hardware, etc.

[0065] The processing circuit 10c generates image data based on the digital signal and stores the image data in the memory 10d. When generating the image data, the processing circuit 10c may compress and / or encode the digital signal according to any compression and / or encoding technique standardized by a working group (e.g., the Joint Photographic Experts Group (JPEG), the Moving Picture Experts Group (MPEG), etc.). The processing circuit 10c may store the digital signal as raw data in the memory 10d.

[0066] The image sensor provided by the embodiments of the present invention is described below. Figure 2 is a schematic diagram for describing an image sensor provided by an embodiment of the present invention. Figure 2 The image sensor 10b shown is a possible implementation of the image sensor provided by the embodiment of the present invention.

[0067] like Figure 2 As shown, the image sensor 10b includes a control circuit 11, a pixel array 12, and a plurality of AD conversion circuits 13. The control circuit 11 controls the pixel array 12 and the plurality of AD conversion circuits 13.

[0068] The pixel array 12 includes a plurality of columns, each column having a plurality of pixels. Figure 2 Only two columns 12a and 12b are shown, but pixel array 12 may include hundreds or thousands of columns. Figure 2 For simplicity, columns 12a and 12b each have only four pixels, but each column of pixel array 12 may include hundreds or thousands of pixels. Each pixel outputs an analog signal based on the intensity of incident light. The analog signal output from each pixel is fed to a multi-step A / D conversion circuit 13.

[0069] The multi-AD conversion circuit 13 includes ADCs 13 a and 13 b corresponding to the columns 12 a and 12 b , respectively. Figure 2 Only two ADCs (ADC 13a and 13b) are shown, but the multi-AD conversion circuit 13 may include hundreds or thousands of ADCs. Hereinafter, the analog signal output from column 12a may be referred to as a "first pixel signal," and the analog signal output from column 12b may be referred to as a "second pixel signal."

[0070] The first pixel signal is fed to ADC 13a, and the second pixel signal is fed to ADC 13b. ADC 13a performs AD conversion on the first pixel signal to generate a first digital signal, and ADC 13b performs AD conversion on the second pixel signal to generate a second digital signal. The first and second digital signals are fed to processing circuit 10c.

[0071] The function of the ADC in the multi-step AD conversion circuit 13 is described below. Figure 3 1 is a schematic block diagram for describing the functions of the ADC in the multi-step AD conversion circuit provided by an embodiment of the present invention. The ADCs in the multi-step AD conversion circuit 13 may have substantially the same structure and functions, so ADC 13a is described below as an example of the ADC in the multi-step AD conversion circuit 13.

[0072] like Figure 3 As shown, the ADC 13a includes a ramp generator 301, a receiving unit 302, a reset unit 303, a comparison unit 304 and a generation unit 305. Figure 3 In FIG. 1 , the ramp generator 301 is arranged in the ADC 13 a , but the ramp generator 301 may be arranged outside the ADC 13 a in the multi-time AD conversion circuit 13 .

[0073] The ramp generator 301 may generate a first ramp reference signal, the level of which changes along a slope from a given initial level within each cycle of the first ramp reference signal. Furthermore, the ramp generator 301 may generate a second ramp reference signal, the level of which follows the first ramp reference signal at a given offset from the level of the first ramp reference signal.

[0074] The given offset can be determined based on the temporal noise in the first pixel signal, the temporal noise of the first reference signal and the second reference signal, and the input reference noise of the comparator in ADC 13a. For example, the given offset can be a value greater than all peak-to-peak amplitudes of the temporal noise.

[0075] If the level of the first ramp reference signal decreases from the initial level in each cycle of the first ramp reference signal, the polarity of the given offset is set to negative. In this case, the level of the first ramp reference signal is greater than the level of the second ramp reference signal.

[0076] Alternatively, if the level of the first ramp reference signal increases from the initial level in each cycle of the first ramp reference signal, the polarity of the given offset is set to positive. In this case, the level of the first ramp reference signal is less than the level of the second ramp reference signal.

[0077] The receiving unit 302 receives a first ramp reference signal and a second ramp reference signal from the ramp generator 301. In one possible variation, the receiving unit 302 may receive only the second ramp reference signal from the ramp generator 301 and generate the first ramp reference signal based on the received second ramp reference signal. Alternatively, the receiving unit 302 may receive only the first ramp reference signal from the ramp generator 301 and generate the second ramp reference signal based on the received first ramp reference signal.

[0078] The reset unit 303 receives the first ramp reference signal and the second ramp reference signal from the receiving unit 302. In the first AD conversion, the reset unit 303 may input the received second ramp reference signal to the comparison unit 304. The comparison unit 304 compares the second ramp reference signal with the first pixel signal output from the column 12a.

[0079] When the comparison result of comparison unit 304 indicates that the second ramp reference signal has reached the analog input signal, reset unit 303 samples the level of the first ramp reference signal. After sampling the level of the first ramp reference signal, reset unit 303 resets the level of the second ramp reference signal to the level sampled from the first ramp reference signal. The reset second ramp reference signal is fed to comparison unit 304 and used for the following AD conversion.

[0080] In the ADC 13 a , the comparison process of the comparison unit 304 and the sampling and resetting processes of the reset unit 303 are performed multiple times within each cycle of the first ramp reference signal.

[0081] In the first AD conversion, the second ramp reference signal received from receiving unit 302 is used in the comparison process. The first reference signal is used to determine a reset level, which indicates the starting point of the second ramp reference signal reset in the subsequent AD conversion. In the subsequent AD conversion, the reset second ramp reference signal is used in the comparison process. Comparison, sampling, and resetting are repeated within each cycle of the first ramp reference signal.

[0082] The generation unit 305 generates a digital signal based on the comparison result output from the comparison unit 304. For example, the generation unit 305 may retain the comparison result output from the comparison unit 304 in each AD conversion, average the retained comparison results output from the comparison unit 304 within a single cycle of the first ramp reference signal, and determine the digital signal based on the average result.

[0083] According to the above configuration of ADC 13a, the amplitude of the second ramp reference signal is reduced by resetting, so that the reset second ramp reference signal can reach the first pixel signal in a shorter time. This can reduce the time required for AD conversion and increase the number of AD conversions without reducing the AD conversion speed. Increasing the number of AD conversions can improve the signal-to-noise ratio of the digital signal and the quality of the image data.

[0084] ADC 13a is connected to ADC 13b and other ADCs in multi-ADC circuit 13 via a common reference line to distribute the first and second reference signals. To avoid comparison errors caused by crosstalk noise on the common reference line, ADC 13a can pause to generate digital signals for a predetermined period after at least one ADC resets the second ramp reference signal. This improves image data quality.

[0085] A specific example of the structure of the multi-AD conversion circuit provided by an embodiment of the present invention is described below.

[0086] Figure 4 1 is a schematic circuit diagram for describing the structure of a multi-step AD conversion circuit provided by an embodiment of the present invention. For simplicity, only ADCs 13a and 13b in the multi-step AD conversion circuit 13 are described below, assuming that the level of the first pixel signal is set to be greater than the level of the second pixel signal.

[0087] like Figure 4 As shown, the multi-AD conversion circuit 13 includes switches 101, 102, 103, 104, 201, 202, 203 and 204, buffer amplifiers 105 and 205, capacitors 106, 107, 108, 206, 207 and 208, comparators 109 and 209, conversion counters 110 and 210, counters 111 and 211 and average calculators 112 and 212.

[0088] The first portion including switches 101, 102, 103, and 104, buffer amplifier 105, capacitors 106, 107, and 108, comparator 109, conversion counter 110, counter 111, and average calculator 112 corresponds to ADC 13a. The second portion including switches 201, 202, 203, and 204, buffer amplifier 205, capacitors 206, 207, and 208, comparator 209, conversion counter 210, counter 211, and average calculator 212 corresponds to ADC 13b.

[0089] exist Figure 4 In FIG, “V1” and “V2” represent the voltage levels of the first pixel signal and the second pixel signal, respectively. “Vramp1” and “Vramp2” represent the voltage levels of the first reference signal and the second reference signal, respectively. “Vmod1” and “Vmod2” represent the modified voltage levels of the second reference signals of ADCs 13 a and 13 b, respectively. “COMP1” and “COMP2” are output signals representing the comparison results of comparators 109 and 209, respectively.

[0090] In this example, Vramp2 is reduced from a given initial level, and Vramp1 is set to have a higher voltage level than Vramp2. Furthermore, Vramp1 is reduced at exactly the same rate as Vramp2. The voltage difference (dV) between Vramp1 and Vramp2 is designed to be sufficiently large for the temporal noise in the input pixel signal and the input reference noise of the comparator in the multi-pass AD conversion circuit 13. For example, dV can be set to 1.7 mV. Hereinafter, dV may be referred to as "offset voltage."

[0091] The first pixel signal (V1) is fed to the negative (–) input terminal of comparator 109, and Vmod1 is fed to the positive (+) input terminal of comparator 109 via capacitor 108. Comparator 109 compares V1 and Vmod1. Since Vramp2 is not modified in the first AD conversion, comparator 109 compares V1 and Vramp2 in the first AD conversion. In the subsequent AD conversion, Vramp2 is modified, and comparator 109 compares V1 with Vmod1 corresponding to the modified Vramp2 in ADC 13a. Vramp1 is used to determine the reset level of Vmod1.

[0092] Comparator 109 outputs COMP1 at HI when V1 is equal to or lower than Vmod1, or at LO when V1 is higher than Vmod1. COMP1 is fed to switches 101 and 104, conversion counter 110, and counter 111.

[0093] Conversion counter 110 counts the number of pulses of COMP1 within one cycle of the ramp reference signal and outputs data representing a first value (N1a) indicating the count result to average calculator 112. Counter 111 counts the number of pulses of the main clock (CLK) fed to counter 111 when the level of COMP1 is LOW and outputs data representing a second value (N2a) indicating the count result to average calculator 112. Average calculator 112 divides N2a by N1a to calculate an average value corresponding to the first digital signal.

[0094] In a similar manner, the second pixel signal (V2) is fed to the negative (-) input terminal of the comparator 209, Vmod2 is fed to the positive (+) input terminal of the comparator 209 through the capacitor 208, and the comparator 209 compares V2 and Vmod2. Since Vramp2 is not modified in the first AD conversion, the comparator 209 compares V2 and Vramp2 in the first AD conversion. In the subsequent AD conversions, Vramp2 is modified, and the comparator 209 compares V2 with Vmod2 corresponding to the modified Vramp2 in the ADC 13b. Vramp1 is used to determine the reset level of Vmod2.

[0095] The comparator 209 outputs COMP2 at a level of HI (high) when V2 is equal to or lower than Vmod2, or at a level of LO (low) when V2 is higher than Vmod2. COMP2 is fed to the switches 201 and 204, the conversion counter 210, and the counter 211.

[0096] The conversion counter 210 counts the number of pulses of COMP2 in one period of the ramp reference signal, and outputs data indicating a first value (N1b) indicative of the count result to the average calculator 212. The counter 211 counts the number of pulses of CLK fed to the counter 211 when COMP2 is at a level of LO, and outputs data indicating a second value (N2b) indicative of the count result to the average calculator 212. The average calculator 212 divides N2b by N1b to calculate an average value corresponding to the second digital signal.

[0097] The operation of the multiple AD conversion circuit 13 and Figure 5 the timing chart shown below is further described. Figure 5 is a timing chart for describing the operation of the multiple AD conversion circuit provided by the embodiment of the present application.

[0098] In Figure 5 the example shown, the pixel reset duration for resetting the image sensor 10b starts at time T1, and the image output duration for generating image data starts at time T6. At timing T1, the pixel reset pulse (PIX_RESET) goes high, and the pixels are reset according to PIX_RESET. During the pixel reset duration, a given pixel reset level (Vreset) appears on each input signal line (IN). The information indicating Vreset can be stored in the memory 10d.

[0099] At timing T1, the control circuit 11 controls switches 102, 104, 201, and 204 to turn on and then off to start the first AD conversion. Based on this on / off operation, the offset voltage is sampled and held in capacitors 108 and 208, thereby resetting capacitors 108 and 208. After resetting capacitors 108 and 208, the first AD conversion begins by lowering Vramp2.

[0100] At timing T2, Vramp2 reaches Vreset, and each of the comparators 109 and 209 turns its output HI. Each of the conversion counters 110 and 210 counts to 1, and the counters 111 and 211 pause to count the number of CLK pulses. At timing T2, the control circuit 11 controls the switches 101 and 201 to open. After the switches 101 and 201 are opened, Vmod1 equivalent to (Vramp_init+dV) is retained in each of the capacitors 106 and 206, where Vramp_init represents the input signal level (Vreset) sampled only when Vramp2 reaches Vreset.

[0101] At timing T3, the control circuit 11 controls the switches 103 and 203 to be turned on to reset each of Vmod1 and Vmod2 to (Vramp_init+dV) held in the capacitors 106 and 206. In response to the reset, each of the comparators 109 and 209 changes its output to LO.

[0102] At timing T4, the control circuit 11 controls the switches 103 and 203 to be turned off to start the second AD conversion. After the switches 103 and 203 are turned off, the nodes having Vmod1 and Vmod2 are AC-coupled to Vramp2, so that Vmod1 and Vmod2 follow Vramp2.

[0103] At timing T5, Vmod1 and Vmod2 reach Vreset, and each of the comparators 109 and 209 turns its output HI. Each of the conversion counters 110 and 210 counts to 2, and the counters 111 and 211 pause to count the number of CLK pulses. In the subsequent AD conversion, the AD conversion operation is performed in the same manner as the second AD conversion.

[0104] If the resolution of the AD conversion is 10 bits, four AD conversions are performed in the first cycle of the ramp reference signal, and dV is equal to n LSB (LSB = n*Vramp1 / 2 10 ), each of the average calculators 112 and 212 generates average digital data (Dav) given by the following equation:

[0105] Dav = {D1 + (D1 - n + D2) + (D1 - n + D3) + (D1 - n + D4)} / 4,

[0106] where Dk (k = 1, 2, 3, 4) represents the number of CLK pulses counted by each of the counters 111 and 211 during the k-th AD conversion. The pixel reset level is set to Dav output from each of the average calculators 112 and 212 for the pixel reset duration, and used for the image output duration.

[0107] At timing T6, the pixel transfer pulse (PIX TRANS) goes high to initiate the first AD conversion for the image output duration, VI appears on the input signal line (IN) of the ADC 13a, and V2 appears on the input signal line (IN) of the ADC 13b. At timing T7, Vmodl and Vmod2 start to decrease from (Vramp_init + dV) held in each of the capacitors 106 and 206.

[0108] At timing T10, Vramp2 reaches VI, the comparator 109 changes its output to HI. The counter 111 stops counting the number of pulses of CLK, and the conversion counter 110 counts 1. At timing T10, the switch 101 is turned off so that Vrampl equivalent to (Vramp_init_pixl + dV) is held in the capacitor 106, where Vramp_init_pixl represents the input signal level (VI) sampled only when Vramp2 reaches VI.

[0109] At timing Tll, the control circuit 11 controls the switch 103 to turn on to reset Vmodl to (Vramp_init_pixl + dV) held in the capacitor 106. In response to the reset, the comparator 109 changes its output to LO.

[0110] At timing T12, the control circuit 11 controls the switch 103 to turn off to initiate the second AD conversion for VI. After the switch 103 is turned off, the node AC with Vmodl is AC-coupled to Vramp2 so that Vmodl follows Vramp2.

[0111] At timing T13, Vmodl reaches VI, and the comparator 109 changes its output to HI. The conversion counter 110 counts 2, and the counter 111 is suspended to count the number of pulses of CLK.

[0112] At timing T14, the control circuit 11 controls the switch 103 to turn on, resetting Vmod1 to (Vramp_init_pix1 + dV). In response to the reset, the comparator 109 changes its output to LO. At timing T15, the control circuit 11 controls the switch 103 to turn off, starting the third AD conversion of V1. In the subsequent AD conversion of V1, the AD conversion operation is performed in the same manner as the second AD conversion.

[0113] At timing T20, Vramp2 reaches V2, and the comparator 209 turns its output HI. The counter 211 stops counting the number of CLK pulses, and the conversion counter 210 counts to 1. At timing T20, the switch 201 is turned off, so that Vramp1 equivalent to (Vramp_init_pix2+dV) is held in the capacitor 206, where Vramp_init_pix2 represents the input signal level (V2) sampled only when Vramp2 reaches V2.

[0114] At timing T21, the control circuit 11 controls the switch 203 to be turned on to reset Vmod2 to (Vramp_init_pix2+dV) held in the capacitor 206. In response to the reset, the comparator 209 changes its output to LO.

[0115] At timing T22, the control circuit 11 controls the switch 203 to be turned off to start the second AD conversion of V2. After the switch 203 is turned off, the node with Vmod2 is AC-coupled to Vramp2 so that Vmod2 follows Vramp2.

[0116] At timing T23, Vmod2 reaches V2, and the comparator 209 turns its output HI. The conversion counter 210 counts to 2, and the counter 211 pauses to count the number of pulses of CLK.

[0117] At timing T24, the control circuit 11 controls the switch 203 to turn on to reset Vmod2 to (Vramp_init_pix2+dV). In response to the reset, the comparator 209 changes its output to LO. At timing T25, the control circuit 11 controls the switch 203 to turn off to start the third AD conversion of V2. In the subsequent AD conversion of V2, the AD conversion operation is performed in the same manner as the second AD conversion.

[0118] exist Figure 5 In the example of , AD conversion of V1 is performed four times within the second cycle of the ramp reference signal. In this case, the average calculator 112 generates average digital data (Dav_pix1) given by the following equation:

[0119] Dav_pix1={D1_pix1+(D1_pix1–n+D2_pix1)+(D1_pix1–n+D3_pix1)+(D1_pix1–n+D4_pix1)} / 4,

[0120] Here, Dk_pix1 (k=1, 2, 3, 4) represents the number of CLK pulses counted by the counter 111 during the kth AD conversion period.

[0121] Similarly, in Figure 5 In the example of , AD conversion of V2 is performed three times within the second cycle of the ramp reference signal. In this case, the average calculator 212 generates average digital data (Dav_pix2) given by the following equation:

[0122] Dav_pix2={D1_pix2+(D1_pix2–n+D2_pix2)+(D1_pix2–n+D3_pix2)} / 3,

[0123] Here, Dk_pix2 (k=1, 2, 3) represents the number of CLK pulses counted by the counter 211 during the kth AD conversion period.

[0124] Dav is subtracted from Dav_pix1 and Dav_pix2 to suppress noise and fluctuations caused by the offset voltage of the buffer amplifiers 105 and 205. The offset voltage may be referred to as a "holding step voltage" that may appear in the capacitors 106 and 206 that hold Vramp1 and may cause a delay time in the comparators 109 and 209.

[0125] The first digital signal (D_pix1) is provided by the following equation:

[0126] D_pix1=Dav_pix1–Dav,

[0127] The second digital signal (D_pix2) is provided by the following equation:

[0128] D_pix2=Dav_pix2–Dav.

[0129] The above-described averaging and subtraction operations can reduce noise in the first digital signal and the second digital signal output from the ADCs 13a and 13b, respectively.

[0130] As described above, in ADC 13a, Vmod2 is reset to the reset level held in capacitor 106. Similarly, ADC 13b performs a reset operation based on the reset level held in capacitor 206. These reset operations can effectively reduce the time required for multiple AD conversions, effectively increasing the number of AD conversions without reducing the AD conversion speed. Increasing the number of AD conversions can improve the signal-to-noise ratio of the digital signal and the quality of the output image.

[0131] (First Modification) A specific example of the structure of a multi-step AD conversion circuit provided by a first modification of the embodiment of the present invention is described below.

[0132] Figure 6 This is a schematic circuit diagram for describing the structure of an ADC in an image sensor according to a first variation of an embodiment of the present invention. For simplicity, only ADCs 13a and 13b in multi-pass AD conversion circuit 13 are described below, assuming that the level of the first pixel signal is set to be greater than the level of the second pixel signal.

[0133] like Figure 6 As shown, the multi-time AD conversion circuit 13 includes switches 101, 102, 103, 104, 121, 201, 202, 203, 204, and 221, buffer amplifiers 105, 122, 205, and 222, capacitors 106, 107, 108, 123, 206, 207, 208, and 223, comparators 109 and 209, conversion counters 110 and 210, counters 111 and 211, average calculators 112 and 212, and a voltage power supply 120. That is, in the first modification, the voltage power supply 120, the switches 121 and 221, the buffer amplifiers 122 and 222, and the capacitors 123 and 223 are added to the multi-time AD conversion circuit 13, as shown in FIG. Figure 6 shown.

[0134] In the first modification, the first portion including switches 101, 102, 103, 104, and 121, buffer amplifiers 105 and 122, capacitors 106, 107, 108, and 123, comparator 109, conversion counter 110, counter 111, and average calculator 112 corresponds to ADC 13a. Furthermore, the second portion including switches 201, 202, 203, 204, and 221, buffer amplifiers 205 and 222, capacitors 206, 207, 208, and 223, comparator 209, conversion counter 210, counter 211, and average calculator 212 corresponds to ADC 13b.

[0135] In this example, an input offset level “Voffset” is fed to the first input terminal ( IN1 ), as Figure 6The voltage source 120 provides an offset voltage (dV) that raises Voffset to Vramp1, which is dV greater than Vramp2.

[0136] In this example, Vramp2 is reduced from a given initial level, and Vramp1 is set to a higher voltage level than Vramp2. Furthermore, Vramp1 is reduced at the exact same rate as Vramp2. dV is designed to be sufficiently large to avoid temporal noise in the input pixel signal and input reference noise of the comparator in the multi-pass A / D conversion circuit 13. Vramp1 is fed to switches 121 and 221.

[0137] The first pixel signal (V1) is fed to the negative (–) input terminal of comparator 109, and Vmod1 is fed to the positive (+) input terminal of comparator 109 via capacitor 108. Comparator 109 compares V1 and Vmod1. Since Vramp2 is not modified in the first AD conversion, comparator 109 compares V1 and Vramp2 in the first AD conversion. In the subsequent AD conversion, Vramp2 is modified, and comparator 109 compares V1 with Vmod1 corresponding to the modified Vramp2 in ADC 13a. Vramp1 is used to determine the reset level of Vmod1.

[0138] Comparator 109 outputs COMP1 at HI when V1 is equal to or lower than Vmod1, or at LO when V1 is higher than Vmod1. COMP1 is fed to switches 101 and 104, conversion counter 110, and counter 111.

[0139] Conversion counter 110 counts the number of pulses of COMP1 within one cycle of the ramp reference signal and outputs data representing a first value (N1a) indicating the count result to average calculator 112. Counter 111 counts the number of pulses of the main clock (CLK) fed to counter 111 when the level of COMP1 is LOW and outputs data representing a second value (N2a) indicating the count result to average calculator 112. Average calculator 112 divides N2a by N1a to calculate an average value corresponding to the first digital signal.

[0140] Similarly, the second pixel signal (V2) is fed to the negative (–) input terminal of comparator 209, and Vmod2 is fed to the positive (+) input terminal of comparator 209 via capacitor 208. Comparator 209 compares V2 with Vmod2. Since Vramp2 is not modified in the first AD conversion, comparator 209 essentially compares V2 with Vramp2 in the first AD conversion. In the subsequent AD conversion, Vramp2 is modified, and comparator 209 compares V2 with Vmod2, which corresponds to the modified Vramp2 in ADC 13b. Vramp1 is used to determine the reset level of Vmod2.

[0141] Comparator 209 outputs COMP2 at HI when V2 is equal to or lower than Vmod2, or at LO when V2 is higher than Vmod2. COMP2 is fed to switches 201 and 204, conversion counter 210, and counter 211.

[0142] Conversion counter 210 counts the number of COMP2 pulses within one cycle of the ramp reference signal and outputs data representing a first value (N1b) indicating the count result to average calculator 212. Counter 211 counts the number of CLK pulses fed to counter 211 when the COMP2 level is LOW and outputs data representing a second value (N2b) indicating the count result to average calculator 212. Average calculator 212 divides N2b by N1b to calculate an average value corresponding to the second digital signal.

[0143] The following further describes the operation of the multiple AD conversion circuit 13 and Figure 7 The timing diagram shown. Figure 7 is a timing chart for describing the operation of the multi-step AD conversion circuit provided by the first modification of the embodiment of the present invention.

[0144] exist Figure 7 In the example shown in FIG1 , the pixel reset duration for resetting image sensor 10b begins at time T1, and the image output duration for generating image data begins at time T6. At timing T1, the pixel reset pulse (PIX_RESET) goes high, and the pixels are reset according to PIX_RESET. During the pixel reset duration, a given reset level (Vreset) appears on each input signal line (IN). Information indicating Vreset can be stored in memory 10d.

[0145] At timing T1, the control circuit 11 controls switches 102, 104, 201, and 204 to turn on and then off, initiating the first AD conversion. This on / off operation samples the offset voltage and holds it in capacitors 108 and 208, thereby resetting capacitors 108 and 208. Furthermore, the control circuit 11 controls switches 121 and 221 to turn off, setting the voltage difference between the terminals of capacitors 123 and 223 to dV. After this voltage difference is established, multiple AD conversions are initiated, and the input levels of buffer amplifiers 122 and 222 begin to decrease at the same rate as Vramp2.

[0146] At timing T2, Vramp2 reaches Vreset, and each of the comparators 109 and 209 turns its output HI. Each of the conversion counters 110 and 210 counts to 1, and the counters 111 and 211 pause to count the number of CLK pulses. At timing T2, the control circuit 11 controls the switches 101 and 201 to open. After the switches 101 and 201 are opened, the output level of the buffer amplifiers 122 and 222 equivalent to (Vramp_init+dV) is held in each of the capacitors 106 and 206, where Vramp_init represents the input signal level (Vreset) sampled only when Vramp2 reaches Vreset.

[0147] At timing T3, the control circuit 11 controls the switches 103 and 203 to be turned on to reset each of Vmod1 and Vmod2 to (Vramp_init+dV) held in the capacitors 106 and 206. In response to the reset, each of the comparators 109 and 209 changes its output to LO.

[0148] At timing T4, the control circuit 11 controls the switches 103 and 203 to be turned off to start the second AD conversion. After the switches 103 and 203 are turned off, the nodes having Vmod1 and Vmod2 are AC-coupled to Vramp2, so that Vmod1 and Vmod2 follow Vramp2.

[0149] At timing T5, Vmod1 and Vmod2 reach Vreset, and each of the comparators 109 and 209 turns its output HI. Each of the conversion counters 110 and 210 counts to 2, and the counters 111 and 211 pause to count the number of CLK pulses. In the subsequent AD conversion, the AD conversion operation is performed in the same manner as the second AD conversion.

[0150] If the resolution of the AD conversion is 10 bits, four AD conversions are performed in the first cycle of the ramp reference signal, and dV is equal to n LSB (LSB = n*Vramp1 / 2 10), each of the average calculators 112 and 212 generates average digital data (Dav) given by the following equation:

[0151] Dav={D1+(D1–n+D2)+(D1–n+D3)+(D1–n+D4)} / 4,

[0152] Here, Dk (k=1, 2, 3, 4) represents the number of CLK pulses counted by each of the counters 111 and 211 during the k-th AD conversion. The pixel reset level is set to Dav output from each of the averaging calculators 112 and 212 during the pixel reset duration and is used during the image output duration.

[0153] At timing T6, the pixel transfer pulse (PIX_TRANS) goes high to start the first AD conversion within the image output duration, V1 appears on the input signal line (IN) of ADC 13a, and V2 appears on the input signal line (IN) of ADC 13b. At timing T7, Vmod1 and Vmod2 begin to decrease from (Vramp_init+dV) held in each of capacitors 106 and 206.

[0154] At timing T10, Vramp2 reaches V1, and the comparator 109 turns its output HI. The counter 111 stops counting the number of CLK pulses, and the conversion counter 110 counts to 1. At timing T10, the switch 101 is turned off, so that Vramp1 equivalent to (Vramp_init_pix1+dV) is held in the capacitor 106, where Vramp_init_pix1 represents the input signal level (V1) sampled only when Vramp2 reaches V1.

[0155] At timing T11, the control circuit 11 controls the switch 103 to be turned on to reset Vmod1 to (Vramp_init_pix1+dV) held in the capacitor 106. In response to the reset, the comparator 109 changes its output to LO.

[0156] At timing T12, the control circuit 11 controls the switch 103 to be turned off to start the second AD conversion of V1. After the switch 103 is turned off, the node with Vmod1 is AC-coupled to Vramp2 so that Vmod1 follows Vramp2.

[0157] At timing T13, Vmod1 reaches V1, and the comparator 109 changes its output to HI. The conversion counter 110 counts to 2, and the counter 111 pauses to count the number of pulses of CLK.

[0158] At timing T14, the control circuit 11 controls the switch 103 to turn on, resetting Vmod1 to (Vramp_init_pix1 + dV). In response to the reset, the comparator 109 changes its output to LO. At timing T15, the control circuit 11 controls the switch 103 to turn off, starting the third AD conversion of V1. In the subsequent AD conversion of V1, the AD conversion operation is performed in the same manner as the second AD conversion.

[0159] At timing T20, Vramp2 reaches V2, and the comparator 209 turns its output HI. The counter 211 stops counting the number of CLK pulses, and the conversion counter 210 counts to 1. At timing T20, the switch 201 is turned off, so that Vramp1 equivalent to (Vramp_init_pix2+dV) is held in the capacitor 206, where Vramp_init_pix2 represents the input signal level (V2) sampled only when Vramp2 reaches V2.

[0160] At timing T21, the control circuit 11 controls the switch 203 to be turned on to reset Vmod2 to (Vramp_init_pix2+dV) held in the capacitor 206. In response to the reset, the comparator 209 changes its output to LO.

[0161] At timing T22, the control circuit 11 controls the switch 203 to be turned off to start the second AD conversion of V2. After the switch 203 is turned off, the node with Vmod2 is AC-coupled to Vramp2 so that Vmod2 follows Vramp2.

[0162] At timing T23, Vmod2 reaches V2, and the comparator 209 turns its output HI. The conversion counter 210 counts to 2, and the counter 211 pauses to count the number of pulses of CLK.

[0163] At timing T24, the control circuit 11 controls the switch 203 to turn on to reset Vmod2 to (Vramp_init_pix2+dV). In response to the reset, the comparator 209 changes its output to LO. At timing T25, the control circuit 11 controls the switch 203 to turn off to start the third AD conversion of V2. In the subsequent AD conversion of V2, the AD conversion operation is performed in the same manner as the second AD conversion.

[0164] exist Figure 7 In the example of , AD conversion of V1 is performed four times within the second cycle of the ramp reference signal. In this case, the average calculator 112 generates average digital data (Dav_pix1) given by the following equation:

[0165] Dav_pix1={D1_pix1+(D1_pix1–n+D2_pix1)+(D1_pix1–n+D3_pix1)+(D1_pix1–n+D4_pix1)} / 4,

[0166] Here, Dk_pix1 (k=1, 2, 3, 4) represents the number of CLK pulses counted by the counter 111 during the kth AD conversion period.

[0167] Similarly, in Figure 7 In the example of , AD conversion of V2 is performed three times within the second cycle of the ramp reference signal. In this case, the average calculator 212 generates average digital data (Dav_pix2) given by the following equation:

[0168] Dav_pix2={D1_pix2+(D1_pix2–n+D2_pix2)+(D1_pix2–n+D3_pix2)} / 3,

[0169] Here, Dk_pix2 (k=1, 2, 3) represents the number of CLK pulses counted by the counter 211 during the kth AD conversion period.

[0170] Dav is subtracted from Dav_pix1 and Dav_pix2 to suppress noise and fluctuations caused by the offset voltage of the buffer amplifiers 105 and 205. The offset voltage may be referred to as a "holding step voltage" that may appear in the capacitors 106 and 206 that hold Vramp1 and may cause a delay time in the comparators 109 and 209.

[0171] The first digital signal (D_pix1) is provided by the following equation:

[0172] D_pix1=Dav_pix1–Dav,

[0173] The second digital signal (D_pix2) is provided by the following equation:

[0174] D_pix2=Dav_pix2–Dav.

[0175] The averaging and subtraction operations can reduce noise in the first digital signal and the second digital signal output from the ADCs 13a and 13b, respectively. In addition, the time required for multiple AD conversions can be effectively reduced.

[0176] (Second Modification) A specific example of the structure of a multi-time AD conversion circuit provided by a second modification of the embodiment of the present invention is described below.

[0177] Figure 8is a schematic circuit diagram for describing the structure of the ADC in the multiple AD conversion circuit provided by the second modification of the embodiment of the present application. For the sake of simplicity, hereinafter, only the ADC 13a in the multiple AD conversion circuit 13 is described.

[0178] As shown in Figure 8 , the ADC 13a includes switches 101, 102, 103, and 104, a buffer amplifier 105, capacitors 106, 107, 108, and 131, a comparator 109, a conversion counter 110, a counter 111, and an average calculator 112. The ADC 13a further includes a D-FF circuit 132, a NOR circuit 133, and AND circuits 134 and 135. That is, in the second modification, a part including the capacitor 131, the DFF circuit 132, the NOR circuit 133, and the AND circuits 134 and 135 is added to the ADC 13a, as shown in Figure 4 . Although VI is fed to the negative (-) input terminal of the comparator 109 through the capacitor 131, the added part works in a similar manner to the ADC 13a in Figure 4 . Therefore, hereinafter, mainly the D-FF circuit 132, the NOR circuit 133, and the AND circuits 134 and 135 are described.

[0179] In Figure 8 , "GATE_A" and "GATE_B" represent a gate clock, and "CLK_A" represents a control clock fed to each ADC in the multiple AD conversion circuit 13. CLK_A is a pulse signal such that one pulse appears every M pulses of CLK, where M is a predetermined value. If the AD conversion resolution of the ADC 13a is 10 bits, M can be set to 64 (64 = 1024 / 16). In this case, the maximum number of AD conversions within a single period of the ramp reference signal is set to "16".

[0180] As shown in Figure 8 , CLK is fed to an input terminal of the AND circuit 135, and CLK_A is fed to an input terminal of the NOR circuit 133 and an input terminal of the AND circuit 134. Further, an inverted signal of CLK_A is fed to the other input terminal of the AND circuit 135.

[0181] GATE_A is a signal obtained by gating the output of the DFF circuit 132 with CLK_A. GATE_A output from the AND circuit 134 is fed to the switch 103 and the conversion counter 110. GATE_B is output from the AND circuit 135 and fed to the clock terminal of the counter 111. COMP1 is output from the comparator 109 and fed to the switch 101, the enable terminal of the counter 111, the clock terminal of the DFF circuit 132, and the other input terminal of the NOR circuit 133.

[0182] The signal fed to the D input terminal of the DFF circuit 132 is uniformly HI, and the inverted signal output from the NOR circuit 133 is fed to the R input terminal of the DFF circuit 132. The signal output from the Q output terminal of the DFF circuit 132 is fed to the other input terminal of the AND circuit 134.

[0183] In the second modification, Vramp1 and Vramp2 supplied to the ADC in the multi-AD conversion circuit 13 are controlled according to GATE_B generated by CLK and CLK_A. For example, Figure 4 The ramp generation unit shown can supply Vramp1 and Vramp2 to the ADC in the multi-time AD conversion circuit 13 . Figure 9 is a schematic circuit diagram for further describing the structure of an ADC in an image sensor provided by a second variation of an embodiment of the present invention.

[0184] like Figure 9 As shown, the ramp generation unit includes ramp generators 141 and 142, and AND circuits 143 and 144. CLK is fed to an input terminal of each of AND circuits 143 and 144. An inverted signal of CLK_A is fed to the other input terminal of each of AND circuits 143 and 144. AND circuits 143 and 144 perform an AND operation on CLK and CLK_A, and output GATE_B to ramp generators 141 and 142, respectively. GATE_B is a series of pulses extracted from CLK when CLK_A is at the LOW level.

[0185] Ramp generator 141 generates Vramp1 that decreases from a given initial level and controls Vramp1 according to GATE_B so that the level of Vramp1 remains at the given initial level during the absence of GATE_B pulses. Similarly, ramp generator 142 generates and controls Vramp2 so that its level remains at the given initial level during the absence of GATE_B pulses.

[0186] According to the above configuration, comparator 109 changes its output to LOW in synchronization with the rise time of CLK_A, and counter 111 pauses to count the number of CLK pulses when CLK_A is HIGH. In other words, after the ramp reference signal is reset, AD conversion by ADC 13a is paused for a predetermined period corresponding to the pulse width of CLK_A. Therefore, switching noise generated when resetting the ramp reference signal does not affect the AD conversion by the ADC in multi-pass AD conversion circuit 13.

[0187] As described above, the ADCs in the multi-ADC circuit 13 operate based on the common ramp reference signal (Vramp1, Vramp2). When the ramp reference signal is reset by any ADC, switching noise can be transmitted through the common reference line. However, according to the second variation, each ADC suspends AD conversion during the duration of the CLK_A high level, thereby avoiding comparator errors caused by switching noise. This can improve the quality of the output image from the image sensor 10b.

[0188] As described above, the embodiments and their variations can reduce the time required for AD conversion, thereby effectively increasing the number of AD conversions without reducing the AD conversion speed. Increasing the number of AD conversions can improve the signal-to-noise ratio of the digital signal and the quality of the output image based on the digital signal.

[0189] The above disclosure only discloses exemplary embodiments and is not intended to limit the scope of protection of the present invention. It should be understood by those skilled in the art that the above embodiments and all or part of other embodiments and modifications that can be derived according to the scope of the claims of the present invention are within the scope of the present invention.

Claims

1. A method for performing multiple analog-to-digital conversions using an analog-to-digital converter (ADC), characterized in that: include: receiving a first ramp reference signal and a second ramp reference signal, wherein the level of the first ramp reference signal changes along a slope from an initial level in each cycle of the first ramp reference signal, and the level of the second ramp reference signal follows the first ramp reference signal at a given offset from the level of the first ramp reference signal; comparing the second ramp reference signal with the analog input signal; When the second ramp reference signal reaches the analog input signal, sampling the level of the first ramp reference signal, and after the sampling, resetting the level of the second ramp reference signal to the level sampled from the first ramp reference signal; A digital signal is generated according to the comparison result, wherein the comparison, the sampling, and the resetting are performed multiple times within each cycle of the first ramp reference signal, and the comparison after the resetting is performed using the reset second ramp reference signal.

2. The method according to claim 1, characterized in that The given offset is determined based on temporal noise in the analog input signal and the first and second reference signals, and input-referenced noise of a comparator performing the comparison.

3. The method according to claim 2, characterized in that The given offset is set to a value greater than all peak-to-peak amplitudes of the temporal noise.

4. The method according to claim 2 or 3, characterized in that The first reference signal is fed to the comparator through a capacitive element, and the second reference signal serves as a clamping voltage of the capacitive element.

5. The method according to claim 4, characterized in that In each period of the first ramp reference signal, the level of the first ramp reference signal decreases from the initial level, and the polarity of the given offset is set to negative.

6. The method according to claim 4, characterized in that In each period of the first ramp reference signal, the level of the first ramp reference signal increases from the initial level, and the polarity of the given offset is set to positive.

7. The method according to claim 4, characterized in that The ADC is connected to other ADCs through a common reference line to distribute the first reference signal and the second reference signal to the ADC and the other ADCs, and the generation of the ADC is suspended for a predetermined period after at least one of the ADC and the other ADCs is reset.

8. The method according to claim 4, characterized in that The receiving includes: receiving the second ramp reference signal from a ramp generator, and generating the first ramp reference signal according to the received second ramp reference signal.

9. The method according to claim 4, characterized in that The receiving includes: receiving the first ramp reference signal from a ramp generator, and generating the second ramp reference signal according to the received first ramp reference signal.

10. The method according to claim 4, characterized in that The generating includes retaining the comparison result in each AD conversion, averaging the retained comparison results in each period of the first ramp reference signal, and determining the digital signal according to the average value.

11. An analog-to-digital converter (ADC) for performing multiple analog-to-digital conversions, characterized in that: The ADC comprises: a receiving circuit configured to receive a first ramp reference signal and a second ramp reference signal, wherein the level of the first ramp reference signal changes along a slope from an initial level in each cycle of the first ramp reference signal, and the level of the second ramp reference signal follows the first ramp reference signal at a given offset from the level of the first ramp reference signal; a comparing unit, configured to compare the second ramp reference signal with an analog input signal; a reset unit, configured to sample the level of the first ramp reference signal when the second ramp reference signal reaches the analog input signal, and after the sampling, reset the level of the second ramp reference signal to the level sampled from the first ramp reference signal; A generating unit is configured to generate a digital signal according to the comparison result, wherein the comparison, the sampling and the resetting are performed multiple times within each cycle of the first ramp reference signal, and the comparison after the reset is performed using the reset second ramp reference signal.

12. The ADC according to claim 11, wherein: The given offset is determined based on temporal noise in the analog input signal and the first and second reference signals, and input-referenced noise of a comparator performing the comparison.

13. The ADC according to claim 12, wherein: The given offset is set to a value greater than all peak-to-peak amplitudes of the temporal noise.

14. The ADC according to claim 12 or 13, wherein: The first reference signal is fed to the comparison unit through a capacitive element, and the second reference signal serves as a clamping voltage of the capacitive element.

15. The ADC according to claim 14, wherein: In each period of the first ramp reference signal, the level of the first ramp reference signal decreases from the initial level, and the polarity of the given offset is set to negative.

16. The ADC according to claim 14, wherein: In each period of the first ramp reference signal, the level of the first ramp reference signal increases from the initial level, and the polarity of the given offset is set to positive.

17. The ADC according to claim 14, wherein: The ADC is connected to other ADCs through a common reference line to distribute the first reference signal and the second reference signal to the ADC and the other ADCs, and the generation of the ADC is suspended for a predetermined period after at least one of the ADC and the other ADCs is reset.

18. The ADC according to claim 14, wherein: In the receiving, the receiving circuit receives the second ramp reference signal from the ramp generator, and generates the first ramp reference signal according to the received second ramp reference signal.

19. The ADC according to claim 14, wherein: In the receiving, the receiving circuit receives the first ramp reference signal from a ramp generator, and generates the second ramp reference signal according to the received first ramp reference signal.

20. The ADC according to claim 14, wherein: In the generating, the generating unit retains the comparison result in each AD conversion, averages the retained comparison results in the each period of the first ramp reference signal, and determines the digital signal based on the average value.

21. An image sensor, characterized in that: include: A plurality of pixels for generating analog signals according to the intensity of incident light, and an analog-to-digital converter (ADC), each ADC being the same as the ADC according to any one of claims 11 to 20, wherein the ADC converts the analog signals output from the plurality of pixels into digital signals.

22. A device equipped with a camera function, characterized in that: The device comprises: An optical system; an image sensor comprising a plurality of pixels configured to generate analog signals according to an intensity of incident light passing through the optical system; and an analog-to-digital converter (ADC), each of the ADCs being the same as the ADC according to any one of claims 11 to 20, wherein the ADC converts the analog signals output from the plurality of pixels into digital signals; and a signal processing circuit configured to generate image data according to the digital signals.

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