Signaling of global motion vectors in picture header

Abstract

A decoder includes circuitry configured to receive a bitstream, extract a header, determine a global motion model using the header, and decode a current block of a current frame using the global motion model. Related apparatuses, systems, techniques, and articles of manufacture are also described.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 838,509, filed April 25, 2019, entitled “Signal Transmission of Global Motion Vectors in Image Header,” which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention generally relates to the field of video compression. In particular, this invention relates to the signal transmission of a global motion vector in an image header. Background Technology

[0004] A video codec can include electronic circuitry or software that compresses or decompresses digital video. It can convert uncompressed video into a compressed format and vice versa. In the case of video compression, the device that compresses the video (and / or performs some of the functions of that device) is generally called an encoder, while the device that decompresses the video (and / or performs some of the functions of that device) is called a decoder. Summary of the Invention

[0005] On one hand, a decoder includes circuitry configured to receive a bitstream, extract a header, use the header to determine a global motion model, and use the global motion model to decode the current block of the current frame.

[0006] On the other hand, one method involves receiving a bitstream by a decoder. This method includes extracting a header from the bitstream. This method includes using the header to determine a global motion model. This method includes using the global motion model to decode the current block of the current frame.

[0007] Details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the following description. Other features and advantages of the subject matter described herein will become apparent from the specification, the drawings, and the claims. Attached Figure Description

[0008] To illustrate the invention, the accompanying drawings show various aspects of one or more embodiments of the invention. However, it should be understood that the invention is not limited to the precise arrangements and mechanisms shown in the drawings, wherein:

[0009] Figure 1 This is a motion vector diagram illustrating example frames with global and local motion;

[0010] Figure 2 This section describes three example motion models that can be used for global motion, including the exponent values ​​(0, 1, or 2) for these three example motion models.

[0011] Figure 3This is a flowchart illustrating the process of implementing some examples based on the current topic;

[0012] Figure 4 This is a system block diagram of an example decoder based on some example implementations of the current topic;

[0013] Figure 5 This is a flowchart illustrating the process of implementing some examples based on the current topic;

[0014] Figure 6 This is a system block diagram of an example encoder based on some example implementations of the current topic; and

[0015] Figure 7 It is a block diagram of a computational system that can be used to implement any one or more of the methods disclosed herein, and any one or more parts thereof.

[0016] The accompanying drawings are not necessarily drawn to scale and may be illustrated by dashed lines, diagrams, and partial views. In some cases, details that are not essential for understanding the embodiments or that would make other details difficult to understand have been omitted. The same reference numerals denote the same elements in the various drawings. Detailed Implementation

[0017] Global motion in video refers to motion that occurs throughout the entire frame. Global motion can be caused by camera movement, such as, but not limited to, camera panning and zooming, which can produce motion within a frame that typically affects the entire frame. Motion existing within a portion of the video can be called local motion. Local motion can be caused by moving objects in the scene; for example, but not limited to, local motion can be caused by objects moving from left to right in the scene. Video can contain a combination of local and global motion. Some implementations of the current topic provide efficient methods for transmitting global motion to the decoder, and for using global motion vectors to improve scaling efficiency.

[0018] Figure 1 This is a diagram illustrating an exemplary embodiment, showing motion vectors of an example frame 100 with global and local motion. Frame 100 may include multiple pixel blocks, shown as squares, and motion vectors associated with them, shown as arrows. Squares pointing upwards and to the left (e.g., pixel blocks) indicate blocks with what can be considered global motion, while squares pointing in other directions (indicated by 104) indicate blocks with local motion. Figure 1In the illustrated example, many blocks share the same global motion. Sending a global motion signal (e.g., an image parameter set PPS or a sequence parameter set SPS) in the header and using the signaled global motion reduces the amount of motion vector information required for the blocks and can lead to improved prediction. Although the examples described below for illustrative purposes involve determining and / or applying global or local motion vectors at the block level, global motion vectors can be determined and / or applied to any region of the frame and / or the entire frame and / or image. Regions include areas composed of multiple blocks, regions defined by any geometric form, such as, but not limited to, regions defined by geometric and / or exponential coding, where one or more lines and / or curves defining the shape can be angled and / or curved. Although signaling is described herein as being performed at the frame level and / or the header and / or parameter set of the frame, signaling can alternatively or additionally be performed at the sub-image level, where a sub-image can include any region of the frame and / or image, as described above.

[0019] As an example, and continue to refer to Figure 1 It is possible to use MV with two components. x MV y The motion vector (MV) is used to describe simple translational motion. x MV y This describes the displacement of blocks and / or pixels in the current frame. Affine motion vectors can be used to describe more complex motions such as rotation, scaling, and warping, where "affine motion vector" as used in this disclosure is a vector that describes the uniform displacement of a set of pixels or points represented in a video image and / or picture, such as a set of pixels that represent the movement of an object in a view within the video without changing its appearance shape during the motion. Some methods of video encoding and / or decoding can use 4-parameter or 6-parameter affine models for motion compensation in inter-image coding.

[0020] For example, and still refer to Figure 1 The six-parameter affine motion model can describe affine motion as follows:

[0021] x' = ax + by + c

[0022] y'=dx+ey+f

[0023] Four-parameter affine motion can be described as:

[0024] x' = ax + by + c

[0025] y' = -bx + ay + f

[0026] Where (x, y) and (x', y') are the pixel positions in the current image and the reference image, respectively; a, b, c, d, e, and f can represent the parameters of the affine motion model.

[0027] Continue to refer to Figure 1 The parameters describing the affine motion are signaled to a decoder for the application of affine motion compensation. In some methods, the motion parameters can be explicitly signaled or derived by signaling translational control point motion vectors (CPMVs) and then deriving the affine motion parameters from the translational motion vectors. Two control point motion vectors (CPMVs) can be used to derive the affine motion parameters for a four-parameter affine motion model, and three control point translational motion vectors (CPMVs) can be used to obtain the parameters for a six-parameter motion model. Using control point motion vector signals to affine motion parameters allows for the use of efficient motion vector encoding methods to signal and affine motion parameters.

[0028] In some implementation methods, and further reference Figure 1 Global motion signals can be included in headers such as PPS or SPS. Global motion can vary across the image. Motion vectors represented by signals in the image header describe motion relative to previously decoded frames. In some implementations, global motion can be translational or affine. The motion model used (e.g., the number of parameters, whether the model is affine, translational, or otherwise) can also be signaled in the image header.

[0029] Now for reference Figure 2 The illustration shows three non-limiting example embodiments of a motion model 200 that can be used for global motion, including the exponent values ​​(0, 1, or 2) of the three non-limiting example embodiments.

[0030] Still referencing Figure 2 The PPS can be used to send command parameters that vary between images in a sequence. For parameters that remain consistent across an image sequence, signals can be sent within a sequence parameter set to reduce the PPS size and lower the video bitrate. Exemplary image parameter sets (PPS) are shown in Table 1:

[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

[0037] Continue to refer to Figure 2 Additional fields can be added to the PPS to signal global motion. In the case of global motion, the presence of global motion parameters in the image sequence can be represented by signals in the SPS, and the PPS can reference the SPS via the SPSID. In some decoding methods, the SPS is modified to allow the addition of fields to signal the presence of global motion parameters in the SPS. For example, a single-bit field can be added to the SPS. If the global_motion_present bit is 1, global motion-related parameters can be expected in the PPS. If the global_motion_present bit is 0, no field related to global motion parameters exists in the PPS. For example, the PPS shown in Table 1 can be extended to include the global_motion_present field, as shown in Table 2, for example:

[0038]

[0039] Similarly, and still referencing Figure 2 PPS can include the PPS_global_motion_parameters field for frames, as shown in Table 3:

[0040]

[0041]

[0042] For more details, please refer to [link / reference]. Figure 2 The PPS can include fields to characterize global motion parameters using control point motion vectors, as shown in Table 4:

[0043]

[0044] As another non-limiting example, Table 5 below can represent exemplary SPS:

[0045]

[0046]

[0047]

[0048]

[0049]

[0050]

[0051]

[0052]

[0053]

[0054]

[0055] The SPS table described above can be expanded as described above to incorporate global motion presence indicators as shown in Table 6:

[0056]

[0057] As described in this disclosure, additional fields may be incorporated into the SPS to reflect another indicator.

[0058] In one embodiment, still referencing Figure 2 `sps_affine_enabled_flag` specifies whether affine-based motion compensation can be used for inter-frame prediction. If `sps_affine_enabled_flag = 0`, the syntax is constrained so that affine-based motion compensation is not used in CodeLaterVideoSequences (CLVS), and `inter_affine_flag` and `cu_affine_type_flag` may not exist in the CLVS coding unit syntax. Otherwise (`sps_affine_enabled_flag = 1`), affine-based motion compensation can be used in CLVS.

[0059] Continue to refer to Figure 2 `sps_affine_type_flag` specifies whether motion compensation based on a 6-parameter affine model can be used for inter-frame prediction. If `sps_affine_type_flag = 0`, the syntax can be constrained so that motion compensation based on a 6-parameter affine model is not used in CLVS, and `cu_affine_type_flag` may not be stored in the coding unit syntax in CLVS. Otherwise (`sps_affine_type_flag = 1`), motion compensation based on a 6-parameter affine model can be used in CLVS. When it does not exist, it can be inferred that the value of `sps_affine_type_flag` is equal to 0.

[0060] Still referencing Figure 2 Translational CPMVs can be signaled in the PPS. Control points can be predefined. For example, control point MV0 can be associated with the top-left corner of the image, MV1 with the top-right corner, and MV3 with the bottom-left corner. Table 4 illustrates an exemplary method for transmitting CPMV data based on the motion model used.

[0061] In the exemplary embodiments, and still referring to Figure 2, the array amvr_precision_idx, which can be signaled in coding units, coding trees, etc., can specify the resolution AmvrShift of the motion vector difference, which can be defined as a non-limiting example shown in Table 7 as presented below. The array indices x0, y0 can specify the position (x0, y0) of the top-left luma sample of the considered coding block of the image relative to the top-left highlighted sample; when amvr_precision_idx[x0][y0] does not exist, it can be inferred to be equal to 0. When inter_affine_flag[x0][y0] = 0, the variables MvdL0[x0][y0][0], MvdL0[x0][y0][1], MvdL1[x0][y0][0], MvdL1[x0][y0][1] represent the modulation vector differences corresponding to the known blocks, which can be modified by shifting such values by AmvrShift, for example using MvdL0[x0][y0][0] = MvdL0[x0][y0][0] << AmvShift; MvdL0[x0][y0][1] = MvdL0[x0][y0][1] << AmvrShift; MvdL1[x0][y0][0] = MvdL1[x0][y0][0] << AmvrShift; and MvdL1[x0][y0][1] = MvdL1[x0][y0][1] << AmvrShift.When inter_affine_flag[x0][y0] == 1, variables MvdCpL0[x0][y0][0][0], MvdCpL0[x0][y0][0][1], MvdCpL0[x0][y0][1][0], MvdCpL0[x0][y0][1][1], MvdCpL0[x0][y0][2][0], and MvdCpL0[x0][y0][2][1] can be modified by shifting, for example, as follows: MvdCpL0[x0][y0][0][0] = MvdCpL0[x0][y0][0][0] << AmvrShift; MvdCpL1[x0][y0][0][1] = MvdCpL1[x0][y0][0][1] << AmvrShift; MvdCpL0[x0][y0][1][0] = MvdCpL0[x0][y0][1][0] << AmvrShift; MvdCpL1[x0][y0][1][1] = MvdCpL1[x0][y0][1][1] << AmvrShift; MvdCpL0[x0][y0][2][0] = MvdCpL0[x0][y0][2][0] << AmvrShift; and MvdCpL1[x0][y0][2][1] = MvdCpL1[x0][y0][2][1] << AmvrShift.

[0062]

[0063] Continue referring to Figure 2 , the global motion can be relative to a previously encoded frame. When there is only one set of global motion parameters, the motion can be relative to the frame presented immediately before the current frame.

[0064] Figure 3 is a process flow diagram that illustrates an exemplary process 300, which is a signal global motion model for decoding that can improve compression efficiency.

[0065] In step 305, and still referring to Figure 3The decoder receives a bitstream. The current block may be contained within the bitstream received by the decoder. The bitstream may include, for example, data found in the bitstream that serves as input to the decoder when using data compression. The bitstream may contain information necessary for decoding the video. Receiving may include extracting and / or parsing blocks and associated signal information from the bitstream. In some implementations, the current block may contain a coding tree unit (CTU), a coding unit (CU), or a prediction unit (PU). In step 310, a header may be extracted from the bitstream. In step 315, the header may be used to determine a global motion model; the determination of the global motion model may be performed as described above, including the determination of signals such as PPS and / or SPS. In step 320, the determined global motion model may be used to decode the current block of the current frame.

[0066] Figure 4 This is a system block diagram illustrating an instance decoder 400 that can decode bitstream 428 using a global motion model of the signal that improves compression efficiency. Decoder 400 may include an entropy decoder processor 404, an inverse quantization and inverse transform processor 408, a deblocking filter 412, a frame buffer 416, a motion compensation processor 420, and an intra-frame prediction processor 424.

[0067] During operation, and still referencing Figure 4 The bitstream 428 can be received by the decoder 400 and input to the entropy decoder processor 404, which decodes a portion of the bitstream's entropy into quantization coefficients. The quantization coefficients can be provided to the inverse quantization and inverse transform processor 408, which performs inverse quantization and inverse transform to create a residual signal. This residual signal can be added to the output of the motion compensation processor 420 or the intra-prediction processor 424, depending on the processing mode. The outputs of the motion compensation processor 420 and the intra-prediction processor 424 can contain block predictions based on previously decoded blocks. The sum of the predictions and residuals can be processed by the deblocking filter 630 and stored in the frame buffer 640.

[0068] Figure 5 This is a process flowchart illustrating an exemplary process 500, which, according to some aspects of the subject matter of the invention, utilizes global motion of the signal to encode video, thereby improving compression efficiency. In step 505, the video frame may undergo initial block partitioning, for example, using a tree-structured macroblock partitioning scheme, which may include partitioning the image frame into CTUs and CUs. In step 510, the global motion of the current block may be determined. Determining the global motion may include determining a global motion model and associated parameters. In step 515, the global motion model, associated parameters, and block may be encoded and included in the bitstream. Encoding may include, for example, using inter-frame prediction and intra-frame prediction modes.

[0069] Figure 6 This is a system block diagram illustrating an example video encoder 600 that improves the compression efficiency of global motion signals. The example video encoder 600 can receive input video 604, which can be initially partitioned or divided according to a tree-structured macroblock partitioning scheme (e.g., quadtree plus binary tree). Examples of tree-structured macroblock partitioning schemes may include dividing image frames into large blocks called coding tree units (CTUs). In some implementations, each CTU may be further divided into one or more sub-blocks called coding units (CUs). The final result of this partitioning may include a set of sub-blocks called prediction units (PUs). Transform units (TUs) may also be used.

[0070] Still referencing Figure 6 The example video encoder 600 may include an intra-frame prediction processor 608, a motion estimation / compensation processor 612 (also known as an inter-frame prediction processor) capable of supporting global motion signals and processing, a transform / quantization processor 616, an inverse quantization / inverse transform processor 620, an in-loop filter 624, a decoded image buffer 628, and / or an entropy coding processor 632. Bitstream parameters may be input to the entropy coding processor 632 for inclusion in the output bitstream 636.

[0071] During operation, and further reference Figure 6 For each block of the input video 604 frames, it can be determined whether the block is processed via intra-frame prediction or using motion estimation / compensation. The block can be provided to either the intra-frame prediction processor 608 or the motion estimation / compensation processor 612. If the block is to be processed via intra-frame prediction, the intra-frame prediction processor 608 can perform processing to output a predicted value. If the block is to be processed via motion estimation / compensation, the motion estimation / compensation processor 612 can perform processing including global motion signals, if applicable.

[0072] Still referencing Figure 6The residual can be formed by subtracting the predicted value from the input video. The residual can be received by a transform / quantization processor 616, which performs transform processing (e.g., Discrete Cosine Transform (DCT)) to produce quantizable coefficients. The quantization coefficients and any associated signal information can be provided to an entropy encoding processor 632 for entropy encoding and included in the output bitstream 636. The entropy encoding processor 632 can support the encoding of signal information related to the current block. Additionally, the quantization coefficients can be provided to an inverse quantization / inverse transform processor 620, which reproduces pixels that can be combined with the prediction factor and processed by a loop filter 624. The output of the loop filter 624 can be stored in a decoded image buffer 628 for use by a motion estimation / compensation processor 612 capable of performing global motion signal processing.

[0073] Although some changes have been described in detail above, other modifications or additions are possible. For example, in some implementations, the current block can include any symmetric block (8x8, 16x16, 32x32, 64x64, 128x128, etc.) as well as any asymmetric block (8x4, 16x8, etc.).

[0074] In some implementations, a quadtree plus binary decision tree (QTBT) can be used. In QTBT, at the encoding tree unit level, the partitioning parameters of the QTBT are dynamically derived to adapt to local characteristics without transmitting any overhead. Subsequently, at the encoding unit level, the joint classifier decision tree structure can eliminate unnecessary iterations and control the risk of mispredictions. In some implementations, the LTR frame block update mode can be used as an additional option available at each leaf node of the QTBT.

[0075] In some implementations, additional syntax elements can be signaled at different levels of the bitstream. For example, an enable flag can be included for the entire sequence by including an enable flag encoded in the Sequence Parameter Set (SPS). Furthermore, the CTU flag can be encoded at the Code Tree Unit (CTU) level.

[0076] It should be noted that, as will be apparent to those skilled in the art of computers, any one or more aspects and embodiments described herein can be readily implemented using digital electronic circuits, integrated circuits, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), computer hardware, firmware, software, and / or combinations thereof implemented and / or implemented in one or more machines programmed according to the teachings of this specification (e.g., one or more computing devices used as user computing devices for electronic documents, one or more server devices such as document servers, etc.). These aspects or features may include implementations in one or more computer programs and / or software that are executable and / or interpretable on a programmable system including at least one programmable processor, which may be dedicated or general-purpose, coupled to receive data and instructions from a storage system, at least one input device, and at least one output device, and to send data and instructions to the storage system, at least one input device, and at least one output device. It will be apparent to those skilled in the art of software that a skilled programmer can readily prepare appropriate software code based on the teachings of this disclosure. The aspects and implementations employing software and / or software modules discussed above may also include appropriate hardware for assisting in the implementation of machine-executable instructions for the software and / or software modules.

[0077] Such software can be a computer program product employing a machine-readable storage medium. A machine-readable storage medium can be any medium capable of storing and / or encoding a sequence of instructions executable by a machine (e.g., a computing device) and causing the machine to perform any of the methods and / or embodiments described herein. Examples of machine-readable storage media include, but are not limited to, magnetic disks, optical disks (e.g., CDs, CD-Rs, DVDs, DVD-Rs, etc.), magneto-optical disks, read-only memory “ROM” devices, random access memory “RAM” devices, magnetic cards, optical cards, solid-state storage devices, EPROMs, EEPROMs, programmable logic devices (PLDs), and / or any combination thereof. As used herein, machine-readable media are intended to include both single media and collections of physically separate media, such as collections of optical disks or one or more hard disk drives combined with computer memory. As used herein, machine-readable storage media do not include transient signal transmissions.

[0078] Such software may also include information (e.g., data) carried as data signals on a data carrier such as a carrier wave. For example, machine-executable information may include data-bearing signals contained in a data carrier, wherein the signals encode a sequence of instructions or a portion thereof for execution by a machine (e.g., a computing device), and any relevant information (e.g., data structures and data) that causes the machine to perform any of the methods and / or embodiments described herein.

[0079] Examples of computing devices include, but are not limited to, e-book readers, computer workstations, terminal computers, server computers, handheld devices (e.g., tablets, smartphones, etc.), network devices, network routers, network switches, bridges, any machine capable of executing a sequence of instructions specifying an action to be taken by the machine, and any combination thereof. In one example, a computing device may include and / or be included in a kiosk.

[0080] Figure 7 An illustration of one embodiment is shown, illustrating a computing device of exemplary form, a computer system 700, in which a set of instructions can be executed to cause a control system to perform any one or more aspects and / or methods of this disclosure. It is also contemplated that multiple computing devices can be utilized to implement specially configured sets of instructions for causing one or more of the aspects and / or methods of the present invention to perform. The computer system 700 includes a processor 704 and a memory 708 that communicate with each other and with other components via a bus 712. The bus 712 may include any of several types of bus architectures, including but not limited to memory buses, memory controllers, peripheral buses, local buses, and any combinations thereof using any of various bus architectures.

[0081] Memory 708 may include various components (e.g., machine-readable media), including but not limited to random access memory components, read-only components, and any combination thereof. In one example, a basic input / output system 716 (BIOS) may be stored in memory 708, including, for example, basic routines that facilitate the transfer of information between elements within computer system 700 during startup. Memory 708 may also include (e.g., stored on one or more machine-readable media) instructions (e.g., software) 720 embodying any one or more aspects and / or methods of this disclosure. In another example, memory 708 may also include any number of program modules, including but not limited to an operating system, one or more application programs, other program modules, program data, and any combination thereof.

[0082] Computer system 700 may also include storage device 724. Examples of storage devices (e.g., storage device 724) include, but are not limited to, hard disk drives, disk drives, optical disk drives combined with optical media, solid-state storage devices, and any combination thereof. Storage device 724 may be connected to bus 712 via a suitable interface (not shown). Exemplary interfaces include, but are not limited to, SCSI, Advanced Technology Attachment (ATA), Serial ATA, Universal Serial Bus (USB), IEEE 1394 (FireWire), and any combination thereof. In one example, storage device 724 (or one or more components of storage device 724) may be removably interfaced to computer system 700 (e.g., via an external port connector (not shown)). In particular, storage device 724 and associated machine-readable medium 728 may provide non-volatile and / or volatile storage of machine-readable instructions, data structures, program modules, and / or other data for computer system 700. In one example, software 720 may reside wholly or partially within machine-readable medium 728. In another example, software 720 may reside wholly or partially within processor 704.

[0083] Computer system 700 may also include input device 732. In one example, a user of computer system 700 may input commands and / or other information into computer system 700 via input device 732. Examples of input device 732 include (but are not limited to) alphanumeric input devices (e.g., keyboard), positioning devices, joysticks, game controllers, audio input devices (e.g., microphone, voice response system, etc.), cursor control devices (e.g., mouse), touchpads, optical scanners, video capture devices (e.g., still cameras, video cameras), touchscreens, and any combination thereof. Input device 732 may be connected to bus 712 via any of a variety of interfaces (not shown), including but not limited to serial interfaces, parallel interfaces, game ports, USB interfaces, firewire interfaces, direct interfaces to bus 712, and any combination thereof. Input device 732 may include a touchscreen interface, which may be part of or separate from display 736, as will be discussed further below. Input device 732 may be used as a user selection device for selecting one or more graphical representations in the graphical interface described above.

[0084] Users can also input commands and / or other information to computer system 700 via storage device 724 (e.g., removable disk drive, flash drive, etc.) and / or network interface device 740. Network interface devices, such as network interface device 740, can be used to connect computer system 700 to one or more networks, such as network 744, and one or more remote devices 748 connected to network 744. Examples of network interface devices include, but are not limited to, network interface cards (e.g., mobile network interface cards, LAN cards), modems, and any combination thereof. Examples of networks include, but are not limited to, wide area networks (e.g., the Internet, enterprise networks), local area networks (e.g., networks associated with offices, buildings, campuses, or other relatively small geographical areas), telephone networks, data networks associated with telephone / voice providers (e.g., mobile communication provider data and / or voice networks), direct connections between two computing devices, and any combination thereof. Networks such as network 744 can employ wired and / or wireless communication modes. Typically, any network topology can be used. Information (e.g., data, software 720, etc.) can be transmitted to and / or from computer system 700 via network interface device 740.

[0085] Computer system 700 may also include a video display adapter 752 for transmitting displayable images to a display device, such as display device 736. Examples of display devices include, but are not limited to, liquid crystal displays (LCDs), cathode ray tube (CRTs), plasma displays, light-emitting diode (LED) displays, and any combination thereof. Display adapter 752 and display device 736 may be used in conjunction with processor 704 to provide graphical representations of various aspects of this disclosure. In addition to display devices, computer system 700 may include one or more other peripheral output devices, including, but not limited to, audio speakers, printers, and any combination thereof. Such peripheral output devices may be connected to bus 712 via peripheral interface 756. Examples of peripheral interfaces include, but are not limited to, serial ports, USB connections, firewire connections, parallel connections, and any combination thereof.

[0086] The foregoing is a detailed description of illustrative embodiments of the present invention. Various modifications and additions can be made without departing from the spirit and scope of the invention. Features of each of the above embodiments can be suitably combined with features of other described embodiments to provide multiple combinations of features in related new embodiments. Furthermore, although several individual embodiments have been described above, the content described herein is merely an illustration of the application of the principles of the invention. Additionally, although specific methods herein may be shown and / or described as being performed in a particular order, this order is highly variable to those skilled in the art in implementing the embodiments disclosed herein. Therefore, this specification is by way of example only and is not intended to limit the scope of the invention.

[0087] In the foregoing description and claims, phrases such as “at least one” or “one or more” may appear, followed by a combined list of elements or features. The term “and / or” may also appear in a list of two or more elements or features. Unless implied or explicitly contradicted to the context in which it is used, such phrases are intended to mean any element or feature listed individually, or any referenced element or feature in combination with any other referenced element or feature. For example, the phrases “at least one of A and B;”, “one or more of A and B;”, and “A and / or B” each respectively mean “A alone, B alone, or A and B together.” Similar interpretations are also intended for lists comprising three or more items. For example, the phrases “at least one of A, B, and C;”, “one or more of A, B, and C;”, and “A, B, and / or C” each respectively mean “A alone, B alone, C alone, A and B together, A and C together, B and C together, or A and B and C together.” Additionally, the term “based on” as used above and in the claims is intended to mean “at least partially based on,” allowing for the inclusion of unreferenced features or elements.

[0088] Depending on the desired configuration, the subject matter described herein can be embodied in systems, devices, methods, and / or articles. The implementations set forth in the foregoing description do not represent all implementations consistent with the subject matter described herein. Rather, they are merely examples consistent with aspects relating to the described subject matter. While some variations have been described in detail above, other modifications or additions are possible. In particular, additional features and / or variations may be provided in addition to those set forth herein. For example, the above embodiments may involve various combinations and sub-combinations of the disclosed features and / or combinations and sub-combinations of several other features disclosed above. Furthermore, the logical flows depicted in the drawings and / or described herein do not necessarily require the specific order or sequential order shown to achieve the desired results. Other embodiments are within the scope of the appended claims.

Claims

1. A decoder, the decoder comprising circuitry configured to: Receive a bitstream including an encoded image, the encoded image including a first region and a second region, the first region including only a first consecutive plurality of encoded blocks having global motion, and the second region including a second consecutive plurality of encoded blocks having local motion; For each block in the first region, extract the header; The motion model is determined using the header. The motion model is global for all blocks in the first region and is one of translational motion, four-parameter affine motion, or six-parameter affine motion. The parameters of the motion model for each block in the first region are determined based on at least one motion vector transmitted by a signal in the bitstream. as well as The parameters of the motion model are used to decode each block in the first region to reconstruct the global motion in the first region; as well as For each block in the second region, the motion information determined for each block is used to decode each block in order to reconstruct the local motion of the second region.

2. The decoder according to claim 1, wherein, Each block in the first region forms a part of a quadtree plus a binary decision tree.

3. The decoder according to claim 1, wherein, Each block in the first region is a coding tree unit.

4. The decoder according to claim 1, wherein, Each block in the first region is a coding unit.

5. The decoder according to claim 1, wherein, The motion model is an affine motion model, and the motion vector is a control point motion vector.

6. The decoder according to claim 5, wherein, The affine motion model is a four-parameter affine motion model with two control point motion vectors.

7. The decoder according to claim 5, wherein, The affine motion model is a six-parameter affine motion model with three control point motion vectors.

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