A method, device and medium for implementing a RISC-V processor extension instruction

Abstract

A method for implementing extended instructions in a RISC-V processor includes: marking the instructions according to their type and / or the type of registers used; and allocating the instructions to different pipelines for execution based on the markings. The method provided by this invention achieves modular expansion of custom instruction decoding and execution units during instruction parsing, facilitating instruction expansion and optimization; it separates and tracks instructions based on register type, making the processing of various instructions relatively independent, convenient, and fast; simultaneously, it reduces the pipeline occupancy impact of instructions with long execution times, thereby improving instruction execution efficiency.

Description

Technical Field

[0001] This invention relates to a method, apparatus, and medium for implementing extended instructions for a RISC-V processor. Background Technology

[0002] RISC-V is a brand-new instruction set built on the basis of continuous development and maturation of instructions. It has the advantage of being a latecomer, with a clear and simple structure. Its modular design can be freely matched as needed, making it flexible, convenient, and highly scalable. It has a complete toolchain, and due to the openness of its BSD protocol, more and more countries and companies are investing in RISC-V research, and processor designs based on the RISC-V instruction set are becoming increasingly common.

[0003] RISC-V is currently based on a basic instruction set, and its extended instructions are being gradually improved and standardized. RISC-V provides an interface for custom instruction extensions. Currently, there are many ways to extend instructions, and their implementations mostly follow traditional instruction processing pipelines. For different types of instruction extension applications, their flexibility and execution efficiency are somewhat lacking.

[0004] Therefore, a method is needed to solve the problem of pipeline execution being blocked by custom-implemented extended instructions due to long processing times. Summary of the Invention

[0005] To address the above problems, this invention proposes a method for implementing RISC-V processor extended instructions, comprising:

[0006] The instruction is tagged according to its type and / or the type of register used;

[0007] The instructions are assigned to different pipelines for execution based on the flags.

[0008] In some embodiments of the present invention, the instructions are marked according to their type and / or the type of registers used, including:

[0009] The instruction whose instruction type is an extended instruction and which uses a general-purpose register is marked as a first extended instruction, and the value of the first predetermined position of the first extended instruction is set to a first predetermined value;

[0010] The instruction whose instruction type is an extended instruction and which uses an extended register is marked as a second extended instruction, and the value of the first predetermined position of the second extended instruction is set to a second predetermined value.

[0011] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker includes:

[0012] The first extended instruction and the general instruction are assigned to the first Scoreboard, and the first Scoreboard sends the first extended instruction and the general instruction to the first transmitter.

[0013] The second extended instruction is assigned to the second Scoreboard, which then sends the second extended instruction to the second transmitter.

[0014] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0015] The first transmitter sends a first extended instruction to the second transmitter.

[0016] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0017] In response to the second transmitter receiving a first extended instruction from the first transmitter and / or the second scoreboard, it is determined whether the register used by the first extended instruction is occupied;

[0018] In response to the register used by the first extended instruction being occupied, the first extended instruction is sent to the second Scoreboard.

[0019] In some embodiments of the present invention, the instructions are marked according to their type and / or the type of registers used, and the method further includes:

[0020] The order of the first extended instructions in the pipeline is counted and recorded, and the order of the first extended instructions is written into a second predetermined position of the first extended instructions; and

[0021] In response to parsing the second extended instruction, the final value of the order of the first extended instructions is written to the second predetermined position of the second extended instruction, and the order of the first extended instructions is cleared to zero.

[0022] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0023] The second transmitter records the value of the second predetermined position of the transmitted first extended instruction through a shift register;

[0024] In response to the second transmitter receiving a second extended instruction, the second transmitter compares the value at a second predetermined position of the second extended instruction with the value in the shift register;

[0025] In response to the second extended instruction having a value at a second predetermined position that is less than the value of the shift register, the second extended instruction is shifted to read the next value of the shift register or a new value of the shift register is waited for.

[0026] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0027] The second transmitter records the value of the second predetermined position of the first extended instruction transmitted by multiplying the corresponding positions in the queue;

[0028] In response to the second transmitter receiving a second extended instruction, the second transmitter compares the factorial of the value at the second predetermined position of the second extended instruction with the value at the corresponding position in the queue;

[0029] In response to the factorial of the value at the second predetermined position of the second extended instruction being greater than the value at the corresponding position in the queue, the shift instruction is either read from the next shift register or a new shift register value is awaited.

[0030] Another aspect of the present invention provides a processor in which hardware logic implements the steps of the method described in any of the above embodiments.

[0031] Another aspect of the present invention provides a computer having a processor as described in the above embodiments, wherein the hardware logic of the processor implements the steps of any one of the methods described in the above embodiments.

[0032] The method provided by this invention enables modular expansion of custom instruction decoding and execution units during instruction parsing, facilitating instruction expansion and optimization. Instructions are processed separately based on register type, making the processing of various instructions relatively independent, convenient, and fast. Simultaneously, it reduces the pipeline's workload caused by instructions with long execution times, thereby improving instruction execution efficiency. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 A flowchart illustrating an embodiment of a method for implementing RISC-V processor extended instructions provided by an embodiment of the present invention;

[0035] Figure 2 A schematic diagram of the extended instruction structure of an embodiment of a method for implementing extended instructions of a RISC-V processor provided by an embodiment of the present invention;

[0036] Figure 3 A processor provided in this embodiment of the invention has a method for implementing RISC-V processor extended instructions;

[0037] Figure 4 A schematic diagram of a computer with a processor having a method for implementing RISC-V processor extended instructions, provided as an embodiment of the present invention;

[0038] Figure 5 This is a hardware logic structure diagram of an embodiment of a method for implementing RISC-V processor extended instructions provided by an embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0040] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0041] like Figure 1 As shown, a first aspect of the present invention provides a method for implementing RISC-V processor extended instructions, comprising:

[0042] Step S1: Mark the instruction according to its type and / or the type of register used;

[0043] Step S2: Assign the instructions to different pipelines for execution based on the flags.

[0044] In an embodiment of the present invention, a method for implementing RISC-V processor extended instructions is proposed. This method involves implanting special markers at specific locations of the extended instructions in RISC-V and allocating the extended instructions to different pipelines for execution based on the special markers, thereby solving the problem of blocking other instructions during the execution of extended instructions in the RISC-V processor.

[0045] Specifically, in step S1, this invention marks the instructions on the processor pipeline according to the instruction type and register type to distinguish between extended instructions and general instructions. Specifically, extended instructions are custom-marked. Typically, RISC-V extended instructions are 32 bits; in this invention, the free bits in the 32 bits are expanded to achieve custom functionality.

[0046] In step S2, the corresponding processing logic is executed based on the value of the corresponding bit in the 32-bit RISC-V instruction implemented above as a judgment condition.

[0047] In some embodiments of the present invention, the instructions are marked according to their type and / or the type of registers used, including:

[0048] The instruction whose instruction type is an extended instruction and which uses a general-purpose register is marked as a first extended instruction, and the value of the first predetermined position of the first extended instruction is set to a first predetermined value;

[0049] The instruction whose instruction type is an extended instruction and which uses an extended register is marked as a second extended instruction, and the value of the first predetermined position of the second extended instruction is set to a second predetermined value.

[0050] In this embodiment, as Figure 2 As shown, Figure 2 The diagram shows the structure of the decoder's output information for the extended instructions in the implementation of the RISC-V instruction extension method of this invention. Figure 2 In the structure shown, this invention adds a reg_flags field, corresponding to a 3-bit space for RISC-V extended instructions. These 3 bits correspond to the register types of the three registers rs1, rs2, and rd for RISC-V extended instructions. If any of the above three registers uses an extended register, the corresponding bit is set to 1. Extended instructions where all three registers are general-purpose registers are named KG-type instructions. That is, KG-type instructions are also extended instructions, only they use general-purpose registers. Instructions that include extended registers in the above three register types have their corresponding bit set to 0 and are named KK-type instructions. In other words, KK-type instructions represent extended instructions that use extended registers.

[0051] It should be noted that the extended registers in this invention refer to registers other than vector registers or other custom non-standard registers, as well as registers used to distinguish them from standard general-purpose registers as required by the design.

[0052] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker includes:

[0053] The first extended instruction and the general instruction are assigned to the first Scoreboard, and the first Scoreboard sends the first extended instruction and the general instruction to the first transmitter.

[0054] The second extended instruction is assigned to the second Scoreboard, which then sends the second extended instruction to the second transmitter.

[0055] like Figure 5 As shown, in this embodiment, two scoreboards are set up. When decoding instructions according to the method of this invention, the decoder sends the aforementioned KG-type instructions and general instructions to the first scoreboard, and sends the KK-type instructions to the second scoreboard. The first scoreboard has a dedicated first transmitter, and the KG-type instructions and general instructions in the first scoreboard are sent to the first transmitter in the order of instructions in the pipeline. The second scoreboard also has a dedicated second transmitter, and the KK instructions in the second scoreboard are also sent to the second transmitter in the order of instructions in the pipeline.

[0056] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0057] The first transmitter sends a first extended instruction to the second transmitter.

[0058] In this embodiment, the first transmitter further processes the KG instructions sent from the first scoreboard. Specifically, by determining the type of instruction sent by the first scoreboard, the extended KG instructions are forwarded to the second transmitter for execution. The first transmitter only sends general instructions.

[0059] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0060] In response to the second transmitter receiving a first extended instruction from the first transmitter and / or the second scoreboard, it is determined whether the register used by the first extended instruction is occupied;

[0061] In response to the register used by the first extended instruction being occupied, the first extended instruction is sent to the second Scoreboard.

[0062] In this embodiment, the second transmitter reads the address of the register of the KG-type instruction sent by the first transmitter, that is, through... Figure 2 The values ​​of rs1, rs2, and rd are used to determine whether the register used by the KG type instruction is occupied. If it is occupied, the KG type instruction is sent to the second Scoreboard and classified before the corresponding KK instruction.

[0063] It should be noted that the extended instructions KG and KK in this invention usually appear in groups, that is, a KG-type instruction is followed by a KK-type instruction, and the KG-type instruction is usually a pre-execution instruction for the KK-type instruction. In other words, the corresponding logic is implemented in the second scoreboard to associate a matching set of KG and KK-type instructions.

[0064] In some embodiments of the present invention, the instructions are marked according to their type and / or the type of registers used, and the method further includes:

[0065] The order of the first extended instructions in the pipeline is counted and recorded, and the order of the first extended instructions is written into a second predetermined position of the first extended instructions; and

[0066] In response to parsing the second extended instruction, the final value of the order of the first extended instructions is written to the second predetermined position of the second extended instruction, and the order of the first extended instructions is cleared to zero.

[0067] In this embodiment, as Figure 2 As shown, a `set_num` flag is set in the 32-bit instruction of the RISC-V processor to mark the grouping and matching of KG-type and KK-type instructions. In the second scoreboard, KG-type and KK-type instructions are matched and associated. In this embodiment, this mechanism is implemented through the `set_num` flag in the KG-type and KK-type extended instructions. When the decoder decodes instructions in the pipeline, if a KG-type instruction is parsed, it begins to mark the KG-type instruction. That is, for each KG-type instruction parsed, a counter register is set to record the number of KG-type instructions, and the value of the counter register is used as the value of the `set_num` of the KG-type instruction. Furthermore, if a KK-type instruction is parsed, the value of the counter register is written to the corresponding bit of the `set_num` of the KK-type instruction, and the counter register is set to 0, i.e., starting from 0.

[0068] Specifically, taking three KG-type instructions and one KK-type instruction as an example, the order of instructions input to the processor is KG1, KG2, KG3, KK. When the first KG-type instruction is parsed, the value of the counter register is incremented by 1, and this value is written to the `set_num` field of the first KG-type instruction, meaning KG1's `set_num` value is 1. When the second KG-type instruction is parsed, the value of the counter register is incremented by 1 again, and this value is written to the `set_num` field of the second KG-type instruction, KG2, meaning KG2's `set_num` value is 2, and so on, until KG3's `set_num` value is 3. When a KK-type instruction is parsed, the value of the counter register is written to the `set_num` field of the KK-type instruction, and the counter register is cleared, meaning the KK-type instruction's `set_num` value is also 3, and the counter register value is set to 0. The same process is repeated when encountering another KG-type instruction.

[0069] Furthermore, as mentioned earlier, KG-type instructions are sent to the first Scoreboard, while KK-type instructions are sent to the second Scoreboard. KG-type instructions sent to the first Scoreboard are forwarded to the second transmitter via the first transmitter. If the second transmitter cannot transmit due to occupied registers, it will send the KG-type instruction to the second Scoreboard. After the KG-type instruction is sent to the second Scoreboard, the second Scoreboard will match the KG-type and KK-type instructions in the same group. When the second transmitter transmits a KG-type instruction, it will send the set_num value of the transmitted instruction to the Scoreboard. Since the decoding order of KK-type and KG-type instructions is already determined, upon receiving the set_num value of the KG-type instruction transmitted by the second transmitter and the KG-type instruction that could not be transmitted, the KG-type and KK-type instructions can be matched according to the instruction order.

[0070] Specifically, taking two sets of KG and KK type instruction groups as an example, for example, the first set of KG and KK type instructions has two KG type instructions and one KK type instruction. Assuming that the registers of the first KG type instruction and the second KG type instruction are not occupied and are directly issued, the second transmitter will send two set_num values, namely 1 and 2, to the second scoreboard in succession. If the first set of KK type instructions is also 2, it is considered that KG1 and KG2 of the KK type instruction have been issued and executed. If the KK instruction can be issued, it will be directly issued to the execution unit for execution. If a transmission fails, the process continues to wait. During this process, if the second set of three KG-type instructions is also sent to the second transmitter, and KG1 and KG2 of the second set of KG-type instructions cannot be sent due to register occupancy, they are forwarded to the second scoreboard. In this case, when the scoreboard processes these two KG-type instructions, it uses their `set_num` value to compare with the corresponding KK-type instructions in the second scoreboard. If the value is less than the `set_num` value of the corresponding KK-type instruction, then the two KG-type instructions are matched with their corresponding KK-type instructions. Therefore, since the first set of KG and KK-type instructions has already been authenticated, it will not compare with the `set_num` value of the first set of KK-type instructions, even if the second set of KG1 is less than the first set of KK's `set_num` value. This ensures a clear instruction transmission order.

[0071] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0072] The second transmitter records the value of the second predetermined position of the transmitted first extended instruction through a shift register;

[0073] In response to the second transmitter receiving a second extended instruction, the second transmitter compares the value at a second predetermined position of the second extended instruction with the value in the shift register;

[0074] In response to the second extended instruction having a value at a second predetermined position that is less than the value of the shift register, the second extended instruction is shifted to read the next value of the shift register or a new value of the shift register is waited for.

[0075] In this embodiment, when the second transmitter sends KK-type instructions from the second scoreboard, the set_num value of the already sent KG-type instructions needs to be stored in a shift register. As in the example above with KG and KK-type instructions, if KG1 is sent, the set_num value of KG1 (1) is written to the shift register. If the second KG-type instruction, KG2, cannot be sent due to a register issue, the entire second transmitter will block and wait for the execution of the currently executing KK-type instructions (only KK-type extended instructions use the extended register, so usually the execution of KK-type instructions affects the sending of subsequent KG-type instructions). When sending KK-type instructions, to prevent sending errors, it is necessary to verify whether all KG-type instructions have been sent. Therefore, this is done by comparing the set_num value of the KK-type instructions with the current shift register value. The value in the shift register is compared with the set_num value of the already issued KG-type instruction and the set_num value of the KK-type instruction to be issued. If the value of the shift register is less than the set_num value of the KK-type instruction, it means that there are still KG-type instructions that have not been sent. At this time, the KK-type instruction is blocked and waits. The second transmitter sends the corresponding KG-type instruction and records the set_num value of the sent KG-type instruction into the shift register. Then it is judged whether the set_num value of the KK-type instruction to be sent is equal to the value of the shift register. If they are equal, the KK-type instruction is sent. If they are not equal, it continues to block and wait to send the KG-type instruction.

[0076] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0077] The second transmitter records the value of the second predetermined position of the first extended instruction transmitted by multiplying the corresponding positions in the queue;

[0078] In response to the second transmitter receiving a second extended instruction, the second transmitter compares the factorial of the value at the second predetermined position of the second extended instruction with the value at the corresponding position in the queue;

[0079] In response to the factorial of the value at the second predetermined position of the second extended instruction being greater than the value at the corresponding position in the queue, the shift instruction is either read from the next shift register or a new shift register value is awaited.

[0080] In this embodiment, the present invention proposes a solution for out-of-order KG type instructions. It also uses the aforementioned set_num flag for judgment. However, unlike the previous implementation, the shift register is replaced with another queue-based storage structure. When issuing a group of KG and KK type instructions, the set_num of each KG type instruction in the same group is written to the corresponding position in the queue in a cumulative multiplication manner. When issuing a KK type instruction, the factorial of the set_num of the KK type instruction is calculated and compared with the cumulative multiplication of the previously issued KG type instructions in the queue at the corresponding position. If the factorial of the KK type instruction is less than the cumulative multiplication of the previously issued KG type instructions, it indicates that the KG type instructions have not been completely issued and the KK type instructions need to continue waiting. If the two are equal, the KK type instruction can be issued directly. This mechanism enables out-of-order issuance of KG-type instructions. That is, as long as the extended register used by the KG-type instruction is not occupied, the second transmitter can directly issue the KG-type instruction forwarded by the first transmitter without blocking and waiting through the shift register, which can greatly reduce the time cycle wasted by waiting for the KG-type instruction to be issued.

[0081] The method provided by this invention enables modular expansion of custom instruction decoding and execution units during instruction parsing, facilitating instruction expansion and optimization. Instructions are processed separately based on register type, making the processing of various instructions relatively independent, convenient, and fast. Simultaneously, it reduces the pipeline's workload caused by instructions with long execution times, thereby improving instruction execution efficiency.

[0082] like Figure 3 As shown, another aspect of the present invention also proposes a processor 21, wherein hardware logic 22 in the processor implements a method for implementing RISC-V processor extended instructions, comprising:

[0083] The instruction is tagged according to its type and / or the type of register used;

[0084] The instructions are assigned to different pipelines for execution based on the flags.

[0085] In some embodiments of the present invention, the instructions are marked according to their type and / or the type of registers used, including:

[0086] The instruction whose instruction type is an extended instruction and which uses a general-purpose register is marked as a first extended instruction, and the value of the first predetermined position of the first extended instruction is set to a first predetermined value;

[0087] The instruction whose instruction type is an extended instruction and which uses an extended register is marked as a second extended instruction, and the value of the first predetermined position of the second extended instruction is set to a second predetermined value.

[0088] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker includes:

[0089] The first extended instruction and the general instruction are assigned to the first Scoreboard, and the first Scoreboard sends the first extended instruction and the general instruction to the first transmitter.

[0090] The second extended instruction is assigned to the second Scoreboard, which then sends the second extended instruction to the second transmitter.

[0091] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0092] The first transmitter sends a first extended instruction to the second transmitter.

[0093] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0094] In response to the second transmitter receiving a first extended instruction from the first transmitter and / or the second scoreboard, it is determined whether the register used by the first extended instruction is occupied;

[0095] In response to the register used by the first extended instruction being occupied, the first extended instruction is sent to the second Scoreboard.

[0096] In some embodiments of the present invention, the instructions are marked according to their type and / or the type of registers used, and the method further includes:

[0097] The order of the first extended instructions in the pipeline is counted and recorded, and the order of the first extended instructions is written into a second predetermined position of the first extended instructions; and

[0098] In response to parsing the second extended instruction, the final value of the order of the first extended instructions is written to the second predetermined position of the second extended instruction, and the order of the first extended instructions is cleared to zero.

[0099] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0100] The second transmitter records the value of the second predetermined position of the transmitted first extended instruction through a shift register;

[0101] In response to the second transmitter receiving a second extended instruction, the second transmitter compares the value at a second predetermined position of the second extended instruction with the value in the shift register;

[0102] In response to the second extended instruction having a value at a second predetermined position that is less than the value of the shift register, the second extended instruction is shifted to read the next value of the shift register or a new value of the shift register is waited for.

[0103] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0104] The second transmitter records the value of the second predetermined position of the first extended instruction transmitted by multiplying the corresponding positions in the queue;

[0105] In response to the second transmitter receiving a second extended instruction, the second transmitter compares the factorial of the value at the second predetermined position of the second extended instruction with the value at the corresponding position in the queue;

[0106] In response to the factorial of the value at the second predetermined position of the second extended instruction being greater than the value at the corresponding position in the queue, the shift instruction is either read from the next shift register or a new shift register value is awaited.

[0107] like Figure 4 As shown, another aspect of the present invention also proposes a computer 31, the computer 41 having a processor 42 as described in the above embodiments, the processor implementing a method for implementing RISC-V processor extended instructions, comprising:

[0108] The instruction is tagged according to its type and / or the type of register used;

[0109] The instructions are assigned to different pipelines for execution based on the flags.

[0110] In some embodiments of the present invention, the instructions are marked according to their type and / or the type of registers used, including:

[0111] The instruction whose instruction type is an extended instruction and which uses a general-purpose register is marked as a first extended instruction, and the value of the first predetermined position of the first extended instruction is set to a first predetermined value;

[0112] The instruction whose instruction type is an extended instruction and which uses an extended register is marked as a second extended instruction, and the value of the first predetermined position of the second extended instruction is set to a second predetermined value.

[0113] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker includes:

[0114] The first extended instruction and the general instruction are assigned to the first Scoreboard, and the first Scoreboard sends the first extended instruction and the general instruction to the first transmitter.

[0115] The second extended instruction is assigned to the second Scoreboard, which then sends the second extended instruction to the second transmitter.

[0116] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0117] The first transmitter sends a first extended instruction to the second transmitter.

[0118] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0119] In response to the second transmitter receiving a first extended instruction from the first transmitter and / or the second scoreboard, it is determined whether the register used by the first extended instruction is occupied;

[0120] In response to the register used by the first extended instruction being occupied, the first extended instruction is sent to the second Scoreboard.

[0121] In some embodiments of the present invention, the instructions are marked according to their type and / or the type of registers used, and the method further includes:

[0122] The order of the first extended instructions in the pipeline is counted and recorded, and the order of the first extended instructions is written into a second predetermined position of the first extended instructions; and

[0123] In response to parsing the second extended instruction, the final value of the order of the first extended instructions is written to the second predetermined position of the second extended instruction, and the order of the first extended instructions is cleared to zero.

[0124] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0125] The second transmitter records the value of the second predetermined position of the transmitted first extended instruction through a shift register;

[0126] In response to the second transmitter receiving a second extended instruction, the second transmitter compares the value at a second predetermined position of the second extended instruction with the value in the shift register;

[0127] In response to the second extended instruction having a value at a second predetermined position that is less than the value of the shift register, the second extended instruction is shifted to read the next value of the shift register or a new value of the shift register is waited for.

[0128] In some embodiments of the present invention, assigning the instructions to different pipelines for execution based on the marker further includes:

[0129] The second transmitter records the value of the second predetermined position of the first extended instruction transmitted by multiplying the corresponding positions in the queue;

[0130] In response to the second transmitter receiving a second extended instruction, the second transmitter compares the factorial of the value at the second predetermined position of the second extended instruction with the value at the corresponding position in the queue;

[0131] In response to the factorial of the value at the second predetermined position of the second extended instruction being greater than the value at the corresponding position in the queue, the shift instruction is either read from the next shift register or a new shift register value is awaited.

[0132] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0133] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0134] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for implementing RISC-V processor extended instructions, characterized in that, include: The instruction is tagged according to its type and / or the type of register used; The instructions are assigned to different pipelines for execution based on the flags; The step of marking the instruction according to its type and / or the type of register used includes: The instruction that is an extended instruction and uses a general-purpose register is marked as a first extended instruction, and the value of the first predetermined position of the first extended instruction is set to a first predetermined value; the instruction that is an extended instruction and uses an extended register is marked as a second extended instruction, and the value of the first predetermined position of the second extended instruction is set to a second predetermined value. The sequence of the first extended instructions in the pipeline is counted and recorded, and the sequence of the first extended instructions is written into the second predetermined position of the first extended instructions; and in response to the parsing of the second extended instruction, the final value of the sequence of the first extended instructions is written into the second predetermined position of the second extended instructions, and the sequence of the first extended instructions is cleared to zero. Specifically, the first extended instruction is a KG type instruction, and the second extended instruction is a KK type instruction; a set_num flag is set in the 32 bits of the instruction in the RISC-V processor to mark the group matching of the KG type instruction and the KK type instruction; through the set_num flag in the KG type and KK type extended instructions, when the decoder decodes the instructions in the pipeline, if a KG type instruction is parsed, the KG type instruction is marked. For each KG type instruction parsed, a counter register is set to record the number of KG type instructions, and the value of the counter register is used as the set_num value of the KG type instruction; if a KK type instruction is parsed, the value of the counter register is written to the corresponding bit of the set_num of the KK type instruction, and the counter register is set to 0.

2. The method according to claim 1, characterized in that, The step of allocating the instructions to different pipelines for execution based on the flag includes: The first extended instruction and the general instruction are assigned to the first Scoreboard, and the first Scoreboard sends the first extended instruction and the general instruction to the first transmitter. The second extended instruction is assigned to the second Scoreboard, which then sends the second extended instruction to the second transmitter.

3. The method according to claim 2, characterized in that, The step of allocating the instructions to different pipelines for execution based on the marker further includes: The first transmitter sends a first extended instruction to the second transmitter.

4. The method according to claim 3, characterized in that, The step of allocating the instructions to different pipelines for execution based on the marker further includes: In response to the second transmitter receiving a first extended instruction from the first transmitter and / or the second scoreboard, it is determined whether the register used by the first extended instruction is occupied; In response to the register used by the first extended instruction being occupied, the first extended instruction is sent to the second Scoreboard.

5. The method according to claim 2, characterized in that, The step of allocating the instructions to different pipelines for execution based on the marker further includes: The second transmitter records the value of the second predetermined position of the transmitted first extended instruction through a shift register; In response to the second transmitter receiving a second extended instruction, the second transmitter compares the value at a second predetermined position of the second extended instruction with the value in the shift register; In response to the second extended instruction having a value at a second predetermined position that is less than the value of the shift register, the second extended instruction is shifted to read the next value of the shift register or a new value of the shift register is waited for.

6. The method according to claim 2, characterized in that, The step of allocating the instructions to different pipelines for execution based on the marker further includes: The second transmitter records the value of the second predetermined position of the first extended instruction transmitted by multiplying the corresponding positions in the queue; In response to the second transmitter receiving a second extended instruction, the second transmitter compares the factorial of the value at the second predetermined position of the second extended instruction with the value at the corresponding position in the queue; In response to the factorial of the value at the second predetermined position of the second extended instruction being greater than the value at the corresponding position in the queue, the shift instruction is either read from the next shift register or the value of a new shift register is awaited.

7. A processor, characterized in that, The hardware logic in the processor implements the steps of the method according to any one of claims 1-6.

8. A computer, characterized in that, The computer has the processor described in claim 7, and the hardware logic of the processor implements the steps of the method described in any one of claims 1-6.

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