A method and apparatus for processing pooled resources, an electronic device, and a medium

Abstract

The application discloses a processing method and device of pooling resources, electronic equipment and medium. The method is applied to an FPGA cloud platform. The FPGA cloud platform comprises an FPGA acceleration card, a switch, a bottom plate and a host. The bottom plate comprises a card slot, is used for inserting the FPGA acceleration card, and supplies power for the FPGA acceleration card. The switch is connected with a fiber network port of the FPGA acceleration card, is used for realizing data interaction between the FPGA acceleration cards. The host is connected with the switch, is used for sending a UDP message to the FPGA acceleration card through the switch. The FPGA acceleration card is used for receiving the UDP message sent by the switch, then analyzing the UDP message to obtain QP field information, and then inputting data to a Kernel end corresponding to the QP field information for processing. It can be seen that the method disclosed by the application realizes multiple Kernel acceleration operations on the same FPGA acceleration card, and can efficiently utilize the pooling resources.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a method, device, electronic device, and medium for processing pooled resources. Background Art

[0002] With the rapid development of cloud computing technology, more and more businesses are relying on cloud processing. Data analysis and processing consume significant server resources. Meanwhile, with the fading of Moore's Law, the growth of CPU computing power is no longer sufficient to meet the demands of these businesses. Consequently, heterogeneous acceleration systems have become a key option. Field Programmable Gate Array (FPGA) devices, as high-performance, low-power programmable chips, offer higher computational efficiency and significant advantages when processing massive amounts of data. This is especially true when deploying large numbers of servers, significantly reducing hidden operating costs. Therefore, FPGA-based heterogeneous platforms offer a new approach for implementing heterogeneous acceleration platforms. Currently, FPGA-based cloud platforms are widely used in data centers. When a data stream from an application arrives at the data center, it needs to be deployed to the corresponding FPGA in the FPGA resource pool for accelerated processing.

[0003] Figure 1 This is a structural diagram of a traditional cloud platform based on a high-speed serial computer expansion bus standard (PCI-E) card slot server cabinet, such as Figure 1 As shown, 1 is a server cabinet with PCI-E slots, 2 is a fiber optic network port, 3 is an FPGA accelerator card, and 4 is a host. Each cabinet group corresponds to a host, and data is transmitted to the host via the PCI-E interface. The FPGA accelerator cards are all inserted into the cabinet's PCI-E slots, and the FPGA accelerator cards are interconnected via the fiber optic network port. In specific implementation, the host transfers the data to be accelerated to the memory unit (Memory) of the local FPGA accelerator card via the PCI-E interface. The data is then read from the Memory and transferred to the core module (Kernel) for acceleration. After the current acceleration is completed, the data is written to the Memory. The data is then read from the Memory and sent to the remote FPGA accelerator card via the fiber optic network port for further acceleration processing. The same remote FPGA accelerator card performs the same acceleration processing. After the entire data stream is accelerated, the data is sent to the host via the PCI-E interface. In the current method, each FPGA accelerator card can only perform the acceleration operation of one kernel. In small data acceleration applications, the FPGA resources in the resource pool cannot be fully utilized, resulting in resource waste.

[0004] It can be seen that how to efficiently use pooled resources is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0005] The application aims to provide a processing method and device for pooling resources, electronic equipment and medium, which are used for performing multiple Kernel acceleration operations on the same FPGA acceleration card and can efficiently utilize the pooled resources.

[0006] To solve the above technical problems, the application provides an FPGA cloud platform, comprising: an FPGA acceleration card 3, a switch 6, a backplane 5 and a host 4.

[0007] The backplane 5 comprises a card slot for inserting the FPGA acceleration card 3 to supply power for the FPGA acceleration card 3.

[0008] The switch 6 is connected with the fiber network port 2 of the FPGA acceleration card 3 to realize data interaction between the FPGA acceleration cards 3.

[0009] The host 4 is connected with the switch 6 to send a UDP message to the FPGA acceleration card 3 through the switch 6.

[0010] The FPGA acceleration card 3 is used for receiving the UDP message sent by the switch 6, the UDP message comprising data and QP field information, and parsing the UDP message to obtain the QP field information and inputting the data to a Kernel end corresponding to the QP field information for processing, wherein the QP field information corresponds to the Kernel end.

[0011] Preferably, the backplane 5 is multiple.

[0012] To solve the above technical problems, the application further provides a processing method for pooling resources, which is applied to an FPGA cloud platform, and the method comprises the following steps.

[0013] Receiving a UDP message sent by a switch, the UDP message comprising data and QP field information, wherein the QP field information corresponds to a Kernel end.

[0014] Parsing the UDP message to obtain the QP field information.

[0015] Inputting the data to the Kernel end corresponding to the QP field information for processing.

[0016] Preferably, after the processing of the Kernel end is completed, the method further comprises the following steps.

[0017] Polling scheduling is adopted.

[0018] Preferably, after the polling scheduling is adopted, the method further comprises the following steps.

[0019] Packaging and sending the data of the Kernel end.

[0020] Preferably, the UDP message is transmitted in a streaming manner.

[0021] To solve the above technical problems, the application further provides a processing device of pooled resources, comprising:

[0022] The receiving module 10 is configured to receive the UDP packet sent by the switch 6.

[0023] The parsing module 11 is configured to parse the UDP packet to obtain the QP field information.

[0024] The input module 12 is configured to input the data in the UDP packet to the Kernel end corresponding to the QP field information for processing.

[0025] To solve the above technical problems, the application further provides an electronic device, comprising:

[0026] The memory is configured to store the computer program.

[0027] The processor is configured to implement the steps of the processing method of pooled resources when executing the computer program.

[0028] To solve the above technical problems, the application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by the processor to implement the steps of the processing method of pooled resources.

[0029] The application provides a processing method of pooled resources, which is applied to an FPGA cloud platform. Since the FPGA cloud platform comprises an FPGA acceleration card 3, a switch 6, a bottom plate 5 and a host 4, the bottom plate 5 comprises a card slot for inserting the FPGA acceleration card 3 to supply power for the FPGA acceleration card 3, the switch 6 is connected with the fiber network port 2 of the FPGA acceleration card 3 to realize data interaction between the FPGA acceleration cards 3, the host 4 is connected with the switch 6 to send a UDP packet to the FPGA acceleration card 3 through the switch 6, and the FPGA acceleration card 3 is configured to receive the UDP packet sent by the switch 6, the UDP packet comprising data and QP field information, then parse the UDP packet to obtain the QP field information, and then input the data to the Kernel end corresponding to the QP field information for processing, wherein the QP field information corresponds to the Kernel end. The method sends the UDP packet to the FPGA acceleration card 3 through the switch 6 by the host 4, parses the UDP packet after the FPGA acceleration card 3 receives the UDP packet, obtains the QP field information of each data, and then sends the data to the Kernel end corresponding to the QP field information for processing, thereby realizing multiple Kernel acceleration operations on the same FPGA acceleration card 3, effectively avoiding the resource waste that each Kernel acceleration operation can only be processed on one FPGA acceleration card 3, and efficiently utilizing the pooled resources.

[0030] In addition, the processing device for pooling resources, the electronic device and the medium provided by the application correspond to the processing method for pooling resources, and the effects are as above. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0032] Figure 1 The structural diagram of the traditional cloud platform based on the PCI-E card slot server cabinet is shown in Figure 1.

[0033] Figure 2 The structural diagram of the FPGA cloud platform provided by the present application is shown in Figure 2.

[0034] Figure 3 The flowchart of the processing method for pooling resources provided by the present application is shown in Figure 3.

[0035] Figure 4 The structural diagram of the processing device for pooling resources provided by the present application is shown in Figure 4.

[0036] Figure 5 The structural diagram of the electronic device provided by the present application is shown in Figure 5.

[0037] In the figure, 1 is a PCI-E card slot server cabinet, 2 is a fiber network port, 3 is an FPGA acceleration card, 4 is a host computer, 5 is a bottom plate, 6 is a switch, 10 is a receiving module, 11 is an analysis module, 12 is an input module, 20 is a storage, 21 is a processor, 22 is a display screen, 23 is an input / output interface, 24 is a communication interface, 25 is a communication bus, 201 is a computer program, 202 is an operating system, and 203 is data. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0039] The core of the present application is to provide a processing method, device, electronic device and medium for pooling resources, which is used for performing multiple Kernel acceleration operations on the same FPGA acceleration card 3, and can efficiently utilize the pooled resources.

[0040] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0041] Figure 2 This is a structural diagram of an FPGA cloud platform provided by this application. Figure 2 The structure shown is explained.

[0042] The FPGA cloud platform includes an FPGA accelerator card 3, a switch 6, a baseboard 5, and a host 4. The baseboard 5 includes a card slot for inserting the FPGA accelerator card 3 and providing power to the FPGA accelerator card 3. The switch 6 is connected to the optical network port 2 of the FPGA accelerator card 3 to enable data exchange between the FPGA accelerator cards 3. The host 4 is connected to the switch 6 and is used to send User Datagram Protocol (UDP) packets to the FPGA accelerator card 3 through the switch 6. The FPGA accelerator card 3 is used to receive the UDP packet sent by the switch 6. The UDP packet includes data and queue (QP) field information, parses the UDP packet to obtain the QP field information, and inputs the data into the kernel end corresponding to the QP field information for processing. The QP field information corresponds to the kernel end.

[0043] In this embodiment, the FPGA accelerator card 3 is inserted into the card slot of the baseboard 5, and the host 4 is connected to the switch 6. The switch 6 is used to interconnect all the FPGA accelerator cards 3 through the optical network port 2 to form an FPGA cloud platform as a whole. Figure 2 It should be noted that the entire FPGA cloud platform is in the same network, and all connected FPGA acceleration cards 3 in the FPGA cloud platform are resource pools for accelerating data processing. Figure 2 As shown, the switch 6 can connect multiple hosts 4. All hosts 4 are in the same network and can transmit data with the FPGA accelerator card 3 through the switch 6, making it easy for multiple hosts 4 to interact with the same FPGA accelerator card 3. In a specific implementation, there can be multiple baseboards 5. The number of baseboards 5 can be flexibly increased or decreased according to business needs, thereby achieving the purpose of increasing or decreasing the number of FPGA accelerator cards 3 in the resource pool, and no longer being affected by Figure 1 The number of PCI-E card slots in the server cabinet 1 is limited. In addition, when the FPGA cloud platform is working, the PCI-E interface gold finger of the FPGA accelerator card 3 needs to be inserted into the card slot of the baseboard 5 to power the FPGA accelerator card 3.

[0044] In the working of the FPGA cloud platform, the FPGA cloud platform adds QP field information in the UDP message and sends it to the FPGA acceleration card 3 through the switch 6. After the FPGA acceleration card 3 receives the UDP message, it pre-processes the UDP message, parses the data and QP field information in the UDP message, and since the QP field information corresponds to the Kernel end, after the parsing is completed, the data in the message is input to the corresponding Kernel end for processing according to the parsed QP field information. When the Kernel end processing is completed, the accelerated data is packaged and sent to the host 4 through the Ethernet first and then sent to the switch 6. It should be noted that when the UDP message is transmitted through the Ethernet, the UDP message is directly input and output in the form of a stream, and the local cache of the FPGA acceleration card 3 is no longer needed in the transmission process.

[0045] The embodiment provides an FPGA cloud platform, which comprises an FPGA acceleration card 3, a switch 6, a backboard 5 and a host 4; the backboard 5 comprises a card slot for inserting the FPGA acceleration card 3 to supply power for the FPGA acceleration card 3; the switch 6 is connected with the fiber network port 2 of the FPGA acceleration card 3 and is used for realizing data interaction between the FPGA acceleration cards 3; the host 4 is connected with the switch 6 and is used for sending a UDP message to the FPGA acceleration card 3 through the switch 6; the FPGA acceleration card 3 is used for receiving the UDP message sent by the switch 6, the UDP message comprising data and QP field information, then parsing the UDP message to obtain the QP field information, and then inputting the data to the Kernel end corresponding to the QP field information for processing, wherein the QP field information corresponds to the Kernel end. In the embodiment, the host 4 sends the UDP message to the FPGA acceleration card 3 through the switch 6, the FPGA acceleration card 3 receives the UDP message and parses it to obtain the QP field information of each data, and then sends the data to the Kernel end corresponding to the QP field information for processing, thereby realizing multiple Kernel acceleration operations on the same FPGA acceleration card 3, effectively avoiding the resource waste that each Kernel acceleration operation can only be processed on one FPGA acceleration card 3, and efficiently utilizing the pooling resources.

[0046] In the above embodiment, it is mentioned that the backboard 5 can be multiple, and the number of the backboard 5 can be flexibly increased or decreased according to actual needs. In the embodiment, the number of the backboard 5 is set to be multiple, and each backboard 5 comprises multiple card slots for supplying power for the FPGA acceleration card 3 when the FPGA acceleration card 3 is inserted.

[0047] In the embodiment, the number of the backboard 5 is set to be multiple, and the number of the backboard 5 can be flexibly increased or decreased according to actual needs, thereby breaking through the limitation of the number of the card slots of the PCI-E card slot server cabinet 1.

[0048] Figure 3A flowchart of a processing method of pooling resources is provided in the present application, the method is applied to an FPGA cloud platform, and comprises the following steps of:

[0049] S1: receiving a UDP message sent by a switch, wherein the UDP message comprises data and QP field information, and the QP field information corresponds to a Kernel end;

[0050] S2: analyzing the UDP message to obtain the QP field information;

[0051] S3: inputting the data into the Kernel end corresponding to the QP field information for processing.

[0052] In the embodiment, the FPGA acceleration card 3 receives the UDP message sent by the switch 6 and analyzes the UDP message to obtain the QP field information. Since the QP field information corresponds to the Kernel end, the data in the UDP message can be input into the corresponding Kernel end for acceleration processing according to the QP field information, thereby realizing processing of multiple Kernel acceleration operations on the same FPGA acceleration card 3 and efficiently utilizing the pooled resources.

[0053] After the data processing of each Kernel end in the above embodiment is completed, the data of each Kernel end in the FPGA acceleration card 3 needs to be sent out. In the embodiment, the data is sent in an equivalent polling scheduling mode, so that each Kernel port has equivalent bandwidth to output data. The polling scheduling mode in the embodiment is exemplarily described below.

[0054] The Kernel ends are sequentially named as Kernel_0, Kernel_1, …, and Kernel_n. The polling scheduling module in the FPGA acceleration card 3 defaults that the Kernel port responding to the first polling is Kernel_0. Each arbitration response is scheduled in a polling manner, and the responses are sequentially from Kernel_1 to Kernel_n. After the response to the polling of Kernel_n, the responses return to Kernel_0 again. It should be noted that in the embodiment, the new Kernel port responding is the Kernel port closest to the previous responding Kernel port.

[0055] In the embodiment, the data of each Kernel end is sent in an equivalent polling scheduling mode, the interface bandwidth is effectively utilized, and the situation that some Kernel ends are in a waiting state for a long time when sending data can be avoided.

[0056] After the polling scheduling in the above embodiment is completed, in order to guarantee the safety of data in the transmission process, the data of each Kernel end can be packaged and sent. In this embodiment, the data processed by each Kernel end is packaged into a network packet, and then sent to the host 4 through the switch 6. It should be noted that the data of each Kernel end can be packaged and sent separately, or data with the same format can be packaged into a network packet for transmission according to the data format. The present embodiment does not limit this.

[0057] In this embodiment, the data processed by the Kernel end is packaged and sent, which guarantees the safety of data in the transmission process and effectively avoids the loss or alteration of data in the transmission process.

[0058] In the above embodiment, the transmission mode of the UDP packet is not described. In this embodiment, the UDP packet is transmitted in the form of a stream. Since the UDP packet includes data and QP field information, the data and the QP field information are transmitted in the form of a stream.

[0059] In this embodiment, the UDP packet is transmitted in the form of a stream. When the FPGA acceleration card 3 receives the UDP packet for preprocessing and sends the data after the Kernel acceleration is completed, the data no longer needs to be cached in the local memory unit, but is directly input and output in the form of a stream, which shortens the overall transmission time and improves the data processing speed.

[0060] In the above embodiment, the processing method of the pooling resource is described in detail, and the present application also provides an embodiment of a processing device of the pooling resource. It should be noted that the embodiments of the device part are described from two angles, one is based on the functional module, and the other is based on the hardware.

[0061] Figure 4 A structural diagram of a processing device of a pooling resource provided by the present application is shown in FIG. 10. As shown in FIG. 10, the device includes: Figure 4

[0062] The receiving module 10 is configured to receive the UDP packet sent by the switch 6.

[0063] The parsing module 11 is configured to parse the UDP packet to obtain the QP field information.

[0064] The input module 12 is configured to input the data in the UDP packet to the Kernel end corresponding to the QP field information for processing.

[0065] Since the embodiments of the device part correspond to the embodiments of the method part, the embodiments of the device part are described in the description of the embodiments of the method part, which will not be described here. ​

[0066] Figure 5 A structural diagram of an electronic device provided in the present application is shown in FIG. 1, which includes a memory 20 for storing a computer program. Figure 5

[0067] A processor 21 is configured to implement the steps of the processing method of the pooling resource as mentioned in the above embodiments when executing the computer program.

[0068] The electronic device provided in the present embodiment can include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, etc.

[0069] The processor 21 can include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one of a hardware form of a Digital Signal Processing (DSP), a Field-Programmable Gate Array (FPGA), a Programmable Logic Array (PLA). The processor 21 can also include a main processor and a coprocessor. The main processor is a processor for processing data in a wake-up state, also known as a Central Processing Unit (CPU). The coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 can be integrated with a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, the processor 21 can further include an Artificial Intelligence (AI) processor, which is configured to process computing operations related to machine learning.

[0070] The memory 20 can include one or more computer-readable storage media, which can be non-transitory. The memory 20 can further include a high-speed random access memory, and a non-volatile memory such as one or more disk storage devices, flash storage devices. In the present embodiment, the memory 20 is at least used to store the following computer program 201, wherein the computer program is loaded and executed by the processor 21, and can implement the related steps of the processing method of the pooling resource disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 can further include an operating system 202 and data 203, etc., and the storage mode can be temporary storage or permanent storage. The operating system 202 can include Windows, Unix, Linux, etc. The data 203 can include, but is not limited to, a UDP packet, etc.​

[0071] In some embodiments, the electronic device can further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0072] Those skilled in the art can understand that the structure shown in the above-mentioned embodiments does not constitute a limitation on the electronic device, and can include more or fewer components than those shown in the drawings. Figure 5

[0073] Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the processing method of the pooled resource as described in the above method embodiment.

[0074] It can be understood that if the method in the above embodiments is implemented in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or say the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and executes all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0075] The processing method of the pooled resource, the device, the electronic device and the medium provided by the present application are described in detail above. The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be referred to. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part. It should be pointed out that for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0076] ​It also needs to be explained that in the present specification, the relational terms such as first and second and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

Claims

1. An FPGA cloud platform, characterized in that, It comprises: FPGA acceleration card (3), switch (6), backplane (5) and host (4); The backplane (5) comprises a card slot for inserting the FPGA acceleration card (3) and supplying power for the FPGA acceleration card (3); The switch (6) is connected with the fiber network port (2) of the FPGA acceleration card (3) to realize data interaction between the FPGA acceleration cards (3); The host (4) is connected with the switch (6) to send UDP messages to the FPGA acceleration card (3) through the switch (6); The FPGA acceleration card (3) receives the UDP message sent by the switch (6), the UDP message comprising data and queue field information, parses the UDP message to obtain the queue field information, and inputs the data into the Kernel end corresponding to the queue field information for processing, wherein the queue field information corresponds to the Kernel end.

2. The FPGA cloud platform of claim 1, wherein, The backplane (5) is multiple.

3. A method of processing pooled resources, characterized by, The method applied to the FPGA cloud platform of claim 1 comprises: Receiving the UDP message sent by the switch, the UDP message comprising data and queue field information, wherein the queue field information corresponds to the Kernel end; Parsing the UDP message to obtain the queue field information; Inputting the data into the Kernel end corresponding to the queue field information for processing.

4. The method of claim 3, wherein, After the Kernel end processing is completed, it further comprises: Using polling scheduling.

5. The method of claim 4, wherein, After the polling scheduling is used, it further comprises: Packaging and sending the data of the Kernel end.

6. The method of claim 3, wherein, The UDP message is transmitted in a streaming manner.

7. A processing device for pooling resources, characterized by The FPGA cloud platform of claim 1 comprises: A receiving module (10) for receiving the UDP message sent by the switch (6); An analysis module (11) for analyzing the UDP message to obtain queue field information; An input module (12) for inputting the data in the UDP message into the Kernel end corresponding to the queue field information for processing.

8. An electronic device, comprising: It comprises a memory for storing a computer program; A processor for executing the computer program to realize the steps of the processing method of the pooled resource according to any one of claims 3 to 6.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to realize the steps of the processing method of the pooled resource according to any one of claims 3 to 6.

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