Host Memory Access Method, Device, Electronic Device and Storage Medium

Abstract

The present application discloses a method, apparatus, electronic device and computer-readable storage medium for accessing host memory. The method includes: obtaining and parsing a target command to obtain a command type identifier; if the command type identifier is in a first state, obtaining a scatter-gather table data structure by using the target command; obtaining access location information by using the scatter-gather table data structure; accessing the host memory in the host by using the access location information. By setting the command type identifier, the method differentiates the command for accessing the HMB from the command generated based on the NVMe protocol, and reuses the function of the DMA controller in the NVMe controller to access the host side, so as to realize the access to the HMB without separately designing a circuit and without increasing the chip area.

Description

Technical Field

[0001] This application relates to the technical field of solid state drives, and particularly relates to a host memory access method, a host memory access device, an electronic device, and a computer-readable storage medium. Background Art

[0002] With the rapid development of cloud computing, artificial intelligence, and the Internet of Things, etc., the demand for storage by terminal products and servers is increasing. In this process, NVMe (Non-Volatile Memory express) solid state drives (SSDs) have received more and more attention in the storage field with many advantages such as low latency, low power consumption, and high bandwidth, driving the rapid development of the main storage field. HMB (Host Memory Buffer) is a mechanism by which the host can provide memory resources that are not currently needed to the SSD through the NVMe protocol. For an SSD, to access the host memory in the host, it usually needs to design a separate hardware circuit. However, this hardware circuit will increase the chip area of the SSD. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a host memory access method, a host memory access device, an electronic device, and a computer-readable storage medium, which can achieve access to the HMB without separately designing a circuit and without increasing the chip area.

[0004] To solve the above technical problems, this application provides a host memory access method, including:

[0005] Obtain and parse a target command to obtain a command type identifier;

[0006] If the command type identifier is a first state, use the target command to obtain a scatter-gather table data structure;

[0007] Use the scatter-gather table data structure to obtain access location information;

[0008] Use the access location information to access the host memory in the host.

[0009] Optionally, the using the target command to obtain a scatter-gather table data structure includes:

[0010] Obtain scatter-gather table address information from the target command;

[0011] Use the scatter-gather table address information to obtain the scatter-gather table data structure.

[0012] Optionally, the obtaining scatter-gather table address information from the target command includes:

[0013] Read the multiplexed double-word field in the target command to obtain the SGL base address, SGL length, SGL type, and SGL position, and determine the SGL type, the SGL base address, the SGL length, and the SGL position as the scatter-gather table address information.

[0014] Optionally, the obtaining the scatter-gather table data structure by using the scatter-gather table address information includes:

[0015] Determine the object to be accessed by using the SGL position;

[0016] Based on the SGL type, read the object to be accessed by using the SGL base address and the SGL length to obtain initial data;

[0017] If the SGL type is the linked list state, parse the initial data to obtain new scatter-gather table address information;

[0018] If the SGL type is the data block state, determine the initial data as the scatter-gather table data structure.

[0019] Optionally, the obtaining the access position information by using the scatter-gather table data structure includes:

[0020] Parse the lower bit of the host base address, the higher bit of the host base address, and the access length from the scatter-gather table data structure;

[0021] Concatenate the lower bit of the host base address and the higher bit of the host base address to obtain the host base address, and determine the host base address and the access length as the access position information.

[0022] Optionally, the accessing the host memory in the host by using the access position information includes:

[0023] Initiate an access request to the host;

[0024] If the response of the host is detected, access the host memory according to the target access position information corresponding to the target scatter-gather table data structure;

[0025] If the access flag meets the completion condition, determine that the access is completed;

[0026] If the access flag does not meet the completion condition, update the target scatter-gather table address information and update the access flag according to the update situation.

[0027] Optionally, the obtaining and parsing the target command to obtain the command type identifier includes:

[0028] Obtain an initial command from the command queue, and parse the initial command to obtain a command ID field;

[0029] Use the command ID field to perform a legality check on the initial command;

[0030] If the legality check is passed, determine the initial command as the target command, and parse the initial command to obtain the command type identifier.

[0031] This application also provides a host memory access device, including:

[0032] A parsing module, configured to obtain and parse a target command to obtain a command type identifier;

[0033] A first obtaining module, configured to, if the command type identifier is in a first state, use the target command to obtain a scatter-gather table data structure;

[0034] A second obtaining module, configured to obtain access location information by using the scatter-gather table data structure;

[0035] An access module, configured to access the host memory in the host by using the access location information.

[0036] This application also provides an electronic device, including a memory and a processor, wherein:

[0037] The memory is configured to store a computer program;

[0038] The processor is configured to execute the computer program to implement the above-mentioned host memory access method.

[0039] This application also provides a computer-readable storage medium, configured to store a computer program, wherein the computer program, when executed by a processor, implements the above-mentioned host memory access method.

[0040] The host memory access method provided by this application obtains and parses a target command to obtain a command type identifier; if the command type identifier is in a first state, uses the target command to obtain a scatter-gather table data structure; obtains access location information by using the scatter-gather table data structure; and accesses the host memory in the host by using the access location information.

[0041] It can be seen that this method is applied to the DMA (Direct Memory Access) controller of an SSD, and it can realize the function of accessing host - side data under a non - NVMe protocol. When parsing the target command for accessing the HMB, the command - type identifier therein can be recognized. If the command - type identifier is in the first state, it indicates that the target command is used to access the HMB. Therefore, the SGL (Scatter Gather List) data structure can be obtained from the target command. The SGL data structure specified by the target command stores the access - location information corresponding to the host memory. Since the DMA controller can access host data, the host memory in the host can be accessed using the access - location information. By setting the command - type identifier, the commands for accessing the HMB are distinguished from the commands generated based on the NVMe protocol, and the function that the DMA controller of the NVMe controller can access the host - side is reused. Without the need to separately design a circuit and without increasing the chip area, the access to the HMB is realized.

[0042] In addition, the present application also provides a host - memory access device, an electronic device, and a computer - readable storage medium, which also have the above - mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] To more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the provided drawings.

[0044] Figure 1 It is a flowchart of a host - memory access method provided by an embodiment of the present application;

[0045] Figure 2 It is a flowchart of an operation - control state - machine update provided by an embodiment of the present application;

[0046] Figure 3 It is a schematic structural diagram of a host - memory access device provided by an embodiment of the present application;

[0047] Figure 4 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts shall fall within the scope of protection of this application.

[0049] Please refer to Figure 1 , Figure 1 , which is a flowchart of a method for accessing the host memory provided by an embodiment of this application.

[0050] The method includes:

[0051] S101: Obtain and parse a target command to obtain a command type identifier.

[0052] Each step in this application is executed by a DMA controller. When the end-to-end read / write function is adopted, the DMA controller can specifically be a DMA controller for performing a host-side read operation or a DMA controller for performing a host-side write operation. Among them, the target command is a DMA command, which refers to the command that the DMA controller wants to execute. After obtaining the target command, it is parsed to obtain the command type identifier from it. The command type identifier is an identifier that characterizes the type of the target command. In this application, there are two types of target commands. The first is a normal DMA command under the NVMe protocol, and the second is a command for accessing the HMB. Among them, the second command is generated by the CPU of the SSD. The CPU mimics the command constructed by the NVMe controller to generate the second command and sends it to the queue. Executing this command can complete the function of the DMA controller itself that can access the host side, and achieve access to the HMB without specifically designing a hardware circuit for accessing the HMB. The specific form of the command type identifier is not limited. For example, a bit can be added to the general DMA command data structure, and this bit is used as the command type identifier. This bit can be called rd_wr_host, that is, the read / write host-side bit. Further, when this bit is 1, the target command can be determined as a DMA command for accessing the HMB.

[0053] Normally, DMA commands are stored in a command queue and are taken out from the command queue when they need to be executed. To avoid waste of computing resources and avoid command execution errors, S101 can include the following steps:

[0054] Step 11: Obtain an initial command from the command queue and parse the initial command to obtain a command ID field.

[0055] Step 12: Perform a legality check on the initial command using the command ID field.

[0056] Step 13: If the legality check passes, determine the initial command as the target command and parse the initial command to obtain the command type identifier.

[0057] Here, the initial command refers to the command directly obtained from the command queue, from which the command ID field (i.e., the cmd_id field) can be parsed. The command ID field is used to represent the identity of the command. After obtaining the command ID field, the NVMe information can be read from the SRAM (Static Random Access Memory) inside the NVMe controller and used to perform a legality check with the command ID field to determine whether the initial command is a legal DMA command. If so, that is, if the legality check passes and it is confirmed that the initial command is a legal DMA command, parsing and executing it will not cause waste of computing resources or errors, so it is parsed to obtain the command type identifier.

[0058] After obtaining the command type identifier, since there are two types of target commands, different types of target commands need to be processed in different forms. When the command type identifier is in the second state, it indicates that the target command is a DMA command under the NVMe protocol. In this case, the target command can be processed based on the NVMe protocol, and the specific processing process can refer to related technologies.

[0059] S102: If the command type identifier is in the first state, obtain the scatter-gather table data structure using the target command.

[0060] S103: Obtain the access location information using the scatter-gather table data structure.

[0061] If the command type identifier is in the first state, it indicates that the target command is a DMA command for accessing the HMB. This access can be specifically a read or a write. In this case, further according to the indication of the target command, the scatter-gather table data structure for the access location information can be obtained, and then the access location information can be obtained from it. This embodiment does not limit the specific acquisition method of the scatter-gather table data structure. In a feasible implementation, the scatter-gather table address information can be obtained from the target command, and the scatter-gather table data structure can be obtained using the scatter-gather table address information. The scatter-gather table address information, that is, the SGL address information, is used to provide the storage location of the scatter-gather table data structure (i.e., the SGL data structure), so that the SGL data structure can be obtained using the SGL address information, and then the access location information of the host can be obtained from the SGL data structure, and this access location information points to the HMB.

[0062] This embodiment does not limit the specific manner of storing the SGL address information of the target command. In a feasible embodiment, when generating the target command, the CPU first determines the total data length. If the sum of the data length and the offset address length of the PRP1 (Physical Region Page, PRP, physical region page) address does not exceed the page boundary, the NVMe protocol command field PRP1 address field segment is used to carry the data to be transmitted; if the part of the sum of the data length and the offset address length of the PRP1 address that exceeds the page boundary is less than the size of one page, the PRP1 address field segment and the PRP2 address field segment are used to carry the data to be transmitted; if the part of the sum of the data length and the offset address length of the PRP1 address that exceeds the page boundary is greater than the size of one page, the PRP1 address field segment, the PRP2 address field segment, and the Meta address field segment are used to carry the data to be transmitted.

[0063] In another embodiment, a double-word field can be reused. For example, the Meta address field segment of the NVMe command is used to transmit the SGL address information. Specifically, the process of obtaining the scatter-gather list address information from the target command may include:

[0064] Step 21: Read the reused double-word field in the target command to obtain the SGL base address, SGL length, SGL type, and SGL location, and determine the SGL type, SGL base address, SGL length, and SGL location as the scatter-gather list address information.

[0065] Among them, the SGL base address is the start address of the storage location pointed to by the SGL address information, which can be called the SGL base address. The SGL length refers to the length of the storage location, which can be called the SGL length. The SGL type refers to the type of data stored in the storage location. Since the SGL linked list can be nested, the data stored in this storage location can be an SGL data structure, or can be another SGL address information, and this SGL address information points to an SGL data structure or another new SGL address information. Using the SGL type, the data reading method and subsequent processing method can be determined. The SGL location refers to the hardware object to be read, specifically, it can be an on-chip cache or a DRAM (Dynamic Random Access Memory).

[0066] Furthermore, on this basis, the process of obtaining the scatter-gather list data structure using the scatter-gather list address information may include the following steps:

[0067] Step 31: Determine the object to be accessed using the SGL location.

[0068] Step 32: Based on the SGL type, read the object to be accessed using the SGL base address and SGL length to obtain the initial data.

[0069] Step 33: If the SGL type is in the linked list state, parse the initial data to obtain the address information of the new scatter-gather table.

[0070] Step 34: If the SGL type is in the data block state, determine the initial data as the scatter-gather table data structure.

[0071] Using the SGL position, the storage object of the SGL, i.e., the object to be accessed, such as DRAM or on-chip cache, can be determined. When the SGL types are different, it indicates that the data formats to be read are different. Therefore, the data reading methods and subsequent processing methods are also different. For example, reading is performed in units of two doublewords, or in units of three doublewords. Based on the SGL type, within the range delimited by the SGL base address and SGL length, the object to be accessed is read to obtain the initial data. It should be noted that the number of initial data obtained by reading can be one, or can be multiple. That is, the space delimited by the SGL base address and SGL length is relatively large. The reading method determined based on the SGL type can perform readings on different positions of this space respectively. Each reading obtains one initial data, and multiple readings obtain multiple initial data.

[0072] If the SGL type is in the linked list state, for example, 0, it indicates that the initial data read still records the SGL address information. Therefore, it can be parsed to obtain the new SGL address information for further reading using the new SGL address information, and finally the SGL data structure is obtained. If the SGL type is in the data block state, for example, 1, it indicates that the initial data read itself is the SGL data structure.

[0073] In one implementation, the structure of the multiplexed doubleword field can be as shown in Table 1, and the structure of the SGL data structure is as shown in Table 2:

[0074] Table 1 Multiplexed Doubleword Field Data Structure

[0075]

[0076] Table 2 SGL Data Structure

[0077]

[0078] Among them, SGL base address represents the SGL base address; DW1[23:0] is the SGL length, representing the SGL length in bits; DW1[29:24] are reserved bits, DW1

[30] is the sgl_loc bit, that is, the SGL location, indicating that the base address of this SGL is on-chip cache or DRAM; DW1

[31] is the sgl_type, that is, the SGL type, indicating that the SGL pointed to by this SGL address information is a data block or an SGL linked list. When it is a data block, the data read out with the SGL base address is the same data structure as in Table 2. Three doublewords are used to represent a host-side SGL data structure. DW0 and DW1 constitute the host-side base address, and DW2 constitutes the length of the data that can be written starting from this host base address, in bits. If it is an SGL linked list type, it means that the data read out is still the data structure as described in Table 1. Each entry is 2 doublewords, and the definitions of each field are the same as in Table 1. In this way, an SGL linked list can be formed to represent a storage space block of a long enough discrete host memory.

[0079] After obtaining the SGL data structure, the access location information can be read from it. Specifically, the process of obtaining the access location information using the scatter-gather table data structure may include the following steps:

[0080] Step 41: Parse from the scatter-gather table data structure to obtain the low-order host base address, high-order host base address, and access length.

[0081] Step 42: Concatenate the low-order host base address and the high-order host base address to obtain the host base address, and determine the host base address and the access length as the access location information.

[0082] Among them, the low-order host base address is Host base address low, the high-order host base address is Hostbase address high, and the access length is Host length. By concatenating the low-order and high-order parts, the host base address can be obtained, and then the access location information can be determined.

[0083] S104: Access the host memory in the host using the access location information.

[0084] After obtaining the access location information, it can be used to access the HMB in the host, specifically for reading or writing. It can be understood that each SGL data structure can obtain an access location information. When there are multiple SGL address information, multiple SGL data structures can be obtained, and then multiple access location information can be obtained. In this case, when performing data access, in order to ensure the integrity of data access, the access flag can be used to represent the completion status of data access. Specifically, the process of accessing the host memory in the host using the access location information may include the following steps:

[0085] Step 51: Initiate an access request to the host.

[0086] Step 52: If a response from the host is detected, access the host memory according to the target access location information corresponding to the target scatter-gather table data structure.

[0087] Step 53: If the access flag meets the completion condition, determine that the access is complete.

[0088] Step 54: If the access flag does not meet the completion condition, update the target scatter-gather table address information and update the access flag according to the update situation.

[0089] In this embodiment, the number of SGL address information is at least two, which may specifically include the SGL address information directly read from the target command, or the SGL address information obtained when further reading the SGL address information with the SGL type in the linked list state. After initiating a request to the host and obtaining a response, select the target SGL address information from multiple SGL address information and use the corresponding target access location information to access the HMB. After this access is completed, determine whether the access flag meets the completion condition. If it meets the completion condition, for example, it is 1, determine that the access is complete. Or if it does not meet the completion condition, it means that there is still part of the access location information corresponding to the SGL address information that has not been accessed. Therefore, re-select the new target scatter-gather table address information, that is, update the target SGL address information, and update the access flag according to the update situation of the target SGL address information. That is, if there is no SGL address information that has not been the target SGL address information after updating the target SGL address information, set the access flag to the state that meets the completion condition.

[0090] Applying the host memory access method provided by the embodiments of the present application to the DMA (Direct Memory Access) controller of an SSD can implement the function of accessing host - side data under a non - NVMe protocol. When parsing the target command for accessing the HMB, the command - type identifier therein can be recognized. If the command - type identifier is in the first state, it indicates that the target command is used to access the HMB. Therefore, the SGL (Scatter Gather List) data structure can be obtained from the target command. The access location information corresponding to the host memory is stored in the SGL data structure specified by the target command, and since the DMA controller can access host data, the host memory in the host can be accessed using the access location information. By setting the command - type identifier, the commands for accessing the HMB are distinguished from the commands generated based on the NVMe protocol, and the function that the DMA controller of the NVMe controller can access the host - side is reused. Without the need to separately design a circuit and without increasing the chip area, the access to the HMB is achieved.

[0091] Based on the above - mentioned embodiments, please refer to Figure 2 , Figure 2 which is a flowchart for updating an operation control state machine provided by the embodiments of the present application. When the CPU issues a DMA command to the DMA queue, the DMA controller in the IDLE state will automatically load the DMA command from the queue and read the NVMe command information from the NVMe internal SRAM according to the cmd_id field (i.e., the command ID field) in the DMA command to detect and confirm the legality of this DMA command. After determining that the DMA command is legal, the DMA command is executed to initiate a DMA transfer request. When the DMA controller detects that the din_req signal is 1 and the rd_wr_host signal (i.e., the command - type identifier) in the DMA command is 0, it is determined that it is a DMA command under the NVMe protocol. Therefore, the state machine jumps from the IDLE state to the PRP_REQ state to obtain the PRP information corresponding to this DMA command. After receiving the PRP information (i.e., after detecting that prp_ack is 1), it is detected whether there is available storage space in the current internal cache. In one embodiment, the size of the available storage space is in units of 1 KB. If the cache space is greater than 1 KB, the spc_avail signal is 1, and the state machine jumps to the DATA_REQ state, where a request to read host data is initiated. If the rd_ack signal replied by PCIe is 1, the state machine jumps to the DATA_REQ_CHK state. In the DATA_REQ_CHK state, if the current is a DMA command under the NVMe protocol (i.e., the rd_wr_host signal is 0), then ～When the rd_wr_host signal is 1), and the last_data signal indicating that the current data is the last piece of data is 1, or the prp_nbytes0 signal indicating that the PRP information has been used up is 1, the state machine jumps to the PRP_UPD state. In this state, if last_data is 1, the state machine jumps to the IDLE state, and the data transmission is completed. If the DMA data has not been transmitted yet, that is, last_data is 0 and prp_nbytes0 is 1, the state machine jumps to the PRP_REQ state to request new PRP information, and so on.

[0092] In the IDLE state, if din_req is 1 and the rd_wr_host signal is 1, indicating that the DMA command is a command for reading the HMB, the state machine jumps to the SGL_INIT state. In this state, the table 1 information (i.e., the SGL address information) of the multiplexed META field (i.e., the multiplexed double-word field) is loaded, and the init_sgl_ack signal is set to 1, and the state machine jumps to the SGL_REQ state. In this state, the SGL data structure (i.e., the SGL data structure) describing the host address in table 2 is loaded using the SGL address information to obtain the starting address and data length (i.e., the access location information) of the host side to be read by the DMA. The sgl_rd_ack signal is set to 1, and the state machine jumps to the SPAC_WAIT state. The SPAC_WAIT and DATA_REQ states are the same as the DMA operations of the above NVMe protocol and will not be elaborated here. In the DATA_REQ_CHK state, since the current rd_wr_host signal is 1, if the last_data signal is 1, indicating that the current is the last data transmission, the state machine jumps to the IDLE state. If the sgl_nbyte0 signal is 1 (usually, the sgl_nbyte0 signal is opposite to the last_data signal, and the sgl_nbyte0 signal is used to indicate whether there is unaccessed access location information, and both the sgl_nbyte0 signal and the last_data signal can be used as access flag bits), indicating that the currently available host-side address (i.e., the access location information) has been used up but the data has not been transmitted yet, the state machine jumps to the SGL_REQ state to continue requesting SGL, and so on.

[0093] Next, the host memory access device provided by the embodiment of the present application will be introduced. The host memory access device described below can be correspondingly referred to the host memory access method described above.

[0094] Please refer to Figure 3 , Figure 3 FIG.

[0095] A parsing module 110, configured to obtain and parse a target command to obtain a command type identifier;

[0096] A first obtaining module 120, configured to, if the command type identifier is a first status, obtain a scatter-gather table data structure by using the target command;

[0097] A second obtaining module 130, configured to obtain access location information by using the scatter-gather table data structure;

[0098] An access module 140, configured to access a host memory in a host by using the access location information.

[0099] Optionally, the first obtaining module 120 includes:

[0100] An address obtaining unit, configured to obtain scatter-gather table address information from the target command;

[0101] A data structure obtaining unit, configured to obtain the scatter-gather table data structure by using the scatter-gather table address information.

[0102] Optionally, the address obtaining unit includes:

[0103] An information reading unit, configured to read a multiplexed doubleword field in the target command to obtain an SGL base address, an SGL length, an SGL type, and an SGL location, and determine the SGL type, the SGL base address, the SGL length, and the SGL location as the scatter-gather table address information.

[0104] Optionally, the second obtaining module 130 includes:

[0105] An object determining unit, configured to determine an object to be accessed by using the SGL location;

[0106] A reading unit, configured to read the object to be accessed based on the SGL type by using the SGL base address and the SGL length to obtain initial data;

[0107] An initial parsing unit, configured to, if the SGL type is a linked list status, parse the initial data to obtain new scatter-gather table address information;

[0108] A data structure determining unit, configured to, if the SGL type is a data block status, determine the initial data as the scatter-gather table data structure.

[0109] Optionally, the second obtaining module 130 includes:

[0110] A host information parsing unit, configured to parse a host base address low, a host base address high, and an access length from the scatter-gather table data structure;

[0111] A splicing unit, which is used to splice the lower bits of the host base address and the higher bits of the host base address to obtain the host base address, and determine the host base address and the access length as access location information.

[0112] Optionally, the access module 140 includes:

[0113] A request unit, which is used to initiate an access request to the host;

[0114] A reading unit, which is used to access the host memory according to the target access location information corresponding to the target scatter-gather table data structure if a response from the host is detected;

[0115] An end determination unit, which is used to determine that the access is completed if the access flag meets the completion condition;

[0116] An update unit, which is used to update the target scatter-gather table address information and update the access flag according to the update situation if the access flag does not meet the completion condition.

[0117] Optionally, the parsing module 110 includes:

[0118] An ID parsing unit, which is used to obtain an initial command from the command queue and parse the initial command to obtain the command ID field;

[0119] A legality detection unit, which is used to perform legality detection on the initial command by using the command ID field;

[0120] A target determination unit, which is used to determine the initial command as a target command if the legality detection is passed, and parse the initial command to obtain the command type identifier.

[0121] Next, the electronic device provided by the embodiment of the present application will be introduced. The electronic device described below can be correspondingly referred to the host memory access method described above.

[0122] Please refer to Figure 4 , Figure 4 , which is a schematic structural diagram of an electronic device provided by an embodiment of the present application. The electronic device 100 may include a processor 101 and a memory 102, and may further include one or more of a multimedia component 103, an information input / output (I / O) interface 104, and a communication component 105.

[0123] Among them, the processor 101 is used to control the overall operation of the electronic device 100 to complete all or part of the steps in the above host memory access method; the memory 102 is used to store various types of data to support the operation of the electronic device 100. These data may include, for example, instructions for any application or method operating on the electronic device 100, as well as application-related data. The memory 102 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disc, or one or more of them.

[0124] The multimedia component 103 may include a screen and an audio component. Among them, the screen may be a touch screen, for example, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone, and the microphone is used to receive external audio signals. The received audio signals may be further stored in the memory 102 or sent through the communication component 105. The audio component further includes at least one speaker for outputting audio signals. The I / O interface 104 provides an interface between the processor 101 and other interface modules. The above other interface modules may be a keyboard, a mouse, buttons, etc. These buttons may be virtual buttons or physical buttons. The communication component 105 is used for wired or wireless communication between the electronic device 100 and other devices. Wireless communication, such as Wi-Fi, Bluetooth, near field communication (NFC), 2G, 3G, or 4G, or a combination of one or more of them. Accordingly, the communication component 105 may include: a Wi-Fi component, a Bluetooth component, and an NFC component.

[0125] The electronic device 100 can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components, and is used to execute the host memory access method provided in the above embodiments.

[0126] The computer-readable storage medium provided by the embodiments of the present application will be introduced below. The computer-readable storage medium described below can be correspondingly referred to the host memory access method described above.

[0127] The present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned host memory access method are implemented.

[0128] The computer-readable storage medium may include various media capable of storing program codes, such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs.

[0129] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple. For the relevant parts, reference can be made to the description in the method part.

[0130] Those skilled in the art can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed in this document can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been generally described according to their functions in the above description. Whether these functions are executed in the form of hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0131] The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be implemented directly in hardware, in software modules executed by a processor, or in a combination thereof. The software modules may be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0132] Finally, it should also be noted that in this document, relationships such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "including", "comprising" or any other variant are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device.

[0133] Specific examples are used in this document to illustrate the principles and implementation manners of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A method for accessing the host memory, characterized in that A DMA controller applied to a solid-state drive, comprising: Obtain and parse a target command to obtain a command type identifier; If the command type identifier is in a first state, use the target command to obtain a scatter-gather table data structure; wherein, the target command in the first state is a command under a non-NVMe protocol generated by the CPU of the solid-state drive imitating an NVMe controller; Obtain access location information by using the scatter-gather table data structure; Access the host memory in the host by using the access location information; Among them, the obtaining and parsing the target command to obtain the command type identifier includes: Obtain an initial command from a command queue, and parse the initial command to obtain a command ID field; Perform a legality check on the initial command by using the command ID field; If the legality check is passed, determine the initial command as the target command, and parse the initial command to obtain the command type identifier.

2. The host memory access method according to claim 1, characterized in that The using the target command to obtain the scatter-gather table data structure includes: Obtain scatter-gather table address information from the target command; Obtain the scatter-gather table data structure by using the scatter-gather table address information.

3. The host memory access method according to claim 2, wherein The obtaining the scatter-gather table address information from the target command includes: Read a multiplexed double-word field in the target command to obtain an SGL base address, an SGL length, an SGL type, and an SGL position, and determine the SGL type, the SGL base address, the SGL length, and the SGL position as the scatter-gather table address information.

4. The host memory access method according to claim 3, wherein The obtaining the scatter-gather table data structure by using the scatter-gather table address information includes: Determine an object to be accessed by using the SGL position; Based on the SGL type, read the object to be accessed by using the SGL base address and the SGL length to obtain initial data; If the SGL type is in a linked list state, parse the initial data to obtain new scatter-gather table address information; If the SGL type is in a data block state, determine the initial data as the scatter-gather table data structure.

5. The host memory access method according to claim 1, wherein The obtaining the access location information by using the scatter-gather table data structure includes: Parse and obtain a lower host base address, a higher host base address, and an access length from the scatter-gather table data structure; Concatenate the lower host base address and the higher host base address to obtain a host base address, and determine the host base address and the access length as the access location information.

6. The host memory access method according to claim 1, wherein, The accessing the host memory in the host by using the access location information includes: Initiate an access request to the host; If a response from the host is detected, access the host memory according to the target access location information corresponding to the target scatter-gather table data structure; If an access flag meets a completion condition, determine that the access is complete; If the access flag does not meet the completion condition, update the target scatter-gather table address information, and update the access flag according to the update situation.

7. A host memory access device, characterized in that, A DMA controller applied to a solid-state drive, comprising: A parsing module, configured to obtain and parse a target command to obtain a command type identifier; A first acquisition module, configured to, if the command type identifier is the first state, acquire a scatter-gather table data structure by using the target command; wherein the target command in the first state is a command under a non-NVMe protocol generated by a CPU of a solid-state drive imitating an NVMe controller. A second acquisition module, configured to obtain access location information by using the scatter-gather table data structure. An access module, configured to access a host memory in the host by using the access location information. The parsing module is specifically configured to: obtain an initial command from a command queue, parse the initial command to obtain a command ID field; perform a legality check on the initial command by using the command ID field; if the legality check is passed, determine the initial command as the target command, and parse the initial command to obtain the command type identifier.

8. An electronic device, characterized in that, Comprising a memory and a processor, wherein: The memory is configured to store a computer program. The processor is configured to execute the computer program to implement the host memory access method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, For storing a computer program, wherein the computer program, when executed by a processor, implements the host memory access method according to any one of claims 1 to 6.

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