A register verification method, device, equipment and storage medium
By introducing excitation generation unit, verification unit and monitoring unit into the register verification method, multi-threaded test excitation is generated and verified, the problem of multi-threaded stimulation processing in the prior art is solved, and verification efficiency and speed are improved.
Patent Information
- Application Number
- CN202010923821.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-09-04
- Publication Date
- 2025-05-02
- Estimated Expiration
- 2040-09-04
AI Technical Summary
The prior art is difficult to effectively deal with complex multi-threaded excitations, resulting in slow convergence of parallel access verification of registers and long verification cycles.
By introducing excitation generation unit, verification unit and monitoring unit into the register verification method, multi-threaded test excitation is generated and verified, and repeated conflict excitations are filtered out, thereby optimizing the verification process.
It improves the convergence speed of register verification, shortens the verification cycle, and saves verification costs.
Smart Images
Figure CN114139476B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to register verification technology, and in particular to a register verification method, device, equipment and storage medium. Background Art
[0002] In the existing register verification technology, the verification of single-threaded registers has been automated. For the verification of multi-threaded registers, the existing technology cannot handle complex multi-threaded stimuli well to realize parallel access verification of registers. In addition, during the verification process, stimuli are automatically generated, and erroneous or repeated stimuli cannot be automatically screened out, which will slow down the verification convergence speed and the verification cycle is long. Summary of the invention
[0003] In order to solve the above technical problems, the embodiments of the present application hope to provide a register verification method, device, equipment and storage medium.
[0004] The technical solution of this application is implemented as follows:
[0005] In a first aspect, a register verification method is provided, the method comprising:
[0006] Controlling the stimulus generation unit to generate a test stimulus for verifying the target register;
[0007] Detecting that the test stimulus is a multi-threaded stimulus, setting first register information in a register model of the target register based on the multi-threaded stimulus, inputting the multi-threaded stimulus to the target register in parallel, and outputting second register information;
[0008] Verify the target register based on the first register information and the second register information to obtain a verification result;
[0009] The verification result is fed back to the stimulus generation unit, so that the stimulus generation unit filters out repeated conflicting stimuli when generating new multi-threaded test stimuli.
[0010] In a second aspect, a register verification device is provided, the device comprising:
[0011] A stimulus generating unit, used for generating a test stimulus for verifying a target register;
[0012] A verification unit, configured to detect that the test stimulus is a multi-threaded stimulus, set first register information in a register model of the target register based on the multi-threaded stimulus, input the multi-threaded stimulus to the target register in parallel, and output second register information;
[0013] a monitoring unit, configured to verify the target register based on the first register information and the second register information to obtain a verification result;
[0014] The monitoring unit is further configured to feed back the verification result to the incentive generating unit;
[0015] The stimulus generating unit is further configured to filter out repeated conflicting stimuli when generating new multi-threaded test stimuli based on the verification result.
[0016] In a third aspect, an embodiment of the present application provides a register verification device, comprising: a processor and a memory configured to store a computer program that can be run on the processor,
[0017] Wherein, the processor is configured to execute the steps of the aforementioned method when running the computer program.
[0018] In a fourth aspect, an embodiment of the present application further provides a computer storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the aforementioned method are implemented.
[0019] The embodiment of the present application provides a register verification method, device, equipment and storage medium, the method comprising: controlling a stimulus generation unit to generate a test stimulus for verifying a target register; detecting that the test stimulus is a multi-threaded stimulus, setting a first register information in a register model of the target register based on the multi-threaded stimulus, and inputting the multi-threaded stimulus into the target register in parallel, and outputting a second register information; verifying the target register based on the first register information and the second register information to obtain a verification result; feeding back the verification result to the stimulus generation unit, so that the stimulus generation unit filters out repeated conflicting stimuli when generating a new multi-threaded test stimulus. In this way, in the process of verifying multi-threaded access to registers, by feeding back the verification result of the register to the stimulus generation unit, conflicting stimuli can be filtered out in the subsequent stimulus generation process, thereby avoiding the problem of reduced verification convergence speed due to the use of conflicting stimuli, shortening the verification cycle of the register, and saving verification costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 This is a schematic diagram of a first flow chart of a register verification method in an embodiment of the present application;
[0021] Figure 2 This is a schematic diagram of the first component structure of the verification platform in the embodiment of the present application;
[0022] Figure 3 This is a schematic diagram of a dual-thread access conflict in an embodiment of the present application;
[0023] Figure 4 This is a second flow chart of the register verification method in an embodiment of the present application;
[0024] Figure 5 This is a schematic diagram of a third flow chart of the register verification method in an embodiment of the present application;
[0025] Figure 6 This is a schematic diagram of the second component structure of the verification platform in the embodiment of the present application;
[0026] Figure 7 This is a schematic diagram of the composition structure of the register verification device in the embodiment of the present application;
[0027] Figure 8 Schematic diagram of the composition structure of the register verification device in the embodiment of the present application. DETAILED DESCRIPTION
[0028] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.
[0029] The present application embodiment provides a register verification method, such as Figure 1 As shown, the method may specifically include:
[0030] Step 101: controlling a stimulus generation unit to generate a test stimulus for verifying a target register;
[0031] In practical applications, the stimulus generation unit can randomly generate test stimuli to test the read and write functions and task processing performance of the target register.
[0032] In some embodiments, based on preset stimulus constraints, a stimulus generation unit is controlled to generate a test stimulus for verifying a target register; wherein the stimulus constraints are set according to verification requirements of the target register.
[0033] Here, the verification requirement of the register is related to the register implementation function. For example, if the register needs to implement the function of write first and read later, the verification requirement may include verifying whether the register can implement write first and read later for multi-threaded stimulation. Correspondingly, the stimulation constraint condition includes generating multi-threaded stimulation of write first and read later. By setting the stimulation constraint condition, the test stimulation range can be narrowed compared to the random generation method without any constraints, many useless stimulations can be filtered out, the verification convergence speed can be accelerated, and the verification cycle can be shortened.
[0034] Furthermore, the stimulus generation unit can generate both single-threaded and multi-threaded stimuli. Since single-threaded stimuli do not have conflicts when accessing registers, they can only be used to test whether the register read and write functions are correct. Multi-threaded stimuli may have conflicts, so they can be used to test whether the register read and write functions are correct and further test the register task processing performance.
[0035] Step 102: Detecting that the test stimulus is a multi-threaded stimulus, setting first register information in a register model of the target register based on the multi-threaded stimulus, inputting the multi-threaded stimulus to the target register in parallel, and outputting second register information;
[0036] In practical applications, the method also includes building a register model for the target register, and using the register model to verify multi-threaded access to the register. Here, the register model is a set of high-level abstract classes used to model registers and memories with address mapping in the design under test (DUT) (i.e., the target register). It reflects the various characteristics of the registers in the DUT very closely, can generate incentives to act on the DUT and perform register function checks. The register model constructed by the Universal Verification Methodology (UVM) can simply and efficiently implement front-door or back-door operations on the registers of the DUT. It also provides some sequences (i.e., stimulus sounding units) for register testing, which is convenient for users to use directly.
[0037] In the prior art, processors process many instructions in parallel each time, and conventional register read and write instruction verification can no longer meet the needs of large-scale processor register verification. In the embodiment of the present application, based on the register model and the method for parallel access to registers, multi-threaded access to registers can be automatically verified.
[0038] In some embodiments, the multi-threaded stimulus is input into the target register in parallel and the second register information is output, including: determining the driver corresponding to each thread based on the thread identifier of each thread in the multi-threaded stimulus; sending each thread to its corresponding driver respectively; controlling multiple drivers to drive the multi-threaded stimulus to multiple interfaces of the target register at the same time to realize multi-threaded access to the target register; and using multiple monitors to monitor the multiple interfaces respectively to obtain the second register information.
[0039] That is to say, multiple parallel drivers are set in the register verification platform, one driver is used to process one thread task, and the stimulus generation unit can send each thread to the corresponding driver according to the corresponding relationship between the thread and the driver. For the shared register that can process multi-threaded tasks, it includes multiple interfaces, one driver is connected to one interface to realize parallel access of multiple threads, and one monitor is connected to one interface to monitor the access result of each thread.
[0040] Figure 2 Schematic diagram of the first component structure of the verification platform in the embodiment of the present application, such as Figure 2 As shown, the verification platform includes: test cases, verification environment (env) and device under test (DUT).
[0041] The test case includes: coverage monitor, register model and sequence, where sequence is also called stimulus generation unit.
[0042] The verification environment includes: adapter 0 (adapter0), sequencer (sequencer), 4 parallel drivers (D0, D1, D2 and D3), 4 parallel monitors (M0, M1, M2 and M3), predictor (predictor), adapter 1 (adapter1) and reference model of DUT (reference model).
[0043] from Figure 2 It can be seen that the present application can handle complex multi-threaded stimuli by setting multiple parallel drivers and monitors to achieve parallel access verification of DUT.
[0044] Figure 2 The four parallel drivers and four parallel monitors are only for illustrating the multi-threaded parallel access verification process, and are not limited to processing only four threads. The register verification method provided in the embodiment of the present application can verify the parallel access to the register by two or more threads. The multi-threaded access verification method with other numbers is the same as Figure 2 The same is true for this 4-thread access verification method.
[0045] Step 103: verifying the target register based on the first register information and the second register information to obtain a verification result;
[0046] In the embodiment of the present application, the target register is a shared register capable of processing parallel tasks. When multi-threaded stimulation verifies the shared register, it includes performing read-write verification and multi-thread conflict verification on the register. Here, the read-write verification is to verify whether the read or write operation of each thread on the register is correct. Only when the read and write of the register is correct, will it be further verified whether there is a conflict when multiple threads access the register.
[0047] In some embodiments, step 103 may specifically include: performing read and write verification on the target register based on the first register information and the second register information to obtain a first verification result; when the first verification result indicates that the read and write function verification of the target register is successful, performing conflict verification on the multi-threaded stimulus based on the second register information to obtain a second verification result;
[0048] Correspondingly, the feeding back the verification result to the incentive generation unit includes: feeding back the second verification result to the incentive generation unit.
[0049] That is, part of the second register information is used to verify whether the read and write functions of the register are correct, and the other part of the information is used to verify whether the multi-threaded excitation conflicts.
[0050] Specifically, the first register information includes the expected value and mirror value when each thread accesses the target register, and the second register information includes the real value when each thread accesses the target register. The expected value and mirror value in the first register information and the real value of the second register are used to verify whether the read and write functions of the register are correct. The second register information also includes the execution order and execution state when each thread accesses the target register, which is used to verify whether multi-thread access conflicts, wherein the execution state is a read state or a write state.
[0051] by Figure 2Take the example to illustrate the verification process. In actual application, the verification process of DUT specifically includes: sequence generates multi-threaded stimulus, gives the expected value (m_desired) of each thread to the register model, generates the mirror value (m_mirrored) by mapping m_desired in the register model, and sends the multi-threaded stimulus to adapter0. In adapter0, call reg_adapter.reg2bus to convert rw into the transaction corresponding to the bus driver; hand over the transaction to the sequencer, and finally drive it to the corresponding multiple bus interfaces (such as I0, I1, I2 and I3) by multiple parallel bus drivers (such as D0, D1, D2 and D3). Multiple busmonitors (such as M0, M1, M2 and M3) connected to multiple bus interfaces detect the bus transaction and send it to the predictor.
[0052] Predictor will call adapter1.bus2reg to convert the bus transaction into uvm_reg_item. Adapter1 writes the uvm_reg_item of each thread accessing the register to the register model in the form of a queue. The register model updates the real value of the register according to the returned uvm_reg_item. Coveragemonitor monitors the real value of each thread accessing the register, as well as the mirror value (m_mirrored) and the expected value (m_desired) in real time and compares them to verify the correctness of register reading and writing. At the same time, it can also judge in real time whether multi-thread access to shared registers will cause conflicts based on the execution information of each thread on the register, and feedback to the sequence, record the test stimulus that causes conflicts and shut down its operation.
[0053] Figure 3 Schematic diagram of dual-thread access conflict in the embodiment of the present application, as shown in Figure 3As shown, the dual-thread excitation includes: thread 1 (thread identifier is ID0) and thread 2 (thread identifier is ID1); (w, 5) indicates that thread 1 performs a write 5 operation on the target register, and (r) indicates that thread 2 performs a read operation on the target register. In order for the two threads to access correctly, thread 1 must be executed first and then thread 0. However, according to the competition risk mechanism of the target register, the actual access result is that thread 0 is executed first and then thread 1, resulting in the value actually read by thread 2 not being the 6 previously stored in the target register. Therefore, when the dual threads access the register, there is a high probability that an access error will occur, which will affect the convergence speed of the verification. Therefore, this dual-thread excitation is defined as a conflict excitation.
[0054] In actual applications, when the read and write function verification of the target register fails, it is necessary to analyze the read and write problems and modify them, and then use multi-threaded stimulation to re-access the register until the read and write verification is successful, and then further verify whether the multi-threaded stimulation conflicts.
[0055] Step 104: Feedback the verification result to the stimulus generation unit, so that the stimulus generation unit filters out repeated conflicting stimuli when generating new multi-threaded test stimuli.
[0056] In practical applications, the verification result includes at least the identification information of the conflicting stimulus. The stimulus generation unit can determine the conflicting stimulus according to the identification information of the conflicting stimulus and delete the conflicting stimulus. Since running the conflicting stimulus will bring great cost to the later regression test and slow down the convergence verification speed, deleting the conflicting stimulus can shorten the verification cycle of the register and save the verification cost.
[0057] In some embodiments, when the multi-threaded stimulus is a correct stimulus, the verification result may also include flag information of the correct stimulus. Since the verification result of the target register is still successful when the correct stimulus is used again, there is no need to use the correct stimulus to verify the target register to waste verification time. The repeated correct stimulus can be deleted to further shorten the verification cycle.
[0058] Here, the execution subject of step 101 to step 104 can be a processor of a register verification device. The method can build a verification platform based on UVM, which is a verification platform development framework based on the System Verilog class library, and verification engineers can use its reusable components to build a functional verification environment with a standardized hierarchy and interface.
[0059] By adopting the above technical solution, in the process of verifying multi-threaded access to registers, by feeding back the verification results of the registers to the stimulus generation unit, conflicting stimuli can be filtered out in the subsequent stimulus generation process, thereby avoiding the problem of reduced verification convergence speed due to the use of conflicting stimuli, shortening the verification cycle of the registers, and saving verification costs.
[0060] In order to better reflect the purpose of this application, further examples are given based on the above embodiments of this application. Figure 4 As shown, the method specifically includes:
[0061] Step 401: Controlling a stimulus generation unit to generate a multi-threaded stimulus for verifying a target register;
[0062] In practical applications, the stimulus generation unit may randomly generate test stimuli, or generate test stimuli for verifying a target register based on preset stimulus constraints.
[0063] Furthermore, the stimulus generation unit can generate both single-threaded and multi-threaded stimuli. Since single-threaded stimuli do not have conflicts when accessing registers, they can only be used to test whether the register read and write functions are correct. Multi-threaded stimuli may have conflicts, so they can be used to test whether the register read and write functions are correct and further test the register task processing performance.
[0064] Step 402: Setting first register information in a register model of the target register based on the multi-threaded stimulus;
[0065] by Figure 2 For example, sequence generates multi-threaded excitation, and gives the expected value (m_desired) of each thread to the register model. In the register model, the mirror value (m_mirrored) is generated by mapping m_desired. The m_desired and m_mirrored of each thread can be used as the first register information.
[0066] Step 403: determining a driver corresponding to each thread based on the thread identifier of each thread in the multi-threaded excitation;
[0067] In the embodiment of the present application, multiple parallel drivers are set in the register verification platform, one driver is used to process one thread task, and the stimulus generation unit can send each thread to the corresponding driver according to the corresponding relationship between the thread and the driver. For a shared register capable of processing multi-threaded tasks, multiple interfaces are included, one driver is connected to one interface for realizing parallel access of multiple threads, and one monitor is connected to one interface for monitoring the access result of each thread.
[0068] Step 404: Send each thread to its corresponding driver;
[0069] Step 405: controlling a plurality of drivers to simultaneously drive the multi-threaded stimulus to a plurality of interfaces of the target register, so as to implement multi-threaded access to the target register;
[0070] Step 406: using a plurality of monitors to monitor the plurality of interfaces respectively, and obtaining the second register information;
[0071] In some embodiments, the second register information includes the real value, execution order and execution state of each thread when accessing the target register; wherein the execution state is a read state or a write state;
[0072] Correspondingly, this step specifically includes: using the multiple monitors to monitor the multiple interfaces respectively, and obtaining the real value and execution status of each thread when accessing the target register from the multiple interfaces based on the execution order of each thread; based on the execution order when each thread accesses the target register, storing the real value and execution status of each thread in the target queue in sequence; and obtaining the second register information from the target queue.
[0073] Step 407: performing read and write verification on the target register based on the first register information and the second register information to obtain a first verification result;
[0074] Here, the first verification result indicates that the read-write function verification is successful or indicates that the read-write function verification is failed.
[0075] In some embodiments, the first register information includes an expected value and a mirror value when each thread accesses the target register; the second register information includes a real value when each thread accesses the target register;
[0076] Correspondingly, the read and write verification of the target register is performed based on the first register information and the second register information to obtain a first verification result, including: when the expected value, mirror value and real value when all threads in the multi-threaded excitation access the target register are the same, it is determined that the read and write function verification of the target register is successful; when the expected value, mirror value and real value when at least some threads in the multi-threaded excitation access the target register are different, it is determined that the read and write function verification of the target register has failed.
[0077] Exemplarily, when dual-thread incentives access the target register, the dual threads include: thread 1 (ID0) performs a write 5 operation on the target register, and thread 2 (ID1) performs a read operation on the target register. In order to make the two threads access correctly, thread 1 needs to be executed first and then thread 0. Thread 1 is sent to interface 0 (I0) through driver 0 (D0), and thread 2 is sent to interface 1 (I1) through driver 1 (D1). Monitor 0 (M0) monitors I0 to obtain the access result of thread 1, such as monitoring a write 5 operation, and monitor 1 (M1) monitors I1 to obtain the access result of thread 2, such as monitoring a read 6, and M1 monitors M0 first and then M0, then the access result of thread 2 is first stored in the target queue, and then the access result of thread 1 is stored, and the three values corresponding to ID0 are all 5, and the three values corresponding to ID1 are all 6, indicating that the read and write results of each thread are correct, and the register read and write function verification is successful; if there are three values corresponding to at least one thread that are different, it indicates that the register read and write function verification has failed.
[0078] In some embodiments, the method further includes: when the first verification result indicates that the read / write function verification of the target register fails, generating modification prompt information to prompt that the read / write function of the target register is abnormal.
[0079] In actual applications, when the read and write function verification of the target register fails, it is necessary to analyze the read and write problems and modify them, and then use multi-threaded stimulation to re-access the register until the read and write verification is successful, and then further verify whether the multi-threaded stimulation conflicts.
[0080] Step 408: When the first verification result indicates that the read and write function verification of the target register is successful, conflict verification is performed on the multi-threaded stimulus based on the second register information to obtain a second verification result;
[0081] In some embodiments, the second register information further includes an execution order and an execution state when each thread accesses the target register; wherein the execution state is a read state or a write state;
[0082] Correspondingly, the multi-threaded stimulus is conflict verified based on the second register information to obtain a second verification result, including: based on the execution order and execution status when each thread accesses the target register, determining whether the multi-threaded stimulus matches the preset conflict feature; if it matches, determining that the multi-threaded stimulus is a conflict stimulus; if it does not match, determining that the multi-threaded stimulus is a correct stimulus.
[0083] Here, the preset conflict feature is pre-set according to the type of conflict that may exist in the target register. Exemplarily, the conflict feature includes at least one of the following: read after write, write after write, and read after write. For example, for some special registers, read after write and write after write cannot occur, or read after write cannot occur. Therefore, by extracting the conflict features of each conflict type, all conflict features are stored in a conflict list, and when verifying the conflict, the execution order and execution status of each thread when accessing the target register are matched with the conflict features in the conflict list. If there is a matching conflict feature, it indicates that the multi-threaded excitation is a conflict excitation, otherwise it is a non-conflict excitation (also called a correct excitation).
[0084] like Figure 3 As shown, the dual-thread excitation includes: thread 1 (thread identifier is ID0) and thread 2 (thread identifier is ID1); (w, 5) indicates that thread 1 performs a write 5 operation on the target register, and (r) indicates that thread 2 performs a read operation on the target register. In order to make the two threads access correctly, thread 1 needs to be executed first and then thread 0. However, according to the competition risk mechanism of the target register, the actual access result is to execute thread 0 first and then thread 1 (that is, write and read), resulting in the value actually read by thread 2 not being 6 previously stored in the target register, and "write and read" is defined as a conflict excitation in the conflict list. The execution order and execution status in the access result are compared with the conflict list to determine that the conflict feature matches "write and read", and thread 1 and thread 2 are determined to be conflict excitations. The execution of the conflict excitation will affect the convergence speed of the verification. Therefore, in the subsequent verification process, the conflict excitation can be directly deleted according to the excitation identifier and not executed.
[0085] It should be noted that after each multi-threaded stimulus is generated, a stimulus identifier is set to distinguish different incentives. Therefore, the conflicting stimulus information can be fed back to the stimulus generation unit by carrying the stimulus identifier in the verification result.
[0086] Step 409: Feedback the second verification result to the stimulus generation unit, so that the stimulus generation unit filters out repeated conflicting stimuli when generating new multi-threaded test stimuli.
[0087] In some embodiments, when the second verification result indicates that the multi-threaded stimulus is a correct stimulus, the method further includes: feeding back the verification result to the stimulus generation unit so that the stimulus generation unit filters out repeated correct stimuli when generating new multi-threaded test stimuli.
[0088] Since the verification result of reusing the correct stimulus to verify the target register is still successful, there is no need to waste verification time by reusing the correct stimulus to verify the target register. The repeated correct stimulus can be deleted to further shorten the verification cycle.
[0089] By adopting the above technical solution, in the process of verifying multi-threaded access to registers, by feeding back the verification results of the registers to the stimulus generation unit, conflicting stimuli can be filtered out in the subsequent stimulus generation process, thereby avoiding the problem of reduced verification convergence speed due to the use of conflicting stimuli, shortening the verification cycle of the registers, and saving verification costs.
[0090] In order to better reflect the purpose of this application, further examples are given based on the above embodiments of this application. Figure 5 As shown, the method specifically includes:
[0091] Step 501: Start;
[0092] In practical applications, the verification environment should be built and the parameters should be initialized first. Specifically, the verification environment should be built according to the verification schematic diagram, the verification environment should be tested and ensured to pass the verification completely, and the parameters of the environment should be initialized.
[0093] Step 502: Determine whether the test stimulus is empty; if not, execute step 503 or step 507; if yes, execute step 514;
[0094] In actual applications, random stimulus can be automatically generated according to the functional coverage. If the test stimulus is not empty, determine whether the test stimulus accesses an independent register or a shared register. If it is an independent register, execute step 503 to start the verification of the independent register. If it is a shared register, execute step 507 to start the verification of the shared register. If the test stimulus is empty, the verification ends.
[0095] Step 503: Determine that the test stimulus accesses the independent register;
[0096] Step 504: register model read and write verification, if the verification succeeds, return to step 502; if the verification fails, execute step 505;
[0097] Step 505: analysis and modification;
[0098] Step 506: Re-verify. If the verification succeeds, return to step 502; if the verification fails, return to step 505;
[0099] Here, steps 503 to 506 are for verifying the independent registers. Since the independent registers are accessed by a single thread, there is no access conflict, so as long as the read and write verification is successful, it will be sufficient.
[0100] Figure 2 This verification platform can be used to verify both independent registers and shared registers. For independent registers, only one driver and one monitor are needed.
[0101] In use Figure 2 This verification platform verifies independent registers. Figure 2 can be simplified to Figure 6 This structure, Figure 6 Schematic diagram of the second component structure of the verification platform in the embodiment of the present application, such as Figure 6 As shown, the verification platform includes: test cases, verification environment (env) and device under test (DUT).
[0102] The test case includes: coverage monitor, register model and sequence, where sequence is also called stimulus generation unit.
[0103] The verification environment includes: adapter 0, sequencer, driver D0, monitor M0, predictor, adapter 1 and reference model of DUT.
[0104] The three values of the register model are obtained in real time through the coverage monitor, and the three values are checked to see if they are the same. If they are the same, the verification is successful. If the verification fails, the three values are analyzed and modified. This operation is repeated until the verification is successful and the return is made to step 502.
[0105] Step 507: Determine that the test stimulus accesses the shared register;
[0106] Step 508: register model read and write verification, if the verification succeeds, execute step 511; if the verification fails, execute step 509;
[0107] Step 509: analysis and modification;
[0108] Step 510: re-verify. If the verification succeeds, execute step 511; if the verification fails, return to step 509;
[0109] Step 511: extracting multi-thread access results;
[0110] Step 512: Determine whether there is a multi-thread conflict. If yes, execute step 513; if no, return to step 502;
[0111] Step 513: Delete the conflicting stimulus and continue to execute step 502;
[0112] Here, steps 507 to 513 are for verifying the shared registers. Since the shared registers can be accessed by multiple threads, there is a possibility of access conflict. Therefore, in addition to reading and writing verification, it is also necessary to verify whether there is a conflict.
[0113] Here, the test stimulus for accessing shared registers is a complex multi-threaded stimulus. Figure 2 When verifying a shared register, this verification platform first verifies the three values of the register, obtains the three values of the register model in real time through the coverage monitor and verifies them. If the register read and write values are incorrect, analyze and modify them, and repeat this operation until the case passes. If the register verification passes, the coverage monitor extracts the access results of the shared register accessed by multiple threads, and determines whether the access results conflict. If no conflict occurs, return to step 502; otherwise, record and delete the conflict stimulus, and return to step 502.
[0114] Step 514: End.
[0115] By adopting the above technical solution, the technology of multi-threaded access to registers is verified based on the register model, and a multi-threaded register test model can be automatically generated. The register is automatically verified and the conflicting stimulus signal is fed back to the stimulus generation unit to analyze and constrain the conflicting stimulus, which can speed up the verification of the multi-threaded access to register technology, save costs, ensure the quality of digital circuit design products and improve the productivity of digital circuit design products. Repeated correct stimuli can also be analyzed and constrained to speed up the verification convergence speed.
[0116] The present application also provides a register verification device, such as Figure 7 As shown, the device comprises:
[0117] A stimulus generating unit 701, used to generate a test stimulus for verifying a target register;
[0118] A verification unit 702 is used to detect that the test stimulus is a multi-threaded stimulus, set first register information in the register model of the target register based on the multi-threaded stimulus, input the multi-threaded stimulus to the target register in parallel, and output second register information;
[0119] A monitoring unit 703, configured to verify the target register based on the first register information and the second register information to obtain a verification result;
[0120] The monitoring unit 703 is further configured to feed back the verification result to the incentive generating unit;
[0121] The stimulus generating unit 701 is further configured to filter out repeated conflicting stimuli when generating new multi-threaded test stimuli based on the verification result.
[0122] In some embodiments, the verification unit 702 is specifically used to determine the driver corresponding to each thread based on the thread identifier of each thread in the multi-threaded excitation; send each thread to its corresponding driver respectively; control multiple drivers to drive the multi-threaded excitation to multiple interfaces of the target register at the same time to achieve multi-threaded access to the target register; use multiple monitors to monitor the multiple interfaces respectively to obtain the second register information.
[0123] In some embodiments, the second register information includes the real value, execution order and execution state of each thread when accessing the target register; wherein the execution state is a read state or a write state;
[0124] The verification unit 702 is specifically used to use the multiple monitors to monitor the multiple interfaces respectively, and obtain the real value and execution status of each thread when accessing the target register from the multiple interfaces based on the execution order of each thread; based on the execution order when each thread accesses the target register, store the real value and execution status of each thread in the target queue in sequence; and obtain the second register information from the target queue.
[0125] In some embodiments, the monitoring unit 703 is specifically used to perform read and write verification on the target register based on the first register information and the second register information to obtain a first verification result; when the first verification result indicates that the read and write function verification of the target register is successful, the multi-threaded stimulus is conflict verified based on the second register information to obtain a second verification result; and the second verification result is fed back to the stimulus generation unit.
[0126] In some embodiments, the first register information includes an expected value and a mirror value when each thread accesses the target register; the second register information includes a real value when each thread accesses the target register;
[0127] The monitoring unit 703 is specifically used to determine that the read and write function verification of the target register is successful when the expected value, mirror value and real value of all threads in the multi-threaded stimulation when accessing the target register are the same; and to determine that the read and write function verification of the target register has failed when the expected value, mirror value and real value of at least some threads in the multi-threaded stimulation when accessing the target register are different.
[0128] In some embodiments, the second register information further includes an execution order and an execution state when each thread accesses the target register; wherein the execution state is a read state or a write state;
[0129] The monitoring unit 703 is specifically used to determine whether the multi-threaded stimulus matches the preset conflict feature based on the execution order and execution status when each thread accesses the target register; if it matches, determine that the multi-threaded stimulus is a conflict stimulus; if it does not match, determine that the multi-threaded stimulus is a correct stimulus.
[0130] Here, the monitoring unit can be Figure 2 That is to say, the coverage monitor in the embodiment of the present application mainly realizes two functions: first, it collects the three values of value, m_mirrored and m_desired of the register model in real time to verify the correctness of the register read and write function; second, it monitors the access status of the register in real time (register model and register correspond one to one) to determine whether there is a conflict in multi-thread access to the shared register, and feeds back to the test stimulus generation unit.
[0131] In some embodiments, the conflict feature includes at least one of the following: read after write, write after write, and write after read.
[0132] In some embodiments, the monitoring unit 703 is also used to feed back the second verification result to the stimulus generation unit when the second verification result indicates that the multi-threaded stimulus is a correct stimulus, so that the stimulus generation unit filters out repeated correct stimuli when generating a new multi-threaded test stimulus.
[0133] In some embodiments, the monitoring unit 703 is further configured to generate modification prompt information to prompt that the read / write function of the target register is abnormal when the first verification result indicates that the read / write function of the target register has failed to be verified.
[0134] In some embodiments, the stimulus generation unit 701 is further used to control the stimulus generation unit to generate a test stimulus for verifying the target register based on a preset stimulus constraint condition; wherein the stimulus constraint condition is set according to the verification requirement of the target register.
[0135] In some embodiments, the target register is a shared register capable of processing parallel tasks.
[0136] Based on the hardware implementation of each unit in the above register verification device, the embodiment of the present application also provides a register verification device, such as Figure 8 As shown, the device includes: a processor 801 and a memory 802 configured to store a computer program that can be run on the processor;
[0137] The processor 801 is configured to execute the method steps in the aforementioned embodiment when running a computer program.
[0138] Of course, in practical applications, Figure 8As shown, the various components in the device are coupled together via a bus system 803. It is understood that the bus system 803 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 803 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 8 Various buses are labeled as bus system 803.
[0139] In practical applications, the processor may be at least one of an application-specific integrated circuit (ASIC), a digital signal processing device (DSPD), a programmable logic device (PLD), a field-programmable gate array (FPGA), a controller, a microcontroller, and a microprocessor. It is understandable that for different devices, the electronic device used to implement the functions of the processor may also be other, and the embodiments of the present application do not specifically limit this.
[0140] The above-mentioned memory can be a volatile memory (volatile memory), such as a random access memory (RAM); or a non-volatile memory (non-volatile memory), such as a read-only memory (ROM), a flash memory, a hard disk (HDD) or a solid-state drive (SSD); or a combination of the above-mentioned types of memory, and provide instructions and data to the processor.
[0141] In an exemplary embodiment, the embodiment of the present application further provides a computer-readable storage medium, such as a memory including a computer program, and the computer program can be executed by a processor of a register verification device to complete the steps of the aforementioned method.
[0142] The technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.
[0143] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices and equipment can be implemented in other ways. The embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.
[0144] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.
[0145] In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.
[0146] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.
Claims
1. A register verification method, characterized in that: The method comprises: Controlling the stimulus generation unit to generate a test stimulus for verifying the target register; Detecting that the test stimulus is a multi-threaded stimulus, setting first register information in the register model of the target register based on the multi-threaded stimulus, and inputting the multi-threaded stimulus into the target register in parallel, and outputting second register information, wherein the first register information includes an expected value and a mirror value when each thread accesses the target register, and the second register information includes a real value, an execution order, and an execution state when each thread accesses the target register; wherein the execution state is a read state or a write state; Performing read and write verification on the target register based on the first register information and the second register information to obtain a first verification result; When the first verification result indicates that the read and write function verification of the target register is successful, conflict verification is performed on the multi-threaded stimulus based on the second register information to obtain a second verification result; The second verification result is fed back to the stimulus generation unit, so that the stimulus generation unit filters out repeated conflicting stimuli when generating new multi-threaded test stimuli.
2. The method according to claim 1, characterized in that The step of inputting the multi-threaded stimulus to the target register in parallel and outputting the second register information comprises: Determine a driver corresponding to each thread based on the thread identifier of each thread in the multi-threaded stimulus; Send each thread to its corresponding driver; Controlling a plurality of drivers to simultaneously drive the multi-threaded stimulus to a plurality of interfaces of the target register to implement multi-threaded access to the target register; The plurality of interfaces are monitored respectively by a plurality of monitors to obtain the second register information.
3. The method according to claim 2, characterized in that The using a plurality of monitors to monitor the plurality of interfaces respectively to obtain the second register information includes: Using the multiple monitors to monitor the multiple interfaces respectively, and obtaining the real value and execution status of each thread when accessing the target register from the multiple interfaces based on the execution order of each thread; Based on the execution order of each thread when accessing the target register, the real value and execution status of each thread are sequentially stored in the target queue; The second register information is obtained from the target queue.
4. The method according to claim 1, characterized in that: The performing read and write verification on the target register based on the first register information and the second register information to obtain a first verification result includes: When the expected value, the mirror value and the real value when all threads in the multi-threaded stimulation access the target register are the same, it is determined that the read and write function verification of the target register is successful; When the expected value, the mirror value and the real value accessed by at least some threads in the multi-threaded stimulation to the target register are different, it is determined that the read and write function verification of the target register has failed.
5. The method according to claim 4, characterized in that The performing conflict verification on the multi-threaded stimulus based on the second register information to obtain a second verification result includes: Based on the execution order and execution state of each thread when accessing the target register, determining whether the multi-threaded stimulus matches a preset conflict feature; If they match, determining that the multi-threaded incentive is a conflicting incentive; If they do not match, it is determined that the multi-threaded stimulus is a correct stimulus.
6. The method according to claim 5, characterized in that The conflict characteristics include at least one of the following: read after write, write after write, and read after write.
7. The method according to claim 5, characterized in that When the second verification result indicates that the multi-threaded stimulus is a correct stimulus, the method further includes: The second verification result is fed back to the stimulus generation unit, so that the stimulus generation unit filters out repeated correct stimuli when generating new multi-threaded test stimuli.
8. The method according to claim 1, characterized in that The method further comprises: When the first verification result indicates that the read / write function verification of the target register fails, modification prompt information is generated to prompt that the read / write function of the target register is abnormal.
9. The method according to claim 1, characterized in that: The control stimulus generating unit generates a test stimulus for verifying a target register, including: Based on preset stimulus constraints, a stimulus generation unit is controlled to generate a test stimulus for verifying a target register; wherein the stimulus constraints are set according to verification requirements of the target register.
10. The method according to any one of claims 1 to 9, characterized in that: The target register is a shared register that can handle parallel tasks.
11. A register verification device, characterized in that: The device comprises: A stimulus generation unit, used for generating a test stimulus for verifying a target register; A verification unit, configured to detect that the test stimulus is a multi-threaded stimulus, set first register information in a register model of the target register based on the multi-threaded stimulus, input the multi-threaded stimulus to the target register in parallel, and output second register information, wherein the first register information includes an expected value and a mirror value when each thread accesses the target register, and the second register information includes a real value, an execution order, and an execution state when each thread accesses the target register; wherein the execution state is a read state or a write state; A monitoring unit, configured to perform read and write verification on the target register based on the first register information and the second register information to obtain a first verification result; when the first verification result indicates that the read and write function verification of the target register is successful, perform conflict verification on the multi-threaded stimulus based on the second register information to obtain a second verification result; The monitoring unit is further configured to feed back the second verification result to the incentive generating unit; The stimulus generating unit is further configured to filter out repeated conflicting stimuli when generating new multi-threaded test stimuli based on the second verification result.
12. A register verification device, characterized in that: The device comprises: a processor and a memory configured to store a computer program capable of being executed on the processor, Wherein, the processor is configured to execute the steps of the method according to any one of claims 1 to 10 when running the computer program.
13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 10 are implemented.
Citation Information
Patent Citations
Universal verification methodology (UVM) register abstraction layer (RAL) traffic predictor
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