A method for manufacturing a gallium nitride field effect transistor (GAAFET)

Abstract

The embodiment of the application discloses a preparation method of a GAAFET gallium nitride field effect transistor, which comprises the following steps: etching a middle vertical protruding nanowire on the surface of a single crystal substrate, growing an oxide layer on the etched surface on both sides of the nanowire so that the height of the oxide layer is flush with that of the nanowire, and evaporating a metal film, stripping, and annealing to form a gate; growing an oxide layer on the surface of the gate, epitaxially growing a Si epitaxial layer, etching the Si epitaxial layer to the height of the gate oxide layer, growing a long strip-shaped gallium nitride in the direction perpendicular to the nanowire to form a first nanowire, growing an oxide layer, evaporating a metal film, stripping, and annealing; growing an oxide layer, epitaxially growing a Si epitaxial layer, growing a long strip-shaped gallium nitride in the direction perpendicular to the nanowire to form a second nanowire, growing an oxide layer, evaporating a metal film, stripping, and annealing; selectively etching the epitaxially grown Si epitaxial layer, evaporating metal on both ends of the first nanowire and the second nanowire, and forming an ohmic electrode through stripping and annealing.

Description

TECHNICAL FIELD

[0001] The embodiment of the application relates to the field of transistor technology, in particular to a preparation method of a GAAFET gallium nitride field effect transistor. BACKGROUND

[0002] In recent years, wide-bandgap gallium nitride (GaN) has become a famous semiconductor in the application field of power and radio frequency devices due to its superior material performance. A FinFET vertical nanowire complementary metal semiconductor field effect transistor (FinField-Effect Transistor, FinFET for short) with a three-dimensional structure has excellent gate controllability, has attracted high attention and is widely applied.

[0003] The existing FinFET has the following outstanding characteristics: (1) the on and off of the circuit controlled by the gate on both sides are realized; (2) in the FinFET architecture, the gate is designed as a fork-shaped 3D architecture similar to a fish fin, which can greatly improve and reduce the leakage current and also greatly shorten the gate length of the transistor; (3) the FinFET has the advantages of low power consumption and small area. However, the existing FinFET also has obvious defects: due to the narrow channel width, the current density is extremely high, the efficiency is low, and a very high heat is generated, and the GaN channel cannot effectively dissipate heat, so that the internal temperature of the channel is increased, and the device performance is deteriorated. SUMMARY

[0004] To solve the above technical problems, the embodiment of the application provides a preparation method of a GAAFET gallium nitride field effect transistor, which comprises the following steps:

[0005] An intermediate vertical nanowire is etched on the surface of a single crystal substrate, an oxide layer is grown on the etched surface on both sides of the nanowire so that the height of the oxide layer is lower than that of the nanowire, a metal film is evaporated on the surface of the nanowire, and a gate is formed through stripping and annealing;

[0006] An oxide layer is grown on the surface of the gate, a Si epitaxial layer is epitaxially grown on the surface of the oxide layer, the Si epitaxial layer is etched to the height of the gate oxide layer, a long strip-shaped gallium nitride is grown in the direction perpendicular to the nanowire to form a first nanowire, an oxide layer is grown on the first nanowire, and a metal film is evaporated on the surface of the oxide layer and subjected to stripping and annealing;

[0007] An oxide layer is grown on the surface of the first drain, a Si epitaxial layer is epitaxially grown on the surface of the oxide layer, a long strip-shaped gallium nitride is grown in the direction perpendicular to the nanowire to form a second nanowire, an oxide layer is grown on the second nanowire, and a metal film is evaporated on the surface of the oxide layer and subjected to stripping and annealing;

[0008] The Si epitaxial layer is epitaxially grown on the oxide layer on the first drain surface by selective etching, so as to fix the first nanowire and the second nanowire, and metal is evaporated on both ends of the first nanowire and the second nanowire, and an ohmic electrode is formed by peeling and annealing.

[0009] Further, the barrier layer is made by using a photolithography process, and Cl2 / SiCl4 dry etching and TMAH solution wet etching are performed on the surface of the single crystal substrate to form the intermediate vertical protruding nanowire, wherein the width of the nanowire is 10-100 nm.

[0010] Further, the thickness of the Si epitaxial layer is 10-20 nm.

[0011] Further, when the gate or the drain is prepared, the evaporated metal film is Cr, and the thickness is 150-300 nm.

[0012] Further, when the ohmic electrode is prepared, the evaporated metal film is at least one of Ti, Al, Ni or Au, and the thickness is 20-80 nm.

[0013] Further, the single crystal substrate is an N+ type gallium nitride single crystal or a silicon carbide single crystal, and the thickness is 200-500 μm, wherein the N+ type gallium nitride substrate uses silicon as a dopant, and the doping concentration is 5×10 18 cm -3 .

[0014] Further, the oxide layer is aluminum oxide or silicon oxide.

[0015] Further, when the first nanowire and the second nanowire are prepared, the thickness of the grown long strip-shaped gallium nitride is 0.2-0.4 μm.

[0016] Further, the gallium nitride uses magnesium as a dopant, and the doping concentration is 2×10 18 cm -3 -3×10 18 cm -3 .

[0017] Further, it comprises: annealing at 650°C in a nitrogen environment when the electrode is prepared.

[0018] The beneficial effects of the embodiment of the present application are: the present application provides a GAAFET vertical gallium nitride field effect transistor, which adds nanowires on the structure of the existing FinFET, and the advantages are: (1) because the existing vertical GAAFET device is turned on, two MOS tubes are integrated vertically on a substrate, compared with the traditional inverter, the static power consumption is lower, the delay is lower, the device volume is reduced, and the integration degree is improved. (2) Since the upper surface, lower surface and side surface of the nanowire form a channel, a multi-layer channel structure can be formed, further improving the overall carrier mobility of the multi-layer nanowire stack ring gate channel structure and the comprehensive performance of the multi-layer nanowire. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0020] Figure 1 A flowchart of a GAAFET vertical gallium nitride field effect transistor preparation method provided by the embodiment of the present application is shown.

[0021] Figure 2 A perspective view of the GAAFET vertical gallium nitride field effect transistor provided by the embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] In order to make those skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings of the embodiments of the present application.

[0023] The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0024] Please refer to Figure 1 , Figure 1 A flowchart of a GAAFET vertical gallium nitride field effect transistor preparation method provided by the embodiment of the present application is shown.

[0025] In another embodiment of the present application, the preparation method specifically includes the following steps:

[0026] Step one, etching a middle vertical protruding nanowire on the surface of a single crystal substrate, growing an oxide layer on both sides of the nanowire to make the oxide layer lower than the height of the nanowire, and evaporating a metal film on the surface of the nanowire, stripping and annealing to form a gate electrode;

[0027] The single crystal substrate is an N+ type gallium nitride single crystal or a silicon carbide single crystal, with a thickness of 200-500 μm, preferably 300 μm. The N+ type gallium nitride substrate uses silicon as a dopant, with a doping concentration of 5×10 18 cm -3 In the etching process, a photoetching process is used to make a barrier layer, and Cl2 / SiCl4 dry etching and TMAH solution wet etching are performed on the original structure to form a middle vertical protruding nanowire with a width of 10-100 nm, preferably 50 nm.

[0028] An oxide layer, such as Al2O3, is grown on the surface of the device using plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) method. A metal film such as Cr is evaporated on the nanowire using a method such as thermal evaporation, magnetron sputtering or electron beam evaporation, with a thickness of 100-300 nm, preferably 200 nm, to form a gate electrode.

[0029] Step two, growing an oxide layer on the surface of the gate electrode, epitaxially growing a Si epitaxial layer on the surface of the oxide layer, and etching the Si epitaxial layer to the height of the gate oxide layer, growing a long strip-shaped gallium nitride in a direction perpendicular to the nanowire to form a first nanowire, growing an oxide layer on the first nanowire, and evaporating a metal film on the surface of the oxide layer, and stripping and annealing.

[0030] An aluminum oxide (Al2O3) layer is grown on the surface of the device using plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) method, and then a Si (15 nm) epitaxial layer is epitaxially grown on the substrate. The Si layer is grown below 500°C, and after growth, the Si layer is etched to the height of the aluminum oxide layer. A long strip-shaped gallium nitride (GaN) layer is grown using hydride vapor phase epitaxy (HVPE) or molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) method. An aluminum oxide layer is then grown on the surface of the device using plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) method to cover the nanowire. A metal film such as Cr (200 nm) is evaporated using a method such as thermal evaporation, magnetron sputtering or electron beam evaporation. After forming the electrode using a stripping process, annealing is performed at 650°C in a N2 environment to form a first drain electrode.

[0031] Step three, growing an oxide layer on the surface of the first drain electrode, epitaxially growing a Si epitaxial layer on the surface of the oxide layer, growing a long strip of gallium nitride in a direction perpendicular to the nanowire to form a second nanowire, growing an oxide layer on the second nanowire, evaporating a metal film on the surface of the oxide layer, and performing peeling and annealing;

[0032] The specific method of step three is described in step two. The thickness of the first nanowire and the second nanowire is 0.2-0.4 μm. The gallium nitride uses magnesium as a dopant, and the doping concentration is 2×10 18 cm -3 -3×10 18 cm -3 .

[0033] Step four, selectively etching the Si epitaxial layer epitaxially grown on the oxide layer on the surface of the first drain electrode to fix the first nanowire and the second nanowire of the device, and evaporating metal on both ends of the first nanowire and the second nanowire, and performing peeling and annealing to form an ohmic electrode.

[0034] It should be noted that the silicon layer is selectively etched using a tetramethylammonium hydroxide (TMAH) aqueous solution, and after selective etching, a shaping gas annealing (FGA) is performed on the nanowire to remove dislocations. In order to achieve good selective etching between GaN / Si, the solution temperature is selected to be about 60°C, and the aid of ultrasonic stirring is used.

[0035] After the photolithography process, a metal film is evaporated on both ends of the nanowire using methods such as thermal evaporation, magnetron sputtering, or electron beam evaporation, for example, Ti (25 nm), Al (75 nm), Ni (25 nm), or Au (75 nm), and after using a peeling process to form an electrode, annealing is performed at 650°C in a N2 environment.

[0036] Optionally, in the above embodiments, the oxide layer is aluminum oxide or silicon oxide. For example, Figure 2 A GAAFET vertical gallium nitride field effect transistor three-dimensional structure schematic diagram provided by the embodiments of the application is shown in FIG. 1, wherein, as shown in FIG. 1, 1 is a single crystal substrate, 2 is an oxide layer, 3 is a vertically protruding nanowire, 4 is a second nanowire, 5 is a first nanowire, and 6 is an ohmic electrode. Figure 2

[0037] The above only describes some embodiments of the application, and it should be noted that for those skilled in the art, without departing from the principles of the application, a number of improvements and refinements can be made, and these improvements and refinements should also be considered as the protection scope of the application.​

Claims

1. A method of fabricating a GAAFET gallium nitride field effect transistor, comprising: The method comprises the following steps: forming a middle vertical protruding nanowire by etching a surface of a single crystal substrate, growing an oxide layer on both sides of the etched surface of the nanowire to make the height of the oxide layer lower than that of the nanowire, and evaporating a metal film on the surface of the nanowire, and then stripping and annealing to form a gate electrode; growing an oxide layer on the surface of the gate electrode, epitaxially growing a Si epitaxial layer on the surface of the oxide layer, etching the Si epitaxial layer to the height of the gate oxide layer, growing a long strip-shaped gallium nitride in a direction perpendicular to the nanowire to form a first nanowire, growing an oxide layer on the first nanowire, and evaporating a metal film on the surface of the oxide layer, and then stripping and annealing to form a first drain electrode; growing an oxide layer on the surface of the first drain electrode, epitaxially growing a Si epitaxial layer on the surface of the oxide layer, growing a long strip-shaped gallium nitride in a direction perpendicular to the nanowire to form a second nanowire, and growing an oxide layer on the second nanowire, and evaporating a metal film on the surface of the oxide layer, and then stripping and annealing; selectively etching the Si epitaxial layer epitaxially grown on the oxide layer on the surface of the first drain electrode to fix the first nanowire and the second nanowire, and evaporating a metal on both ends of the first nanowire and the second nanowire, and then stripping and annealing to form an ohmic electrode.

2. The production method according to claim 1, characterized by, A blocking layer is prepared by using a photolithography process, and Cl2 / SiCl4 dry etching and TMAH solution wet etching are performed on the surface of a single crystal substrate to form a middle vertical protruding nanowire, wherein the width of the nanowire is 10-100 nm.

3. The preparation method according to claim 1, characterized in that, The thickness of the Si epitaxial layer is 10-20 nm.

4. The method of claim 1, wherein, When the gate electrode or the drain electrode is prepared, the evaporated metal film is Cr, and the thickness is 150-300 nm.

5. The preparation method according to claim 1, characterized in that, When the ohmic electrode is prepared, the evaporated metal film is at least one of Ti, Al, Ni or Au, and the thickness is 20-80 nm.

6. The method of claim 1, wherein, The single crystal substrate is an N+ type gallium nitride single crystal or a silicon carbide single crystal, and the thickness is 200-500 μm, wherein the N+ type gallium nitride substrate uses silicon as a dopant, and the doping concentration is 5×1018 cm-3.

7. The preparation method according to claim 1, characterized in that, The oxide layer is aluminum oxide or silicon oxide.

8. The method of claim 1, wherein, When the first nanowire and the second nanowire are prepared, the thickness of the grown long strip-shaped gallium nitride is 0.2-0.4 μm.

9. The production method according to claim 8, characterized by, The gallium nitride uses magnesium as a dopant, and the doping concentration is 2×1018 cm-3-3×1018 cm-3.

10. The method of claim 1, wherein, When the electrode is prepared, annealing is performed under the condition of 650°C in a nitrogen environment. ​

Images