Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising a substrate, a gate structure located on the substrate, source-drain doped layers located on both sides of the gate structure, and an interlayer dielectric layer located on both sides of the gate structure and covering the source-drain doped layers; forming a mask layer on the gate structure and the interlayer dielectric layer, the mask layer having a first opening, the first opening corresponding to the source-drain doped layers and extending and continuous along the extension direction of the gate structure; forming a sacrificial layer, the sacrificial layer filling part of the first opening; etching the interlayer dielectric layer corresponding to the part of the first opening not filled by the sacrificial layer, to form a first trench exposing the source-drain doped layers. The method improves the electrical performance of the device, simplifies the process, and reduces the cost.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In particular, the feature size is rapidly developing in the direction of micrometers and nanometers, and the pattern line width will also become thinner and thinner, which puts higher requirements on semiconductor processes.

[0003] In the subsequent process of integrated circuits, photolithography is usually used to transfer integrated circuit patterns. However, the thinner the line width of the integrated circuit pattern, the higher the process requirements for photolithography. When the existing photolithography technology cannot meet the corresponding process requirements, a series of problems are likely to occur, resulting in poor performance of devices formed by existing semiconductor processes. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the electrical performance of the device.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising:

[0006] Providing a substrate, the substrate comprising a substrate, a gate structure located on the substrate, source-drain doped layers located on both sides of the gate structure, and an interlayer dielectric layer located on both sides of the gate structure and covering the source-drain doped layers;

[0007] Forming a mask layer on the gate structure and the interlayer dielectric layer, wherein the mask layer is provided with a first opening, the first opening corresponds to the source-drain doping layer and extends and is continuous along an extension direction of the gate structure;

[0008] forming a sacrificial layer, wherein the sacrificial layer fills a portion of the first opening;

[0009] The interlayer dielectric layer corresponding to the portion of the first opening not filled by the sacrificial layer is etched to form a first trench exposing the source / drain doped layer.

[0010] Accordingly, an embodiment of the present invention further provides a semiconductor structure, including:

[0011] A substrate, the substrate comprising a substrate, a gate structure located on the substrate, source-drain doped layers located on both sides of the gate structure, and an interlayer dielectric layer located on both sides of the gate structure and covering the source-drain doped layers;

[0012] A mask layer, covering the gate structure and the interlayer dielectric layer, the mask layer is provided with a first opening, the first opening corresponds to the source-drain doping layer and extends and is continuous along an extension direction of the gate structure;

[0013] a sacrificial layer, wherein the sacrificial layer partially fills the first opening;

[0014] A first trench penetrates the interlayer dielectric layer, wherein the first trench exposes the source-drain doped layer.

[0015] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0016] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a mask layer with a first opening is first formed on the gate structure and the interlayer dielectric layer, so that the first opening corresponds to the source-drain doped layer and extends and is continuous along the extension direction of the gate structure, and then a sacrificial layer is formed so that the sacrificial layer partially fills the first opening; then, the interlayer dielectric layer corresponding to the portion of the first opening not filled by the sacrificial layer is etched to form a first trench exposing the source-drain doped layer. It can be seen that because the first opening extending and continuous along the extension direction of the gate structure is first formed, and then the portion of the first opening above the source-drain doped layer that does not need to be exposed is filled, the continuity of the photolithography pattern of the first opening can ensure that the first opening is in the photolithography process. The dimension stability perpendicular to the extension direction of the gate structure is that since the dimension of the first opening in the extension direction perpendicular to the gate structure is used to define the dimension of the first groove in the extension direction perpendicular to the gate structure, when the interlayer dielectric layer exposed by the first opening is subsequently etched to form the first groove, the dimension stability of the formed first groove can be ensured, which is beneficial to improving the electrical performance of the semiconductor structure; on the other hand, since the sacrificial layer fills part of the first opening, the sacrificial layer acts as a shielding layer when etching the first groove, thereby preventing the interlayer dielectric layer located below the sacrificial layer from being etched away, thereby ensuring that the formed first groove can meet the morphology requirements. Therefore, there is no need to prepare an etching mask for forming the first groove to form the first groove, and the first groove exposing the source and drain doping layer can be formed, thereby simplifying the process and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figures 1 to 9 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0018] Figures 10 to 19 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0019] The devices currently formed still have the problem of poor performance. The reasons for the poor performance of the devices are now analyzed in combination with a method for forming a semiconductor structure.

[0020] Figures 1 to 9 , is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0021] like Figure 1 As shown, a substrate is provided, the substrate comprising a substrate 100, a gate structure 101 located on the substrate 100, a source-drain doped layer 102 located on both sides of the gate structure 101, and an interlayer dielectric layer 103 located on both sides of the gate structure 101 and covering the source-drain doped layer 102; a dielectric layer 106, a mask layer 107, a dielectric layer 108, and a pattern definition layer 109 are sequentially formed on the gate structure 101 and the interlayer dielectric layer 103. A first anti-reflection material layer (not shown) is formed on the pattern definition layer 109; a first photoresist layer 111 is formed on the first anti-reflection material layer; the first anti-reflection material layer is etched using the first photoresist layer 111 as a mask to form a first anti-reflection coating layer 110.

[0022] Among them, Figure 2 As shown, before the step of etching the pattern definition layer 109, in order to ensure etching accuracy, the pattern definition layer exposed by the first photoresist is firstly ion implanted ( Figure 2 , for example, boron ions.

[0023] like Figure 3 As shown, after the ion implantation is completed, the graphic definition layer 109 is etched using the first anti-reflective coating 110 and the first photoresist layer 111 as masks, and the remaining unetched first photoresist layer, the first anti-reflective coating and the graphic material layer that has not been ion implanted are removed by a wet etching process to obtain a graphic layer 112.

[0024] Then, if Figure 4 As shown, a second anti-reflection material layer (not shown) is formed on the dielectric layer 108; a second photoresist layer 114 is formed on the second anti-reflection material layer; and the second anti-reflection material layer is etched using the second photoresist layer 114 as a mask to form a second anti-reflection coating layer 113.

[0025] like Figure 5 As shown, the dielectric layer 108 is etched using the second anti-reflective coating 113 and the second photoresist layer 114 as masks to obtain a patterned dielectric layer 108 .

[0026] Combination Figure 5 refer to Figure 6 and Figure 7 Using the dielectric layer 108 as a mask, the mask layer 107, the dielectric layer 106 and the interlayer dielectric layer 103 are etched respectively to obtain a first trench 115 exposing the source and drain doping layers.

[0027] like Figure 8 As shown, after the first trench 115 is obtained, the remaining mask layer 107 is removed.

[0028] It is easy to understand that the device is divided into an active area and a passive area, and only the active area needs to be electrically connected to the source and drain doping layers. Therefore, the first trench is discontinuous along the extension direction of the gate and presents scattered strips of varying lengths. Fig. 9 As shown, Fig. 9 Schematic diagram of a semiconductor structure from a top view. The thick dashed line frame A area represents the first trench, and the thick solid line frame C area represents Figure 3 The graphic layer 112 in FIG. 1 , the rectangular frame B represents the gate structure.

[0029] In the process of etching to form the first trench 115, due to the presence of the pattern layer 112, the mask layer 107, the dielectric layer 106 and the interlayer dielectric layer 103 below the pattern layer 112 will not be etched away, thereby ensuring that the first trench finally formed is discontinuous along the extension direction of the gate structure and is in a dispersed strip shape ( Fig. 9 A).

[0030] Therefore, the formation process of the graphic layer 112 requires photolithography and etching processes. In addition, the process requirements have a minimum limit on the size of the graphic. When the size of the graphic is smaller than the exposure limit requirement and the distance between each graphic is close, a single exposure process easily causes multiple graphic layers to overlap and connect as one. Therefore, it is impossible to use a single mask to achieve graphic transfer. Because the size of the graphic layer is small, in order to avoid overlapping and connecting multiple graphic layers, multiple masks are required to meet the size and morphology of the graphic layer, and it is not possible to simply use a single exposure to achieve the simultaneous formation of multiple graphic layers 112.

[0031] Since the formation of the graphic layer requires multiple photolithography and etching processes, alignment deviations are inevitable in the alignment process (overlay) between layers. When the first groove is formed by etching downward with the graphic layer as a shielding layer, the photolithography and etching processes need to be used again to form the first groove that exposes the source and drain doping layer. In this way, after multiple photolithography processes, the alignment deviation may exceed the allowable deviation range after accumulation, and finally lead to poor dimensional stability of the formed first groove. For example, if the graphic layer does not match the target graphic, along the extension direction of the fin, if the minimum feature size (i.e., critical dimension (CD)) of the graphic layer is too large, it is easy to cause the first groove to expose the source and drain doping layer and the gate structure at the same time, and the subsequently formed device will cause the source, drain and gate to short-circuit; similarly, along the extension direction of the gate structure, if the size of the graphic layer is offset, the size of the first groove in some areas along the extension direction of the gate structure will be too large, so that the contact resistance of the subsequently formed device will increase.

[0032] Furthermore, the process of preparing the graphic layer using multiple photomasks is cumbersome and increases costs.

[0033] Furthermore, in the process of preparing the semiconductor structure by the above method, if Figure 2 and Figure 3 As shown, after the ion implantation is completed, the graphic definition layer 109 is etched with the first anti-reflective coating 110 and the first photoresist layer 111 as masks, and the remaining first photoresist layer that has not been etched, the first anti-reflective coating and the graphic material layer that has not been ion implanted are removed by a wet etching process. Since the graphic layer 112 is relatively small in size, when wet etching is used to remove the above-mentioned film structure, there is a risk that the graphic layer 112 will be washed away by the etching solution, resulting in the subsequent process of etching downward with the graphic layer as a mask to form the first groove. Due to the loss of the graphic layer, there is no graphic layer covering the underlying film structure at the position where the graphic layer should have existed, resulting in the film structure that should not have been etched being finally etched away, forming a first groove that extends continuously along the direction of the gate structure, that is, the graphic layer 112 cannot play the role of cutting off the first groove.

[0034] It can be seen that when the above method is used to form the first trench exposing the source and drain doping layers, not only is the process complicated, but also the dimensional stability of the first trench cannot be guaranteed, which ultimately leads to poor performance of the formed semiconductor structure.

[0035] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a substrate, a gate structure located on the substrate, source-drain doped layers located on both sides of the gate structure, and an interlayer dielectric layer located on both sides of the gate structure and covering the source-drain doped layers; forming a mask layer on the gate structure and the interlayer dielectric layer, the mask layer having a first opening, the first opening corresponding to the source-drain doped layers and extending and continuous along the extension direction of the gate structure; forming a sacrificial layer, the sacrificial layer filling part of the first opening; etching the interlayer dielectric layer corresponding to the part of the first opening not filled by the sacrificial layer, to form a first trench exposing the source-drain doped layers.

[0036] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a first opening extending and continuous along the extension direction of the gate structure is first formed, and then a portion of the first opening that does not need to expose the source and drain doping layer is filled. Due to the continuity of the photolithography pattern of the first opening, the dimensional stability of the first opening in the extension direction perpendicular to the gate structure can be guaranteed during the photolithography process. Since the size of the first opening in the extension direction perpendicular to the gate structure is used to define the size of the first trench in the extension direction perpendicular to the gate structure, when the interlayer dielectric layer exposed by the first opening is subsequently etched to form the first trench, the dimensional stability of the formed first trench can be guaranteed, which is beneficial to improving the electrical performance of the semiconductor structure. On the other hand, since the sacrificial layer fills part of the first opening, the sacrificial layer acts as a shielding layer when etching the first trench to prevent the interlayer dielectric layer located below the sacrificial layer from being etched away, thereby ensuring that the formed first trench can meet the morphology requirements. Therefore, it is not necessary to prepare an etching mask for forming the first trench to form the first trench, thereby forming the first trench exposing the source and drain doping layer, thereby simplifying the process and reducing costs.

[0037] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figures 10 to 18 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0039] like Fig.10 As shown, a substrate is provided, which includes a substrate 200, a gate structure 201 located on the substrate 200, a source-drain doped layer 202 located on both sides of the gate structure 201, and an interlayer dielectric layer 203 located on both sides of the gate structure 201 and covering the source-drain doped layer 202.

[0040] The substrate provides a process platform for subsequent semiconductor formation.

[0041] The semiconductor structure formed in this embodiment can be a fin field effect transistor (FinFET) as an example. Accordingly, the base includes a substrate 200 and a fin 204 located on the substrate 200. In other embodiments, the semiconductor structure can also be a planar transistor (MOSFET).

[0042] In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon on insulator substrate or a germanium on insulator substrate.

[0043] When the subsequently formed semiconductor structure is in operation, the fin portion 204 at the bottom of the gate structure 201 is used as a channel region.

[0044] In this embodiment, the material of the fin 204 is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0045] The gate structure 201 spans across the fin 204 and covers a portion of a top wall and a portion of a side wall of the fin 204 .

[0046] The gate structure 201 is used to open or close the channel when the semiconductor structure is working.

[0047] Specifically, the material of the gate structure 201 includes metal.

[0048] In this embodiment, the gate structure 201 includes a work function layer (not shown in the figure) and a metal gate layer (not shown in the figure) located on the work function layer.

[0049] When the semiconductor structure is operating, the work function layer is used to adjust the threshold voltage of the transistor.

[0050] In this embodiment, the material of the metal gate layer includes magnesium-tungsten alloy. In other embodiments, the material of the metal gate layer includes one or more of Co, Ru and W.

[0051] When the semiconductor structure is working, the source-drain doped layer 202 is used to provide stress to the channel and improve the migration rate of carriers in the channel.

[0052] In this embodiment, the semiconductor structure is used to form NMOS (Negative channel Metal Oxide Semiconductor), and the source and drain doping layer 202 is silicon carbide or silicon phosphide doped with N-type ions. The N-type ions include one or more of phosphorus ions, arsenic ions and antimony ions.

[0053] In other embodiments, the semiconductor structure can also be used to form a PMOS (Positive Channel Metal Oxide Semiconductor). The source and drain doping layers are silicon germanium doped with P-type ions. The P-type ions include one or more of boron ions, gallium ions, and indium ions.

[0054] The interlayer dielectric layer 203 is used to electrically isolate adjacent devices.

[0055] In this embodiment, the material of the interlayer dielectric layer 203 is an insulating material. Specifically, the material of the interlayer dielectric layer 203 includes silicon oxide. Silicon oxide is a commonly used dielectric material with low cost and has high process compatibility, which is conducive to reducing the process difficulty and process cost of forming the interlayer dielectric layer 203.

[0056] It should be noted that, in the step of providing a substrate, a gate cap layer 205 is formed on the gate structure 201 .

[0057] In the subsequent process of forming the semiconductor structure, the gate cap layer 205 is used to protect the top of the gate structure 201 from being damaged.

[0058] In this embodiment, the gate capping layer 205 is also formed on the interlayer dielectric layer 203. In other embodiments, the gate capping layer may be formed only on the top of the gate structure 201.

[0059] In this embodiment, the material of the gate cap layer 205 includes one or more of silicon nitride, silicon oxynitride, silicon carbonitride and silicon boron nitride carbon.

[0060] Of course, the substrate further includes a dielectric layer 206, and the dielectric layer covers the gate structure 201 and the interlayer dielectric layer 203. In this embodiment, the gate cap layer 205 covers the gate structure 201 and the interlayer dielectric layer 203, so the dielectric layer 206 covers the gate structure 201 and the interlayer dielectric layer 203 by covering the gate cap layer 205, and the dielectric layer 206 is used to electrically isolate the first plug connected to the source-drain doped layer 202 and the second plug connected to the gate structure 201 that are subsequently formed.

[0061] In this embodiment, the material of the dielectric layer 206 is an insulating material. Specifically, the material of the dielectric layer can be one of silicon oxide, silicon nitride or silicon carbide, or a combination of at least two of them. In a specific embodiment, the material of the dielectric layer 206 includes silicon oxide. Silicon oxide is a commonly used dielectric material with low cost and has high process compatibility, which is conducive to reducing the process difficulty and process cost of forming the dielectric layer.

[0062] refer to Figure 11-13 A mask layer 207 is formed on the gate structure 201 and the interlayer dielectric layer 203 . The mask layer 207 has a first opening 210 . The first opening 210 corresponds to the source / drain doping layer 202 and extends and is continuous along the extension direction of the gate structure 201 .

[0063] It should be noted that the first opening 210 corresponds to the source-drain doped layer 202 and extends continuously along the extension direction of the gate structure 201 , which means that along the extension direction of the gate structure, the first opening is a continuous opening as a whole without interruption in the extension direction.

[0064] The mask layer 207 is used as an etching mask for subsequently forming a first trench and is used to define the size of the first trench.

[0065] In this embodiment, the material of the mask layer is titanium nitride. In other embodiments, the material of the mask layer may also be one or a combination of at least two of tantalum nitride, titanium oxide, tantalum oxide, and tungsten-carbon composite materials.

[0066] In this embodiment, a dry etching process is used to form the mask layer 207, and a first opening 210 is formed in the mask layer 207. The dry etching process has anisotropic etching characteristics and good etching profile controllability, which is conducive to making the morphology of the first opening 210 meet the process requirements, and is also conducive to improving the removal efficiency of the mask layer 207 material, and accordingly, the morphology of the first trench formed by the subsequent etching of the dielectric layer 206 exposed by the first opening 210 meets the process requirements.

[0067] Specifically, the steps of forming the mask layer 207 include:

[0068] A mask material layer 207a is formed on the dielectric layer 206 (see Fig.11 ), forming a first anti-reflection material layer on the mask material layer 207a; forming a first photoresist layer 209 (reference Fig.12 ); using the first photoresist layer 209 as a mask to etch the first anti-reflection material layer to form a first anti-reflection coating layer 208; using the first anti-reflection coating layer 208 and the first photoresist layer 209 as a mask, etching the mask material layer 207a to form the mask layer 207 (refer to Fig.13 ).

[0069] like Figure 14-16 As shown, a sacrificial layer 211 is formed, and the sacrificial layer 211 fills a portion of the first opening 210 .

[0070] It should be noted that the sacrificial layer 211 fills part of the first opening 210, which means that the first opening extending continuously is cut off by the sacrificial layer in the extension direction of the first opening, so that the complete first opening is dispersed into several openings of different lengths. Fig. 9 The sacrificial layer 211 is used to shield the dielectric layer 206 area that does not need to be etched, so as to avoid etching the dielectric layer 206 and the interlayer dielectric layer 203 under the sacrificial layer 211 together during the formation of the first groove, thereby ensuring that the formed first groove can meet the morphology requirements.

[0071] In this embodiment, the sacrificial layer 211 includes not only the structure filled into the first opening 210, but also the structure located above the mask layer 207, that is, the sacrificial layer also covers part of the mask layer. Of course, the structure located above the mask layer 207 is provided with a second opening 312 exposing the first opening 210; in other embodiments, the sacrificial layer 211 may only include the structure filled into the first opening 210.

[0072] The material of the sacrificial layer may be one or more of silicon nitride, silicon oxynitride, silicon carbonitride and silicon boron nitride. In this embodiment, the material of the sacrificial layer may be silicon nitride.

[0073] The step of forming a sacrificial layer 211 on the mask layer 207 includes:

[0074] A sacrificial material layer 211a is formed on the mask layer 207 (see Fig.14 ), the sacrificial material layer 211a covers the mask layer 207 and fills the first opening 210, and the top of the sacrificial material layer is a plane;

[0075] The sacrificial material layer 211 a is formed by chemical vapor deposition process.

[0076] Next, the sacrificial material layer 211 a is patterned to form a sacrificial layer 211 , and the sacrificial layer 211 fills a portion of the first opening 210 .

[0077] Specifically, Figure 14-16 As shown, a second anti-reflective material layer is formed on the sacrificial material layer; a second photoresist layer 213 is formed on the second anti-reflective material layer; the second anti-reflective material layer is etched using the second photoresist layer 213 as a mask to form a second anti-reflective coating layer 212; the sacrificial material layer 211a is etched using the second anti-reflective coating layer 212 and the second photoresist layer 213 as masks to form a sacrificial layer 211.

[0078] It should be noted that when the sacrificial layer 211 includes a structure located above the mask layer 207 and is provided with a second opening 312 exposing the first opening 210, the line width of the second opening 312 along the extension direction of the fin is at least equal to the line width of the first opening to ensure that the second opening can completely expose the first opening. Since the line width of the first opening is defined by the pattern of the first photoresist layer, the line width of the second opening is defined by the pattern of the second photoresist layer, that is, the line width of the pattern of the second photoresist layer is at least equal to the line width of the pattern of the first photoresist layer. The line width refers to the dimension along the extension direction of the fin 204.

[0079] By making the second opening 312 completely expose the first opening 210 below, it can be ensured that when the first groove is subsequently formed, the dielectric layer below the first opening exposed is etched using the mask layer as a mask. Due to the continuity of the photolithography pattern of the first opening of the mask layer, the dimensional stability of the first opening in the extension direction perpendicular to the gate structure can be ensured during the photolithography process. Since the size of the first opening in the extension direction perpendicular to the gate structure is used to define the size of the first trench in the extension direction perpendicular to the gate structure, when the interlayer dielectric layer exposed by the first opening is subsequently etched to form the first groove, the dimensional stability of the formed first groove can be ensured, which is beneficial to improving the electrical performance of the semiconductor structure.

[0080] It is easy to understand that since the second opening of the sacrificial layer is formed by dry etching and does not require photolithography, the alignment deviation of the sacrificial layer along the extension direction of the gate structure is much smaller than the alignment deviation of multiple photolithography, and therefore will not affect the size of the unfilled first opening along the extension direction of the gate structure.

[0081] In order to reduce the process precision, in the present embodiment, the line width of the second opening 312 is greater than the line width of the first opening 210. Thus, in the actual processing, even if the second opening has an alignment deviation during the photolithography process, it can ensure that the second opening completely exposes the first opening, thereby increasing the process window and reducing the process precision requirements.

[0082] like Fig.17 As shown, the dielectric layer 206 and the interlayer dielectric layer 203 corresponding to the first opening not filled by the sacrificial layer are etched to form a first trench 313 exposing the source-drain doped layer.

[0083] It should be noted that Fig.17 Three interlayer dielectric layers 203 are shown, Fig.17 The first groove 313 in the cross-section corresponds to only two interlayer dielectric layers 203 , and the second groove (not shown) corresponding to the other interlayer dielectric layer 203 is in other cross-sections.

[0084] Specifically, the mask layer 207 and the sacrificial layer 211 are used as masks, and the dielectric layer 206 and the interlayer dielectric layer 203 are etched by a dry etching process to form a first groove 313 exposing the source-drain doped layer 202. The dry etching process has anisotropic etching characteristics and good etching profile controllability, which is conducive to making the morphology of the first groove 313 meet the process requirements. In the process of forming the first groove 313 by the dry etching process, the top of the source-drain doped layer 202 can be used as the etching stop position to reduce damage to other film structures.

[0085] It should be noted that, in the step of forming the first trench 313 , the gate cap layer 205 is also etched.

[0086] The first trench 313 is used to provide a process space for subsequently forming a metal plug connected to the source and drain doping layers.

[0087] The method for forming a semiconductor structure provided by an embodiment of the present invention first forms a first opening that is continuous and extends along the extension direction of the gate structure, and then fills the part of the first opening that does not need to expose the source and drain doping layer. Due to the continuity of the photolithography pattern of the first opening, the dimensional stability of the first opening in the extension direction perpendicular to the gate structure can be guaranteed during the photolithography process. Since the size of the first opening in the extension direction perpendicular to the gate structure is used to define the size of the first trench in the extension direction perpendicular to the gate structure, when the interlayer dielectric layer exposed by the first opening is subsequently etched to form the first trench, the dimensional stability of the formed first trench can be guaranteed, which is beneficial to improving the electrical performance of the semiconductor structure. On the other hand, since the sacrificial layer fills part of the first opening, when etching the first trench, the sacrificial layer acts as a shielding layer to prevent the interlayer dielectric layer located below the sacrificial layer from being etched away, thereby ensuring that the formed first trench can meet the morphology requirements. Therefore, it is not necessary to make an etching mask for forming the first trench to form the first trench, thereby forming the first trench exposing the source and drain doping layer, thereby simplifying the process and reducing costs.

[0088] like Fig.18 and Fig.19 As shown, after forming the first trench exposing the source-drain doped layer, the method further includes:

[0089] The sacrificial layer and the mask layer are removed.

[0090] In this embodiment, the sacrificial layer and the mask layer are removed by dry etching process. The dry etching process has anisotropic etching characteristics and good etching profile controllability, which is conducive to making the morphology of the first groove 313 meet the process requirements. During the etching process, the top of the dielectric layer 206 can be used as the etching stop position to reduce damage to other film structures. In other embodiments, the sacrificial layer and the mask layer can also be removed by planarization.

[0091] Specifically, the step of removing the sacrificial layer and the mask layer by dry etching process includes:

[0092] like Fig.18 and Fig.19 As shown, a plug protection layer 214 is formed, and the plug protection layer 214 at least fills the first opening, the first trench and the second opening; and the plug protection layer, the sacrificial layer and the mask layer are etched.

[0093] The plug protection layer 214 is used to completely fill the first opening, the first trench and the second opening to prevent the morphology of the first trench from being affected during the subsequent etching process.

[0094] In this embodiment, the plug protection layer 214 also covers the sacrificial layer to reduce the deposition process parameter requirements. Of course, in other embodiments, the plug protection layer can also only fill the first opening, the first groove and the second opening, that is, the top surface of the plug protection layer can be flush with the top surface of the sacrificial layer.

[0095] The plug protection layer may be filled in the first opening, the first trench and the second opening by various appropriate methods.

[0096] The material of the plug protection layer can be selected to have the same etching rate as the sacrificial layer, so as to ensure that the plug protection layer is etched while the sacrificial layer is dry-etched. In this embodiment, the material of the plug protection layer 214 includes spin-on-carbon (SOC). Spin-on-carbon has good filling performance and a simple formation process.

[0097] Accordingly, an embodiment of the present invention further provides a semiconductor structure. Fig.17 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0098] The semiconductor structure comprises:

[0099] A substrate, the substrate comprising a substrate 200, a gate structure 201 located on the substrate, source-drain doped layers 202 located on both sides of the gate structure 201, and an interlayer dielectric layer 203 located on both sides of the gate structure 201 and covering the source-drain doped layers 202;

[0100] A mask layer 207 covering the gate structure 201 and the interlayer dielectric layer 203 , wherein the mask layer 207 is provided with a first opening 210 , wherein the first opening 210 corresponds to the source / drain doping layer 202 and extends and is continuous along an extension direction of the gate structure 201 ;

[0101] A sacrificial layer 211 , wherein the sacrificial layer 211 partially fills the first opening 210 ;

[0102] A first trench 313 penetrates the interlayer dielectric layer, and the first trench 313 exposes the source-drain doped layer 202 .

[0103] The substrate provides a process platform for subsequent semiconductor formation.

[0104] The semiconductor structure formed in this embodiment can be a fin field effect transistor (FinFET) as an example. Accordingly, the base includes a substrate 200 and a fin 204 located on the substrate 200. In other embodiments, the semiconductor structure can also be a planar transistor (MOSFET).

[0105] In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon on insulator substrate or a germanium on insulator substrate.

[0106] When the subsequently formed semiconductor structure is in operation, the fin portion 204 at the bottom of the gate structure 201 is used as a channel region.

[0107] In this embodiment, the material of the fin 204 is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0108] The gate structure 201 spans across the fin 204 and covers a portion of a top wall and a portion of a side wall of the fin 204 .

[0109] The gate structure 201 is used to open or close the channel when the semiconductor structure is working.

[0110] Specifically, the material of the gate structure 201 includes metal.

[0111] In this embodiment, the gate structure 201 includes a work function layer (not shown in the figure) and a metal gate layer (not shown in the figure) located on the work function layer.

[0112] When the semiconductor structure is operating, the work function layer is used to adjust the threshold voltage of the transistor.

[0113] In this embodiment, the material of the metal gate layer includes magnesium-tungsten alloy. In other embodiments, the material of the metal gate layer includes one or more of Co, Ru and W.

[0114] When the semiconductor structure is working, the source-drain doped layer 202 is used to provide stress to the channel and improve the migration rate of carriers in the channel.

[0115] In this embodiment, the semiconductor structure is used to form NMOS (Negative channel Metal Oxide Semiconductor), and the source and drain doping layer 202 is silicon carbide or silicon phosphide doped with N-type ions. The N-type ions include one or more of phosphorus ions, arsenic ions and antimony ions.

[0116] In other embodiments, the semiconductor structure can also be used to form a PMOS (Positive Channel Metal Oxide Semiconductor). The source and drain doping layers are silicon germanium doped with P-type ions. The P-type ions include one or more of boron ions, gallium ions, and indium ions.

[0117] The interlayer dielectric layer 203 is used to electrically isolate adjacent devices.

[0118] In this embodiment, the material of the interlayer dielectric layer 203 is an insulating material. Specifically, the material of the interlayer dielectric layer 203 includes silicon oxide. Silicon oxide is a commonly used dielectric material with low cost and has high process compatibility, which is conducive to reducing the process difficulty and process cost of forming the interlayer dielectric layer 203.

[0119] In this embodiment, the substrate further includes a gate capping layer 205, and the gate capping layer 205 is disposed on the gate structure 201 and the interlayer dielectric layer 203. In other embodiments, the gate capping layer may be disposed only on the top of the gate structure 201.

[0120] In this embodiment, the material of the gate cap layer 205 includes one or more of silicon nitride, silicon oxynitride, silicon carbonitride and silicon boron nitride carbon.

[0121] Of course, the substrate further includes a dielectric layer 206 which covers the gate structure 201 and the interlayer dielectric layer 203. The dielectric layer 206 is used to electrically isolate a first plug connected to the source-drain doped layer 202 and a second plug connected to the gate structure 201 which are subsequently formed in the first trench 313.

[0122] In this embodiment, the material of the dielectric layer 206 is an insulating material. Specifically, the material of the dielectric layer can be one of silicon oxide, silicon nitride or silicon carbide, or a combination of at least two of them. In a specific embodiment, the material of the dielectric layer 206 includes silicon oxide. Silicon oxide is a commonly used dielectric material with low cost and has high process compatibility, which is conducive to reducing the process difficulty and process cost of forming the dielectric layer.

[0123] It should be noted that the first opening 210 corresponds to the source-drain doped layer 202 and extends continuously along the extension direction of the gate structure 201 , which means that along the extension direction of the gate structure, the first opening is a continuous opening as a whole without interruption in the extension direction.

[0124] In this embodiment, the material of the mask layer is titanium nitride. In other embodiments, the material of the mask layer may also be one or a combination of at least two of tantalum nitride, titanium oxide, tantalum oxide, and tungsten-carbon composite materials.

[0125] In this embodiment, the mask layer 207 is formed by a dry etching process.

[0126] It should be noted that the sacrificial layer 211 partially fills the first opening 210, which means that the first opening extending continuously is cut off by the sacrificial layer in the extension direction of the first opening, so that the complete first opening is dispersed into several openings of different lengths. Fig. 9 The dotted box A area in the figure.

[0127] The material of the sacrificial layer may be one or more of silicon nitride, silicon oxynitride, silicon carbonitride and silicon boron nitride. In this embodiment, the material of the sacrificial layer may be silicon nitride.

[0128] In this embodiment, the sacrificial layer 211 includes not only the structure filled into the first opening 210, but also the structure located above the mask layer 207, that is, the sacrificial layer also covers part of the mask layer. Of course, the structure located above the mask layer 207 is provided with a second opening 312 exposing the first opening 210; in other embodiments, the sacrificial layer 211 may only include the structure filled into the first opening 210.

[0129] The material of the sacrificial layer may be one or more of silicon nitride, silicon oxynitride, silicon carbonitride and silicon boron nitride. In this embodiment, the material of the sacrificial layer may be silicon nitride.

[0130] It should be noted that when the sacrificial layer 211 includes a structure located above the mask layer 207 and is provided with a second opening 312 exposing the first opening 210, the line width of the second opening 312 along the extension direction of the fin is at least equal to the line width of the first opening to ensure that the second opening can completely expose the first opening. Since the line width of the first opening is defined by the pattern of the first photoresist layer, the line width of the second opening is defined by the pattern of the second photoresist layer, that is, the line width of the pattern of the second photoresist layer is at least equal to the line width of the pattern of the first photoresist layer. The line width refers to the dimension along the extension direction of the fin 204.

[0131] By making the second opening 312 completely expose the first opening 210 below, it can be ensured that when the first groove is subsequently formed, the dielectric layer below the first opening exposed is etched using the mask layer as a mask. Due to the continuity of the photolithography pattern of the first opening of the mask layer, the dimensional stability of the first opening in the extension direction perpendicular to the gate structure can be ensured during the photolithography process. Since the size of the first opening in the extension direction perpendicular to the gate structure is used to define the size of the first trench in the extension direction perpendicular to the gate structure, when the interlayer dielectric layer exposed by the first opening is subsequently etched to form the first groove, the dimensional stability of the formed first groove can be ensured, which is beneficial to improving the electrical performance of the semiconductor structure.

[0132] It is easy to understand that since the second opening of the sacrificial layer is formed by dry etching and does not require photolithography, the alignment deviation of the sacrificial layer along the extension direction of the gate structure is much smaller than the alignment deviation of multiple photolithography, and therefore will not affect the size of the unfilled first opening along the extension direction of the gate structure.

[0133] In order to reduce the process precision, in the present embodiment, the line width of the second opening 312 is greater than the line width of the first opening 210. Thus, in the actual processing, even if the second opening has an alignment deviation during the photolithography process, it can ensure that the second opening completely exposes the first opening, thereby increasing the process window and reducing the process precision requirements.

[0134] It should be noted that Fig.17 Three interlayer dielectric layers 203 are shown, Fig.17 The first groove 313 in the cross-section only corresponds to two interlayer dielectric layers 203 , and the second groove corresponding to the other interlayer dielectric layer 203 is in the other cross-section.

[0135] The first trench 313 is used to provide a process space for subsequently forming a metal plug connected to the source and drain doping layers.

[0136] The semiconductor structure provided by the embodiment of the present invention first forms a first opening extending and continuous along the extension direction of the gate structure, and then fills the part of the first opening that does not need to expose the source and drain doping layer. Due to the continuity of the photolithography pattern of the first opening, the dimensional stability of the first opening in the extension direction perpendicular to the gate structure can be guaranteed during the photolithography process. Since the size of the first opening in the extension direction perpendicular to the gate structure is used to define the size of the first trench in the extension direction perpendicular to the gate structure, when the interlayer dielectric layer exposed by the first opening is subsequently etched to form the first trench, the dimensional stability of the formed first trench can be guaranteed, which is beneficial to improving the electrical performance of the semiconductor structure. On the other hand, since the sacrificial layer fills part of the first opening, when etching the first trench, the sacrificial layer acts as a shielding layer to prevent the interlayer dielectric layer located below the sacrificial layer from being etched away, thereby ensuring that the formed first trench can meet the morphology requirements. Therefore, it is not necessary to make an etching mask for forming the first trench to form the first trench, thereby forming the first trench exposing the source and drain doping layer, thereby simplifying the process and reducing costs.

[0137] The semiconductor structure described in this embodiment can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0138] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, It is characterized in that include: Providing a substrate, the substrate comprising a substrate, a gate structure located on the substrate, source-drain doped layers located on both sides of the gate structure, and an interlayer dielectric layer located on both sides of the gate structure and covering the source-drain doped layers; Forming a mask layer on the gate structure and the interlayer dielectric layer, wherein the mask layer is provided with a first opening, the first opening corresponds to the source-drain doping layer and extends and is continuous along an extension direction of the gate structure; forming a sacrificial layer, wherein the sacrificial layer fills a portion of the first opening; The interlayer dielectric layer corresponding to the portion of the first opening not filled by the sacrificial layer is etched to form a first trench exposing the source / drain doped layer.

2. The method for forming a semiconductor structure according to claim 1, It is characterized in that The sacrificial layer also covers a portion of the mask layer.

3. The method for forming a semiconductor structure according to claim 2, It is characterized in that The steps of forming the sacrificial layer include: forming a sacrificial material layer on the mask layer, wherein the sacrificial material layer covers the mask layer and fills the first opening, and the top of the sacrificial material layer is a plane; The sacrificial material layer is patterned to form a sacrificial layer, and the sacrificial layer fills a portion of the first opening.

4. The method for forming a semiconductor structure according to claim 1, It is characterized in that The substrate further comprises a dielectric layer, and the mask layer is formed on the dielectric layer; While etching the interlayer dielectric layer, the dielectric layer corresponding to the portion of the first opening not filled by the sacrificial layer is also etched.

5. The method for forming a semiconductor structure according to claim 4, It is characterized in that The dielectric layer and the interlayer dielectric layer are etched using a dry etching process.

6. The method for forming a semiconductor structure according to claim 1, It is characterized in that After forming the first trench exposing the source-drain doped layer, the method further includes: The sacrificial layer and the mask layer are removed.

7. The method for forming a semiconductor structure according to claim 6, It is characterized in that The sacrificial layer and the mask layer are removed by a dry etching process.

8. The method for forming a semiconductor structure according to claim 6, It is characterized in that The step of removing the sacrificial layer and the mask layer is: forming a plug protection layer, wherein the plug protection layer at least fills the first opening and the first trench; The plug protection layer, the sacrificial layer and the mask layer are etched.

9. The method for forming a semiconductor structure according to claim 4, It is characterized in that The material of the dielectric layer is one of silicon oxide, silicon nitride or silicon carbide, or a combination of at least two of them.

10. The method for forming a semiconductor structure according to any one of claims 1 to 9, It is characterized in that The material of the sacrificial layer is one or more of silicon nitride, silicon oxynitride, silicon carbonitride and silicon boron nitride carbon.

11. The method for forming a semiconductor structure according to any one of claims 1 to 9, It is characterized in that The material of the mask layer is one of titanium nitride, tantalum nitride, titanium oxide, tantalum oxide, and a tungsten-carbon composite material, or a combination of at least two of them.

12. The method for forming a semiconductor structure according to claim 3, It is characterized in that The sacrificial material layer is formed by a chemical vapor deposition process.

13. A semiconductor structure, Its characteristics are that include: A substrate, the substrate comprising a substrate, a gate structure located on the substrate, source-drain doped layers located on both sides of the gate structure, and an interlayer dielectric layer located on both sides of the gate structure and covering the source-drain doped layers; A mask layer, covering the gate structure and the interlayer dielectric layer, the mask layer is provided with a first opening, the first opening corresponds to the source-drain doping layer and extends and is continuous along an extension direction of the gate structure; a sacrificial layer, wherein the sacrificial layer partially fills the first opening; A first trench penetrates the interlayer dielectric layer, wherein the first trench exposes the source-drain doped layer.

14. The semiconductor structure according to claim 13, It is characterized in that The sacrificial layer also covers a portion of the mask layer.

15. The semiconductor structure according to claim 13, It is characterized in that Also includes: The dielectric layer is located between the interlayer dielectric layer and the mask layer, and the first trench also penetrates the dielectric layer.

16. The semiconductor structure according to claim 13, It is characterized in that The material of the sacrificial layer is one or more of silicon nitride, silicon oxynitride, silicon carbonitride and silicon boron nitride carbon.

17. The semiconductor structure according to claim 13, It is characterized in that The material of the mask layer is one of titanium nitride, tantalum nitride, titanium oxide, tantalum oxide, and a tungsten-carbon composite material, or a combination of at least two of them.

18. The semiconductor structure according to claim 15, It is characterized in that The material of the dielectric layer is one of silicon oxide, silicon nitride or silicon carbide, or a combination of at least two of them.

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