Silicon Carbide Semiconductor Device and Method of Manufacturing the Same

Abstract

The present application discloses a silicon carbide semiconductor device and a manufacturing method thereof. The epitaxial wafer includes: a semiconductor substrate; a first epitaxial layer disposed on the surface of the semiconductor substrate; a second epitaxial layer disposed on the surface of the first epitaxial layer facing away from the semiconductor substrate; and a third epitaxial layer disposed on the surface of the second epitaxial layer facing away from the first epitaxial layer. A gate is formed through a trench provided on the third epitaxial layer, and moreover, ion implantation can be performed in the second epitaxial layer based on the trench before forming the gate, so as to form a doped region that is inverted with respect to the second epitaxial layer in the second epitaxial layer, solving the problem that it is not easy to form a doped region with a relatively large depth in a silicon carbide semiconductor power device.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and more specifically, to a silicon carbide (SiC) semiconductor device and a manufacturing method thereof. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily lives and work, bringing great convenience to people's daily lives and work and becoming an indispensable important tool for people today.

[0003] The main structure for an electronic device to achieve various functions is an integrated circuit, and semiconductor devices are important component electronic elements of the integrated circuit. Due to its excellent characteristics in high-power application fields, silicon carbide semiconductor devices have become a major development direction in the semiconductor field.

[0004] Due to the characteristics of silicon carbide materials, if doping with a large implantation depth is to be achieved, high-energy ion implantation will cause lattice damage. Therefore, in the existing manufacturing methods, when manufacturing a silicon carbide semiconductor device with a large-depth doped region, during the manufacturing process of the epitaxial wafer, it is necessary to first form the required doped region in the previously formed epitaxial layer through etching and ion implantation, and then form the subsequent epitaxial layer. Summary of the Invention

[0005] In view of this, the present application provides a silicon carbide semiconductor device and a manufacturing method thereof, and the solutions are as follows:

[0006] A manufacturing method of a silicon carbide semiconductor device includes:

[0007] Providing an epitaxial wafer, the epitaxial wafer including: a semiconductor substrate; a first epitaxial layer disposed on the surface of the semiconductor substrate; a second epitaxial layer disposed on the surface of the first epitaxial layer facing away from the semiconductor substrate; a third epitaxial layer disposed on the surface of the second epitaxial layer facing away from the first epitaxial layer;

[0008] Forming a well region, a source region, and a trench in the third epitaxial layer;

[0009] Based on the trench, performing ion implantation in the second epitaxial layer to form a doped region that is inverted with the second epitaxial layer; the doped region penetrates through the second epitaxial layer;

[0010] Forming a gate in the trench.

[0011] Preferably, in the above manufacturing method, the second epitaxial layer has a region to be implanted and a first well region surrounding the region to be implanted;

[0012] Forming a well region, a source region, and a trench in the third epitaxial layer includes:

[0013] By ion implantation, a second well region, a third well region, and a source region are sequentially formed in the third epitaxial layer; the second well region is located between the first well region and the third well region, and the source region is located on a side of the third well region away from the second well region;

[0014] The trench is formed in a surface of the third epitaxial layer away from the second epitaxial layer; a bottom of the trench is located between the second epitaxial layer and the third well region;

[0015] Wherein, both the source region and the third well region are in contact with a sidewall of the trench; the second well region has a spacing from the sidewall of the trench.

[0016] Preferably, in the above manufacturing method, the manufacturing method of the epitaxial wafer includes:

[0017] The first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are sequentially epitaxially formed on a surface of the semiconductor substrate;

[0018] Wherein, the first epitaxial layer and the third epitaxial layer have the same doping type and are inversely doped with the second epitaxial layer.

[0019] Preferably, in the above manufacturing method, it further includes:

[0020] Forming a metal source electrode connected to the source region;

[0021] Forming a metal drain electrode on a surface of the semiconductor substrate away from the first epitaxial layer.

[0022] The present application further provides a silicon carbide semiconductor device prepared by the above manufacturing method, including:

[0023] An epitaxial wafer, the epitaxial wafer includes: a semiconductor substrate; a first epitaxial layer provided on a surface of the semiconductor substrate; a second epitaxial layer provided on a surface of the first epitaxial layer away from the semiconductor substrate; a third epitaxial layer provided on a surface of the second epitaxial layer away from the first epitaxial layer;

[0024] A well region, a source region, and a trench provided in the third epitaxial layer;

[0025] A doping region penetrating the second epitaxial layer, the doping region is inversely doped with the second epitaxial layer and is formed by ion implantation based on the trench;

[0026] A gate provided in the trench.

[0027] Preferably, in the above-mentioned silicon carbide semiconductor device, the second epitaxial layer has an area to be implanted and a first well region surrounding the area to be implanted; the third epitaxial layer has a second well region, a third well region, and the source region; the second well region is located between the first well region and the third well region, and the source region is located on a side of the third well region away from the second well region; both the source region and the third well region are in contact with the sidewall of the trench; there is a gap between the second well region and the sidewall of the trench; the trench is located in the surface of the third epitaxial layer away from the semiconductor substrate; the bottom of the trench is located between the second epitaxial layer and the third well region;

[0028] The thickness of the third epitaxial layer does not exceed 1 μm; the distance between the bottom of the trench and the first epitaxial layer is less than 1 μm.

[0029] Preferably, in the above-mentioned silicon carbide semiconductor device, in the direction from the bottom of the trench to the opening, the width of the trench satisfies a uniform condition.

[0030] Preferably, in the above-mentioned silicon carbide semiconductor device, in the direction from the bottom of the trench to the opening, the width of the trench gradually increases.

[0031] Preferably, in the above-mentioned silicon carbide semiconductor device, the width of the doped region is not greater than the width of the trench.

[0032] Preferably, in the above-mentioned silicon carbide semiconductor device, the doped region, the first epitaxial layer, and the third epitaxial layer have the same doping type;

[0033] The doping concentration of the doped region is greater than the doping concentrations of the first epitaxial layer and the third epitaxial layer.

[0034] As can be seen from the above description, in the silicon carbide semiconductor device and its manufacturing method provided by the technical solution of the present application, the epitaxial wafer includes: a semiconductor substrate; a first epitaxial layer provided on the surface of the semiconductor substrate; a second epitaxial layer provided on the surface of the first epitaxial layer away from the semiconductor substrate; a third epitaxial layer provided on the surface of the second epitaxial layer away from the first epitaxial layer. A gate is formed through the trench provided on the third epitaxial layer, and moreover, based on the trench before the gate is formed, ion implantation can be performed in the second epitaxial layer to form a doped region that is inverted with respect to the second epitaxial layer in the second epitaxial layer, solving the problem that it is difficult to form a doped region with a relatively large depth in a silicon carbide semiconductor power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] To more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on the provided drawings.

[0036] The structures, proportions, sizes, etc. shown in the accompanying drawings of this specification are only used to cooperate with the content disclosed in the specification for those familiar with this technology to understand and read, and are not used to limit the conditions for the implementation of the present application. Therefore, they do not have a substantial technical meaning. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects that the present application can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present application.

[0037] Figure 1 It is a schematic structural diagram of a DMOSFET;

[0038] Figure 2 It is a schematic structural diagram of a UMOSFET;

[0039] Figure 3 It is a waveform diagram of the voltage overshoot and oscillation phenomenon during the MOSFET switching instant;

[0040] Figures 4 - 10 It is a process flow diagram of a method for manufacturing a silicon carbide semiconductor device provided by an embodiment of the present application;

[0041] Figure 11 It is a schematic structural diagram of a silicon carbide semiconductor device provided by an embodiment of the present application;

[0042] Figure 12 For Figure 10 The schematic diagram of the main current path of the silicon carbide semiconductor device shown at the instant of turn-on;

[0043] Figure 13 For Figure 12 The schematic diagram of the equivalent parasitic parameters of the silicon carbide semiconductor device shown;

[0044] Figure 14 It is a layout of a silicon carbide semiconductor device provided by an embodiment of the present application in terms of trench design and ion implantation area of the doping region. Detailed implementation manners

[0045] Next, embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application.

[0046] Due to its excellent properties, SiC material has strong attraction in high power and becomes one of the ideal materials for high-performance power MOSFETs. SiC vertical power MOSFET devices mainly include the lateral double-diffused DMOSFET and the vertical-gate-groove-structured UMOSFET.

[0047] As Figure 1 shown, Figure 1 FIG. is a schematic structural diagram of a DMOSFET, including: a substrate 2 of n+ (heavily doped n-type); an n- (lightly doped n-type) drift region 3 disposed on the surface of the substrate 2; a p-type well region 4 located within the drift region 3; and a source region 5 located within the p-type well region. The source region 5 includes an n+ doped region 51 and a p+ (heavily doped p-type) doped region 52. A gate dielectric layer 7 is disposed on the surface of the drift region 3, and a gate 8 is provided on the surface of the gate dielectric layer 7. The surface of the substrate 2 on the side opposite to the drift region 3 has a drain 1.

[0048] The DMOSFET structure adopts a planar diffusion technology and uses refractory materials such as polysilicon gates as masks, and the edges of the polysilicon gates are used to define the p-base region and the n+ source region. The name DMOS comes from this double-diffusion process. The surface channel region is formed by utilizing the lateral diffusion difference between the p-type base region and the n+ source region.

[0049] As Figure 2 shown, Figure 2 FIG. is a schematic structural diagram of a UMOSFET. Different from the structure shown in Figure 1 FIG., a U-shaped groove is provided in the UMOSFET, and the surface of the U-shaped groove is covered with a gate dielectric layer 7, and the gate 8 is filled in the U-shaped groove. The vertical-gate-groove-structured UMOSFET is named after the U-shaped trench structure. The U-shaped trench structure is formed in the gate region by reactive ion etching. The U-shaped trench structure has a higher channel density (the channel density is defined as the channel width of the active region), which significantly reduces the on-state characteristic resistance of the device.

[0050] After years of research in the industry, some manufacturers have taken the lead in launching commercial products for planar SiC MOSFETs. For ordinary lateral DMOSFET structures, modern technological progress has reached the point where reducing the MOS cell size cannot lower the on-resistance. The main reason is the limitation of the JFET neck region resistance. Even with smaller lithography dimensions, it is difficult to reduce the on-resistance per unit area to 2 mΩ·cm 2 , and the trench structure can effectively solve this problem. The U-shaped trench structure is as shown in Figure 2 . It uses the trench etching technology in the memory storage capacitor manufacturing process, changing the conductive channel from lateral to vertical. Compared with the ordinary structure, it eliminates the JFET neck resistance, greatly increases the cell density, and improves the current handling capacity of power semiconductors.

[0051] However, there are still several problems in the actual process fabrication and application of SiC UMOSFETs:

[0052] 1) The high electric field in the SiC drift region results in a very high electric field on the gate dielectric layer. This problem is exacerbated at the trench corners, causing the gate dielectric layer to break down rapidly under high drain voltages; poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit.

[0053] 2) Since SiC power MOSFETs are mainly applied in high-voltage, high-frequency, and high-current fields, parasitic parameters in the circuit will generate spike glitches during high-frequency switching processes. As shown in Figure 3 , Figure 3 is the waveform diagram of the voltage overshoot and oscillation phenomenon during the MOSFET switching instant. Based on Figure 3 , it can be seen that it causes an instantaneous overvoltage in the device current path, increasing the loss during the switching process at the same time; or a large surge voltage is formed due to changes in power loads, etc. Therefore, the MOSFET's ability to withstand surge voltages and overvoltage protection are also very important.

[0054] Because conventional MOSFET devices themselves do not have the ability to self-suppress surge voltages and overvoltage protection capabilities, complex buffer circuits, surge voltage suppression circuits, and overvoltage protection circuits often need to be designed in actual applications. And this externally matched suppression and overvoltage protection circuit often has a time delay. The high-frequency spike voltage surges during the actual switching process are still borne by the device itself, sometimes resulting in breakdown failures in the device channel region, as well as the gradual failure of the gate structure and the electrode ohmic contact region, causing device reliability problems.

[0055] 3) The depth of ion implantation is limited, making it difficult to implement many targeted trench gate protection structures and anti-surge designs in terms of technology. Generally, the depth of the trench used to form the gate is above 1μm - 2μm. Since the gate structure in the trench needs to be protected, the actual manufacturing process of the buried protection structure cannot be directly completed by ion implantation because in the silicon carbide process, the depth of ion implantation is difficult to exceed 1μm. The prior art generally forms the required doped regions in the epitaxial layer formed first through etching and ion implantation, and then forms two P-type epitaxial layers with specific structures, resulting in a complex manufacturing process and a high manufacturing cost.

[0056] To make the above objects, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0057] As Figures 4 - 10 shown, Figures 4 - 10 is a process flow chart of a method for manufacturing a silicon carbide semiconductor device provided by an embodiment of the present application. The manufacturing method includes:

[0058] Step S11: As Figure 4 shown, provide an epitaxial wafer, and the epitaxial wafer includes: a semiconductor substrate 10; a first epitaxial layer 11 disposed on the surface of the semiconductor substrate 10; a second epitaxial layer 12 disposed on the surface of the first epitaxial layer 11 facing away from the semiconductor substrate 10; and a third epitaxial layer 13 disposed on the surface of the second epitaxial layer 12 facing away from the first epitaxial layer 11.

[0059] Among them, the epitaxial wafer is a silicon carbide epitaxial wafer, and the semiconductor substrate 10 and each epitaxial layer on its surface are all made of silicon carbide material.

[0060] Step S12: As Figures 5 - 8 shown, form a well region, a source region 15, and a trench 20 in the third epitaxial layer 13;

[0061] Step S13: As Figure 9 shown, based on the trench 20, perform ion implantation in the second epitaxial layer 12 to form a doped region 17 that is inverted with the second epitaxial layer 12; the doped region 17 penetrates the second epitaxial layer 12;

[0062] Step S14: As Figure 10 shown, form a gate 18 in the trench 20.

[0063] Among them, Figure 10Only one cell structure of the semiconductor device is shown herein. The semiconductor device may be a silicon carbide MOSFET device. In an actual product, the semiconductor device may have multiple cell structures. The number of cells and the layout manner can be set according to requirements, and the embodiments of the present application do not make specific limitations thereon.

[0064] In the manufacturing method described in the embodiments of the present application, the method for manufacturing the epitaxial wafer includes: epitaxially forming the first epitaxial layer 11, the second epitaxial layer 12, and the third epitaxial layer 13 on the surface of the semiconductor substrate 10 in sequence; wherein, the doping types of the first epitaxial layer 11 and the third epitaxial layer 13 are the same, and are of inverse doping with the second epitaxial layer 12.

[0065] The semiconductor substrate 10 can be set as an n+-type doped silicon carbide substrate, the first epitaxial layer 11 and the third epitaxial layer 13 are both n-type doped silicon carbide epitaxial layers, and the second epitaxial layer 12 is a p-type doped silicon carbide epitaxial layer. In this way, the p-type doped second epitaxial layer 12 is a buried layer. By cleverly using the epitaxial wafer with this buried layer and using the trench 20 required by the gate 8 for ion implantation to form the doped region 17, the shielding of the trench gate structure and the difficulty of the silicon carbide material implantation process are solved. Moreover, the doped region 17 can form a modifiable JFET structure in the device current path, automatically adjusting the device resistance and the self-locking protection effect while also having a smaller device cell size.

[0066] In the semiconductor device, the well region structure includes: a first well region 141, a second well region 142, and a third well region 143. The second epitaxial layer 12 has a region to be implanted and a first well region 141 surrounding the region to be implanted; the region to be implanted is used to form the doped region 17.

[0067] In step S12, forming a well region, a source region 15, and a trench 20 in the third epitaxial layer 13 includes:

[0068] First, as Figures 5 - 7 shown, by ion implantation, a second well region 142, a third well region 143, and a source region 15 are sequentially formed in the third epitaxial layer 13; the second well region 142 is located between the first well region 141 and the third well region 143, and the source region 15 is located on a side of the third well region 143 away from the second well region 142.

[0069] Specifically, as Figure 5As shown, based on the mask layer 01, ion implantation is performed to form a second well region 142 within the third epitaxial layer 13. The second well region 142 surrounds a non-implanted region. The required non-implanted region is formed based on the patterned mask layer 01. The vertical projections of the trench 20 and the doped region 17 are both within this non-implanted region, and in the direction parallel to the epitaxial wafer (i.e., Figures 5 - 8 the horizontal direction), there is a spacing from this non-implanted region. Further, as Figure 6 shown, through ion implantation again, a third well region 143 is formed on the second well region 142. The third well region 143 covers the second well region 142 and the non-implanted region it surrounds. Further, as Figure 7 shown, through ion implantation again, a source region 15 is formed on the third well region 143.

[0070] Then, as Figure 8 shown, the trench 20 is formed within the surface of the third epitaxial layer 13 facing away from the second epitaxial layer 12; the bottom of the trench 20 is located between the second epitaxial layer 12 and the third well region 143.

[0071] Among them, both the source region 15 and the third well region 143 are in contact with the sidewall of the trench 20; when forming the source region 15 through ion implantation, the ion implantation region covers the region for forming the trench 20. Therefore, after the subsequent formation of the trench, the remaining source region 15 can be directly in contact with the sidewall of the trench 20. Similarly, when forming the third well region 143 through ion implantation, the ion implantation region covers the region for forming the trench 20. Therefore, after the subsequent formation of the trench, the remaining third well region 143 can be directly in contact with the sidewall of the trench 20.

[0072] There is a spacing between the second well region 142 and the sidewall of the trench 20. By setting the size of the non-implanted region surrounded by the second well region 142 to be larger than the size of the trench 20, and setting the vertical projection of the trench 20 to be within the non-implanted region and having a spacing from the non-implanted region, it can be ensured that the second well region 142 is not in contact with the sidewall of the trench 20 and there is a spacing between them.

[0073] As Figure 10 shown, the manufacturing method further includes:

[0074] Forming a metal source electrode 21 connected to the source region 15;

[0075] Forming a metal drain 19 on the surface of the semiconductor substrate 10 facing away from the first epitaxial layer 11.

[0076] The source region 15 includes a first region 151 and a second region 152 with opposite doping types, and the source region 15 is in contact with both the first region 151 and the second region 152. The first region 151 can be set as an n+-type doped region, and the second region 152 as a p+-type doped region.

[0077] In the silicon carbide semiconductor device formed by the manufacturing method described in the embodiments of the present application, the well region structure includes three layers, namely a first well region 141, a second well region 142, and a third well region 143. The uppermost third well region 143 is located on the left and right sides of the trench 20 and is in contact with the sidewalls of the trench 20. The middle second well region 142 includes two parts located on the left and right sides of the trench 20 and is not in contact with the sidewalls of the trench 20. The lowermost first well region 141 is located below the trench 20 and has no contact with the trench 20.

[0078] The distances between the left and right parts of the second well region 142 and the vertical central axis of the cell structure are greater than the distances between the left and right parts of the first well region 141 and the vertical central axis of the cell structure. Specifically, the vertical central axis of the cell structure is the central axis of the trench 20, as Figure 10 shown by the dashed line in the figure. Relative to the second well region 142, the first well region 141 is closer to the central axis.

[0079] A specific JFET structure can be formed on the current path between the source and drain through the doping region 17, and the conduction characteristics of the JFET structure can be optimized and adjusted through the graphic design, ion implantation concentration, and graphic profile of the doping region 17 to improve the performance of the semiconductor device.

[0080] The technical solution of the present application cleverly involves the second epitaxial layer 12 and the doping region 17 penetrating the second epitaxial layer 12 in the epitaxial wafer, solving the problems of the shielding of the gate oxide structure of the SiC trench MOSFET and the deep implantation process in the silicon carbide material. At the same time, the doping region 17 can also introduce a JFET structure that can be modulated by ion implantation on the current path of the device. While automatically adjusting the on-resistance and self-locking protection effect of the device, it can also maintain a small device cell size.

[0081] From the above description, it can be seen that the silicon carbide semiconductor device formed based on the manufacturing method described in the embodiments of the present application has at least the following beneficial effects:

[0082] The silicon carbide semiconductor device can introduce a JFET structure on the current path of the cell structure, automatically adjust the on-resistance and self-locking protection effect of the device while maintaining a small device cell size, and the conduction characteristics of the JFET structure are optimized and adjusted by the graphic design, ion implantation concentration, and graphic profile of the doping region 17. The design and process are flexible, and it has good manufacturability.

[0083] Using an epitaxial wafer with a buried layer (the second epitaxial layer 12) and a JFET structure modulated by the implantation of the doping region 17, the depletion regions on both sides can be automatically expanded under a large surge voltage, thereby increasing the on-resistance of the JFET structure, which is equivalent to a buffer circuit structure self-suppressing surge spikes. At the same time, when the surge voltage is too large, the depletion regions on both sides continue to expand and overlap with each other, playing a blocking effect to protect the gate dielectric layer on the inner trench surface, and playing a certain role in overvoltage protection against spike voltage.

[0084] Although introducing the JFET structure will increase a certain on-resistance, it has the effects of switch buffering and self-suppression of surge voltage.

[0085] The silicon carbide semiconductor device can increase the self-suppression resistance of the device to surge voltage and overvoltage, and avoid device damage and reduction of reliability caused by the time delay in the actual operation of the overvoltage protection circuit and the overcurrent protection circuit.

[0086] At the same time, it also plays a buffering role in the spike jitter during the circuit switching process, reducing the switching loss; it can reduce the buffer circuit and the buffer circuit structure in the circuit design, reduce discrete components, thereby reducing costs, and also reducing the actual module volume and enhancing reliability.

[0087] Based on the above embodiments, another embodiment of the present application further provides a silicon carbide semiconductor device. The silicon carbide semiconductor device can be prepared by using the manufacturing method described in the above embodiments, and its structure can be as Figure 10 shown, including:

[0088] An epitaxial wafer, the epitaxial wafer includes: a semiconductor substrate 10; a first epitaxial layer 11 disposed on the surface of the semiconductor substrate 10; a second epitaxial layer 12 disposed on the surface of the first epitaxial layer 11 facing away from the semiconductor substrate 10; a third epitaxial layer 13 disposed on the surface of the second epitaxial layer 12 facing away from the first epitaxial layer 11;

[0089] A well region, a source region 15 and a trench disposed in the third epitaxial layer;

[0090] A doping region 17 penetrating the second epitaxial layer 12, the doping region 17 is of reverse doping with the second epitaxial layer and is formed by ion implantation based on the trench;

[0091] A gate 18 disposed in the trench. The gate 18 includes a filling medium filling the trench and a metal gate located on the surface of the filling medium. The trench surface has a gate dielectric layer. After forming the gate dielectric layer, the gate 18 is formed in the trench. The filling medium can be polysilicon or the like. Before forming the gate dielectric layer in the trench, the doping region 17 is formed.

[0092] Among them, the second epitaxial layer 12 has an area to be implanted and a first well region 141 surrounding the area to be implanted; the third epitaxial layer 13 has a second well region 142, a third well region 142, and the source region 15; the second well region 142 is located between the first well region 141 and the third well region 143, and the source region 15 is located on a side of the third well region 143 away from the second well region 142; both the source region 15 and the third well region 143 are in contact with the sidewall of the trench; the bottom of the trench is located between the second epitaxial layer 12 and the third well region 143; the second well region 142 is located on both sides of the trench and has a spacing from the sidewall of the trench.

[0093] In the silicon carbide semiconductor device, the thickness of the third epitaxial layer 13 does not exceed 1 μm, so that the ion implantation depths of both the second well region 142 and the third well region 143 do not exceed 1 μm, and the second well region 142 and the third well region 143 can be formed in the third epitaxial layer 13 of the silicon carbide material by ion implantation without causing lattice damage.

[0094] In the embodiment of the present application, the distance between the bottom of the trench and the first epitaxial layer 11 is less than 1 μm, so that when forming the doped region 17 by ion implantation based on the trench, the ion implantation depth of the doped region 17 is less than 1 μm, and the doped region 17 can be formed in the second epitaxial layer 12 of the silicon carbide material by ion implantation without causing lattice damage. There is a non-zero spacing between the doped region 17 and the bottom of the trench.

[0095] Optionally, in the direction from the bottom of the trench to the opening ( Figure 10 the direction from bottom to top), the width of the trench satisfies a uniform condition, that is, the width of the trench is the same or approximately the same in this direction, that is to say, the trench is a rectangular trench. Generally, the second epitaxial layer 12 is an epitaxial layer with a uniform thickness. Setting the width of the trench to satisfy the uniform condition facilitates the formation of a doped region 17 with a uniform width in this direction.

[0096] In other ways, the structure of the electronic device can also be as Figure 11 shown, Figure 11 which is a schematic structural diagram of a silicon carbide semiconductor device provided by an embodiment of the present application. The difference between this way and the structure shown in Figure 10 is that in the direction from the bottom of the trench to the opening, the width of the trench gradually increases, that is, the trench is a V-shaped groove or an inverted trapezoidal groove. If it is a V-shaped trench, the doped region 17 is a V-shaped structure. If it is an inverted trapezoidal trench, when the ion implantation window is larger than the bottom of the trench, the doped region is an inverted trapezoidal structure as shown in Figure 11 If the ion implantation window is not larger than the bottom of the trench, the doped region is a rectangular structure.

[0097] In the embodiment of the present application, the width of the doping region 17 is not greater than the width of the trench, so as to be able to form the doping region 17 by ion implantation based on the trench, thereby reducing the depth of ion implantation.

[0098] The doping types of the doping region 17, the first epitaxial layer 11 and the third epitaxial layer 13 are the same.

[0099] The silicon carbide semiconductor device is an NMOS. The semiconductor substrate 10 is an n+-type substrate, the first epitaxial layer 11 and the third epitaxial layer 13 are both n-type doped, the second epitaxial layer 12 is p-type doped, and the doping region 17 is n-type doped. In the embodiment of the present application, the relationship of doping concentrations is n+ > n > n-, p+ > p > p-. n-, n and n+ are of the same doping type, all being the first type of doping. p-, p and p+ are of the same doping type, all being the second type of doping. The first type of doping and the second type of doping are of opposite doping types.

[0100] Obviously, the silicon carbide semiconductor device can also be a PMOS. The doping type can be set according to requirements to form an NMOS or a PMOS.

[0101] The doping concentration of the doping region 17 is greater than the doping concentrations of the first epitaxial layer 11 and the third epitaxial layer 13. The doping region 17 is n+-type doped.

[0102] As Figure 12 shown, Figure 12 is Figure 10 a schematic diagram of the main current path of the silicon carbide semiconductor device at the instant of turn-on. There is a current path between the source and the drain. Figure 12 The middle dotted curve shown represents the circuit path, and the current passes through the JFET structure formed based on the doping region 17. Due to the rapid change of the current, a high-frequency spike voltage is generated in the circuit. At the same time, due to the rapid change of the voltage on the current path, the depletion region ( Figure 12 the region between the left and right dotted curves in Figure 13 ) of the JFET structure corresponds to different voltage change situations and will expand or contract rapidly. At this time, the JFET structure is equivalent to a parallel structure of a variable resistor R and a junction capacitor C, as Figure 13 shown, Figure 12 is a schematic diagram of the equivalent parasitic parameters of the silicon carbide semiconductor device shown.

[0103] Through specific circuit applications and device electrical model simulations, by selecting the appropriate thickness d and doping concentration of the second epitaxial layer 12, as well as optimizing and adjusting the graphic design, concentration, and graphic profile design of the ion implantation structure in the doping region 17, appropriate parasitic parameter values (the required variable resistor R and a junction capacitance C) can be obtained. When actually applied to circuit modules with different switching frequencies, it can effectively suppress voltage spikes and reduce turn-on losses at the same time.

[0104] In the embodiments of the present application, only a single cell structure is used to illustrate the silicon carbide semiconductor device. Obviously, when manufacturing the semiconductor device, multiple cell structures can be fabricated simultaneously based on the wafer-level process, and then the wafer is divided to form the silicon carbide semiconductor device, and the silicon carbide semiconductor device has multiple cell structures.

[0105] As Figure 14 shown, Figure 14 is a layout of a silicon carbide semiconductor device provided by an embodiment of the present application in terms of trench design and ion implantation area of the doping region. The implantation window of the doping region 17 is located within the trench 20. The channel characteristics of the JFET structure can be adjusted by the graphic design, ion implantation concentration, and graphic profile design of the doping region 17. The implantation window area of the doping region 17 can be less than or equal to the area of the trench 20.

[0106] In this specification, the various embodiments are described in a progressive, or parallel, or a combination of progressive and parallel manners. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0107] It should be noted that in the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be intermediate components present at the same time.

[0108] It should also be noted that, in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the article or device comprising the above elements.

[0109] The foregoing description of the disclosed embodiments enables those skilled in the art to practice or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for manufacturing a silicon carbide semiconductor device, characterized in that, Comprising: Providing an epitaxial wafer, the epitaxial wafer comprising: a semiconductor substrate; a first epitaxial layer disposed on the surface of the semiconductor substrate; a second epitaxial layer disposed on the surface of the first epitaxial layer facing away from the semiconductor substrate; a third epitaxial layer disposed on the surface of the second epitaxial layer facing away from the first epitaxial layer, wherein the semiconductor substrate and each epitaxial layer on its surface are made of silicon carbide material, the doping types of the first epitaxial layer and the third epitaxial layer are the same, and are of opposite doping type to the second epitaxial layer; Forming a well region, a source region, and a trench in the third epitaxial layer; Based on the trench, performing ion implantation in the second epitaxial layer to form a doped region that is of opposite type to the second epitaxial layer; the doped region penetrates the second epitaxial layer; Forming a gate in the trench.

2. The manufacturing method according to claim 1, wherein, The second epitaxial layer has a region to be implanted and a first well region surrounding the region to be implanted; Forming a well region, a source region, and a trench in the third epitaxial layer, comprising: By ion implantation, sequentially forming a second well region, a third well region, and a source region in the third epitaxial layer; the second well region is located between the first well region and the third well region, and the source region is located on the side of the third well region facing away from the second well region; Forming the trench in the surface of the third epitaxial layer facing away from the second epitaxial layer; the bottom of the trench is located between the second epitaxial layer and the third well region; Wherein, the source region and the third well region are both in contact with the side wall of the trench; the second well region has a spacing from the side wall of the trench.

3. The manufacturing method according to claim 1, characterized in that, The manufacturing method of the epitaxial wafer comprises: Epitaxially forming the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer in sequence on the surface of the semiconductor substrate.

4. The manufacturing method according to any one of claims 1-3, characterized in that, Further comprising: Forming a metal source electrode connected to the source region; Forming a metal drain electrode on the surface of the semiconductor substrate facing away from the first epitaxial layer.

5. A silicon carbide semiconductor device prepared by the manufacturing method according to any one of claims 1-4, characterized in that, Comprising: An epitaxial wafer, the epitaxial wafer comprising: a semiconductor substrate; a first epitaxial layer disposed on the surface of the semiconductor substrate; a second epitaxial layer disposed on the surface of the first epitaxial layer facing away from the semiconductor substrate; a third epitaxial layer disposed on the surface of the second epitaxial layer facing away from the first epitaxial layer; A well region, a source region, and a trench disposed in the third epitaxial layer; A doped region penetrating the second epitaxial layer, the doped region is of opposite doping type to the second epitaxial layer and is formed by ion implantation based on the trench; A gate disposed in the trench.

6. The silicon carbide semiconductor device according to claim 5, wherein The second epitaxial layer has a region to be implanted and a first well region surrounding the region to be implanted; the third epitaxial layer has a second well region, a third well region, and the source region; the second well region is located between the first well region and the third well region, and the source region is located on the side of the third well region facing away from the second well region; the source region and the third well region are both in contact with the side wall of the trench; the second well region has a spacing from the side wall of the trench; the trench is located in the surface of the third epitaxial layer facing away from the semiconductor substrate; The bottom of the trench is located between the second epitaxial layer and the third well region; The thickness of the third epitaxial layer does not exceed 1 μm; the distance between the bottom of the trench and the first epitaxial layer is less than 1 μm.

7. The silicon carbide semiconductor device according to claim 5, wherein, In the direction from the bottom of the trench towards the opening, the width of the trench satisfies the uniform condition.

8. The silicon carbide semiconductor device according to claim 5, characterized in that, In the direction from the bottom of the trench towards the opening, the width of the trench gradually increases.

9. The silicon carbide semiconductor device according to claim 5, wherein The width of the doped region is not greater than the width of the trench.

10. The silicon carbide semiconductor device according to claim 5, wherein, The doping concentration of the doped region is greater than the doping concentrations of the first epitaxial layer and the third epitaxial layer.

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