Three-dimensional integrated wafer and testing method thereof, three-dimensional integrated chip

Abstract

The application provides a three-dimensional integrated wafer and a testing method thereof, and a three-dimensional integrated chip. The three-dimensional integrated wafer comprises a wafer assembly composed of a plurality of wafer layers, the wafer layers are arranged in a stack and are connected through a connecting structure; the wafer assembly comprises a plurality of chip units, and a detection loop is arranged around each chip unit, the detection loop is configured to detect the connection of the plurality of wafer layers in each chip unit. The structure can effectively monitor the wafer layering problem in the chip, and improves the yield of the chip.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a three-dimensional integrated wafer and its testing method, and a three-dimensional integrated chip. Background Technology

[0002] With the development of semiconductor technology, the cost of reducing process size has become increasingly prohibitive. However, with the successful application of technologies such as TSV (Through Silicon Via), Hybrid Bonding, and silicon wafer thinning, 3D chip stacking technology can effectively enhance the functionality and performance of electronic products while reducing chip size, and is therefore widely used.

[0003] Current 3D chip stacking technologies mostly employ wafer-level bonding, typically using two or more wafers stacked together. Taking hybrid bonding as an example, two wafers are bonded face-to-face to create a metal-to-metal bond, thus achieving the desired functionality. The quality of the bond, and whether delamination occurs on the bonding surfaces of the two wafers, is crucial to this technology. Most current research focuses on improving the tighter bonding between wafers through process technology. However, even the most advanced process technologies cannot completely prevent delamination in some areas of the wafer due to uncontrollable factors during the bonding process. Delamination can lead to wafer breakage in subsequent processes. Furthermore, this defect is a source of other defects, severely impacting wafer manufacturing yield. Therefore, effectively monitoring wafer delamination has become a critical issue. Summary of the Invention

[0004] This invention provides a three-dimensional integrated wafer and its testing method, as well as a three-dimensional integrated chip. The method and structure can effectively monitor wafer delamination issues in the chip, thereby improving the chip yield.

[0005] To solve the above-mentioned technical problems, the first technical solution provided by the present invention is: to provide a three-dimensional integrated wafer, comprising: a wafer assembly composed of multiple wafer layers, wherein the multiple wafer layers are stacked and connected by a connection structure; the wafer assembly includes multiple chip units, and a detection loop is arranged around each chip unit, wherein the detection loop is configured to detect the connection status of the multiple wafer layers in each chip unit.

[0006] The wafer assembly includes multiple dicing channels along a first direction and / or a second direction, which divide the wafer assembly into multiple chip units. A portion of the detection loop of the wafer assembly is disposed on the dicing channels, and the first direction is perpendicular to the second direction.

[0007] The detection loops corresponding to two adjacent chip units are arranged on both sides of the cutting channel, and the detection loops corresponding to any chip unit are independent of each other.

[0008] Each of the detection loops further includes: a first energized pad located on the cutting track, and the signal input terminal of the detection loop is connected to the first energized pad; a second energized pad located on the cutting track, and the signal output terminal of the detection loop is connected to the second energized pad; the first energized pad receives the detection current, and the output signal of the detection loop is detected from the second energized pad.

[0009] Each of the detection loops includes multiple detection sub-loops: the signal input terminal of each detection sub-loop is connected to the first power-on pad; the signal output terminal of each detection sub-loop is connected to the second power-on pad.

[0010] The first energized pad and the second energized pad are the pads for the test circuit in the cut track.

[0011] In the adjacent chip units, the detection loops on both sides of the dicing channel are connected to the same set of test pads, adjacent test pads in the same set of test pads are connected, and the first power-on pad and the second power-on pad are each one of the same set of test pads.

[0012] In the adjacent chip units, the detection loops on both sides of the dicing track are connected to two sets of test pads. The two sets of test pads are not connected to each other, and adjacent test pads in each set of test pads are connected. The first power-on pad is one of the test pads in one set of test pads, and the second power-on pad is one of the test pads in another set of test pads.

[0013] The detection loop further includes a switching switch, wherein the signal input terminal is connected to the first energized pad through the switching switch, and the signal output terminal is connected to the second energized pad through the switching switch.

[0014] The wafer assembly is surrounded by a peripheral detection loop, which is configured to detect the connection status of multiple wafer layers in the wafer assembly.

[0015] The plurality of wafer layers include a first wafer layer and a second wafer layer; the detection loop includes: a first conductive layer located on the first wafer layer, the first conductive layer including at least two first conductive sheets; a second conductive layer located on the second wafer layer, the second conductive layer including at least two second conductive sheets; the first conductive sheets and the second conductive sheets are connected in series through the connection structure to form the detection loop.

[0016] The connection structure includes: a first connecting key, one end of which is connected to the first conductive sheet and the other end is close to the second wafer layer; a second connecting key, one end of which is connected to the second conductive sheet and the other end is close to the first wafer layer; each first conductive sheet is connected to two first connecting keys, each second conductive sheet is connected to two second connecting keys, each second conductive sheet has an overlapping portion in its vertical projection with two adjacent first conductive sheets, and each first connecting key is connected to one second connecting key, thereby connecting the first conductive sheet and the second conductive sheet in series to form the detection loop.

[0017] The three-dimensional integrated wafer further includes: an isolation ring located between the dicing channel and the chip cell, and a detection loop located on the side of the isolation ring away from the chip cell; or, the detection loop is located between the isolation rings; or, the detection loop is the isolation ring.

[0018] To solve the above-mentioned technical problems, the second technical solution provided by the present invention is: to provide a three-dimensional integrated chip, comprising: chip units; the chip units are surrounded by at least some cutting marks, the cutting marks being marks for a detection loop after the wafer assembly is cut; the detection loop is disposed around each of the chip units.

[0019] To solve the above-mentioned technical problems, the third technical solution provided by the present invention is: to provide a testing method for three-dimensional integrated wafers, including: using the detection loop around each chip unit to detect the connection of multiple wafer layers in each chip unit.

[0020] The step of detecting the connection status of multiple wafer layers in each chip unit using the detection loop surrounding each chip unit includes: inputting a detection current into the detection loop; receiving an output signal from the detection loop, the output signal including a voltage signal; determining a resistance value based on the detection current and the voltage signal; and indicating that the connection status of the multiple wafer layers in the chip unit is normal if the resistance value is within a preset range, otherwise, the connection status of the multiple wafer layers in the chip unit is abnormal.

[0021] The beneficial effects of this invention, which differ from the prior art, are that the three-dimensional integrated wafer of this invention has a detection loop set around the chip unit. By detecting the connection of multiple wafer layers in each chip unit through the detection loop, the wafer layering problem in the chip can be effectively monitored, thereby improving the chip yield. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0023] Figure 1 This is a schematic diagram of the structure of an embodiment of the three-dimensional integrated wafer of the present invention;

[0024] Figure 2 for Figure 1 A partial structural schematic diagram of an embodiment of a three-dimensional integrated wafer is shown;

[0025] Figures 3a-3b for Figure 2 A schematic diagram of the structure at position A in the middle;

[0026] Figure 4 for Figure 1 A partial structural schematic diagram of another embodiment of the three-dimensional integrated wafer shown;

[0027] Figures 5-6 for Figure 4 Schematic diagram of the structure at position B in the middle;

[0028] Figure 7 for Figure 1 A schematic diagram of a cross-sectional view of a three-dimensional integrated wafer;

[0029] Figure 8 for Figure 1 A schematic diagram of the structure of the chip unit;

[0030] Figure 9 This is a schematic diagram of the structure of an embodiment of the three-dimensional integrated chip of the present invention;

[0031] Figure 10 This is a flowchart illustrating one embodiment of a testing method for three-dimensional integrated wafers. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0033] Please see Figure 1 , Figure 1This is a schematic diagram of a structure of an embodiment of the three-dimensional integrated wafer of the present invention. The three-dimensional integrated wafer includes a wafer assembly 100, which includes multiple wafer layers stacked together and connected by interconnection structures. The wafer assembly 100 includes multiple chip units 110, and a detection loop 120 is disposed around each chip unit 110. The detection loop 120 is configured to detect the interconnection status of the multiple wafer layers in each chip unit 110.

[0034] Specifically, the wafer assembly 100 includes a plurality of dicing channels 130 along a first direction and / or a second direction, the dicing channels 130 dividing the wafer assembly 100 into a plurality of chip units 110, and a portion of the detection loop 120 is disposed in the dicing channels 130, wherein the first direction is perpendicular to the second direction. Figure 1 As shown, the detection loop 120 of the chip unit 110 near the edge of the wafer assembly 100 is located in a non-cutting channel position. As shown in chip unit 1, the detection loop 120 on its left and upper sides is located in a non-cutting channel position; as shown in chip unit 3, the detection loop 120 on its upper side is located in a non-cutting channel position; as shown in chip unit 2, the detection loop 120 on its left and lower sides is located in a non-cutting channel position.

[0035] Understandably, in one embodiment, devices formed by multiple wafer layers within the same chip unit 110 have the same area. For example, chip unit 1 is composed of stacked logic chips and memory chips, wherein the logic chips and memory chips have the same area. In another embodiment, chip unit 1 may further include multiple memory chips, which are arranged in a flat manner and stacked and bonded to logic chips; that is, the area of ​​the multiple memory chips is the same as or smaller than the area of ​​the logic chips. Understandably, in this case, a detection loop is provided at the edge of the multiple memory chips near the logic chips.

[0036] Specifically, in the chip fabrication process, the wafer assembly 100 needs to be cut from the dicing channel into multiple chip units 110. In the embodiments of this application, during the wafer-level fabrication process, the bonding status of the wafer layer corresponding to each chip unit 110 is detected by a detection loop, which can ensure the bonding yield of the cut chips. Furthermore, this application can also locate the specific location of bonding problems in a timely manner, facilitating the search for corresponding solutions for timely improvement, further reducing costs, and ensuring yield.

[0037] In one embodiment of this application, the detection loops 120 corresponding to two adjacent chip units 110 are disposed on both sides of the cutting channel 130, specifically as follows: Figure 1As shown, the detection loops 120 of adjacent chip units 1 and 2 are located on the upper and lower sides of the dicing channel 130, respectively, and the detection loops 120 of adjacent chip units 1 and 3 are located on the left and right sides of the dicing channel 130, respectively. Specifically, the detection loops 120 corresponding to any chip unit are independent of each other. For example, the detection loops 120 corresponding to chip units 1, 2, and 3 do not interfere with each other and can each detect the wafer layer connectivity of its corresponding chip unit.

[0038] In one embodiment, the stacked wafer further includes a test pad group 140. The test pad group 140 is located on the dicing 130 and between the detection loops 120 on both sides of the dicing 130. The test pad group 140 is the pad for the test circuit corresponding to the chip unit 110. This test circuit is a circuit for testing the function of the chip unit 110. For example, WAT (Wafer Acceptable Test) is a method that uses a specific test instrument to measure a specific test key at the dicing line position of a wafer during the wafer manufacturing process to confirm whether there are any abnormalities in the wafer manufacturing process. WAT is widely used by wafer foundries and bonding plants to monitor process fluctuations during the wafer fabrication stage and detect production line abnormalities because it can be performed at any stage of wafer manufacturing.

[0039] In one embodiment, such as Figure 2 As shown, each detection loop 120 also includes a first power-on pad 11 and a second power-on pad 12. Both the first power-on pad 11 and the second power-on pad 12 are located in the cutting path 130. Figure 3a As shown, Figure 3a for Figure 2 The schematic diagram at position A shows that the signal input terminal n1 of the detection loop 120 is connected to the first power-on pad 11, and the signal output terminal n2 of the detection loop 120 is connected to the second power-on pad 12. (Specific details to follow.) Figure 2 and Figure 3a In this configuration, the signal input terminal n1 of the detection loop 120 of chip unit 1 is connected to the first power-on pad 11, and the signal output terminal n2 of the detection loop 120 of chip unit 1 is connected to the second power-on pad 12. Similarly, the signal input terminal n1 of the detection loop 120 of chip unit 3 is connected to the first power-on pad 11, and the signal output terminal n2 of the detection loop 120 of chip unit 3 is connected to the second power-on pad 12.

[0040] The first power pad 11 receives a detection current, drives the detection loop 120 through the detection current, and detects the output signal of the detection loop 120 from the second power pad 12. Based on the output signal, the connection status of multiple wafer layers in the chip unit is determined.

[0041] like Figure 3a As shown, since the detection loops 120 of chip unit 1 and chip unit 3 share the same first power-on pad 11, when the first power-on pad 11 receives the detection current, both chip unit 1 and chip unit 3 will be detected simultaneously. This makes it difficult to pinpoint the exact location of the connection fault. For example, if an abnormal connection is detected, it cannot be determined whether the abnormality is in chip unit 1 or chip unit 3. Therefore, chip unit 1 and chip unit 3 need to be detected individually. There are two methods; the first method is as follows... Figure 3a As shown, a switching switch is added. For example, the signal input terminal n1 of the detection loop 120 of chip unit 1 is connected to the first power-on pad 11 through switching switch T1, and the signal output terminal n2 of the detection loop 120 of chip unit 1 is connected to the second power-on pad 12 through switching switch T3. The signal input terminal n1 of the detection loop 120 of chip unit 3 is connected to the first power-on pad 11 through switching switch T2, and the signal output terminal n2 of the detection loop 120 of chip unit 3 is connected to the second power-on pad 12 through switching switch T4. When chip unit 1 is being tested, switching switches T1 and T3 are turned on, the first power-on pad 11 receives a current signal to drive the detection loop 120, and receives the output signal of the detection loop 120 from the second power-on pad 12. When chip unit 3 is being tested, switching switches T2 and T4 are turned on, the first power-on pad 11 receives a current signal to drive the detection loop 120, and receives the output signal of the detection loop 120 from the second power-on pad 12. The second method is as follows... Figure 3b As shown, the detection loops 120 of chip unit 1 and chip unit 3 are connected to different power-on pads. For example, the signal input terminal n1 of the detection loop 120 of chip unit 1 is connected to the first power-on pad 11, and the signal output terminal n2 is connected to the second power-on pad 12; the signal input terminal n1 of the detection loop 120 of chip unit 3 is connected to the first power-on pad 13, and the signal output terminal n2 is connected to the second power-on pad 14. When detecting chip unit 1, the first power-on pad 11 receives a current signal to drive the detection loop 120, and receives the output signal of the detection loop 120 from the second power-on pad 12. When detecting chip unit 3, the first power-on pad 13 receives a current signal to drive the detection loop 120, and receives the output signal of the detection loop 120 from the second power-on pad 14.

[0042] The method described above can detect the connection status of the wafer layer of chip unit 110 and locate the connection fault to a specific chip unit 110. In another embodiment, the connection fault can also be located to a specific position within chip unit 110. In this embodiment, the detection loop 120 includes multiple sub-detection loops. That is, the detection loop 120 around chip unit 110 is divided into multiple segments. Each sub-detection loop has a signal input terminal and a signal output terminal. Specifically, the signal input terminal of each sub-detection loop is connected to a first power-on pad, and the signal output terminal of each sub-detection loop is connected to a second power-on pad. It is understood that the first power-on pads of each sub-detection loop are independent of each other, and the second sub-detection loops are also independent of each other. To reduce wiring, the first and second power-on pads of each sub-detection loop are positioned close to the sub-detection loop. Through this embodiment, the connection status around the chip unit can be detected in segments around the chip unit, thereby accurately locating the specific position of the connection fault.

[0043] The method described above in this application additionally provides energized pads corresponding to the detection loop 120 within the dicing channel 130, which increases the number of components within the dicing channel 130. In another embodiment of this application, the energization of the detection loop 120 can also be achieved using existing pads within the dicing channel. That is, the first energized pad 11 and the second energized pad 12 are pads for a test circuit in the dicing channel 130, and this test circuit is a WAT ​​test circuit.

[0044] like Figure 4 As shown, the detection loop 120 connects to the test pads in the test pad group 140. According to existing products, there are multiple test pad groups 140, and the test pads in each group are interconnected, but the test pads in multiple groups are not connected to each other. In adjacent chip units 110, the detection loop 120 on both sides of the dicing track 130 connects two groups of test pads. The two groups of test pads are not connected to each other, and adjacent test pads in each group are connected. The first power-on pad is one test pad in one group of test pads, and the second power-on pad is one test pad in another group of test pads. Specifically, as shown... Figure 5 As shown, Figure 5 for Figure 4A schematic diagram of position B. In this embodiment, the test pad group includes test pad group 31 and test pad group 32. The test pads in test pad group 31 are interconnected, and the test pads in test pad group 32 are interconnected, but test pad group 31 and test pad group 32 are not connected. Specifically, in adjacent chip units 1 and 3, the signal input terminal n1 of the detection loop 120 of chip unit 1 is connected to test pad 310 (test pad 310 is the first powered pad) in test pad group 31, and the signal output terminal n2 is connected to test pad 320 (test pad 320 is the second powered pad) in test pad group 32. Similarly, the signal input terminal n1 of the detection loop 120 of chip unit 3 is connected to test pad 310 (test pad 310 is the first powered pad) in test pad group 31, and the signal output terminal n2 is connected to test pad 320 (test pad 320 is the second powered pad) in test pad group 32. It should be noted that in the existing standard WAT test structure, 22 test pads are usually grouped into a test pad group.

[0045] With the above Figure 3a The embodiment shown is the same, but the detection loop further includes a switching switch, the signal input terminal is connected to the first energized pad through the switching switch, and the signal output terminal is connected to the second energized pad through the switching switch.

[0046] In another embodiment, the first power-on pad and the second power-on pad connected to the detection loop of chip unit 1, and the first power-on pad and the second power-on pad connected to the detection loop of chip unit 3, can be different test pads.

[0047] In another embodiment, in adjacent chip cells, the detection loops on both sides of the dicing track are connected to the same set of test pads, adjacent test pads in the same set are connected, and the first power-on pad and the second power-on pad are each one of the same set of test pads. Specifically, as follows... Figure 5 As shown, in this embodiment, the test loops of chip unit 1 and chip unit 3 are connected to two different test pads in test pad group 31. Specifically, the signal input terminal n1 of the detection loop of chip unit 1 is connected to test pad 310 (first powered pad) of test pad group 31, and the signal output terminal n2 is connected to test pad 311 (second powered pad) of test pad group 31; the signal input terminal n1 of the detection loop of chip unit 3 is connected to test pad 310 (first powered pad) of test pad group 31, and the signal output terminal n2 is connected to test pad 311 (second powered pad) of test pad group 31.

[0048] In one feasible embodiment of this application, a peripheral detection loop can also be provided around the wafer assembly. This peripheral detection loop is configured to detect the connection status of multiple wafer layers in the wafer assembly. Specifically, when inspecting a 3D integrated wafer, a drive current can first be applied to the peripheral detection loop to detect the connection status of the wafer layers in the 3D integrated wafer. If an abnormal connection is found, the connection status of the wafer layers in the chip unit 110 can be further detected through the detection loop around the chip unit 110. This can save on inspection procedures and improve efficiency.

[0049] This application uses the bonding of two wafer layers as an example for illustration, specifically as follows: Figure 7 As shown, the wafer layer includes a first wafer layer 71 and a second wafer layer 72. The detection loop 120 includes a first conductive layer and a second conductive layer. The first conductive layer is located on the first wafer layer 71 and includes at least two first conductive sheets 711; the second conductive layer is located on the second wafer layer 72 and includes at least two second conductive sheets 721. The first conductive sheets 711 and the second conductive sheets 721 are connected in series through the connection structure to form the detection loop 120. Specifically, the connection structure includes a first connecting bond 712 and a second connecting bond 722. One end of the first connecting bond 712 is connected to the first conductive sheet 711, and the other end is close to the second wafer layer 72; one end of the second connecting bond 722 is connected to the second conductive sheet 721, and the other end is close to the first wafer layer 71. Each first conductive sheet 711 is connected to the first connecting key 712, each second conductive sheet 721 is connected to two second connecting keys 722, each second conductive sheet 721 has an overlapping portion with the vertical projection of the two adjacent first conductive sheets 711, and each first connecting key 712 is connected to a corresponding second connecting key 722, thereby connecting the first conductive sheet 711 and the second conductive sheet 721 in series to form the detection loop 120.

[0050] In such Figure 7 In the embodiment shown, the signal input terminal of the detection loop 120 can be either the first connection key 712 or the second connection key 722.

[0051] In one embodiment of this application, the stacked wafer further includes an isolation ring 81, which is used to block cutting cracks during wafer dicing and protect the chip cells from damage. Figure 8 As shown, the isolation ring 81 is located between the dicing channel 83 and the chip unit 84, and the detection loop 82 is located on the side of the isolation ring 81 away from the chip unit 84. That is, the detection loop 82 is located within the dicing channel 83. In this way, the detection loop 82 can form a new isolation ring, further protecting the chip unit 84 during dicing.

[0052] In another embodiment, the detection loop 82 may be located between the isolation rings 81. Alternatively, in another embodiment, the detection loop 82 is an isolation ring 81. That is, when fabricating the isolation ring 81, the structure of the isolation ring 81 is fabricated as described above for the detection loop 82.

[0053] This application's stacked wafer incorporates a chain-like metal layer and a hybrid bonding via at the junction of two wafers within a WAT ​​(Wafer Acceptability Test) structure. This structure is brought out through WAT test pads, enabling WAT testing to detect the wafer and bonding process during manufacturing. Monitoring the test results (resistance value) characterizes the delamination of the bonding process, allowing for timely adjustments and improvements to the bonding process. Specifically, the fabrication process includes... Figure 7 The first wafer layer 71 and the second wafer layer 72 are shown, and then the first wafer layer 71 and the second wafer layer 72 are hybrid bonded. After the wafer bonding is completed, a WAT ​​test is performed under a certain current, and the output signal of the detection loop is collected to determine the voltage value of the output signal. The corresponding resistance can be calculated from the current and voltage, and the resistance data is collected. When the obtained resistance value is greater than the preset resistance value, it indicates that there is a partial open circuit in the area covered by the detection loop. This indicates that a delamination problem has occurred in the area covered by the WAT test structure, and the delamination location can be confirmed based on the circuit coverage location. By slicing the wafer at this location, the cause of the delamination can be confirmed, and problems in the wafer bonding process can be found in a timely manner and corresponding improvements can be made to avoid similar problems causing greater economic losses. Using the method of this patent, the accuracy and efficiency of electrical testing are significantly improved compared to observation by the naked eye and microscope. Only simple modifications are needed to the existing factory-side WAT test structure to accurately judge the delamination situation in the wafer, effectively ensuring that chips with similar delamination problems do not reach the customer and cause more serious quality problems. It can be used to monitor delamination issues caused by process problems during 3D bonding, and can pinpoint the location of the problem within the wafer, laying the foundation for subsequent process improvement solutions. Furthermore, since this structure essentially adds a seal ring around the chip, it effectively prevents delamination issues along the 3D bonding interface from occurring during subsequent chip dicing.

[0054] Please see Figure 9 This is a schematic diagram of the structure of an embodiment of the three-dimensional integrated chip of the present invention, specifically including a chip unit 91. The chip unit 91 is surrounded by at least some cutting marks 92, which correspond to the markings of the detection loop after the wafer assembly is cut. The detection loop is disposed around each of the chip units, and this detection loop is as described above. Figures 1 to 8 The detection loop in any of the embodiments shown.

[0055] Understandably, the detection loop in this application is located at the dicing channel. When the wafer assembly is diced, the detection loop may be damaged, so there may be residue of the detection loop around the diced chip unit.

[0056] Please see Figure 10 This is a flowchart illustrating an embodiment of the three-dimensional integrated wafer of the present invention, which utilizes a detection loop around each chip unit to detect the connectivity of multiple wafer layers within each chip unit. Specifically, it includes:

[0057] Step S101: Input detection current into the detection loop.

[0058] Step S102: Receive the output signal output by the detection loop, the output signal including a voltage signal.

[0059] Step S103: Determine the resistance value based on the detected current and the voltage signal.

[0060] Specifically, if the current and voltage are known, the resistance value can be calculated.

[0061] Step S104: If the resistance value is within a preset range, the connection of the multiple wafer layers in the chip unit is normal; otherwise, the connection of the multiple wafer layers in the chip unit is abnormal.

[0062] Specifically, if the resistance value is within a preset range, the interconnection of the wafer layers in the chip unit is normal; otherwise, the interconnection of the wafer layers in the chip unit is abnormal. For example, if the resistance value is greater than a preset resistance value, it is determined that the interconnection of the wafer layers in the chip unit is abnormal.

[0063] If no anomalies are detected, the subsequent manufacturing process can continue to complete the wafer manufacturing process. If an anomaly is detected, the abnormal location can be sliced ​​to determine the cause of the delamination, and the subsequent wafer bonding process can be improved based on the cause of the delamination.

[0064] The stacked wafer inspection method of this application incorporates a chain-like metal layer and a hybrid bonding via connection structure designed at the junction of two wafers into the WAT (Wafer Acceptability Test) structure. This structure is led out through WAT test pads, thereby enabling WAT testing during wafer and bonding manufacturing processes. By monitoring the test results (resistance value), the delamination of the bonding during manufacturing is characterized, and the bonding process can be adjusted and improved in a timely manner based on the results. Specifically, the fabrication process includes... Figure 7The first wafer layer 71 and the second wafer layer 72 are shown, and then the first wafer layer 71 and the second wafer layer 72 are hybrid bonded. After the wafer bonding is completed, a WAT ​​test is performed under a certain current, and the output signal of the detection loop is collected to determine the voltage value of the output signal. The corresponding resistance can be calculated from the current and voltage, and the resistance data is collected. When the obtained resistance value is greater than the preset resistance value, it indicates that there is a partial open circuit in the area covered by the detection loop. This indicates that a delamination problem has occurred in the area covered by the WAT test structure, and the delamination location can be confirmed based on the circuit coverage location. By slicing the wafer at this location, the cause of the delamination can be confirmed, and problems in the wafer bonding process can be found in a timely manner and corresponding improvements can be made to avoid similar problems causing greater economic losses. Using the method of this patent, the accuracy and efficiency of electrical testing are significantly improved compared to observation by the naked eye and microscope. Only simple modifications are needed to the existing factory-side WAT test structure to accurately judge the delamination situation in the wafer, effectively ensuring that chips with similar delamination problems do not reach the customer and cause more serious quality problems. It can be used to monitor delamination issues caused by process problems during 3D bonding, and can pinpoint the location of the problem within the wafer, laying the foundation for subsequent process improvement solutions. Furthermore, since this structure essentially adds a seal ring around the chip, it effectively prevents delamination issues along the 3D bonding interface from occurring during subsequent chip dicing.

[0065] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A three-dimensional integrated wafer, characterized in that, include: A wafer assembly consisting of multiple wafer layers, wherein the multiple wafer layers are stacked and connected by a connection structure; The wafer assembly includes multiple chip units, and a detection loop is arranged around each chip unit. The detection loop is configured to detect the connection status of multiple wafer layers in each chip unit. The wafer assembly includes multiple dicing channels along a first direction and / or a second direction. A portion of the detection loop of the wafer assembly is disposed on the dicing channels. The first direction is perpendicular to the second direction. The dicing channels divide the wafer assembly into multiple chip units. Each of the aforementioned detection loops further includes: The first energized pad is located on the cutting track, and the signal input terminal of the detection loop is connected to the first energized pad. The second energized pad is located on the cutting track, and the signal output terminal of the detection loop is connected to the second energized pad. The first energized pad receives the detection current, and the output signal of the detection loop is detected from the second energized pad; Each of the aforementioned detection loops includes multiple detection sub-loops: The signal input terminal of each detection sub-loop is connected to the first power-on pad; the signal output terminal of each detection sub-loop is connected to the second power-on pad. The first and second power-on pads are pads for the test circuit in the dicing track; the test circuit is a wafer-acceptable test circuit. The chip unit includes a logic chip and multiple memory chips. The multiple memory chips are arranged in a flat manner and are stacked and bonded to the logic chip. The detection loop is set at the edge of the multiple memory chips near the logic chip.

2. The three-dimensional integrated wafer according to claim 1, characterized in that, The detection loops corresponding to two adjacent chip units are arranged on both sides of the cutting channel, and the detection loops corresponding to any chip unit are independent of each other.

3. The three-dimensional integrated wafer according to claim 2, characterized in that, In adjacent chip units, the detection loops on both sides of the dicing track are connected to the same set of test pads, adjacent test pads in the same set of test pads are connected, and the first power-on pad and the second power-on pad are each one of the same set of test pads.

4. The integrated wafer according to claim 2, characterized in that, In adjacent chip units, the detection loops on both sides of the dicing track connect two sets of test pads. The two sets of test pads are not connected to each other, and adjacent test pads in each set of test pads are connected. The first power-on pad is one of the test pads in one set of test pads, and the second power-on pad is one of the test pads in another set of test pads.

5. The three-dimensional integrated wafer according to claim 3 or 4, characterized in that, The detection loop further includes: A switching switch is provided, wherein the signal input terminal is connected to the first energized pad through the switching switch, and the signal output terminal is connected to the second energized pad through the switching switch.

6. The three-dimensional integrated wafer according to claim 1, characterized in that, A peripheral detection loop is provided around the wafer assembly, and the peripheral detection loop is configured to detect the connection status of multiple wafer layers in the wafer assembly.

7. The three-dimensional integrated wafer according to claim 5, characterized in that, The plurality of wafer layers includes a first wafer layer and a second wafer layer; The detection loop includes: A first conductive layer is located on the first wafer layer, and the first conductive layer includes at least two first conductive sheets; A second conductive layer is located on the second wafer layer, and the second conductive layer includes at least two second conductive sheets; The first conductive sheet and the second conductive sheet are connected in series through the connection structure to form the detection loop.

8. The three-dimensional integrated wafer according to claim 7, characterized in that, The connection structure includes: The first connecting bond has one end connected to the first conductive sheet and the other end close to the second wafer layer; The second connecting bond has one end connected to the second conductive sheet and the other end close to the first wafer layer; Each first conductive sheet is connected to two first connecting keys, each second conductive sheet is connected to two second connecting keys, each second conductive sheet has an overlapping portion with the vertical projection of two adjacent first conductive sheets, and each first connecting key is connected to a second connecting key, thereby connecting the first conductive sheets and the second conductive sheets in series to form the detection loop.

9. The three-dimensional integrated wafer according to claim 1, characterized in that, Also includes: An isolation ring is located between the dicing channel and the chip unit, and the detection loop is located on the side of the isolation ring away from the chip unit; Alternatively, the detection loop may be located between the isolation rings; Alternatively, the detection loop may be the isolation loop.

10. A three-dimensional integrated chip, characterized in that, include: Chip unit; The chip unit is surrounded by at least some cutting marks, which are markings for the detection loop after the wafer assembly is cut; The detection loop is arranged around each of the chip units; The chip unit is composed of a wafer assembly consisting of multiple wafer layers, which are stacked and connected by a connection structure; the detection loop is configured to detect the connection status of the multiple wafer layers in each chip unit; The three-dimensional integrated chip is formed by cutting a three-dimensional integrated wafer. The wafer assembly includes multiple dicing channels along a first direction and / or along a second direction. A portion of the detection loop of the wafer assembly is disposed on the dicing channel. The first direction is perpendicular to the second direction. The dicing channel divides the wafer assembly into multiple chip units. Each of the aforementioned detection loops further includes: The first energized pad is located on the cutting track, and the signal input terminal of the detection loop is connected to the first energized pad. The second energized pad is located on the cutting track, and the signal output terminal of the detection loop is connected to the second energized pad. The first energized pad receives the detection current, and the output signal of the detection loop is detected from the second energized pad; Each of the aforementioned detection loops includes multiple detection sub-loops: The signal input terminal of each detection sub-loop is connected to the first power-on pad; the signal output terminal of each detection sub-loop is connected to the second power-on pad. The first and second power-on pads are pads for the test circuit in the dicing track; the test circuit is a wafer-acceptable test circuit. The chip unit includes a logic chip and multiple memory chips. The multiple memory chips are arranged in a flat manner and are stacked and bonded to the logic chip. The detection loop is set at the edge of the multiple memory chips near the logic chip.

11. A testing method for a three-dimensional integrated wafer, characterized in that, The testing method is based on the three-dimensional integrated wafer according to any one of claims 1 to 9, and the method includes: The connection status of the plurality of wafer layers in each chip cell is detected using the detection loop surrounding each chip cell.

12. The test method according to claim 11, characterized in that, The step of detecting the connectivity of multiple wafer layers in each chip cell using the detection loop surrounding each chip cell includes: Input a detection current into the detection loop; Receive the output signal from the detection loop, the output signal including a voltage signal; The resistance value is determined based on the detected current and the voltage signal; If the resistance value is within a preset range, the connection of the multiple wafer layers in the chip unit is normal; otherwise, the connection of the multiple wafer layers in the chip unit is abnormal.

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