Isolation structure and manufacturing method of magnetic isolation chip and capacitive isolation chip

Abstract

The present invention provides an isolation structure and a manufacturing method for a magnetic isolation chip and a capacitive isolation chip. The stress of the entire film layer is refined by converting a part of the entire film layer with relatively large stress in the isolation structure into a plurality of independent film layer units, which are distributed in an interspersed manner on adjacent film layers. The stress of the entire film layer is thereby adapted to the stress of the adjacent film layers, thereby improving the reliability of the isolation structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor process technology, and more specifically, to an isolation structure and a manufacturing method of a magnetic isolation chip and a capacitive isolation chip. Background Art

[0002] With the continuous development of science and technology, various transformer products have been widely used in people's lives and work, bringing great convenience to people's daily lives.

[0003] Based on the transformer, in order to improve its transmission power, it is necessary to increase the voltage and / or increase the current. Generally speaking, increasing the voltage is a technical means that is relatively easy to achieve in terms of electricity or cost. Therefore, for the safety of the low-voltage side, it is necessary to add an isolation chip to the transformer. The isolation chips currently used in transformers are mainly magnetic isolation chips and capacitive isolation chips.

[0004] Taking magnetic isolation chips and capacitive isolation chips as examples, in the isolation structure of current magnetic isolation chips and / or capacitive isolation chips, the stress of some film layers is relatively large, which can easily cause the film layer to rupture, thereby affecting the reliability of the isolation structure. Summary of the invention

[0005] In view of this, in order to solve the above problems, the present invention provides an isolation structure and a manufacturing method of a magnetic isolation chip and a capacitive isolation chip, and the technical solution is as follows:

[0006] An isolation structure of a magnetic isolation chip, the isolation structure comprising:

[0007] substrate;

[0008] In a first direction, a first metal layer, a first film layer, and at least one group of stacked film layers are sequentially arranged on one side of the substrate; each group of the stacked film layers includes a second film layer and a third film layer stacked in the first direction; the first direction is perpendicular to the substrate and points from the substrate to the first metal layer;

[0009] Wherein, the second film layer in any of the stacked film layers is composed of a plurality of independent film layer units, and the film layer units are filled with the third film layer.

[0010] Preferably, in the above isolation structure, when the stacked film layers are at least two groups,

[0011] In the first direction, in two adjacent groups of the stacked film layers, the orthographic projections of any film layer unit in one group of the stacked film layers and any film layer unit in the other group of the stacked film layers on the substrate do not overlap or partially overlap.

[0012] Preferably, in the above isolation structure, the thickness of the second film layer is 0.1 μm-0.3 μm.

[0013] Preferably, in the above isolation structure, the first film layer and the third film layer are made of the same material, which is SiO2.

[0014] Preferably, in the above isolation structure, the material of the second film layer is Al2O3, ZrO2 or SiC.

[0015] Preferably, in the above isolation structure, the isolation structure further comprises:

[0016] A second metal layer is disposed on a side of the last group of stacked film layers away from the substrate;

[0017] The first metal layer and the second metal layer are respectively composed of a plurality of independent metal units.

[0018] Preferably, in the above isolation structure, the isolation structure further comprises:

[0019] a fourth film layer disposed on a side of the second metal layer facing away from the substrate;

[0020] The first film layer, the third film layer and the fourth film layer are made of the same material.

[0021] Preferably, in the above isolation structure, the first film layer fills the gaps between the multiple independent metal units in the first metal layer, and the fourth film layer fills the gaps between the multiple independent metal units in the second metal layer.

[0022] Preferably, in the above isolation structure, the isolation structure further comprises:

[0023] a first through hole penetrating the fourth film layer, the third film layer in the stacked film layers, and the first film layer, wherein the first through hole exposes a portion of the metal unit in the first metal layer;

[0024] A second through hole penetrates the fourth film layer, wherein the second through hole exposes a portion of the metal unit in the second metal layer.

[0025] A method for manufacturing an isolation structure of a magnetic isolation chip, the manufacturing method comprising:

[0026] providing a substrate;

[0027] In a first direction, a first metal layer, a first film layer, and at least one group of stacked film layers are sequentially formed on one side of the substrate; each group of the stacked film layers includes a second film layer and a third film layer stacked in the first direction; the first direction is perpendicular to the substrate and points from the substrate to the first metal layer;

[0028] Wherein, the second film layer in any of the stacked film layers is composed of a plurality of independent film layer units, and the film layer units are filled with the third film layer.

[0029] Preferably, in the above manufacturing method, when the stacked film layers are at least two groups,

[0030] In the first direction, in two adjacent groups of the stacked film layers, the orthographic projections of any film layer unit in one group of the stacked film layers and any film layer unit in the other group of the stacked film layers on the substrate do not overlap or partially overlap.

[0031] Preferably, in the above manufacturing method, the thickness of the second film layer is 0.1 μm-0.3 μm.

[0032] Preferably, in the above manufacturing method, the first film layer and the third film layer are made of the same material, which is SiO2.

[0033] Preferably, in the above manufacturing method, the material of the second film layer is Al2O3, ZrO2 or SiC.

[0034] Preferably, in the above production method, the production method further comprises:

[0035] forming a second metal layer on a side of the last group of stacked film layers facing away from the substrate;

[0036] The first metal layer and the second metal layer are respectively composed of a plurality of independent metal units.

[0037] Preferably, in the above production method, the production method further comprises:

[0038] forming a fourth film layer on a side of the second metal layer facing away from the substrate;

[0039] The first film layer, the third film layer and the fourth film layer are made of the same material.

[0040] Preferably, in the above manufacturing method, the first film layer fills the gaps between the multiple independent metal units in the first metal layer, and the fourth film layer fills the gaps between the multiple independent metal units in the second metal layer.

[0041] Preferably, in the above production method, the production method further comprises:

[0042] forming a first through hole penetrating the fourth film layer, the third film layer in the stacked film layers, and the first film layer, wherein the first through hole exposes a portion of the metal unit in the first metal layer;

[0043] A second through hole is formed penetrating the fourth film layer, wherein the second through hole exposes a portion of the metal unit in the second metal layer.

[0044] An isolation structure of a capacitor isolation chip, the isolation structure comprising:

[0045] substrate;

[0046] In a first direction, a first metal layer, a first film layer, and at least one group of stacked film layers are sequentially arranged on one side of the substrate; each group of the stacked film layers includes a second film layer and a third film layer stacked in the first direction; the first direction is perpendicular to the substrate and points from the substrate to the first metal layer;

[0047] Wherein, the second film layer in any of the stacked film layers is composed of a plurality of independent film layer units, and the film layer units are filled with the third film layer.

[0048] Preferably, in the above isolation structure, when the stacked film layers are at least two groups,

[0049] In the first direction, in two adjacent groups of the stacked film layers, the orthographic projections of any film layer unit in one group of the stacked film layers and any film layer unit in the other group of the stacked film layers on the substrate do not overlap or partially overlap.

[0050] Preferably, in the above isolation structure, the thickness of the second film layer is 0.1 μm-0.3 μm.

[0051] Preferably, in the above isolation structure, the first film layer and the third film layer are made of the same material, which is SiO2.

[0052] Preferably, in the above isolation structure, the material of the second film layer is Al2O3, ZrO2 or SiC.

[0053] Preferably, in the above isolation structure, the isolation structure further comprises:

[0054] A fourth film layer is disposed on a side of the stacked film layer away from the substrate;

[0055] The first film layer, the third film layer and the fourth film layer are made of the same material.

[0056] Preferably, in the above isolation structure, the isolation structure further comprises:

[0057] A second metal layer disposed on a side of the fourth film layer facing away from the substrate;

[0058] Wherein, the first metal layer and the second metal layer are respectively a whole-surface film layer.

[0059] A method for manufacturing an isolation structure of a capacitor isolation chip, the manufacturing method comprising:

[0060] providing a substrate;

[0061] In a first direction, a first metal layer, a first film layer, and at least one group of stacked film layers are sequentially formed on one side of the substrate; each group of the stacked film layers includes a second film layer and a third film layer stacked in the first direction; the first direction is perpendicular to the substrate and points from the substrate to the first metal layer;

[0062] Wherein, the second film layer in any of the stacked film layers is composed of a plurality of independent film layer units, and the film layer units are filled with the third film layer.

[0063] Preferably, in the above manufacturing method, when the stacked film layers are at least two groups,

[0064] In the first direction, in two adjacent groups of the stacked film layers, the orthographic projections of any film layer unit in one group of the stacked film layers and any film layer unit in the other group of the stacked film layers on the substrate do not overlap or partially overlap.

[0065] Preferably, in the above manufacturing method, the thickness of the second film layer is 0.1 μm-0.3 μm.

[0066] Preferably, in the above manufacturing method, the first film layer and the third film layer are made of the same material, which is SiO2.

[0067] Preferably, in the above manufacturing method, the material of the second film layer is Al2O3, ZrO2 or SiC.

[0068] Preferably, in the above production method, the production method further comprises:

[0069] forming a fourth film layer on a side of the stacked film layer facing away from the substrate;

[0070] The first film layer, the third film layer and the fourth film layer are made of the same material.

[0071] Preferably, in the above production method, the production method further comprises:

[0072] forming a second metal layer on a side of the fourth film layer facing away from the substrate;

[0073] Wherein, the first metal layer and the second metal layer are respectively a whole-surface film layer.

[0074] Compared with the prior art, the present invention has the following beneficial effects:

[0075] The isolation structure provided by the present invention includes: a substrate; a first metal layer and at least one group of stacked film layers arranged in sequence on one side of the substrate in a first direction; each group of the stacked film layers includes a first film layer and a second film layer stacked in the first direction; the first direction is perpendicular to the substrate and points from the substrate to the first metal layer; wherein the second film layer in any of the stacked film layers is composed of multiple independent film layer units.

[0076] That is to say, by converting the entire film layer with larger stress in the isolation structure into multiple independent film layer units, which are distributed in an interspersed manner on adjacent film layers, the stress of the entire film layer is refined, so that its stress is adapted to the stress of the adjacent film layers, thereby improving the reliability of the isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0078] Figure 1 A schematic diagram of an isolation structure of a magnetic isolation chip provided by an embodiment of the present invention;

[0079] Figure 2 A schematic flow chart of a method for manufacturing an isolation structure of a magnetic isolation chip provided by an embodiment of the present invention;

[0080] Figure 3-Figure 14 for Figure 2 A structural schematic diagram corresponding to the manufacturing method shown;

[0081] Fig.15 A schematic diagram of an isolation structure of a capacitive isolation chip provided by an embodiment of the present invention;

[0082] Fig.16 A schematic flow chart of a method for manufacturing an isolation structure of a capacitor isolation chip provided by an embodiment of the present invention;

[0083] Figure 17-Figure 24 for Fig.16 Schematic diagram of the structure corresponding to the manufacturing method shown. DETAILED DESCRIPTION

[0084] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0085] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0086] refer to Figure 1 , Figure 1 A schematic diagram of an isolation structure of a magnetic isolation chip provided in an embodiment of the present invention.

[0087] The isolation structure comprises:

[0088] Substrate 11;

[0089] In a first direction, a first metal layer 12, a first film layer 13 and at least one group of stacked film layers 14 are sequentially arranged on one side of the substrate 11; each group of the stacked film layers 14 includes a second film layer 15 and a third film layer 16 stacked in the first direction; the first direction is perpendicular to the substrate 11 and points from the substrate 11 to the first metal layer 12;

[0090] The second film layer 15 in any of the stacked film layers 14 is composed of a plurality of independent film layer units, and the space between the film layer units is filled with the third film layer 16 .

[0091] In this embodiment, the entire film layer with relatively large stress in the isolation structure is converted into multiple independent film layer units, which are distributed in an interspersed manner on adjacent film layers, thereby refining the stress of the entire film layer so that its stress is adapted to the stress of the adjacent film layers, thereby improving the reliability of the isolation structure.

[0092] It should be noted that Figure 1 Two groups of stacked film layers are used as an example for explanation.

[0093] like Figure 1 As shown, the isolation structure also includes:

[0094] In the first direction, multiple dielectric layers are sequentially arranged between the substrate 11 and the first metal layer 12;

[0095] exist Figure 1 In the embodiment, the interlayer dielectric layer 17, the first metal interlayer dielectric layer 18, the other dielectric layers 19 and the second metal interlayer dielectric layer 20 are taken as examples for description.

[0096] Optionally, the other dielectric layer 19 may be a silicon dioxide dielectric layer. Optionally, the other dielectric layer 19 may be a multi-layer dielectric layer.

[0097] The interlayer dielectric layer 17 , the first metal interlayer dielectric layer 18 , the other dielectric layers 19 and the second metal interlayer dielectric layer 20 are mainly used for electrical insulation between metal layers.

[0098] Further, such as Figure 1 As shown, in the isolation structure, the substrate 11 has a source region 21, a drain region 22, and a gate oxide layer 23 and a gate polycrystalline layer 24 arranged on the substrate 11. The source region 21, the drain region 22, and the gate polycrystalline layer 24 are respectively led to a source 26, a drain 27 and a gate 28 through a through hole 25.

[0099] Optionally, in another embodiment of the present invention, when the stacked film layers 14 are at least two groups,

[0100] In the first direction, in two adjacent groups of the stacked film layers 14 , the orthographic projections of any film layer unit in one group of the stacked film layers 14 and any film layer unit in the other group of the stacked film layers 14 on the substrate 11 do not overlap or partially overlap.

[0101] In this embodiment, the number of groups of stacked film layers 14 is used as an example to illustrate that by cross-distributing the film layer units in one group of the stacked film layers 14 with the film layer units in the other group of the stacked film layers 14 in two adjacent groups of stacked film layers 14, the isolation effect of the isolation structure can be improved.

[0102] Optionally, in another embodiment of the present invention, the material of the first film layer 13 is the same as the material of the third film layer 16, including but not limited to insulating materials such as SiO2; the material of the second film layer 15 includes but is not limited to wide bandgap materials such as Al2O3, ZrO2 or SiC.

[0103] In this embodiment, the second film layer 15 of ZrO2 material has high anti-magnetism and dielectric constant, and can play an outstanding isolation effect with the first film layer 13 and the third film layer 16 of insulating materials such as SiO2 in the isolation structure process of the magnetic isolation chip.

[0104] The first film layer 13 and the third film layer 16 made of insulating materials such as SiO 2 and the second film layer 15 made of ZrO 2 can also improve the pressure resistance of the isolation structure.

[0105] However, since the stress adaptability of the second film layer 15 made of the entire surface ZrO2 material and the first film layer 13 and the third film layer 16 made of the entire surface insulating material such as SiO2 is poor, it is easy to cause film cracking problems, thereby reducing the reliability of the isolation structure.

[0106] Based on this, in an embodiment of the present invention, the second film layer 15 of the entire surface ZrO2 material with relatively large stress is converted into a plurality of independent film layer units, which are interspersed and distributed in adjacent film layers (i.e., the first film layer 13 and the third film layer 16 of the entire surface SiO2 or other insulating materials), thereby minimizing the stress of the second film layer 15 of the entire surface ZrO2 material, thereby adapting its stress to the stress of the adjacent film layers, thereby improving the reliability of the isolation structure.

[0107] Optionally, in another embodiment of the present invention, the thickness of the second film layer 15 is 0.1 μm-0.3 μm, including endpoint values.

[0108] In this embodiment, the thickness of the second film layer 15 may be 0.15 μm, 0.2 μm, or 0.24 μm, etc. Specifically, the thickness of the second film layer 15 may be determined according to different processes, which is not limited in the embodiment of the present invention.

[0109] Furthermore, it should be noted that the number of layers of the second film layer 15 and the thickness of each layer will have a relatively large impact on the isolation withstand voltage of the isolation structure; generally, the more layers of the second film layer 15 and the thicker the thickness, the stronger the withstand voltage of the isolation structure.

[0110] Optionally, in another embodiment of the present invention, Figure 1 As shown, the isolation structure also includes:

[0111] A second metal layer 29 disposed on a side of the last group of stacked film layers 14 facing away from the substrate 11;

[0112] The first metal layer 12 and the second metal layer 29 are respectively composed of a plurality of independent metal units.

[0113] In this embodiment, two groups of stacked film layers 14 are taken as an example for description, and the first metal layer 12 and the second metal layer 29 are made of the same material.

[0114] The multiple independent metal units in the second metal layer 29 constitute a primary metal coil; the multiple independent metal units in the first metal layer 12 constitute a secondary metal coil.

[0115] It should be noted that the isolation structure of the magnetic isolation chip has a basic architecture of two coil structures formed by metal and a multi-layer dielectric layer located therebetween to form magnetic isolation.

[0116] Optionally, in another embodiment of the present invention, Figure 1 As shown, the isolation structure also includes:

[0117] A fourth film layer 30 disposed on a side of the second metal layer 29 facing away from the substrate 11;

[0118] The first film layer 13 , the third film layer 16 and the fourth film layer 30 are made of the same material.

[0119] In this embodiment, two groups of stacked film layers 14 are used as an example for explanation, and the first film layer 13, the third film layer 16 and the fourth film layer 30 are made of the same material, that is, including but not limited to insulating materials such as SiO2. The fourth film layer 30 fills the gaps between the multiple independent metal units in the second metal layer 29, and the first film layer 13 fills the gaps between the multiple independent metal units in the first metal layer 12.

[0120] It should be noted that Figure 1 Only part of the membrane layer structure of the isolation structure of the magnetic isolation chip is schematically shown. In the actual product structure, the isolation structure of the magnetic isolation chip also includes other membrane layer structures.

[0121] like Figure 1 As shown, the isolation structure also includes:

[0122] A first through hole 31 penetrating the fourth film layer 30, the third film layer 16 in the stacked film layer, and the first film layer 13, wherein the first through hole 31 exposes a portion of the metal unit in the first metal layer 12, that is, exposes the secondary metal coil;

[0123] The second through hole 32 penetrates through the fourth film layer 30 , and the second through hole 32 exposes a portion of the metal unit in the second metal layer 29 , that is, exposes the primary metal coil.

[0124] The first through hole 31 and the second through hole 32 serve as electrical connections.

[0125] Optionally, based on the above embodiment of the present invention, another embodiment of the present invention further provides a method for manufacturing an isolation structure of a magnetic isolation chip, referring to Figure 2 , Figure 2 A schematic flow chart of a method for manufacturing an isolation structure of a magnetic isolation chip provided in an embodiment of the present invention.

[0126] The production method comprises:

[0127] S101: providing a substrate;

[0128] S102: forming a first metal layer, a first film layer, and at least one group of stacked film layers in sequence on one side of the substrate in a first direction; each group of the stacked film layers includes a second film layer and a third film layer stacked in the first direction; the first direction is perpendicular to the substrate and points from the substrate to the first metal layer;

[0129] Wherein, the second film layer in any of the stacked film layers is composed of a plurality of independent film layer units, and the film layer units are filled with the third film layer.

[0130] In this embodiment, if Figure 3 As shown, a substrate 11 is provided, and a plurality of dielectric layers are arranged on the substrate 11;

[0131] exist Figure 3 In the embodiment, the interlayer dielectric layer 17, the first metal interlayer dielectric layer 18, the other dielectric layers 19 and the second metal interlayer dielectric layer 20 are taken as examples for description.

[0132] Optionally, the other dielectric layer 19 may be a silicon dioxide dielectric layer. Optionally, the other dielectric layer 19 may be a multi-layer dielectric layer.

[0133] The interlayer dielectric layer 17 , the first metal interlayer dielectric layer 18 , the other dielectric layers 19 and the second metal interlayer dielectric layer 20 are mainly used for electrical insulation between metal layers.

[0134] Further, in Figure 3 The middle substrate has a source region 21 , a drain region 22 , and a gate oxide layer 23 and a gate polycrystalline layer 24 disposed on the substrate 11 . The source region 21 , the drain region 22 , and the gate polycrystalline layer 24 are respectively connected to a source electrode 26 , a drain electrode 27 and a gate electrode 28 through a through hole 25 .

[0135] like Figure 4 As shown, the first metal layer 12 is formed on one side of the substrate 11 , that is, the first metal layer 12 is formed on the side of the second metal interlayer dielectric layer 20 facing away from the substrate 11 .

[0136] like Figure 5 As shown, the first metal layer 12 is etched to form a plurality of independent metal units, which constitute the secondary metal coils in the isolation structure of the magnetic isolation chip.

[0137] like Figure 6 As shown, a SiO2 film layer is further deposited on the first metal layer 12, that is, the first film layer 13 is described by taking the SiO2 film layer as an example.

[0138] Specifically, a SiO2 film layer is deposited on the first metal layer 12 by processes including but not limited to PECVD (plasma enhanced chemical vapor deposition) or HDP (high density plasma chemical vapor deposition) or SACVD (sub-atmospheric pressure chemical vapor deposition).

[0139] like Figure 7 As shown, this layer of SiO2 film is planarized.

[0140] Specifically, it includes but is not limited to performing a planarization process on the SiO2 film layer by a method such as CMP (chemical mechanical polishing) to planarize the surface of the SiO2 film layer. The first film layer 13 fills the gaps between the multiple independent metal units in the first metal layer 12 .

[0141] like Figure 8 As shown, a ZrO2 film layer is formed on the SiO2 film layer by a method including but not limited to electron beam evaporation, that is, the second film layer 15 is described by taking the ZrO2 film layer as an example.

[0142] like Fig. 9 As shown, a photolithography process is used to define the position where the ZrO2 film layer needs to be retained, that is, the ZrO2 film layer is patterned, and then anisotropic etching is used to remove excess ZrO2 film layer portions, so that the entire surface of the ZrO2 film layer forms a plurality of independent film layer units; it should be noted that the plurality of independent film layer units may be in the shape of long strips, coils, or circles, etc.

[0143] like Fig.10 As shown, a layer of SiO2 film is continuously deposited, that is, the third film layer 16 is described by taking the SiO2 film layer as an example.

[0144] Specifically, it includes but is not limited to depositing a SiO2 film layer using processes such as PECVD (plasma enhanced chemical vapor deposition) or HDP (high density plasma chemical vapor deposition) or SACVD (sub-atmospheric pressure chemical vapor deposition).

[0145] like Fig.11 As shown, this layer of SiO2 film is planarized.

[0146] Specifically, it includes but is not limited to performing a planarization process on the SiO2 film layer by a method such as CMP (chemical mechanical polishing) to planarize its surface.

[0147] At this time, a first set of stacked film layers 14 is formed.

[0148] It should be noted that the number of stacked film layers can be set according to actual needs, and some of the above steps can be repeated. In the embodiment of the present invention, two groups of stacked film layers are taken as an example for description.

[0149] like Fig.12 As shown, a layer of metal, namely, the second metal layer 29 is deposited by means of PVD (physical vapor deposition) or the like, but is not limited thereto.

[0150] like Fig.13 As shown, the second metal layer 29 is etched to form a plurality of independent metal units, which constitute the primary metal coil in the isolation structure of the magnetic isolation chip.

[0151] like Fig.14 As shown, a SiO2 film layer is further deposited on the second metal layer 29, that is, the fourth film layer 30 is described by taking the SiO2 film layer as an example.

[0152] Specifically, a SiO2 film layer is deposited on the second metal layer 29 by a process including but not limited to PECVD (plasma enhanced chemical vapor deposition) or HDP (high density plasma chemical vapor deposition) or SACVD (sub-atmospheric pressure chemical vapor deposition). The fourth film layer 30 fills the gaps between the multiple independent metal units in the second metal layer 29.

[0153] like Figure 1 As shown, a first through hole 31 is formed passing through the fourth film layer 30, the third film layer 16 and the first film layer 13, the first through hole 31 exposes part of the metal unit in the first metal layer 12, that is, exposes the secondary metal coil; and a second through hole 32 is formed passing through the fourth film layer 30, the second through hole 32 exposes part of the metal unit in the second metal layer 29, that is, exposes the primary metal coil.

[0154] Optionally, the present application also provides an isolation structure of a capacitor isolation chip, see Fig.15 , Fig.15 A schematic diagram of an isolation structure of a capacitive isolation chip provided in an embodiment of the present invention.

[0155] The isolation structure comprises:

[0156] Substrate 11;

[0157] In a first direction, a first metal layer 12, a first film layer 13 and at least one group of stacked film layers 14 are sequentially arranged on one side of the substrate 11; each group of the stacked film layers 14 includes a second film layer 15 and a third film layer 16 stacked in the first direction; the first direction is perpendicular to the substrate 11 and points from the substrate 11 to the first metal layer 12;

[0158] The second film layer 15 in any of the stacked film layers 14 is composed of a plurality of independent film layer units, and the space between the film layer units is filled with the third film layer 16 .

[0159] In this embodiment, the entire film layer with relatively large stress in the isolation structure is converted into multiple independent film layer units, which are distributed in an interspersed manner on adjacent film layers, thereby refining the stress of the entire film layer so that its stress is adapted to the stress of the adjacent film layers, thereby improving the reliability of the isolation structure.

[0160] It should be noted that Fig.15 Two groups of stacked film layers are used as an example for explanation.

[0161] like Fig.15 As shown, the isolation structure also includes:

[0162] In the first direction, multiple dielectric layers are sequentially arranged between the substrate 11 and the first metal layer 12;

[0163] exist Fig.15 In the embodiment, the interlayer dielectric layer 17, the first metal interlayer dielectric layer 18, the other dielectric layers 19 and the second metal interlayer dielectric layer 20 are taken as examples for description.

[0164] Optionally, the other dielectric layer 19 may be a silicon dioxide dielectric layer. Optionally, the other dielectric layer 19 may be a multi-layer dielectric layer.

[0165] The interlayer dielectric layer 17 , the first metal interlayer dielectric layer 18 , the other dielectric layers 19 and the second metal interlayer dielectric layer 20 are mainly used for electrical insulation between metal layers.

[0166] Further, such as Fig.15 As shown, in the isolation structure, the substrate 11 has a source region 21, a drain region 22, and a gate oxide layer 23 and a gate polycrystalline layer 24 arranged on the substrate 11. The source region 21, the drain region 22, and the gate polycrystalline layer 24 are respectively led to a source 26, a drain 27 and a gate 28 through a through hole 25.

[0167] Optionally, in another embodiment of the present invention, when the stacked film layers 14 are at least two groups,

[0168] In the first direction, in two adjacent groups of the stacked film layers 14 , the orthographic projections of any film layer unit in one group of the stacked film layers 14 and any film layer unit in the other group of the stacked film layers 14 on the substrate 11 do not overlap or partially overlap.

[0169] In this embodiment, the number of groups of stacked film layers 14 is used as an example to illustrate that by cross-distributing the film layer units in one group of the stacked film layers 14 with the film layer units in the other group of the stacked film layers 14 in two adjacent groups of stacked film layers 14, the isolation effect of the isolation structure can be improved.

[0170] Optionally, in another embodiment of the present invention, the material of the first film layer 13 and the third film layer 16 is the same, including but not limited to insulating materials such as SiO2; the material of the second film layer 15 includes but is not limited to wide bandgap materials such as Al2O3, ZrO2 or SiC.

[0171] In this embodiment, the second film layer 15 of ZrO2 material has high anti-magnetism and dielectric constant, and can play an outstanding isolation effect with the first film layer 13 and the third film layer 16 of insulating materials such as SiO2 in the isolation structure process of the capacitor isolation chip.

[0172] The first film layer 13 and the third film layer 16 made of insulating materials such as SiO 2 and the second film layer 15 made of ZrO 2 can also improve the pressure resistance of the isolation structure.

[0173] However, since the stress compatibility between the second film layer 15 made of the entire surface ZrO2 material and the first film layer and the third film layer 16 made of the entire surface insulating material such as SiO2 is poor, it is easy to cause film cracking, thereby reducing the reliability of the isolation structure.

[0174] Based on this, in an embodiment of the present invention, the second film layer 15 of the entire surface ZrO2 material with relatively large stress is converted into a plurality of independent film layer units, which are interspersed and distributed in adjacent film layers (i.e., the first film layer 13 and the third film layer 16 of the entire surface SiO2 or other insulating materials), thereby minimizing the stress of the second film layer 15 of the entire surface ZrO2 material, thereby adapting its stress to the stress of the adjacent film layers, thereby improving the reliability of the isolation structure.

[0175] Optionally, in another embodiment of the present invention, the thickness of the second film layer 15 is 0.1 μm-0.3 μm, including endpoint values.

[0176] In this embodiment, the thickness of the second film layer 15 may be 0.15 μm, 0.2 μm, or 0.24 μm, etc. Specifically, the thickness of the second film layer 15 may be determined according to different processes, which is not limited in the embodiment of the present invention.

[0177] Furthermore, it should be noted that the number of layers of the second film layer 15 and the thickness of each layer will have a relatively large impact on the isolation withstand voltage of the isolation structure; generally, the more layers of the second film layer 15 and the thicker the thickness, the stronger the withstand voltage of the isolation structure.

[0178] Optionally, in another embodiment of the present invention, Fig.15 As shown, the isolation structure also includes:

[0179] A fourth film layer 29 disposed on a side of the stacked film layer 14 away from the substrate 11;

[0180] The first film layer 13 , the third film layer 16 and the fourth film layer 29 are made of the same material.

[0181] In this embodiment, two groups of stacked film layers 14 are taken as an example for description, and the materials of the first film layer 13, the third film layer 16 and the fourth film layer 29 are the same, that is, including but not limited to insulating materials such as SiO2.

[0182] Optionally, in another embodiment of the present invention, Fig.15 As shown, the isolation structure also includes:

[0183] A second metal layer 30 disposed on a side of the fourth film layer 29 facing away from the substrate 11;

[0184] The first metal layer 12 and the second metal layer 30 are respectively a whole-surface film layer.

[0185] In this embodiment, two groups of stacked film layers 14 are taken as an example for description, and the first metal layer 12 and the second metal layer 30 are made of the same material.

[0186] It should be noted that the isolation structure of the capacitor isolation chip has a basic architecture that forms capacitor isolation through two oppositely disposed metal layers and a multi-layer dielectric layer located therebetween.

[0187] Fig.15 Only part of the film layer structure of the isolation structure of the capacitor isolation chip is schematically shown. In the actual product structure, the isolation structure of the capacitor isolation chip also includes other film layer structures.

[0188] Optionally, based on the above embodiment of the present invention, another embodiment of the present invention further provides a method for manufacturing an isolation structure of a capacitor isolation chip, referring to Fig.16 , Fig.16 A schematic flow chart of a method for manufacturing an isolation structure of a capacitor isolation chip provided in an embodiment of the present invention.

[0189] The production method comprises:

[0190] S201: providing a substrate;

[0191] S202: forming a first metal layer, a first film layer, and at least one group of stacked film layers in sequence on one side of the substrate in a first direction; each group of the stacked film layers includes a second film layer and a third film layer stacked in the first direction; the first direction is perpendicular to the substrate and points from the substrate to the first metal layer;

[0192] Wherein, the second film layer in any of the stacked film layers is composed of a plurality of independent film layer units, and the film layer units are filled with the third film layer.

[0193] In this embodiment, if Fig.17As shown, a substrate 11 is provided, and a plurality of dielectric layers are arranged on the substrate 11;

[0194] exist Fig.17 In the embodiment, the interlayer dielectric layer 17, the first metal interlayer dielectric layer 18, the other dielectric layers 19 and the second metal interlayer dielectric layer 20 are taken as examples for description.

[0195] Optionally, the other dielectric layer 19 may be a silicon dioxide dielectric layer. Optionally, the other dielectric layer 19 may be a multi-layer dielectric layer.

[0196] The interlayer dielectric layer 17 , the first metal interlayer dielectric layer 18 , the other dielectric layers 19 and the second metal interlayer dielectric layer 20 are mainly used for electrical insulation between metal layers.

[0197] Further, in Fig.17 The middle substrate has a source region 21 , a drain region 22 , and a gate oxide layer 23 and a gate polycrystalline layer 24 disposed on the substrate 11 . The source region 21 , the drain region 22 , and the gate polycrystalline layer 24 are respectively connected to a source electrode 26 , a drain electrode 27 and a gate electrode 28 through a through hole 25 .

[0198] like Fig.18 As shown, a first metal layer 12 is formed on one side of the substrate 11, that is, a first metal layer 12 is formed on the side of the second metal interlayer dielectric layer 20 away from the substrate 11. The first metal layer 12 is a metal film layer with a whole surface layer, serving as one of the metal layers in the isolation structure of the capacitor isolation chip.

[0199] like Fig.19 As shown, a SiO2 film layer is further deposited on the first metal layer 12, that is, the first film layer 13 is described by taking the SiO2 film layer as an example.

[0200] Specifically, a SiO2 film layer is deposited on the first metal layer 12 by processes including but not limited to PECVD (plasma enhanced chemical vapor deposition) or HDP (high density plasma chemical vapor deposition) or SACVD (sub-atmospheric pressure chemical vapor deposition).

[0201] like Fig. 20 As shown, a ZrO2 film layer is formed on the SiO2 film layer by a method including but not limited to electron beam evaporation, that is, the second film layer 15 is described by taking the ZrO2 film layer as an example.

[0202] like Fig.21As shown, a photolithography process is used to define the position where the ZrO2 film layer needs to be retained, that is, the ZrO2 film layer is patterned, and then anisotropic etching is used to remove excess ZrO2 film layer portions, so that the entire surface of the ZrO2 film layer forms a plurality of independent film layer units; it should be noted that the plurality of independent film layer units may be in the shape of long strips, coils, or circles, etc.

[0203] like Fig. 22 As shown, a layer of SiO2 film is continuously deposited, that is, the third film layer 16 is described by taking the SiO2 film layer as an example.

[0204] Specifically, it includes but is not limited to depositing a SiO2 film layer using processes such as PECVD (plasma enhanced chemical vapor deposition) or HDP (high density plasma chemical vapor deposition) or SACVD (sub-atmospheric pressure chemical vapor deposition).

[0205] like Fig.23 As shown, this layer of SiO2 film is planarized.

[0206] Specifically, it includes but is not limited to performing a planarization process on the SiO2 film layer by a method such as CMP (chemical mechanical polishing) to planarize its surface.

[0207] At this time, a first set of stacked film layers 14 is formed.

[0208] It should be noted that the number of stacked film layers can be set according to actual needs, and some of the above steps can be repeated. In the embodiment of the present invention, two groups of stacked film layers are taken as an example for description.

[0209] like Fig.24 As shown, a layer of SiO2 film is continuously deposited, that is, the fourth film layer 29 is described by taking the SiO2 film layer as an example.

[0210] Specifically, it includes but is not limited to depositing a SiO2 film layer using processes such as PECVD (plasma enhanced chemical vapor deposition) or HDP (high density plasma chemical vapor deposition) or SACVD (sub-atmospheric pressure chemical vapor deposition).

[0211] Due to the limitation of the thickness of the SiO2 film deposition at one time, by forming at least one fourth film layer 29 on the side of the third film layer 16 away from the substrate 11, the pressure resistance of the isolation structure can be at least improved while playing the role of film flattening.

[0212] like Fig.15 As shown, the method finally includes but is not limited to depositing a layer of metal, namely, the second metal layer 30, by means of PVD (physical vapor deposition) or the like.

[0213] The second metal layer 30 is a metal film layer with a whole surface, and serves as another metal layer disposed opposite to the first metal layer 12 in the isolation structure of the capacitor isolation chip.

[0214] It should be noted that the isolation structure of the capacitor isolation chip has a basic architecture that forms capacitor isolation through two oppositely disposed metal layers and a multi-layer dielectric layer located therebetween.

[0215] The above is a detailed introduction to the isolation structure and manufacturing method of a magnetic isolation chip and a capacitive isolation chip provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

[0216] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0217] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device that includes a series of elements is inherent to the elements, or also includes elements inherent to these processes, methods, articles or devices. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0218] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An isolation structure of a magnetic isolation chip, characterized in that: The isolation structure comprises: substrate; In a first direction, a first metal layer, a first film layer, and at least one group of stacked film layers are sequentially arranged on one side of the substrate; each group of the stacked film layers includes a second film layer and a third film layer stacked in the first direction; the first direction is perpendicular to the substrate and points from the substrate to the first metal layer; Wherein, the second film layer in any of the stacked film layers is composed of a plurality of independent film layer units, and the film layer units are filled with the third film layer.

2. The isolation structure according to claim 1, characterized in that: When the stacked film layers are at least two groups, In the first direction, in two adjacent groups of the stacked film layers, the orthographic projections of any film layer unit in one group of the stacked film layers and any film layer unit in the other group of the stacked film layers on the substrate do not overlap or partially overlap.

3. The isolation structure according to claim 1, characterized in that: The thickness of the second film layer is 0.1 μm-0.3 μm.

4. The isolation structure according to claim 1, characterized in that: The first film layer and the third film layer are made of the same material, which is SiO2.

5. The isolation structure according to claim 1, characterized in that: The material of the second film layer is Al2O3, ZrO2 or SiC.

6. The isolation structure according to claim 1, characterized in that: The isolation structure also includes: A second metal layer is disposed on a side of the last group of stacked film layers away from the substrate; The first metal layer and the second metal layer are respectively composed of a plurality of independent metal units.

7. The isolation structure according to claim 6, characterized in that: The isolation structure also includes: a fourth film layer disposed on a side of the second metal layer facing away from the substrate; The first film layer, the third film layer and the fourth film layer are made of the same material.

8. The isolation structure according to claim 7, characterized in that: The first film layer fills the gaps between the multiple independent metal units in the first metal layer, and the fourth film layer fills the gaps between the multiple independent metal units in the second metal layer.

9. The isolation structure according to claim 7, characterized in that: The isolation structure also includes: a first through hole penetrating the fourth film layer, the third film layer in the stacked film layers, and the first film layer, wherein the first through hole exposes a portion of the metal unit in the first metal layer; A second through hole penetrates the fourth film layer, wherein the second through hole exposes a portion of the metal unit in the second metal layer.

10. A method for manufacturing an isolation structure of a magnetic isolation chip, characterized in that: The production method comprises: providing a substrate; In a first direction, a first metal layer, a first film layer, and at least one group of stacked film layers are sequentially formed on one side of the substrate; each group of the stacked film layers includes a second film layer and a third film layer stacked in the first direction; the first direction is perpendicular to the substrate and points from the substrate to the first metal layer; Wherein, the second film layer in any of the stacked film layers is composed of a plurality of independent film layer units, and the film layer units are filled with the third film layer.

11. The manufacturing method according to claim 10, characterized in that: When the stacked film layers are at least two groups, In the first direction, in two adjacent groups of the stacked film layers, the orthographic projections of any film layer unit in one group of the stacked film layers and any film layer unit in the other group of the stacked film layers on the substrate do not overlap or partially overlap.

12. The manufacturing method according to claim 10, characterized in that: The thickness of the second film layer is 0.1 μm-0.3 μm.

13. The manufacturing method according to claim 10, characterized in that: The first film layer and the third film layer are made of the same material, which is SiO2.

14. The manufacturing method according to claim 10, characterized in that: The material of the second film layer is Al2O3, ZrO2 or SiC.

15. The manufacturing method according to claim 10, characterized in that: The production method further comprises: forming a second metal layer on a side of the last group of stacked film layers facing away from the substrate; The first metal layer and the second metal layer are respectively composed of a plurality of independent metal units.

16. The manufacturing method according to claim 15, characterized in that: The production method further comprises: forming a fourth film layer on a side of the second metal layer facing away from the substrate; The first film layer, the third film layer and the fourth film layer are made of the same material.

17. The manufacturing method according to claim 16, characterized in that: The first film layer fills the gaps between the multiple independent metal units in the first metal layer, and the fourth film layer fills the gaps between the multiple independent metal units in the second metal layer.

18. The manufacturing method according to claim 16, characterized in that: The production method further comprises: forming a first through hole penetrating the fourth film layer, the third film layer in the stacked film layers, and the first film layer, wherein the first through hole exposes a portion of the metal unit in the first metal layer; A second through hole is formed penetrating the fourth film layer, wherein the second through hole exposes a portion of the metal unit in the second metal layer.

19. An isolation structure of a capacitor isolation chip, characterized in that: The isolation structure comprises: substrate; In a first direction, a first metal layer, a first film layer, and at least one group of stacked film layers are sequentially arranged on one side of the substrate; each group of the stacked film layers includes a second film layer and a third film layer stacked in the first direction; the first direction is perpendicular to the substrate and points from the substrate to the first metal layer; Wherein, the second film layer in any of the stacked film layers is composed of a plurality of independent film layer units, and the film layer units are filled with the third film layer.

20. The isolation structure according to claim 19, characterized in that: When the stacked film layers are at least two groups, In the first direction, in two adjacent groups of the stacked film layers, the orthographic projections of any film layer unit in one group of the stacked film layers and any film layer unit in the other group of the stacked film layers on the substrate do not overlap or partially overlap.

21. The isolation structure according to claim 19, characterized in that: The thickness of the second film layer is 0.1 μm-0.3 μm.

22. The isolation structure according to claim 19, characterized in that: The first film layer and the third film layer are made of the same material, SiO2.

23. The isolation structure according to claim 19, characterized in that: The material of the second film layer is Al2O3, ZrO2 or SiC.

24. The isolation structure according to claim 19, characterized in that: The isolation structure also includes: A fourth film layer is disposed on a side of the stacked film layer away from the substrate; The first film layer, the third film layer and the fourth film layer are made of the same material.

25. The isolation structure according to claim 24, characterized in that: The isolation structure also includes: A second metal layer disposed on a side of the fourth film layer facing away from the substrate; Wherein, the first metal layer and the second metal layer are respectively a whole-surface film layer.

26. A method for manufacturing an isolation structure of a capacitor isolation chip, characterized in that: The production method comprises: providing a substrate; In a first direction, a first metal layer, a first film layer, and at least one group of stacked film layers are sequentially formed on one side of the substrate; each group of the stacked film layers includes a second film layer and a third film layer stacked in the first direction; the first direction is perpendicular to the substrate and points from the substrate to the first metal layer; Wherein, the second film layer in any of the stacked film layers is composed of a plurality of independent film layer units, and the film layer units are filled with the third film layer.

27. The manufacturing method according to claim 26, characterized in that: When the stacked film layers are at least two groups, In the first direction, in two adjacent groups of the stacked film layers, the orthographic projections of any film layer unit in one group of the stacked film layers and any film layer unit in the other group of the stacked film layers on the substrate do not overlap or partially overlap.

28. The method according to claim 26, characterized in that: The thickness of the second film layer is 0.1 μm-0.3 μm.

29. The method according to claim 26, characterized in that: The first film layer and the third film layer are made of the same material, SiO2.

30. The method according to claim 26, characterized in that: The material of the second film layer is Al2O3, ZrO2 or SiC.

31. The method according to claim 26, characterized in that: The production method further comprises: forming a fourth film layer on a side of the stacked film layer facing away from the substrate; The first film layer, the third film layer and the fourth film layer are made of the same material.

32. The method according to claim 31, characterized in that: The production method further comprises: forming a second metal layer on a side of the fourth film layer facing away from the substrate; Wherein, the first metal layer and the second metal layer are respectively a whole-surface film layer.

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