Surface doping methods for trench sidewalls and semiconductor devices

Abstract

This application discloses a surface doping method for trench sidewalls and a semiconductor device. The doping method includes: providing a semiconductor substrate having trenches; forming a diffusion-doped region based on the trenches, wherein at least a portion of the sidewalls of the trenches have the diffusion-doped region; wherein the doping concentration of the diffusion-doped region located on the trench sidewalls remains constant along the trench depth direction. By applying the technical solution provided by this invention, a diffusion-doped region can be formed based on trenches on a semiconductor substrate, compared to conventional ion implantation methods, achieving a diffusion-doped region with a constant doping concentration along the semiconductor substrate thickness direction.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a method for surface doping of trench sidewalls and a semiconductor device. Background Technology

[0002] In the field of integrated circuits, deep trench isolation (DTI) technology can be used to isolate signal crosstalk between high-voltage devices, while optimizing the key parameters of high-voltage devices, improving breakdown voltage and reducing device size. This results in a driving circuit with lower power consumption, lower process cost, higher operating frequency and a larger safe operating area.

[0003] In existing technologies, due to the generally straight angle of deep trenches, the shadowing effect of the trench sidewalls limits the doping capabilities of traditional ion implantation methods to a very short, thin layer at the top or bottom of the trench. Appropriate doping doses cannot be applied to the upper and lower middle sections of the trench sidewalls. Furthermore, if the channel doping concentration and depth of the parasitic tubes on the trench sidewalls are insufficient, the parasitic tubes are prone to opening, leading to PN junction leakage. Summary of the Invention

[0004] In view of this, this application provides a method for doping the sidewalls of a trench and a semiconductor device, which forms a diffusion doping region based on a trench on a semiconductor substrate. Compared with the conventional ion implantation method, a diffusion doping region with a constant doping concentration can be formed along the thickness of the semiconductor substrate.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A method for surface doping of a trench sidewall, the doping method comprising:

[0007] A semiconductor substrate is provided, the semiconductor substrate having trenches;

[0008] A diffusion-doped region is formed based on the trench, and at least a portion of the sidewalls of the trench have the diffusion-doped region;

[0009] The doping concentration of the diffusion doping region located on the sidewall of the trench remains constant along the depth direction of the trench.

[0010] Preferably, in the above doping method, the trench includes N segmented regions arranged sequentially in the direction from the bottom of the trench to the opening, and the N segmented regions are sequentially the first segmented region to the Nth segmented region in the direction, where N is a positive integer;

[0011] The formation of a diffusion-doped region based on the trench includes:

[0012] A doped layer is formed on the sidewall of the i-th segment region, where i is a positive integer not greater than N;

[0013] Based on the doped layer, a diffusion-doped region is formed in the sidewall of the i-th segment region;

[0014] After the diffusion-doped region is formed, the doped layer is removed.

[0015] Preferably, in the above doping method, when N > 1 and i = N, a doped layer is formed on the sidewall of the i-th segment region, including:

[0016] A first filling structure is formed in the region from the first segment to the (N-1)th segment.

[0017] The doped layer is formed on the sidewall of the Nth segment region;

[0018] After the diffusion doping region is formed, the doped layer and the first filling structure are removed sequentially.

[0019] Preferably, in the above doping method, forming a first filling structure in the first segment region to the (N-1)th segment region includes:

[0020] A second oxide layer is formed on the sidewalls and bottom of the trench;

[0021] A dielectric material is filled into the trench where the second oxide layer is formed.

[0022] Remove the second oxide layer and the dielectric material in the Nth segment region to expose the trench sidewall of the Nth segment region.

[0023] Preferably, in the above doping method, removing the second oxide layer and the dielectric material in the Nth segment region includes:

[0024] After etching away the dielectric material in the Nth segment region, the second oxide layer on the sidewall of the Nth segment region is then etched away.

[0025] Preferably, in the above doping method, the dielectric material is polycrystalline silicon;

[0026] Etching to remove the dielectric material in the Nth segment region includes:

[0027] Based on the etch-back depth of the polysilicon, the depth of the Nth segment region in the direction is controlled to control the depth of the diffused doped region in the direction.

[0028] Preferably, in the above doping method, etching away the second oxide layer on the sidewall of the Nth segment region includes:

[0029] The second oxide layer is removed by wet etching.

[0030] Preferably, in the above doping method, when N > 1 and i = 1, forming a doped layer on the sidewall of the i-th segment region includes:

[0031] The doped layer is formed on the sidewalls and bottom of the trench;

[0032] A second filling structure is formed in the first segment region where the doped layer is formed;

[0033] Remove the doped layer from the sidewalls of the second segment region to the Nth segment region;

[0034] After the diffusion-doped region is formed, the second filling structure and the doped layer are removed sequentially.

[0035] Preferably, in the above doping method, forming a second filling structure in the first segment region of the doped layer includes:

[0036] Polysilicon is filled in the first segment region, and the depth of the first segment region is controlled based on the depth of the polysilicon filling, so as to control the depth of the diffusion-doped region in the direction.

[0037] Preferably, in the above doping method, when N is greater than 2, i is greater than 1, and less than N, a doped layer is formed on the sidewall of the i-th segment region, including:

[0038] A third filling structure is formed in the region from the first segment to the (i-1)th segment.

[0039] The doped layer is formed on the sidewall of the i-th segment region;

[0040] A fourth filling structure is formed in the i-th segment region where the doped layer is formed;

[0041] After the diffusion-doped region is formed, the fourth filling structure, the doped layer, and the third filling structure are removed sequentially.

[0042] Preferably, in the above doping method, forming a doped layer on the sidewall of the i-th segment region includes:

[0043] The doped layer is formed on the sidewalls of the i-th segment region to the N-th segment region;

[0044] The fourth filling structure is formed within the i-th segment region;

[0045] Based on the fourth filling structure, the doped layer on the sidewalls of the i-th segment region to the N-th segment region is removed.

[0046] Preferably, in the above doping method, forming the fourth filling structure in the i-th segment region includes:

[0047] Polysilicon is filled in the i-th segment region, and the depth of the i-th segment region is controlled based on the depth of the filled polysilicon, so as to control the depth of the diffusion-doped region in the direction.

[0048] Preferably, in the above doping method, when N = i = 1, forming a doped layer on the sidewall of the i-th segment region includes:

[0049] The doped layer is formed on the entire sidewall and bottom surface of the trench;

[0050] Annealing is performed based on the doped layer to form a diffused doped region throughout the sidewalls and bottom surface of the entire trench.

[0051] Preferably, in the above doping method, the doped layer is a borosilicate glass layer, and a P-type doped region is formed in the sidewall of the i-th segment region through the diffusion of boron atoms;

[0052] Alternatively, the doped layer is a phosphorus silicate glass layer, in which an N-type doped region is formed within the sidewall of the i-th segment region through the diffusion of phosphorus atoms.

[0053] The present invention also provides a semiconductor device, the semiconductor device comprising:

[0054] Semiconductor substrate;

[0055] Trenches formed in the semiconductor substrate;

[0056] The trench has at least a portion of its sidewalls having a diffusion-doped region, and the doping concentration of the diffusion-doped region located on the sidewalls of the trench remains constant along the trench depth direction.

[0057] Preferably, in the above-described semiconductor device, in the direction from the bottom of the trench to the opening, the trench includes N segmented regions arranged sequentially, the N segmented regions being the 1st segmented region to the Nth segmented region in the direction, where N is a positive integer;

[0058] The i-th segment region has a diffusion-doped region within its sidewall; wherein the diffusion-doped region is formed based on ion diffusion in the doped layer on the sidewall of the i-th segment region.

[0059] Preferably, in the above-described semiconductor device, when N > 1 and i = N, the diffusion-doped region is located within the sidewall surface of the Nth segment region and has no overlap with the 1st to N-1th segment regions and the bottom of the trench.

[0060] Preferably, in the above-described semiconductor device, when N > 1 and i = 1, the diffusion-doped region is located within the surface of the sidewall of the first segment region and the bottom of the trench, and has no overlap with the second to Nth segment regions.

[0061] Preferably, in the above-described semiconductor device, when N is greater than 2, i is greater than 1, and i is less than N, the diffusion-doped region is located within the sidewall surface of the i-th segment region and has no overlap with the sidewalls of the 1st segment region to the (i-1)th segment region and the sidewalls of the (i+1)th segment region to the Nth segment region.

[0062] Preferably, in the above-described semiconductor device, when N = i = 1, the diffusion-doped region is located within the surface of the sidewalls and bottom of the entire trench.

[0063] Preferably, in the above-described semiconductor device, in the direction perpendicular to the trench depth, the doping concentration of the diffusion doping region located on the trench sidewall gradually decreases from the trench sidewall toward the semiconductor substrate.

[0064] As described above, the surface doping method and semiconductor device for trench sidewalls provided by the present invention include: providing a semiconductor substrate having trenches; forming a diffusion-doped region based on the trenches, wherein at least a portion of the sidewalls of the trenches have the diffusion-doped region; and wherein the doping concentration of the diffusion-doped region located on the sidewalls of the trenches remains constant along the depth direction of the trenches. By applying the technical solution provided by the present invention, a diffusion-doped region is formed based on trenches on a semiconductor substrate, which, compared to conventional ion implantation methods, allows for the formation of a diffusion-doped region with a constant doping concentration along the thickness direction of the semiconductor substrate.

[0065] Furthermore, a doped layer can be formed on the trench sidewall of the i-th segment region, and a diffusion-doped region can be formed within the sidewall of the i-th segment region based on this doped layer, and finally the doped layer can be removed. Applying the technical solution of this application, doping can be performed in appropriate segmented regions of the trench sidewall, enabling in-surface doping of sidewalls at any depth of the trench to form diffusion-doped regions that are the same type or inverse type as the semiconductor substrate. The same type diffusion-doped region can reduce the electric field of the trench sidewall, reduce the on-resistance, and improve device performance; the inverse type diffusion-doped region can increase the threshold voltage of the parasitic diode, reduce PN junction leakage current, and increase the drive current of the circuit device.

[0066] In addition, this method can also be used to enrich the doping of the collector region of bipolar NPN devices, reduce the series resistance of the collector, and increase the drive current of the device.

[0067] In summary, the technical solution of this application can perform doping in appropriate segmented areas of the trench sidewall to form diffusion-doped regions that are the same type or the opposite type as the semiconductor substrate. The same type diffusion-doped region can reduce the electric field of the trench sidewall, reduce the on-resistance, and improve the device performance. The opposite type diffusion-doped region can increase the threshold voltage of the parasitic tube, reduce the leakage current of the PN junction, and increase the driving current of the circuit device.

[0068] Furthermore, the diffusion-doped region formed by the technical solution of this application differs from the doped structure formed by the traditional implantation doping method. Traditional implantation doping methods exhibit a longitudinal doping concentration gradient on the trench sidewalls (the doping concentration gradually decreases from top to bottom along the trench depth direction), while the doped structure formed by the technical solution of this application does not have a longitudinal concentration gradient. Instead, it exhibits a lateral concentration gradient only in the direction from the trench sidewalls to the active region (from the trench sidewalls along the direction perpendicular to the trench depth into the semiconductor substrate) (the concentration gradually decreases from the trench sidewalls along the direction perpendicular to the trench depth into the active region), which improves device performance to a certain extent. Attached Figure Description

[0069] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0070] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0071] Figures 1-13 A process flow diagram of a surface doping method for trench sidewalls provided in an embodiment of the present invention;

[0072] Figures 14-18 A process flow diagram of another surface doping method for trench sidewalls provided in an embodiment of the present invention;

[0073] Figures 19-26 A process flow diagram of another surface doping method for trench sidewalls provided in an embodiment of the present invention;

[0074] Figures 27-29 A process flow diagram of another surface doping method for trench sidewalls provided in an embodiment of the present invention. Detailed Implementation

[0075] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0076] Because deep trenches are generally quite straight, traditional ion implantation methods can only dope a very short, thin layer at the top or bottom of the trench due to the shadowing effect of the trench sidewalls. The upper and lower middle sections of the deep trench sidewalls cannot be doped with appropriate doses. If the channel doping concentration and depth of the parasitic tubes on the trench sidewalls are insufficient, the parasitic tubes are prone to opening, leading to PN junction leakage.

[0077] In view of this, the present invention provides a surface doping method for trench sidewalls and a semiconductor device.

[0078] The doping method includes:

[0079] A semiconductor substrate is provided, the semiconductor substrate having trenches;

[0080] A diffusion-doped region is formed based on the trench, and at least a portion of the sidewalls of the trench have the diffusion-doped region;

[0081] The doping concentration of the diffusion doping region located on the sidewall of the trench remains constant along the depth direction of the trench.

[0082] By applying the technical solution of this application, a diffusion doped region is formed based on trenches on a semiconductor substrate. Compared with the traditional ion implantation method, a diffusion doped region with a constant doping concentration can be formed along the thickness of the semiconductor substrate.

[0083] Furthermore, doping can be performed in appropriate segmented regions on the trench sidewalls to form diffusion-doped regions that are the same type or the opposite type to the semiconductor substrate. The same type diffusion-doped regions can reduce the electric field on the trench sidewalls, reduce the on-resistance, and improve device performance. The opposite type diffusion-doped regions can increase the threshold voltage of the parasitic transistor, reduce the leakage current of the PN junction, and increase the drive current of the circuit device.

[0084] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0085] refer to Figures 1-13 , Figures 1-13 This invention provides a process flow diagram of a surface doping method for trench sidewalls, the doping method comprising:

[0086] Step S11: As Figure 1 As shown, a semiconductor substrate 11 is provided, which can be a P-type substrate or an N-type substrate; the semiconductor substrate 11 has trenches 12.

[0087] Step S12: As Figures 2-13 As shown, a diffusion-doped region 20 is formed based on the trench 12, and at least a portion of the sidewalls of the trench 12 have the diffusion-doped region 20;

[0088] The doping concentration of the diffusion doping region 20 located on the sidewall of the trench 12 remains constant along the depth direction of the trench 12.

[0089] In this embodiment of the invention, in the direction from the bottom of the groove 12 to the opening, the groove 12 includes N segmented regions arranged sequentially, which are the first segmented region to the Nth segmented region in the direction, where N is a positive integer;

[0090] In step S12, the method for forming the diffusion-doped region 20 based on the trench 12 includes:

[0091] Step S21: As Figures 2-9 As shown, a doped layer 17 is formed on the sidewall of the i-th segment region, where i is a positive integer not greater than N;

[0092] Before forming the doped layer 17, the method further includes: smoothing the sidewalls and bottom of the trench 12.

[0093] In this embodiment of the invention, the method for smoothing the sidewalls and bottom of the trench 12 includes:

[0094] First, such as Figure 2 As shown, a sacrificial layer 13 is formed on the surface of the trench 12;

[0095] Then, as Figure 3 As shown, the sacrificial layer 13 is removed by etching.

[0096] The sacrificial layer 13 can be a first oxide layer, which can be a SiO2 layer. Since the sidewalls of the trench 12 are relatively rough after the etching step of the trench 12, a SiO2 layer can be grown through the furnace tube, and then the SiO2 layer can be removed by wet etching, so that the sidewalls of the trench 12 form a relatively smooth morphology.

[0097] In this embodiment of the invention, after the sidewalls and bottom of the trench 12 are leveled, a doped layer 17 can be further formed on the sidewalls of the trench 12 in the i-th segment region.

[0098] The method for forming a doped layer 17 on the sidewall of the Nth segment region when N > 1 and i = N includes:

[0099] Step S211: As Figures 4-8 As shown, a first filling structure 18 is formed in the first segment region to the (N-1)th segment region;

[0100] The method for forming the first filling structure 18 in the first segment region to the (N-1)th segment region includes:

[0101] First, such as Figure 4 and Figure 5 As shown, a second oxide layer 19 is formed on the sidewalls and bottom of the trench 12; wherein, the second oxide layer 19 includes a thermo-oxidative oxide layer 14 and a low-pressure tetraethyl orthosilicate source silicon dioxide layer 15, the low-pressure tetraethyl orthosilicate source silicon dioxide layer 15 being disposed on the side surface of the thermo-oxidative oxide layer 14 facing away from the semiconductor substrate 11.

[0102] Then, as Figure 6 As shown, a dielectric material 16 is filled in the trench 12 where the second oxide layer 19 is formed; the dielectric material 16 may be polycrystalline silicon.

[0103] Finally, as Figure 7 and Figure 8 As shown, the second oxide layer 19 and the dielectric material 16 in the Nth segment region are removed to expose the sidewall of the trench 12 in the Nth segment region; wherein, the dielectric material 16 in the Nth segment region can be removed first by etching back through polysilicon etching process, and then the thermal oxide layer 14 and the low-pressure tetraethyl orthosilicate source silicon dioxide layer 15 on the sidewall of the Nth segment region can be removed by wet etching process.

[0104] In this embodiment of the invention, the depth of the Nth segment region in the direction can be determined based on the etch-back depth of the polysilicon (dielectric material 16), thereby controlling the depth of the diffusion-doped region 20 in the direction. This allows doping to be performed in appropriate segmented regions on the trench sidewalls to form diffusion-doped regions that are the same type or the opposite type as the semiconductor substrate. The same type diffusion-doped region can reduce the electric field on the trench sidewalls, reduce the on-resistance, and improve device performance. The opposite type diffusion-doped region can increase the threshold voltage of the parasitic transistor, reduce the leakage current of the PN junction, and increase the drive current of the circuit device, thereby improving the leakage current of the PN junction and enhancing electrical isolation.

[0105] Step S212: As Figure 9 As shown, a doped layer 17 is formed on the sidewalls and bottom of the Nth segment region;

[0106] The doped layer 17 can be a borosilicate glass layer, which can form a P-type doped region in the sidewall of the Nth segment region through the diffusion of boron atoms; or, the doped layer 17 can be a phosphosilicate glass layer, which can form an N-type doped region in the sidewall of the Nth segment region through the diffusion of phosphorus atoms.

[0107] Step S22: As Figure 10 As shown, based on the doped layer 17, a diffusion-doped region 20 is formed in the sidewall of the Nth segment region; wherein, the diffusion-doped region 20 can be a P-type diffusion-doped region or an N-type diffusion-doped region.

[0108] In this embodiment of the invention, a borosilicate glass layer can be deposited on the sidewalls and bottom of the Nth segment region, and then subjected to annealing diffusion. The annealing temperature can be 850℃~1250℃, and the annealing time can be 30min~480min, which allows the P-type dopant ions (boron) in the borosilicate glass layer to diffuse into the sidewalls of the Nth segment region, forming a P-type diffusion doped region; or, a phosphosilicate glass layer can be deposited on the sidewalls and bottom of the Nth segment region, and then subjected to annealing diffusion, which allows the N-type dopant ions (phosphorus) in the phosphosilicate glass layer to diffuse into the sidewalls of the Nth segment region, forming an N-type diffusion doped region.

[0109] Step S23: As Figure 11 As shown, after the diffusion-doped region 20 is formed, the doped layer 17 is removed. In this embodiment of the invention, the doped layer 17 can be removed by a wet etching process.

[0110] Furthermore, after forming the diffusion-doped region 20, the first filling structure 18 in the first segment region to the (N-1)th segment region is removed.

[0111] First, such as Figure 12 As shown, remove the medium material 16 from the trench, and then as follows: Figure 13 As shown, the second oxide layer 19 on the sidewalls of the first segment region to the (N-1)th segment region is removed. If the dielectric material 16 can be polysilicon, a single polysilicon etch-back process can be used to simultaneously etch and remove the polysilicon in the trench, and then another etching process can be used to simultaneously remove the second oxide layer 19 on the trench sidewalls.

[0112] Therefore, Figures 1-13In the illustrated configuration, a doped layer 17 is formed on the sidewall of the trench 12 in the Nth segment region, and a diffusion-doped region 20 is formed within the sidewall of the Nth segment region based on this doped layer 17. This achieves doping (i.e., top doping) within the Nth segment region of the trench 12 sidewall to form a diffusion-doped region that is either the same type or the opposite type as the semiconductor substrate. The same type diffusion-doped region can reduce the electric field on the trench sidewall, reduce on-resistance, and improve device performance; the opposite type diffusion-doped region can increase the threshold voltage of the parasitic diode, reduce PN junction leakage current, and increase the drive current of the circuit device.

[0113] Based on the above embodiments, another embodiment of the present invention also provides another surface doping method for trench sidewalls, such as... Figures 1-3 and Figures 14-18 As shown, Figures 14-18 This is a process flow diagram of another surface doping method for trench sidewalls provided in an embodiment of the present invention. The doping method includes:

[0114] Step S31: As Figure 1 As shown, a semiconductor substrate 11 is provided, which can be a P-type substrate or an N-type substrate; the surface of the semiconductor substrate 11 has a trench 12; the trench 12 includes N segmented regions arranged sequentially in the direction of the bottom of the trench 12 pointing towards the opening, the N segmented regions being the first segmented region to the Nth segmented region in the direction, where N is a positive integer greater than 1;

[0115] Step S32: As Figures 14-16 As shown, a doped layer 17 is formed on the sidewall of the i-th segment region, where i is a positive integer not greater than N;

[0116] Before forming the doped layer 17, the method further includes: smoothing the sidewalls and bottom of the trench 12.

[0117] In this embodiment of the invention, the method for smoothing the sidewalls and bottom of the trench 12 includes:

[0118] First, such as Figure 2 As shown, a sacrificial layer 13 is formed on the surface of the trench 12;

[0119] Then, as Figure 3 As shown, the sacrificial layer 13 is removed by etching.

[0120] The sacrificial layer 13 can be a first oxide layer, which can be a SiO2 layer. Since the sidewalls of the trench 12 are relatively rough after the etching step of the trench 12, a SiO2 layer can be grown through the furnace tube, and then the SiO2 layer can be removed by wet etching, so that the sidewalls of the trench 12 form a relatively smooth morphology.

[0121] In this embodiment of the invention, after the sidewalls and bottom of the trench 12 are leveled, a doped layer 17 can be further formed on the sidewalls of the trench 12 in the i-th segment region.

[0122] The method for forming a doped layer 17 on the sidewall of the first segment region when N > 1 and i = 1 includes:

[0123] Step S321: As Figure 14 As shown, the doped layer 17 is formed on the sidewalls and bottom of the trench 12;

[0124] The doped layer 17 can be a borosilicate glass layer, which can form a P-type doped region in the sidewall of the first segment region through the diffusion of boron atoms; or, the doped layer 17 can be a phosphosilicate glass layer, which can form an N-type doped region in the sidewall of the first segment region through the diffusion of phosphorus atoms.

[0125] Step S322: As Figure 15 As shown, a second filling structure 30 is formed in the first segment region of the doped layer 17; the second filling structure 30 can be polycrystalline silicon.

[0126] The method for forming the second filling structure 30 in the first segment region of the doped layer 17 includes: filling the first segment region with polysilicon, and controlling the depth of the first segment region based on the depth of the filled polysilicon to control the depth of the diffused doped region 20 in the direction. Specifically, the trench can be filled with polysilicon first, and then etched back through the polysilicon to retain the polysilicon in the first segment region.

[0127] Step S323: As Figure 16 As shown, the doped layer 17 on the sidewalls of the second to Nth segment regions is removed; the doped layer 17 can be removed by a wet etching process.

[0128] Step S324: As Figure 17 As shown, based on the doped layer 17, a diffusion doped region 20 is formed in the sidewall and bottom of the first segment region; wherein, the diffusion doped region 20 can be a P-type diffusion doped region or an N-type diffusion doped region.

[0129] In this embodiment of the invention, a borosilicate glass layer can be deposited on the sidewalls and bottom of the first segment region, and then annealed and diffused to allow P-type dopant ions (boron) in the borosilicate glass layer to diffuse into the sidewalls and bottom of the first segment region, forming a P-type diffusion doped region; or, a phosphosilicate glass layer can be deposited on the sidewalls and bottom of the first segment region, and then annealed and diffused to allow N-type dopant ions (phosphorus) in the phosphosilicate glass layer to diffuse into the sidewalls and bottom of the first segment region, forming an N-type diffusion doped region.

[0130] Step S325: As Figure 18 As shown, after the diffusion doping region 20 is formed, the second filling structure 30 and the doped layer 17 in the first segment region are removed.

[0131] In this embodiment of the invention, the second filling medium 30 in the first segment region can be removed first by etching back polysilicon using a polysilicon etching process; then the doped layer 17 can be removed by a wet etching process.

[0132] Therefore, in this method, a doped layer 17 is formed on the sidewall of the trench 12 in the first segment region, and a diffusion-doped region 20 is formed within the sidewall of the first segment region based on the doped layer 17. This achieves doping (i.e., bottom doping) in the first segment region of the trench 12 sidewall to form a diffusion-doped region that is the same type or the opposite type as the semiconductor substrate. The same type diffusion-doped region can reduce the electric field of the trench sidewall, reduce the on-resistance, and improve device performance; the opposite type diffusion-doped region can increase the threshold voltage of the parasitic diode, reduce the leakage current of the PN junction, and increase the drive current of the circuit device.

[0133] Based on the above embodiments, another embodiment of the present invention provides yet another method for surface doping of trench sidewalls, such as... Figures 1-6 and Figures 19-26 As shown, Figures 19-26 This is a process flow diagram of another surface doping method for trench sidewalls provided in an embodiment of the present invention. The doping method includes:

[0134] Step S41: As Figure 1 As shown, a semiconductor substrate 11 is provided, which can be a P-type substrate or an N-type substrate; the surface of the semiconductor substrate 11 has a trench 12; the trench 12 includes N segmented regions arranged sequentially in the direction of the bottom of the trench 12 pointing towards the opening, the N segmented regions being the first segmented region to the Nth segmented region in the direction, where N is a positive integer greater than 1;

[0135] Step S42: As Figures 2-6 and Figures 19-23 As shown, a doped layer 17 is formed on the sidewall of the i-th segment region, where i is a positive integer not greater than N;

[0136] Before forming the doped layer 17, the method further includes: smoothing the sidewalls and bottom of the trench 12.

[0137] In this embodiment of the invention, the method for smoothing the sidewalls and bottom of the trench 12 includes:

[0138] First, such as Figure 2 As shown, a sacrificial layer 13 is formed on the surface of the trench 12;

[0139] Then, as Figure 3 As shown, the sacrificial layer 13 is removed by etching.

[0140] The sacrificial layer 13 can be a first oxide layer, which can be a SiO2 layer. Since the sidewalls of the trench 12 are relatively rough after the etching step of the trench 12, a SiO2 layer can be grown through the furnace tube, and then the SiO2 layer can be removed by wet etching, so that the sidewalls of the trench 12 form a relatively smooth morphology.

[0141] In this embodiment of the invention, after the sidewalls and bottom of the trench 12 are leveled, a doped layer 17 can be further formed on the sidewalls of the trench 12 in the i-th segment region.

[0142] The method for forming a doped layer 17 on the sidewall of the i-th segment region when N is greater than 2, i is greater than 1, and less than N includes:

[0143] Step S421: As Figures 4-6 and Figure 21 , Figure 22 As shown, a third filling structure 18 is formed in the region from the first segment to the (i-1)th segment;

[0144] The method for forming the third filling structure 18 in the region from the first segment to the (i-1)th segment includes:

[0145] First, such as Figure 4 and Figure 5 As shown, a second oxide layer 19 is formed on the sidewalls and bottom of the trench 12; wherein, the second oxide layer 19 includes a thermo-oxidative oxide layer 14 and a low-pressure tetraethyl orthosilicate source silicon dioxide layer 15, the low-pressure tetraethyl orthosilicate source silicon dioxide layer 15 being disposed on the side surface of the thermo-oxidative oxide layer 14 facing away from the semiconductor substrate 11.

[0146] Then, as Figure 6 As shown, a dielectric material 16 is filled in the trench 12 where the second oxide layer 19 is formed; the dielectric material 16 may be polycrystalline silicon.

[0147] Finally, as Figure 19 and Figure 20 As shown, the second oxide layer 19 and the dielectric material 16 in the i-th segment region to the N-th segment region are removed to expose the sidewalls of the trench 12 in the i-th segment region to the N-th segment region; wherein, the dielectric material 16 in the N-th segment region to the i-th segment region can be removed first by etching back through polysilicon etching process, and then the thermal oxide layer 14 and the low-pressure tetraethyl orthosilicate source silicon dioxide layer 15 on the sidewalls of the N-th segment region to the i-th segment region can be removed by wet etching process.

[0148] In this embodiment of the invention, the depth of the i-th segment region in the direction can be determined based on the etch-back depth of the polysilicon, thereby controlling the depth of the diffusion-doped region 20 in the direction. This allows doping to be performed in appropriate segmented regions on the trench sidewall to form diffusion-doped regions that are the same type or the opposite type as the semiconductor substrate. The same type diffusion-doped region can reduce the electric field on the trench sidewall, reduce the on-resistance, and improve device performance. The opposite type diffusion-doped region can increase the threshold voltage of the parasitic transistor, reduce the leakage current of the PN junction, and increase the drive current of the circuit device.

[0149] Step S422: As Figure 21 As shown, the doped layer 17 is formed on the sidewalls and bottom of the i-th segment region to the N-th segment region;

[0150] The doped layer 17 can be a borosilicate glass layer, which can form a P-type doped region in the sidewall of the i-th segment region through the diffusion of boron atoms; or, the doped layer 17 can be a phosphosilicate glass layer, which can form an N-type doped region in the sidewall of the i-th segment region through the diffusion of phosphorus atoms.

[0151] Step S423: As Figure 22 As shown, a fourth filling structure 21 is formed in the i-th segment region where the doped layer 17 is formed; the fourth filling structure 21 shown can be polycrystalline silicon.

[0152] The method for forming the fourth filling structure 21 in the i-th segment region where the doped layer 17 is formed includes: filling the i-th segment region with polysilicon, and controlling the depth of the i-th segment region based on the depth of the filled polysilicon to control the depth of the diffused doped region 20 in the direction. Specifically, the i-th to N-th segment regions can be filled with polysilicon first, and then the polysilicon in the (i+1)-th segment region and the N-th segment region can be removed by polysilicon etch-back, leaving the polysilicon in the i-th segment region.

[0153] Step S424: As Figure 23 As shown, based on the fourth filling structure 21, the doped layer 17 on the sidewalls of the (i+1)th segment region to the Nth segment region is removed; wherein, the doped layer 17 can be removed by wet etching.

[0154] Step S43: As Figure 24 As shown, based on the doped layer 17, a diffusion-doped region 20 is formed in the sidewall of the i-th segment region; wherein, the diffusion-doped region 20 can be a P-type diffusion-doped region or an N-type diffusion-doped region.

[0155] In this embodiment of the invention, a borosilicate glass layer can be deposited on the sidewall of the i-th segment region, and then annealed and diffused to allow P-type dopant ions (boron) in the borosilicate glass layer to diffuse into the sidewall of the i-th segment region, forming a P-type diffusion-doped region; or, a phosphosilicate glass layer can be deposited on the sidewall of the i-th segment region, and then annealed and diffused to allow N-type dopant ions (phosphorus) in the phosphosilicate glass layer to diffuse into the sidewall of the i-th segment region, forming an N-type diffusion-doped region.

[0156] Step S44: As Figure 25 As shown, after the diffusion doping region 20 is formed, the fourth filling structure 21 and the doped layer 17 in the i-th segment region are removed.

[0157] The fourth filling structure 21 in the i-th segment region can be removed first by etching back polysilicon; then the doped layer 17 can be removed by wet etching.

[0158] Step S45: As Figure 26 As shown, after forming the diffusion-doped region 20, the third filling structure 18 in the (i-1)th segment region to the first segment region is removed. Specifically, the dielectric material 16 in the (i-1)th segment region to the first segment region can be removed first by polysilicon etch-back process, and then the thermal oxide layer 14 and the low-voltage tetraethyl orthosilicate source silicon dioxide layer 15 can be removed by wet etching process.

[0159] Therefore, in this method, a doped layer 17 is formed on the sidewall of the trench 12 in the i-th segment region, and a diffusion-doped region 20 is formed within the sidewall of the i-th segment region based on the doped layer 17. This achieves doping (i.e., central doping) within the i-th segment region of the trench 12 sidewall to form a diffusion-doped region that is the same type or the opposite type as the semiconductor substrate. The same type diffusion-doped region can reduce the electric field of the trench sidewall, reduce the on-resistance, and improve device performance; the opposite type diffusion-doped region can increase the threshold voltage of the parasitic diode, reduce the leakage current of the PN junction, and increase the drive current of the circuit device.

[0160] Based on the above embodiments, another embodiment of this application provides yet another surface doping method for trench sidewalls, in which N = i = 1, and can be as follows: Figures 1-3 As shown, a desired semiconductor substrate 11 is provided, and the sidewalls and bottom of the trench 12 in the semiconductor substrate 11 are planarized. At this time, a doped layer is formed on the sidewall of the i-th segment region, including:

[0161] First, such as Figure 27 As shown, the doped layer 17 is formed on the entire sidewalls and bottom surface of the trench 12;

[0162] Then, as Figure 28As shown, annealing is performed based on the doped layer 17 to form a diffusion doped region 20 in the entire sidewall and bottom surface of the trench 12.

[0163] Finally, as Figure 29 As shown, the doped layer 17 is removed.

[0164] In this embodiment, a diffusion-doped region 20 can be formed on the surface of the sidewalls and bottom of the entire trench 12 to form a diffusion-doped region that is the same type or the opposite type as the semiconductor substrate. The same type diffusion-doped region can reduce the electric field of the trench sidewall, reduce the on-resistance, and improve the device performance. The opposite type diffusion-doped region can increase the threshold voltage of the parasitic tube, reduce the leakage current of the PN junction, and increase the drive current of the circuit device.

[0165] Based on the above embodiments, another embodiment of the present invention also provides a semiconductor device, such as... Figure 13 or Figure 18 or Figure 26 or Figure 29 As shown, the semiconductor device includes:

[0166] Semiconductor substrate 11;

[0167] The trench 12 is disposed in the semiconductor substrate 11;

[0168] The trench 12 has at least a portion of its sidewalls having a diffusion doping region 20, and the doping concentration of the diffusion doping region 20 located on the sidewalls of the trench 12 remains constant along the depth direction of the trench 12.

[0169] In this embodiment of the invention, in the direction from the bottom of the groove 12 to the opening, the groove 12 includes N segmented regions arranged sequentially, which are the first segmented region to the Nth segmented region in the direction, where N is a positive integer;

[0170] The i-th segment region has a diffusion-doped region 20 within its sidewall; wherein the diffusion-doped region 20 is formed based on ion diffusion in the doped layer 17 on the sidewall of the i-th segment region.

[0171] As described in the above embodiments, in the semiconductor device described in the embodiments of this application,

[0172] When N > 1 and i = N, the diffusion doping region 20 is located inside the sidewall surface of the Nth segment region and has no overlap with the 1st segment region to the (N-1)th segment region and the bottom of the trench;

[0173] When N > 1 and i = 1, the diffusion doping region 20 is located within the surface of the sidewall of the first segment region and the bottom of the trench, and has no overlap with the second to Nth segment regions;

[0174] When N is greater than 2, i is greater than 1, and i is less than N, the diffusion doping region 20 is located inside the sidewall surface of the i-th segment region, and has no overlap with the sidewalls of the 1st segment region to the (i-1)th segment region, and the sidewalls of the (i+1)th segment region to the Nth segment region.

[0175] When N = i = 1, the diffusion doping region 20 is located within the surface of the sidewalls and bottom of the entire trench 12.

[0176] Based on the diffusion mechanism, in the direction perpendicular to the depth of the trench 12, the doping concentration of the diffusion-doped region 20 located on the sidewall of the trench 12 gradually decreases from the sidewall of the trench 12 towards the semiconductor substrate 11; the doping concentration of the diffusion-doped region 20 remains constant along the depth direction of the trench 12. In the prior art, doping is generally formed by ion implantation and annealing. Since the trench depth is generally tens of micrometers, the doping concentration can only be higher in the region above the trench sidewall (close to the surface of the semiconductor substrate), and the doping concentration decreases closer to the bottom of the trench. However, by adopting the technical solution of this application, the doping concentration within the surface of the trench sidewall does not have a longitudinal concentration gradient distribution, but only a lateral concentration gradient distribution.

[0177] As described above, the semiconductor device provided by the present invention includes a semiconductor substrate and trenches disposed in the semiconductor substrate. At least a portion of the sidewalls of the trenches have diffusion-doped regions, and the doping concentration of the diffusion-doped regions located on the trench sidewalls remains constant along the trench depth direction. By applying the technical solution of this application, diffusion-doped regions are formed based on trenches on the semiconductor substrate. Compared to conventional ion implantation methods, this method can form diffusion-doped regions with a constant doping concentration along the thickness direction of the semiconductor substrate.

[0178] Furthermore, by applying the technical solution of this application, doping can be performed in appropriate segmented regions on the trench sidewall to form diffusion-doped regions that are the same type or the opposite type as the semiconductor substrate. The same type diffusion-doped region can reduce the electric field on the trench sidewall, reduce the on-resistance, and improve the device performance. The opposite type diffusion-doped region can increase the threshold voltage of the parasitic tube, reduce the leakage current of the PN junction, and increase the driving current of the circuit device.

[0179] In addition, this method can also be used to enrich the doping of the collector region of the NPN bipolar device, reduce the collector series resistance, and increase the device drive current.

[0180] In summary, the technical solution of this application can perform doping in appropriate segmented areas of the trench sidewall to form diffusion-doped regions that are the same type or the opposite type as the semiconductor substrate. The same type diffusion-doped region can reduce the electric field of the trench sidewall, reduce the on-resistance, and improve the device performance. The opposite type diffusion-doped region can increase the threshold voltage of the parasitic tube, reduce the leakage current of the PN junction, and increase the driving current of the circuit device.

[0181] Furthermore, the diffusion-doped region formed by the technical solution of this application differs from the doped structure formed by the traditional implantation doping method. Traditional implantation doping methods exhibit a longitudinal doping concentration gradient on the trench sidewalls (the doping concentration gradually decreases from top to bottom along the trench depth direction), while the doped structure formed by the technical solution of this application does not have a longitudinal concentration gradient. Instead, it exhibits a lateral concentration gradient only in the direction from the trench sidewalls to the active region (from the trench sidewalls along the direction perpendicular to the trench depth into the semiconductor substrate) (the concentration gradually decreases from the trench sidewalls along the direction perpendicular to the trench depth into the active region), which improves device performance to a certain extent.

[0182] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. For the semiconductor devices disclosed in the embodiments, since they correspond to the doping methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the doping method section.

[0183] It should be noted that, in the description of this application, the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.

[0184] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0185] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of surface doping of a trench sidewall, characterized by, The doping method comprises: providing a semiconductor substrate having a trench therein; forming a diffusion doping region based on the trench, at least part of the sidewall of the trench having the diffusion doping region; wherein the doping concentration of the diffusion doping region located at the sidewall of the trench remains unchanged along the depth direction of the trench; in the direction from the bottom of the trench to the opening, the trench comprises N segment regions arranged in sequence, the N segment regions being the 1st segment region to the Nth segment region in sequence in the direction, N being a positive integer; forming a diffusion doping region based on the trench, comprising: forming a doping layer on the sidewall of the ith segment region, i being a positive integer not greater than N; forming a diffusion doping region in the sidewall of the ith segment region based on the doping layer; after forming the diffusion doping region, removing the doping layer; when N is greater than 2, i is greater than 1 and less than N, forming a doping layer on the sidewall of the ith segment region, comprising: forming a third filling structure in the 1st segment region to the (i-1)th segment region; forming the doping layer on the sidewall of the ith segment region; forming a fourth filling structure in the ith segment region in which the doping layer is formed; wherein, after forming the diffusion doping region, the fourth filling structure, the doping layer and the third filling structure are sequentially removed.

2. The method of claim 1, wherein, forming a doping layer on the sidewall of the ith segment region, comprising: forming the doping layer on the sidewall of the 1st segment region to the Nth segment region; forming the fourth filling structure in the ith segment region; based on the fourth filling structure, removing the doping layer on the sidewall of the (i+1)th segment region to the Nth segment region.

3. The doping method according to claim 2, characterized in that, forming the fourth filling structure in the ith segment region, comprising: filling polysilicon in the ith segment region, and based on the depth of the filled polysilicon, controlling the depth of the ith segment region to control the depth of the diffusion doping region in the direction.

4. The doping method according to any one of claims 1 to 3, characterized in that, the doping layer is a borosilicate glass layer, and a P-type doping region is formed in the sidewall of the ith segment region by diffusion of boron atoms; or, the doping layer is a phosphosilicate glass layer, and an N-type doping region is formed in the sidewall of the ith segment region by diffusion of phosphorus atoms.

5. A semiconductor device, characterized by, The semiconductor device comprises: a semiconductor substrate; a trench provided in the semiconductor substrate; wherein at least part of the sidewall of the trench has a diffusion doping region, and the doping concentration of the diffusion doping region located at the sidewall of the trench remains unchanged along the depth direction of the trench; in the direction from the bottom of the trench to the opening, the trench comprises N segment regions arranged in sequence, the N segment regions being the 1st segment region to the Nth segment region in sequence in the direction, N being a positive integer; the sidewall of the ith segment region has a diffusion doping region; wherein the diffusion doping region is formed based on ion diffusion in a doping layer on the sidewall of the ith segment region. When N is greater than 2, i is greater than 1 and i is less than N, the diffusion doped region is located in the sidewall surface of the ith segment region and has no overlapping part with the sidewalls of the 1st segment region to the (i-1)th segment region and the (i+1)th segment region to the Nth segment region; forming a doped layer on the sidewall of the ith segment region comprises: forming a third filling structure in the 1st segment region to the (i-1)th segment region; forming the doped layer on the sidewall of the ith segment region; forming a fourth filling structure in the ith segment region where the doped layer is formed; wherein, after the diffusion doped region is formed, the fourth filling structure, the doped layer and the third filling structure are sequentially removed.

6. The semiconductor device according to claim 5, wherein In a direction perpendicular to the depth direction of the trench, the doping concentration of the diffusion doped region located on the sidewall of the trench gradually decreases from the sidewall of the trench into the semiconductor substrate.

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