semiconductor packaging

Abstract

A semiconductor package includes: a semiconductor chip having first and second contact pads alternately arranged in a first direction; an insulating film having first openings defining first pad regions of the first contact pads, and second openings defining second pad regions of the second contact pads; first and second conductive capping layers on the first and second pad regions, respectively; and an insulating layer on the insulating film, having first and second contact holes connected to the first and second conductive capping layers, respectively. Each of the first and second pad regions includes a bonding region having a first width and a detection region having a second width greater than the first width, and each of the second pad regions is arranged in a direction opposite to each of the plurality of first pad regions.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2020-0112245 filed on September 3, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor chip and a semiconductor package including the semiconductor chip. Background Art

[0004] As demands for high performance, high speed, and / or multifunctionality of semiconductor devices increase, the integration of semiconductor devices also increases. When manufacturing semiconductor chips corresponding to the trend of highly integrated semiconductor devices, contact pads may be implemented with fine widths or fine pitches.

[0005] When such contact pads are assembled in a semiconductor package on which a semiconductor chip is mounted, they can be electrically connected to external terminals provided in the semiconductor package. Before being assembled into a semiconductor package, a probe can be used to apply an electrical signal to the contact pads to test whether they are operating normally. Summary of the Invention

[0006] An aspect of the present inventive concept is to provide a semiconductor package that improves the problem of reliability degradation due to thermal shock.

[0007] According to one aspect of the present invention, a semiconductor package includes: a semiconductor chip having an active surface with a plurality of first contact pads and a plurality of second contact pads alternately arranged in a first direction; an insulating film on the active surface of the semiconductor chip, the insulating film having a plurality of first openings defining first pad regions of the plurality of first contact pads and a plurality of second openings defining second pad regions of the plurality of second contact pads; a plurality of first conductive cap layers and a plurality of second conductive cap layers, the plurality of first conductive cap layers and the plurality of second conductive cap layers being on the first pad regions and the second pad regions, respectively, each having an extension extending on the insulating film; an insulating layer on the insulating film, the insulating layer having extensions connected to the plurality of first conductive cap layers and the plurality of second conductive cap layers, respectively. a plurality of first contact holes and a plurality of second contact holes of a second conductive cover layer; and a redistribution layer, on the insulating layer, and connected to the plurality of first conductive cover layers and the plurality of second conductive cover layers through the plurality of first contact holes and the plurality of second contact holes, respectively, wherein each of the first pad area and the second pad area includes a bonding area having a first width and a detection area having a second width greater than the first width, and each of the first pad areas is arranged in the order of the bonding area and the detection area in a second direction intersecting with the first direction, and each of the second pad areas is arranged in the order of the bonding area and the detection area in a direction opposite to the second direction.

[0008] According to one aspect of the present invention, a semiconductor package includes: a semiconductor chip having an active surface; and a redistribution structure on the active surface of the semiconductor chip, wherein the semiconductor chip includes: a plurality of first contact pads and a plurality of second contact pads alternately arranged in a first direction on the active surface; an insulating film on the active surface of the semiconductor chip and having a plurality of first openings defining first pad areas of the plurality of first contact pads and a plurality of second openings defining second pad areas of the plurality of second contact pads; and a plurality of first conductive cap layers and a plurality of second conductive cap layers on the first pad areas and the second pad areas, respectively, each of the first conductive cap layers and the second conductive cap layers having an extension extending on the insulating film, wherein the redistribution structure includes: an insulating layer on the insulating film and a redistribution layer on the insulating layer, wherein the insulating layer includes a plurality of first contact holes and a plurality of second contact holes respectively connected to the plurality of first conductive cover layers and the plurality of second conductive cover layers, wherein the redistribution layer is connected to the plurality of first conductive cover layers and the plurality of second conductive cover layers through the plurality of first contact holes and the plurality of second contact holes, respectively, wherein each of the first pad area and the second pad area includes a bonding area having a first width and a detection area having a second width greater than the first width, wherein each of the first pad areas is arranged in the order of the bonding area and the detection area in a second direction intersecting the first direction, and wherein each of the second pad areas is arranged in the order of the bonding area and the detection area in a direction opposite to the second direction.

[0009] According to one aspect of the present inventive concept, a semiconductor package includes: a semiconductor chip having an active surface with a plurality of first contact pads and a plurality of second contact pads alternately arranged in a first direction; an insulating film on the active surface of the semiconductor chip and having a plurality of first openings and a plurality of second openings having shapes corresponding to the plurality of first contact pads and the plurality of second contact pads, respectively; a plurality of first conductive cap layers and a plurality of second conductive cap layers on the plurality of first contact pads and the plurality of second contact pads, respectively, each of the plurality of first conductive cap layers and the plurality of second conductive cap layers having an extension extending on the insulating film; an insulating layer on the insulating film and having a plurality of first and second conductive cap layers connected to the plurality of first and second contact pads, respectively. a plurality of first conductive cover layers and a plurality of first contact holes and a plurality of second contact holes of the plurality of second conductive cover layers; and a redistribution layer, on the insulating layer, and connected to the plurality of first conductive cover layers and the plurality of second conductive cover layers through the plurality of first contact holes and the plurality of second contact holes, respectively, wherein each of the plurality of first contact pads and the plurality of second contact pads includes a bonding area having a first width and a detection area having a second width greater than the first width, and each of the plurality of first contact pads and the plurality of second contact pads is arranged so that the bonding area of ​​the first contact pad is adjacent to the detection area of ​​the second contact pad, and the bonding area of ​​the second contact pad is adjacent to the detection area of ​​the first contact pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and effects of the present inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a schematic cross-sectional view illustrating a semiconductor package according to an example embodiment of the inventive concept;

[0012] Figure 2A and Figure 2B are taken along lines I1-I1′ and I2-I2′ respectively. Figure 1 a plan view of a semiconductor package;

[0013] Figure 3 It shows Figure 1 a bottom view of a semiconductor package;

[0014] Figure 4A yes Figure 3 an enlarged view of a portion A of a semiconductor package (before a redistribution structure is applied), and Figure 4B It is along Figure 4A a cross-sectional view taken along line II-II′ of an enlarged portion of FIG.

[0015] Figure 5A yes Figure 3An enlarged view of a portion A of a semiconductor package (after applying a redistribution structure), and Figure 5B It is along Figure 5A a cross-sectional view taken along line II-II′ of an enlarged portion of FIG.

[0016] Figure 6 is a plan view illustrating an array of conductive capping layers used in example embodiments according to the present inventive concepts;

[0017] Figure 7A 、 Figure 8A 、 Figure 9A and Figure 10A is a plan view illustrating a process of manufacturing an interconnection structure of a semiconductor chip according to an example embodiment of the inventive concept, and Figure 7B 、 Figure 8B 、 Figure 9B and Figure 10B are along Figure 7A 、 Figure 8A 、 Figure 9A and Figure 10A a cross-sectional view taken along line II-II′ of the plan view;

[0018] 11A to 11D is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an example embodiment of the inventive concept;

[0019] Figure 12A and Figure 12B They are shown respectively Figure 11D Plan and cross-sectional views of the results of the process;

[0020] Figure 13A and Figure 13B are respectively a schematic plan view and a cross-sectional view illustrating a semiconductor chip that may be used in a semiconductor package according to example embodiments of the inventive concepts;

[0021] Figure 14A and Figure 14B are a schematic plan view and a cross-sectional view, respectively, illustrating a semiconductor chip that may be used in a semiconductor package according to example embodiments of the inventive concepts; and

[0022] Figure 15 is a schematic cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0023] Hereinafter, example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0024] Figure 1 is a schematic cross-sectional view illustrating a semiconductor package 100 according to an example embodiment of the inventive concept, Figure 2A and Figure 2Bare taken along line I1-11′ and line I2-I2′ respectively Figure 1 A plan view of the semiconductor package 100, and Figure 3 It shows Figure 1 FIG. 1 is a bottom view of the semiconductor package 100 .

[0025] refer to Figure 1 、 Figure 2A and Figure 2B The semiconductor package 100 according to the present example embodiment includes: a support frame 110 having a first surface 110A and a second surface 110B arranged opposite to each other and having a cavity 110H; a semiconductor chip 120 arranged in the cavity 110H and having an active surface 121A on which a plurality of contact pads 122 are arranged; a redistribution structure 140 arranged on the first surface 110A of the support frame 110 and the active surface 121A of the semiconductor chip 120; and a sealant 130 for sealing the semiconductor chip 120 arranged in the cavity 110H. Figure 2A and Figure 2B The illustrated redistribution structure 140 may have an area larger than that of the semiconductor chip 120 .

[0026] The semiconductor chip 120 may be manufactured from a semiconductor wafer. For example, the semiconductor chip 120 may include a semiconductor substrate 121 (e.g., silicon (Si), germanium (Ge), and gallium arsenide (GaAs)). The semiconductor chip 120 may be an integrated circuit IC having a plurality of (e.g., tens to thousands) contact pads 122. For example, the semiconductor chip 120 may include a microprocessor (e.g., a central processing unit (CPU), a graphics processing unit, and / or an application processor (AP)), a logic chip (e.g., a field programmable gate array (FPGA) and an application-specific IC (ASIC)), or a memory chip (e.g., a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), and / or a flash memory).

[0027] The plurality of contact pads 122 may be arranged in various shapes (eg, number, size, and / or pitch) on the active surface of the semiconductor chip 120. For example, the contact pads 122 may be arranged in one or more rows along the four corners of the active surface, as shown in FIG. Figure 2B Example embodiments thereof are not limited thereto, and in some example embodiments, the contact pads 122 may be arranged over the entire area including the central region of the active surface.

[0028] The semiconductor chip 120 has an interconnection structure for connecting the redistribution layer 145 of the redistribution structure 140 and the plurality of contact pads 122. Figure 1As shown, this interconnect structure may include: a passivation structure (eg, an insulating protection film 123 and an insulating film 124); and a plurality of conductive cap layers 125, each connected to a plurality of contact pads 122. Figure 4A and Figure 4B The interconnection structure of the semiconductor chip 120 used in the present exemplary embodiment on the contact pads 122 arranged at a fine pitch is described in detail.

[0029] Figure 4A It shows Figure 3 An enlarged view of a portion A of the semiconductor package 100 (with the redistribution structure omitted), and Figure 4B It is along Figure 4A A cross-sectional view taken along line II-II′ of an enlarged portion of FIG.

[0030] refer to Figure 4A and Figure 4B According to this example embodiment, the semiconductor chip 120 may include: a semiconductor substrate 121; a first contact pad 122A and a second contact pad 122B, arranged on an active surface 121A of the semiconductor substrate 121; and an insulating protection film 123 and an insulating film 124, sequentially disposed on the active surface 121A. It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, the elements should not be limited by these terms; rather, these terms are merely used to distinguish one element from another. Therefore, the first element discussed may be referred to as the second element without departing from the scope of the present inventive concept.

[0031] like Figure 2B As shown, a plurality of first contact pads 122A and a plurality of second contact pads 122B may be provided and may be alternately arranged in a first direction (eg, D1). For example, each of the first contact pads 122A and the second contact pads 122B may have the same square shape. Figure 4A As shown, each of the first and second contact pads 122A and 122B may have a rectangular shape extending in a second direction (eg, D2) intersecting the first direction (eg, D1).

[0032] For example, the first contact pad 122A and the second contact pad 122B may include a metal, such as aluminum (Al). The insulating protective film 123 may be provided on the semiconductor substrate 121 and may include, for example, at least one material selected from oxides, nitrides, and oxynitrides. In a specific example, the insulating protective film 123 may be SiO2 / SiN. The insulating film 124 may include an organic material, and may specifically be a photosensitive organic material. For example, the insulating film 124 may include photosensitive polyimide (PSPI).

[0033] In this example embodiment, insulating protection film 123 and insulating film 124 may have first and second openings Oa and Ob that may define a first pad region Pa and a second pad region Pb of first and second contact pads 122A and 122B, respectively.

[0034] Each of the first pad area Pa and the second pad area Pb may include: a bonding area Pa1 and a bonding area Pb1 having a first width W1, and a detection area Pa2 and a detection area Pb2 having a second width W2 wider than the first width W1. In other words, the first pad area Pa and the second pad area Pb may each have a hammer shape, and it can be understood that the detection area Pa2 and the detection area Pb2 may have a larger area corresponding to the head area of ​​the hammer shape.

[0035] The adjacent first pad area Pa and second pad area Pb may be arranged in reverse. Specifically, the first pad area Pa may be arranged in the order of the bonding area Pa1 and the detection area Pa2 in a second direction (e.g., D2) intersecting the first direction (e.g., D1), and the second pad area Pb may be arranged in the order of the bonding area Pb1 and the detection area Pb2 in a direction (e.g., -D2) opposite to the second direction (e.g., D2). For example, in some embodiments, the bonding area Pa1 of the first pad area Pa may be adjacent to the detection area Pb2 of the second pad area Pb (e.g., in the first direction D1), and the detection area Pa2 of the first pad area Pa may be adjacent to the bonding area Pb1 of the second pad area Pb (e.g., in the first direction D1).

[0036] As mentioned above, Figure 2B The plurality of contact pads 122 shown may have a rectangular shape and may be Figure 4A As shown, the adjacent first opening Oa and second opening Ob may be hammer-shaped and may be arranged inversely. In addition, in this embodiment, the first opening Oa and second opening Ob may be arranged so that the bonding area Pa1 and bonding area Pb1 from the adjacent first pad area Pa and second pad area Pb and the detection area Pb2 and detection area Pa2 face each other in the first direction (e.g., D1).

[0037] Each of the first contact pad 122A and the second contact pad 122B may have a detection trace PM provided in the detection area Pa2 and the detection area Pb2. By introducing the detection area Pa2 and the detection area Pb2 having a larger width W2, the probe can stably contact the contact pad 122. Here, the detection trace PM may be a recessed trace generated in the process of contacting the contact pad 122A and the contact pad 122B using a probe for conducting a test. For example, the probe may include a high-hardness metal (e.g., tungsten W), and because the front end is the end, the trace of the probe may be (e.g., in this article, for example, for Figure 9A and Figure 9B The probe inspection process discussed herein) is formed in the surface of contact pad 122A and contact pad 122B.

[0038] The first conductive capping layer 125A and the second conductive capping layer 125B may be disposed on the first pad region Pa and the second pad region Pb, respectively. Each of the first conductive capping layer 125A and the second conductive capping layer 125B may include: a first region 125A_1 and a first region 125B_1 having a third width Wa wider than the first width W1; and a second region 125A_2 and a second region 125B_2 having a fourth width Wb wider than the third width Wa. Similar to the shape and arrangement of the first pad region Pa and the second pad region Pb, the first conductive capping layer 125A and the second conductive capping layer 125B may have a hammer shape arranged in reverse. The first conductive capping layer 125A may be disposed in the order of the first region 125A_1 and the second region 125A_2 in a second direction (e.g., D2), and the second conductive capping layer 125B may be disposed in the order of the first region 125B_1 and the second region 125B_2 in a direction (-D2) opposite to the second direction (e.g., D2). For example, in some embodiments, the first region 125A_1 of the first conductive cap layer 125A may be adjacent to the second region 125B_2 of the second conductive cap layer 125B (e.g., in the first direction D1), and the second region 125A_2 of the first conductive cap layer 125A may be adjacent to the first region 125B_1 of the second conductive cap layer 125B (e.g., in the first direction D1).

[0039] The first conductive cover layer 125A and the second conductive cover layer 125B may be closely arranged. Figure 4A As shown, the second regions 125A_2 and the second region 125B_2 of the adjacent first and second conductive capping layers 125A and 125B may have portions overlapping each other in the second direction D2.

[0040] Each of the first conductive cap layer 125A and the second conductive cap layer 125B may have an extension extending on the insulating film. The length of the extension may be in the range of 5 μm to 30 μm in the first direction (e.g., D1). The lengths of the portions extending from the first region 125A_1 and the first region 125B_1 and the second region 125A_2 and the second region 125B_2 may be substantially the same. For example, the third width Wa of the first region 125A_1 and the first region 125B_1 may be approximately 5 μm to 30 μm wider than the first width W1 of the bonding region Pa1 and the bonding region Pb1. Similarly, the fourth width Wb of the second region 125A_2 and the second region 125B_2 may be approximately 5 μm to 30 μm wider than the second width W2 of the detection region Pa2 and the detection region Pb2.

[0041] Such an extension portion can compensate for errors caused by misalignment of the photoresist patterns of the first and second conductive capping layers 125A and 125B with the first and second openings Oa and Ob (see, for example, Figure 13A and Figure 13B In some embodiments, the widths of the extensions of the first conductive capping layer 125A and the second conductive capping layer 125B may be in the range of 3 μm to 20 μm, respectively.

[0042] The insulating protection film 123 and the insulating film 124 and the first and second conductive capping layers 125 may be provided in a wafer-level process for manufacturing the semiconductor chip 120 (see, for example, FIG. Figures 6 to 10B ), which can then be segmented at the chip level.

[0043] like Figure 1 and Figure 3 As shown, the conductive cap layer 125 can be connected to the redistribution layer 145 (particularly the redistribution via 143) of the redistribution structure 140. The redistribution structure 140 can redistribute the contact pads 122 of the semiconductor chip 120. The redistribution structure 140 can be formed at the packaging level after being divided into semiconductor chips (for example, see FIG. 12A to FIG. 12B ).

[0044] Figure 5A yes Figure 3 An enlarged view of a portion A of the semiconductor package 100 (after applying the redistribution structure), and Figure 5B It is along Figure 5A A cross-sectional view taken along line II-II′ of an enlarged portion of FIG.

[0045] The redistribution structure 140 includes an insulating layer 141 disposed on the insulating film 124 so as to overlie and / or cover the first and second conductive capping layers 125A and 125B; and a redistribution layer 145 disposed on the insulating layer 141. The insulating layer 141 includes first and second contact holes CHa and CHb connected to the first and second conductive capping layers 125A and 125B, respectively. The redistribution layer 145 may include a redistribution pattern 142 disposed on the insulating layer 141; and redistribution vias 143 connected to the first and second conductive capping layers 125A and 125B through the first and second contact holes CHa and CHb, respectively. The redistribution pattern 142 may include a redistribution line 142L.

[0046] The first contact hole CHa and the second contact hole CHb may be respectively disposed in the first region 125A_1 of the first conductive cap layer 125A and the first region 125B_1 of the second conductive cap layer 125B. The region disposed on the probe trace PM in the first conductive cap layer 125A and the second conductive cap layer 125B may have a non-flat surface. Because the redistribution path 143 is formed in the first region 125A_1 and the first region 125B_1 where the probe trace PM does not exist, contact failure due to the probe trace PM can be prevented. In some example embodiments, the first contact hole CHa and the second contact hole CHb may be respectively disposed in a region overlapping with the bonding region Pa1 in the first conductive cap layer 125A and the bonding region Pb1 in the second conductive cap layer 125B. The redistribution path 143 can be stably formed in a flat region.

[0047] The redistribution structure 140 may be formed using a photolithography process. For example, the insulating layer 141 may include a photoimageable dielectric (PID) material. The redistribution layer 145 may be formed by an electroplating process using a seed layer. In this case, the redistribution pattern 142 may have a finer pattern (e.g., a smaller thickness and / or line width) than other patterns using a printed circuit board process (e.g., the first to third conductor patterns 112a, 112b, and 112c further described herein). For example, the redistribution layer 145 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0048] As described above, the contact pads 122 of the semiconductor chip 120 can be redistributed through the redistribution layer 145 of the redistribution structure 140 and can be electrically connected to an external device (e.g., a motherboard) through the electrical connection structure 190. The redistribution layer 145 of the redistribution structure 140 can be connected not only to the first conductive capping layer 125A and the second conductive capping layer 125B of the semiconductor chip 120, but also to the conductive line structure (e.g., the first conductive line pattern 112a) of the support frame 110.

[0049] In this embodiment, the support frame 110 may be a structure for maintaining the rigidity of the semiconductor package 100 . The support frame 110 includes a conductive line structure connecting the first surface 110A and the second surface 110B, and may be electrically connected to the semiconductor chip 120 through the redistribution layer 145 .

[0050] Go back for reference Figures 1 to 3The conductive structure of the support frame 110 may include a plurality of conductive patterns 112a, 112b, and 112c and a plurality of conductive paths 113a and 113b. For example, the conductive structure of the support frame 110 may include: a first insulating layer 111a; a first conductive pattern 112a connected to the redistribution layer 145 of the redistribution structure 140 and within the first insulating layer 111a; a second conductive pattern 112b disposed on a side of the first insulating layer 111a opposite to the first conductive pattern 112a (e.g., at least a portion of the first insulating layer 111a is between the first conductive pattern 112a and the second conductive pattern 112b); a second insulating layer 111b disposed on the first insulating layer 111a and on / covering the second conductive pattern 112b; and a third conductive pattern 112c disposed on the second insulating layer 111b. The first conductive path 113a may pass through the first insulating layer 111a to electrically connect to the first conductive pattern 112a and the second conductive pattern 112b. The second conductive wire via 113 b may pass through the second insulating layer 111 b to be electrically connected to the second conductive wire pattern 112 b and the third conductive wire pattern 112 c .

[0051] In this embodiment, the first conductive pattern 112a can be recessed into the first insulating layer 111a. Due to this recessing step, the process of forming the sealant 130 (see FIG. 1 ) can be prevented and / or reduced. Figure 11B ) contamination of the first conductor pattern 112a caused by the resin used to form the sealant 130.

[0052] For the first insulating layer 111a and the second insulating layer 111b, an insulating resin mixed with a reinforcing material such as an inorganic filler (e.g., silica, alumina) or glass fiber can be used. For example, the first insulating layer 111a and the second insulating layer 111b may include Ajinomoto buildup film (ABF), FR-4, bismaleimide triazine (BT), or prepreg. The wire structure may include, for example, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0053] In some embodiments, the semiconductor package 100 may be implemented as a package-on-package (POP) using such a wire structure. The support frame 110 may include a cavity 110H for accommodating the semiconductor chip 120 .

[0054] The sealant 130 may protect the semiconductor chip 120. The sealant 130 may be on and / or cover the second surface 110B of the support frame 110 and the inactive surface 121B of the semiconductor chip 120, and may fill at least a portion of the sidewalls of the cavity 110H and the side surfaces of the semiconductor chip 120. For example, the sealant 130 may include a resin, such as ABF or epoxy molding compound (EMC).

[0055] A passivation layer 160 may be provided as a component for protecting the redistribution structure 140 from external physical and chemical damage. For example, the passivation layer 160 may include a photosensitive insulating material, such as a photosensitive insulating resin, ABF, or a solder resist. The passivation layer 160 has a plurality of openings that expose a portion of the redistribution layer 145. An under-bump metallization (UBM) layer 180 may be provided in the openings of the passivation layer 160 and may be connected to the redistribution layer 145, and an electrical connection structure 190 may be formed on the UBM layer 180 and may be connected to an external circuit (e.g., a motherboard), etc. The electrical connection structure 190 is used as a connection terminal for physically and / or electrically connecting the semiconductor package 100 from the outside. The electrical connection structure 190 may include a conductive material such as a low-melting-point alloy (e.g., Sn-Al-Cu).

[0056] like Figures 1 to 3 As shown, the redistribution structure 140 may have an area larger than that of the semiconductor chip 120. The redistribution structure 140 may have a fan-out region that does not overlap with the semiconductor chip 120, and at least one electrical connection structure 190 may be disposed in the fan-out region.

[0057] Figure 6 is a plan view illustrating an array of conductive capping layers used in example embodiments according to the inventive concepts.

[0058] refer to Figure 6 , Figure 5A The illustrated example combination of the first conductive capping layer 125A and the second conductive capping layer 125B is arranged in an alternating pattern. Figure 6 The legend can be understood as Figure 4A A portion of an array of first and second conductive capping layers 125A and 125B is shown.

[0059] As described above, the insulating film 124 is provided on the first contact pad 125A and the second contact pad 125B, and the first pad region Pa and the second pad region Pb have a hammer shape that can be provided through the first opening Oa and the second opening Ob of the insulating film 124. The first pad region Pa and the second pad region Pb can be arranged so that the adjacent pad regions are arranged opposite to each other. Similarly, the first conductive cap layer 125A and the second conductive cap layer 125B can be similarly provided in a hammer shape arranged opposite to each other.

[0060] The position of the redistribution path 143 connected to the first and second conductive cap layers 125A and 125B through the first and second contact holes CHa and CHb can be formed in an area overlapping with the bonding area Pa1 and the bonding area Pb1 except for the probe area Pa2 and the probe area Pb2. Therefore, a contact failure of the redistribution path 143 caused by the probe mark PM can be prevented.

[0061] As described above, when viewed in the direction (eg, D1) in which the first and second contact pads 122A and 122B are arranged, the redistribution vias 143 may be arranged in a zigzag pattern Z1. Similarly, the probing traces PM may be arranged in a zigzag pattern Z2.

[0062] Figure 7A 、 Figure 8A 、 Figure 9A and Figure 10A is a plan view illustrating a process of manufacturing a bonding structure of a semiconductor chip according to an example embodiment of the inventive concept, and Figure 7B 、 Figure 8B 、 Figure 9B and Figure 10B are along Figure 7A 、 Figure 8A 、 Figure 9A and Figure 10A A cross-sectional view taken along line II-II′ of the plan view.

[0063] First, refer to Figure 7A and Figure 7B , an insulating protection film 123 and an insulating film 124 may be sequentially formed on the active surface 121A of the semiconductor substrate 121 .

[0064] The first contact pad 122A and the second contact pad 122B may be disposed on the active surface and as shown in FIG. Figure 2B As shown, the plurality of first contact pads 122A and the plurality of second contact pads 122B may be alternately arranged accordingly. Figure 7AAs shown, the first contact pad 122A and the second contact pad 122B may have the same rectangular shape, and may have, for example, a rectangular shape extending in a direction intersecting the arrangement direction. For example, the first contact pad 122A and the second contact pad 122B may include metal (e.g., aluminum Al).

[0065] The insulating protective film 123 may be disposed on the semiconductor substrate 121 and may include, for example, at least one material selected from oxides, nitrides, and oxynitrides. In a specific example, the insulating protective film 123 may include SiO2 / SiN. The insulating film 124 may include an organic material, and may specifically be a photosensitive organic material. For example, the insulating film 124 may include PSPI.

[0066] Then, refer to Figure 8A and Figure 8B , first and second openings Oa and Ob that expose some areas of the first and second contact pads 122A and 122B may be formed on the insulating protection film 123 and the insulating film 124 .

[0067] The first pad area Pa and the second pad area Pb may be defined by the first opening Oa and the second opening Ob, respectively. Each of the first pad area Pa and the first pad area Pb may include a bonding area Pa1 and a bonding area Pb1 having a first width W1, and a detection area Pa2 and a detection area Pb2 having a second width W2 wider than the first width W1 (see, for example, Figure 4A ). The adjacent first pad area Pa and the second pad area Pb can be arranged opposite to each other. In this embodiment, the first opening Oa and the second opening Ob can be arranged so that the bonding area Pa1 and the bonding area Pb1 in the adjacent first pad area Pa and the second pad area Pb and the detection area Pb2 and the detection area Pa2 face each other. As described above, in the adjacent first pad area Pa and the second pad area Pb, the detection area Pa2 and the detection area Pb2 have large areas that can be arranged in a staggered manner, thereby ensuring that the detection area has a sufficient area in a limited area.

[0068] In this exemplary embodiment, a form is shown in which openings of the same size are continuously formed in the insulating protection film 123 and the insulating film 124, but after forming the insulating protection film 123, openings corresponding to the first opening Oa and the second opening Ob may be formed, and after forming the insulating film 124, openings may be formed in the insulating film 124 that overlap with the openings in the insulating protection film 123. In this case, the sizes of the openings of the insulating protection film 123 and the insulating film 124 may be different from each other.

[0069] Next, refer to Figure 9A and Figure 9B, a probing test may be performed on the probing region Pa2 and the probing region Pb2 of each of the first pad region Pa and the second pad region Pb.

[0070] During the probing test process, a probing mark PM may be formed in the probing area Pa2 and the probing area Pb2 in each of the first and second contact pads 122A and 122B by the probe needle PR. Figure 9B As shown, the detection trace PM can be provided in the recessed structure of the first contact pad 122A and the second contact pad 122B. The detection trace PM of the first contact pad 122A and the second contact pad 122B can be arranged not side by side in the direction in which the first contact pad 122A and the second contact pad 122B are arranged, but can be arranged alternately along the detection area Pa2 and the detection area Pb2.

[0071] Then, refer to Figure 10A and Figure 10B , a first conductive capping layer 125A and a second conductive capping layer 125B may be formed on the first pad region Pa and the second pad region Pb, respectively.

[0072] The first conductive capping layer 125A and the second conductive capping layer 125B may have shapes corresponding to the first pad area Pa and the second pad area Pb, respectively. Similar to the shapes and arrangements of the first pad area Pa and the second pad area Pb, the first conductive capping layer 125A and the second conductive capping layer 125B may have hammer shapes arranged in reverse. Specifically, each of the first conductive capping layer 125A and the second conductive capping layer 125B may include: a first region 125A_1 and a first region 125B_1 having a third width greater than the first width; and a second region 125A_2 and a second region 125B_2 having a fourth width wider than the third width (see, for example, FIG. 1 ). Figure 4A ).like Figure 10A As shown, the second regions 125A_2 and the second region 125B_2 of the adjacent first and second conductive capping layers 125A and 125B may have portions overlapping each other in the second direction (eg, D2).

[0073] The first and second conductive capping layers 125A and 125B may have portions extending on the insulating film 124. Such extensions may compensate for errors caused by misalignment of the photoresist patterns of the first and second conductive capping layers 125A and 125B with the first and second openings Oa and Ob.

[0074] 11A to 11D 1 is a cross-sectional view showing each main process of a method of manufacturing a semiconductor package according to an example embodiment of the inventive concept. 11A to 11D As shown, the process of forming the redistribution structure 140 may be performed at a packaging level after being separated into semiconductor chips.

[0075] refer to Figure 11A , the support frame 110 having the cavity 110H is attached to the first adhesive film 200 , and the semiconductor chip 120 is disposed in the cavity 110H of the support frame 110 .

[0076] A support frame 110 is provided having a first surface 110A and a second surface 110B disposed opposite to each other and having a cavity 110H passing through the first surface 110A and the second surface 110B. Specifically, the support frame 110 can be provided by the following process: preparing a carrier film (not shown) on which a metal film is formed, and using the metal film as a seed layer to form a first conductor pattern 112a; forming a first insulating layer 111a covering the first conductor pattern 112a on the metal film; forming a second conductor pattern 112b and / or a first conductor path 113a on and / or in the first insulating layer 111a; forming a second insulating layer 111b covering the second conductor pattern 112b on the first insulating layer 111a; and forming a third conductor pattern 112c and / or a second conductor path 113b on and / or in the second insulating layer 111b. Then, after separating the support frame 110 from the carrier film, the desired support frame 110 can be obtained by removing the metal film remaining on the first conductor pattern 112a. When the metal film is removed, a recessed portion can be formed in the support frame 110. The first to third conductor patterns 112a, 112b, and 112c can be formed by patterning using a dry film or the like and then filling the pattern using a known electroplating process. The first insulating layer 111a and the second insulating layer 111b can be formed using a known lamination method or a spin coating and curing method. The formation of the cavity 110H can be performed using laser drilling and / or mechanical drilling and / or sandblasting.

[0077] The first adhesive film 200 can fix the support frame 110. For example, the first adhesive film 200 can include a thermosetting adhesive tape or a UV-curable adhesive tape. The semiconductor chip 120 is attached to the first adhesive film 200 in the cavity 110H. The semiconductor chip 120 is placed face down so that the active surface on which the contact pads 122 are provided is attached to the first adhesive film 200. Figure 10A and Figure 10B As described above, the semiconductor chip 120 may include: a conductive capping layer 125 connected to the pad region of the contact pad 122; and an insulating protection film 123 and an insulating film 124 sequentially disposed on the active surface.

[0078] Then, refer to Figure 11B , the semiconductor chip 120 is sealed using a sealant 130 .

[0079] The sealant 130 is configured to seal the semiconductor chip 120 disposed in the cavity 110H. In the present embodiment, the sealant 130 may be on the second surface 110B of the support frame 110 and the passive surface of the semiconductor chip 120 and / or cover the second surface 110B of the support frame 110 and the passive surface of the semiconductor chip 120, and may fill at least a portion of the space in the cavity 110H. The sealant 130 may be formed by known methods. For example, the sealant 130 may be formed by laminating and then curing a precursor. Alternatively, the sealant 130 may also be formed by applying a liquid resin for the sealant 130 on the first adhesive film 200 to seal the semiconductor chip 120 and then curing it.

[0080] Next, refer to Figure 11C , the semiconductor chip 120 and the support frame 110 are disposed on the second adhesive film 300 , and the first adhesive film 200 is removed to expose the active surface of the semiconductor chip 120 .

[0081] The second adhesive film 300 may include a material similar to that of the first adhesive film 200. The first adhesive film 200 may be peeled off after the adhesive strength is weakened by heat treatment or ultraviolet irradiation depending on the type. The first conductive capping layer 125A and the second conductive capping layer 125B connected to the first pad area Pa and the second pad area Pb, respectively, of the conductive capping layer 125 may be exposed (see FIG. Figure 4A ).

[0082] Then, refer to Figure 11D , a redistribution structure 140 may be formed on the first surface 110A of the support frame 110 from which the first adhesive film 200 is removed and the active surface of the semiconductor chip 120 .

[0083] The process of forming the redistribution structure 140 according to this embodiment can be performed by a photolithography process and an electroplating process. For example, the insulating layer 141 may include a PID material. Figure 5A 、 Figure 5B 、 Figure 12A and Figure 12B As shown, an insulating layer 141 can be formed on the first surface 110A of the support frame 110 and the active surface of the semiconductor chip 120, and a first contact hole CHa and a second contact hole CHb connected to the first conductive cap layer 125A and the second conductive cap layer 125B, respectively, are formed in the insulating layer 141 using a photolithography process. Then, a redistribution layer 145 can be formed on the insulating layer 141 in an electroplating process. The redistribution layer 145 may include: a redistribution pattern 142 provided on the insulating layer 141; and a redistribution path 143, connected to the first conductive cap layer 125A and the second conductive cap layer 125B, respectively, through the first contact hole CHa and the second contact hole CHb (see Figure 5AAs described above, since the first and second contact holes CHa and CHb are provided in the first and second regions 125A_1 and 125B_1, the redistribution via 143 may be formed in the first and second regions 125A_1 and 125B_1 where the probe mark PM does not exist.

[0084] In addition, references to e.g. Figures 1 to 3 , a passivation layer 160 may be formed on the redistribution structure 140, and a UBM layer 180 and an electrical connection structure 190 connected to the redistribution layer 145 may be formed. The passivation layer 160 may be formed by laminating a precursor before curing, or by applying a liquid resin before curing. An opening is formed in the passivation layer 160 to expose a portion of the redistribution layer 145 of the redistribution structure 140. A UBM layer 180 is formed on the exposed area of ​​the redistribution layer 145 by a known metallization method, and an electrical connection structure 190 is formed on the UBM layer 180. The above process is performed in units of large panels, and after the above process is completed, the structure may be separated into individual semiconductor packages using a sawing process.

[0085] Figure 13A and Figure 13B are a schematic plan view and a cross-sectional view, respectively, illustrating a semiconductor chip 120A that may be used in a semiconductor package according to example embodiments of the inventive concepts.

[0086] Apart from Figure 13A and Figure 13B The semiconductor chip 120A shown does not align the first conductive cap layer 125A′ and the second conductive cap layer 125B′ with the first opening Oa and the second opening Ob. Figures 1 to 6 Therefore, unless otherwise indicated, Figure 1 and Figure 6 The description of the illustrated embodiment can be combined with the description of the present embodiment.

[0087] In this embodiment, unlike the previous embodiment, the first conductive capping layer 125A′ and the second conductive capping layer 125B′ may not be accurately aligned on the first pad area Pa and the second pad area Pb exposed to the first opening Oa and the second opening Ob, and may be misaligned in one direction. The photoresist patterns of the first conductive capping layer 125A′ and the second conductive capping layer 125B′ can be understood as having an error due to misalignment with the first opening Oa and the second opening Ob.

[0088] Therefore, the extensions used in this embodiment may include: first and second extensions on both sides of each of the first and second conductive capping layers 125A′ and 125B′ along a direction (e.g., D1) in which the first and second contact pads 122A and 122B are arranged, and the width Wc of the first extension may be different from the width Wc′ of the second extension. As described above, the extensions of the first and second conductive capping layers 125A′ and 125B′ can compensate for errors caused by misalignment, thereby preventing the first and second openings Oa and Ob from being exposed even when misalignment occurs.

[0089] Figure 14A and Figure 14B are a schematic plan view and a cross-sectional view, respectively, illustrating a semiconductor chip 120B that may be used in a semiconductor package according to example embodiments of the inventive concepts. Figure 14B It is along Figure 14A A cross-sectional view taken along line II-II′.

[0090] It can be understood that, in addition to the first contact pad 122A′ and the second contact pad 122B′ themselves having a hammer shape arranged in reverse, Figure 14A and Figure 14B The semiconductor chip 120B shown has Figures 1 to 6 Therefore, unless otherwise indicated, Figure 1 and Figure 6 The description of the illustrated exemplary embodiment may be combined with the description of the present exemplary embodiment.

[0091] The semiconductor chip 120B according to the present exemplary embodiment includes a first contact pad 122A′ and a second contact pad 122B′ having a hammer shape arranged inversely. Unlike the previous exemplary embodiments, the hammer shape is not limited to the shapes of the first opening Oa and the second opening Ob, but the first contact pad 122A′ and the second contact pad 122B′ themselves can be defined as having a hammer shape.

[0092] Each of the first contact pad 122A′ and the second contact pad 122B′ includes: a bonding area 122A′_1 and a bonding area 122B′_1 having a first width; and, a detection area 122A′_2 and a detection area 122B′_2 having a second width wider than the first width, and the first contact pad 122A′ can be arranged in the order of the bonding area and the detection area in a second direction (e.g., D2) intersecting the first direction (e.g., D1), and the second contact pad 122B′ can be arranged in the order of the bonding area and the detection area in a direction opposite to the second direction (e.g., -D2).

[0093] The first opening Oa' and the second opening Ob' formed in the insulating protection film 123 and the insulating film 124 may have shapes corresponding to the shapes of the first contact pad 122A' and the second contact pad 122B', respectively. The first opening Oa' and the second opening Ob' may also have hammer shapes similar to the hammer shapes of the first contact pad 122A' and the second contact pad 122B'. The detection areas 122A'_2 and the detection areas 122B'_2 of the adjacent first contact pad 122A' and the second contact pad 122B' may have portions that overlap with each other in the second direction (e.g., D2).

[0094] Each of the first and second conductive capping layers 125A and 125B includes a first region 125A_1 and a first region 125B_1 having a third width wider than the first width, and a second region 125A_2 and a second region 125B_2 having a fourth width wider than the third width. The second regions 125A_2 and the second regions 125B_2 of the adjacent first and second conductive capping layers 125A and 125B may also overlap in the second direction. Similar to the previous example embodiments, contact holes CHa and CHb for forming redistribution paths may be provided in the first region 125A_1 of the first and second conductive capping layers 125A and 125B.

[0095] Figure 15 is a schematic cross-sectional view illustrating a semiconductor package 100A according to an example embodiment of the inventive concepts.

[0096] refer to Figure 15 It can be understood that, in addition to having a vertical interconnection portion 110' instead of having a frame including a wire structure ( Figure 1 110 in the embodiment), and in addition to adding a redistribution layer 155 to the sealant 130, the semiconductor package 100A according to this example embodiment has Figures 1 to 3 Therefore, unless otherwise indicated, Figures 1 to 3 The description of the illustrated embodiment may be combined with the description of this exemplary embodiment.

[0097] Unlike the previous example embodiments, the semiconductor package 100A according to the present example embodiment may be a wafer-level package. The semiconductor package 100A may include a conductive pillar 110' connecting the second redistribution layer 155 and the first redistribution layer 145 of the redistribution structure 140. A vertical connecting conductor (e.g., a conductive pillar 110') may be provided to pass through the sealant 130 that seals the semiconductor chip 120 to electrically connect the first redistribution layer 145 and the second redistribution layer 155. In the present example embodiment, the conductive pillar 110' is shown as being directly connected through the redistribution path 143 and the redistribution path 153, but is not limited thereto, and in other example embodiments may be directly connected through the redistribution pattern 142 and the redistribution pattern 152.

[0098] The semiconductor package 100A may further include an additional redistribution layer 155 (also referred to as a "back-side redistribution layer") disposed on the sealant 130 and electrically connected to the conductive pillars 110'. The redistribution layer 155 may include a redistribution path 153 connected to the conductive pillars 110' and a redistribution pattern 152. In a portion of the redistribution pattern 152, a second passivation layer 160B may be provided as a pad region. The second passivation layer 160B may include a material similar to that of the first passivation layer 160A. The semiconductor package 100A may be provided in a lower package structure of a package-on-package (POP) system.

[0099] As described above, according to example embodiments, even when the pitch of contact pads of a semiconductor chip is fine, a method of stably forming a contact hole for a redistribution via while sufficiently ensuring a probe area may be provided.

[0100] Various features, aspects, and effects of the present inventive concept may not be limited to the above description and may be more easily understood in the course of describing specific embodiments of the present inventive concept.

[0101] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor package comprising: a semiconductor chip including an active surface having a plurality of first contact pads and a plurality of second contact pads arranged alternately in a first direction; an insulating film on the active surface of the semiconductor chip and including a plurality of first openings respectively defining first pad regions of the plurality of first contact pads and a plurality of second openings respectively defining second pad regions of the plurality of second contact pads; a plurality of first conductive cover layers and a plurality of second conductive cover layers, respectively on the first pad region and the second pad region, each of the plurality of first conductive cover layers and the plurality of second conductive cover layers comprising an extension portion extending on the insulating film; an insulating layer on the insulating film and including a plurality of first contact holes and a plurality of second contact holes connected to the plurality of first conductive cap layers and the plurality of second conductive cap layers, respectively; as well as a redistribution layer on the insulating layer and connected to the plurality of first conductive cap layers and the plurality of second conductive cap layers through the plurality of first contact holes and the plurality of second contact holes, respectively; wherein each of the first pad region and the second pad region comprises a bonding region having a first width and a detection region having a second width greater than the first width, and wherein each of the first pad areas is arranged in the order of the bonding area and the detection area in a second direction intersecting the first direction, and Each of the second pad regions is arranged in the order of the bonding region and the detection region in a direction opposite to the second direction.

2. The semiconductor package according to claim 1, wherein Each of the plurality of first contact pads and the plurality of second contact pads includes the same square shape in a plan view.

3. The semiconductor package according to claim 2, wherein Each of the plurality of first contact pads and the plurality of second contact pads includes a rectangular shape extending in the second direction.

4. The semiconductor package according to claim 1, wherein The first pad area and the second pad area are arranged such that the bonding area and the detection area of ​​two adjacent first pad areas and second pad areas face each other in the first direction.

5. The semiconductor package according to claim 1, wherein Each of the plurality of first contact pads and the plurality of second contact pads includes a recessed probing trace in the probing region. The semiconductor package according to claim 1 , wherein: Each of the plurality of first contact holes and the plurality of second contact holes overlaps the bonding region of one of the first pad region or the second pad region.

7. The semiconductor package according to claim 1, wherein Each of the plurality of first conductive capping layers and the plurality of second conductive capping layers includes a first region having a third width greater than the first width and a second region having a fourth width greater than the third width, Each of the plurality of first conductive capping layers and the plurality of second conductive capping layers is arranged such that a first region of a first conductive capping layer is adjacent to a second region of a second conductive capping layer and vice versa.

8. The semiconductor package according to claim 7, wherein Second regions of adjacent first and second conductive capping layers among the plurality of first and second conductive capping layers include portions overlapping each other in the second direction.

9. The semiconductor package according to claim 1, wherein The extension portion has a first extension portion and a second extension portion on both sides of each of the plurality of first conductive cover layers and the plurality of second conductive cover layers along the first direction, and Wherein, the width of the first extension portion is different from the width of the second extension portion.

10. The semiconductor package according to claim 1, further comprising: An insulating protection film is provided between the active surface of the semiconductor chip and the insulating film.

11. The semiconductor package according to claim 1 , further comprising: an additional insulating layer on the redistribution layer, and an additional redistribution layer connected to the redistribution layer through the additional insulating layer.

12. A semiconductor package comprising: Semiconductor chips, including active surfaces; as well as a redistribution structure on the active surface of the semiconductor chip, The semiconductor chip includes: a plurality of first contact pads and a plurality of second contact pads, which are alternately arranged in a first direction on the active surface; an insulating film on the active surface of the semiconductor chip, and including a plurality of first openings defining first pad regions of the plurality of first contact pads and a plurality of second openings defining second pad regions of the plurality of second contact pads; and a plurality of first conductive cap layers and a plurality of second conductive cap layers, respectively on the first pad regions and the second pad regions, each of the first conductive cap layers and the second conductive cap layers including an extension extending on the insulating film. The redistribution structure includes an insulating layer on the insulating film and a redistribution layer on the insulating layer. wherein the insulating layer comprises a plurality of first contact holes and a plurality of second contact holes respectively connected to the plurality of first conductive cover layers and the plurality of second conductive cover layers; The redistribution layer is connected to the first conductive cover layers and the second conductive cover layers through the first contact holes and the second contact holes, respectively. Each of the first pad area and the second pad area includes a bonding area having a first width and a detection area having a second width greater than the first width. wherein each of the first pad areas is arranged in the order of the bonding area and the detection area in a second direction intersecting the first direction, and Each of the second pad regions is arranged in the second direction in the order of the detection region and the bonding region.

13. The semiconductor package according to claim 12, wherein The redistribution structure has an area larger than an area of ​​the semiconductor chip.

14. The semiconductor package according to claim 13, further comprising: An encapsulant is on the redistribution structure and on the semiconductor chip.

15. The semiconductor package according to claim 13, further comprising: A support frame is on the redistribution structure and surrounds the semiconductor chip.

16. The semiconductor package according to claim 15, wherein The support frame has a first surface in contact with the redistribution structure and a second surface opposite to the first surface. The support frame further includes a conductive line structure connected to the redistribution layer and passing through the first surface and the second surface.

17. The semiconductor package according to claim 13, further comprising: a sealant on the redistribution structure and on the semiconductor chip; as well as A conductive pillar is connected to the redistribution layer and passes through the sealant.

18. A semiconductor package comprising: a semiconductor chip including an active surface having a plurality of first contact pads and a plurality of second contact pads arranged alternately in a first direction; an insulating film on the active surface of the semiconductor chip and including a plurality of first openings and a plurality of second openings having shapes corresponding to the plurality of first contact pads and the plurality of second contact pads, respectively; a plurality of first conductive capping layers and a plurality of second conductive capping layers, respectively on the plurality of first contact pads and the plurality of second contact pads, each of the plurality of first conductive capping layers and the plurality of second conductive capping layers including a portion extending on the insulating film; an insulating layer on the insulating film and including a plurality of first contact holes and a plurality of second contact holes connected to the plurality of first conductive cap layers and the plurality of second conductive cap layers, respectively; as well as a redistribution layer on the insulating layer and connected to the plurality of first conductive cap layers and the plurality of second conductive cap layers through the plurality of first contact holes and the plurality of second contact holes, respectively; wherein each of the plurality of first contact pads and the plurality of second contact pads comprises a bonding region having a first width and a detection region having a second width greater than the first width, Each of the plurality of first contact pads and the plurality of second contact pads is arranged such that a bonding area of ​​a first contact pad is adjacent to a detection area of ​​a second contact pad and a bonding area of ​​the second contact pad is adjacent to the detection area of ​​the first contact pad.

19. The semiconductor package according to claim 18, wherein Probe regions of adjacent first and second contact pads among the plurality of first contact pads and the plurality of second contact pads overlap with each other in the second direction.

20. The semiconductor package according to claim 19, wherein Each of the plurality of first conductive cover layers and the plurality of second conductive cover layers includes a first region having a third width greater than the first width and a second region having a fourth width greater than the third width, and the head. Wherein, adjacent first conductive capping layers and second conductive capping layers among the plurality of first conductive capping layers and the plurality of second conductive capping layers include second regions having overlapping portions in the second direction.

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