Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The preparation method comprises the following steps: providing a substrate; forming a stack structure on the substrate, the stack structure comprising a plurality of stack pairs, wherein the stack structure comprises a first array region, a second array region, and a first connection region arranged between the first array region and the second array region, the first connection region comprising a plurality of sub-connection regions arranged in sequence in a first direction; etching the stack structure on the plurality of sub-connection regions to form a plurality of initial step blocks, each initial step block comprising a first initial part and a second initial part, the first initial part and the second initial part having a height difference; and etching the plurality of initial step blocks to form a plurality of step blocks arranged in sequence, wherein a step in the step block comprises at least two stack pairs. In the application, two stack pairs form a step, and no residue is left in the step corner of the step, so that the subsequent operation space of the step block is larger.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and particularly relates to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] By improving process technology, circuit design, programming algorithm and manufacturing process, the planar storage unit is reduced to a smaller size. However, as the feature size of the storage unit approaches the lower limit, the planar process and manufacturing technology become challenging and costly. As a result, the storage density for the planar storage unit approaches the upper limit.

[0003] In order to solve the density limitation in the planar storage unit, and reduce the development cost of the storage unit, a three-dimensional storage device is developed. SUMMARY

[0004] The present application provides a preparation method of a semiconductor device, comprising: providing a substrate; forming a stack structure on the substrate, the stack structure comprising a plurality of stack pairs, wherein the stack structure comprises a first array region, a second array region and a first connection region arranged between the first array region and the second array region, the first connection region comprising a plurality of sub-connection regions arranged in the first direction in sequence; etching the stack structure on the plurality of sub-connection regions to form a plurality of initial stepped blocks, each of the initial stepped blocks comprising a first initial part and a second initial part, the first initial part and the second initial part having a height difference; etching the plurality of initial stepped blocks to form a plurality of stepped blocks arranged in sequence, the steps in the stepped blocks comprising at least two stack pairs.

[0005] The stepped block comprises a first stepped part and a second stepped part, the first stepped part and the second stepped part are arranged oppositely, and the steps in the first stepped part and the steps in the second stepped part are arranged in a staggered manner.

[0006] In the first direction, the stepped block comprises adjacent first and second stepped blocks, the starting step of the second stepped block is at least one height of a stack pair higher than the tail end step of the first stepped block.

[0007] The first initial part of the initial stepped block is three heights of the stack pair higher than the second initial part.

[0008] The etching of the plurality of initial stepped blocks to form the plurality of sequentially arranged stepped blocks comprises: etching the plurality of initial stepped blocks in units of at least two stack pairs of heights to form a plurality of intermediate stepped blocks, a first initial part of the initial stepped block is etched to form a first stepped part of the intermediate stepped block, a second initial part of the initial stepped block is etched to form a second stepped part of the intermediate stepped block, the first stepped part of the intermediate stepped block is arranged opposite to the second stepped part, and the steps of the first stepped part are staggered with the steps of the second stepped part, and the first stepped part is higher than the second stepped part by three stack pairs of heights.

[0009] The first connection region further comprises a first top gate region and a second top gate region, and a plurality of sub-connection regions are connected between the first top gate region and the second top gate region in the first direction; before etching the stack structure on the plurality of sub-connection regions, the preparation method further comprises: etching the stack structure on the first top gate region in units of one stack pair of heights to form a first top selection gate stepped block, and / or etching the stack structure on the second top gate region in units of one stack pair of heights to form a second top selection gate stepped block, wherein the starting step of the stepped block at the top is at least one stack pair of heights higher than the tail end step of the first top selection gate stepped block and / or the second top selection gate stepped block.

[0010] The stack structure further comprises a second connection region and a third connection region, the second connection region is located on a side of the first array region away from the first connection region in the first direction, and the third connection region is located on a side of the second array region away from the first connection region, the second connection region comprises a first bottom gate region, and the third connection region comprises a second bottom gate region; after forming the intermediate stepped block and before forming the stepped block, the preparation method further comprises: etching the stack structure on the first bottom gate region in units of one stack pair of heights to form a first initial bottom selection gate stepped block; and / or etching the stack structure on the second bottom gate region in units of one stack pair of heights to form a second initial bottom selection gate stepped block; wherein the bottom end step of the intermediate stepped block is at least four stack pairs of heights higher than the tail end step of the first initial bottom selection gate stepped block and / or the second initial bottom selection gate stepped block.

[0011] After forming the intermediate step blocks, the first initial bottom select gate step blocks and / or the second initial bottom select gate step blocks, and before forming the step blocks, the preparation method further comprises: performing an etching process on the plurality of intermediate step blocks to form a plurality of the step blocks arranged in sequence; and performing an etching process on the first initial bottom select gate step blocks to form first bottom select gate step blocks; and / or performing an etching process on the second initial bottom select gate step blocks to form second bottom select gate step blocks; wherein a top end step of the first bottom select gate step blocks and / or the second bottom select gate step blocks is at least one height of a stack pair higher than a tail end step of the step blocks located at the bottom.

[0012] After forming the step blocks, the preparation method further comprises: forming a channel structure in the stack structure on the first array region and in the stack structure on the second array region, wherein the channel structure penetrates into the substrate through a plurality of the stack pairs.

[0013] The stack structure further comprises a plurality of bridge regions located between the sub-connection regions in the second direction; before etching the stack structure on the plurality of sub-connection regions, the preparation method further comprises: forming a mask layer on the stack structure, wherein the mask layer covers the stack structure on the plurality of bridge regions.

[0014] The present application provides a semiconductor device, comprising: a substrate; a plurality of step blocks arranged in sequence on the substrate, wherein a step in the step blocks comprises at least two stack pairs.

[0015] The step blocks comprise a first step portion and a second step portion, the first step portion and the second step portion are oppositely arranged, and steps in the first step portion and steps in the second step portion are arranged in a staggered manner.

[0016] In the first direction, the step blocks comprise adjacent first step blocks and second step blocks, and a starting step of the second step blocks is at least one height of a stack pair higher than a tail end step of the first step blocks.

[0017] The semiconductor device further comprises first top select gate step blocks and second top select gate step blocks, and the plurality of step blocks are located between the first top select gate step blocks and the second top select gate step blocks in the first direction; a starting step of the step blocks located at the top is at least one height of a stack pair higher than a tail end step of the first top select gate step blocks and / or the second top select gate step blocks.

[0018] The semiconductor device further comprises a first bottom select gate step block and a second bottom select gate step block, the first bottom select gate step block is located on the side of the first top select gate step block away from the step block, and the second bottom select gate step block is located on the side of the second top select gate step block away from the step block; the top end step of the first bottom select gate step block and / or the second bottom select gate step block is at least one height of a stack pair higher than the tail end step of the step block located at the bottom.

[0019] The semiconductor device further comprises a first storage array and a second storage array, the first storage array is located between the first bottom select gate step block and the first top select gate step block, the second storage array is located between the second bottom select gate step block and the second top select gate step block, and a channel structure is formed on the first storage array and the second storage array, and the channel structure penetrates into the substrate through a plurality of stack pairs.

[0020] The semiconductor device further comprises a plurality of bridge structures, and the plurality of bridge structures are arranged at intervals in the second direction, and the plurality of step blocks are located between the plurality of bridge structures.

[0021] In summary, the present application sets that each step of the step block comprises two stack pairs, that is, during etching of the stack structure, etching is performed on two stack pairs as an etching unit each time, two stack pairs form a step, and there is no residual material remaining in the corner of adjacent steps, and the subsequent operation space of the step block is larger. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0023] Figure 1 is a flowchart of the preparation method of the semiconductor device provided by the embodiments of the present application.

[0024] Figure 2 is a top view structural schematic diagram of the semiconductor device of the present application.

[0025] Figure 3 is Figure 2 is a structural schematic diagram of the initial step block in

[0026] Figure 4 is Figure 2 is a structural schematic diagram of a plurality of step blocks in

[0027] Figure 5 is a structural diagram of one step block in Figure 2 .

[0028] Figure 6 is a first structural diagram of the first top selection step block or the second top selection step block.

[0029] Figure 7 is a second structural diagram of the first top selection step block or the second top selection step block.

[0030] Figure 8 is a structural diagram of an intermediate step block.

[0031] Figure 9 is a structural diagram of three adjacent step blocks and a first top selection gate step block.

[0032] Figure 10 is a layer structural diagram of a bottom step block and a first bottom selection gate step block.

[0033] Figure 11 is a top view diagram of a first mask layer for forming the semiconductor device.

[0034] Figure 12 is a top view diagram of a second mask layer for forming the semiconductor device.

[0035] Figure 13 is a top view diagram of a third mask layer for forming the semiconductor device.

[0036] Figure 14 is a top view diagram of a fourth mask layer for forming the semiconductor device. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0038] The present application provides a preparation method of a semiconductor device. Please refer to Figure 1 , Figure 1A flowchart of a semiconductor device manufacturing method is provided in the present application. In the present application, each step of the step block 20 includes two stacked pairs 120, that is, in the process of etching the stacked structure, two stacked pairs 120 are etched as an etching unit each time, two stacked pairs 120 form a step, and there is no residue in the corner of the adjacent step. The subsequent operation space of the step block 20 is larger. The present application improves the step formed by a single stacked pair 120 and multiple stacked pairs 120 (such as three stacked pairs 120 and N stacked pairs 120), and when removing the residue in the corner of the step, the residue in the corner of the step formed by multiple stacked pairs 120 (such as three stacked pairs 120 and N stacked pairs 120) is removed cleanly, and the residue in the corner of the step formed by a single stacked pair 120 still exists, and the subsequent operation space of the step block 20 is smaller.

[0039] A semiconductor device manufacturing method is shown in Figure 1 . As shown in Figure 1 , the method can be roughly summarized as follows: providing a substrate 110 (S1), forming a stacked structure on the substrate 110, the stacked structure including multiple stacked pairs 120 (S2), etching the stacked structure on the multiple sub-connection regions 101 to form multiple initial step blocks 500 (S3), etching the multiple initial step blocks 500 to form multiple step blocks 20 arranged in sequence (S4). The following will be described respectively.

[0040] Please refer to Figure 1 , the method first performs the operations of S1-S4:

[0041] S1, providing a substrate 110. The material of the substrate 110 is, for example, silicon, and of course it can also be other silicon-containing substrates 110, such as Silicon On Insulator (SOI), SiGe, Si:C, etc. The substrate 110 can form various potential wells required by the device through ion implantation and other processes, such as p-type / n-type or deep or shallow potential wells.

[0042] S2, please refer to Figure 2A stack structure is formed on the substrate 110, and the stack structure includes a plurality of stack pairs 120. The stack structure includes the first array region 50, the second array region 60, and the first connection region 10 disposed between the first array region 50 and the second array region 60. The first connection region 10 includes a plurality of sub-connection regions 101 disposed in sequence in the first direction. It can be understood that the plurality of stack pairs 120 are stacked in the third direction Z. The stack pair 120 is a stack of an insulating layer and a gate sacrificial layer, that is, each stack pair 120 includes one layer of insulating layer and one layer of gate sacrificial layer. The insulating layer is formed of, for example, silicon oxide, and the gate sacrificial layer is formed of, for example, silicon nitride, which will be replaced by metal as a gate layer in a subsequent process. The insulating layer can also be silicon oxynitride, and the gate sacrificial layer can also be amorphous silicon, polysilicon, aluminum oxide, etc.

[0043] S3, please refer to Figure 3 The stack structure on the plurality of sub-connection regions 101 is etched to form a plurality of initial stepped blocks 500. Each initial stepped block 500 includes a first initial portion 501 and a second initial portion 502, and the first initial portion 501 and the second initial portion 502 have a height difference.

[0044] S4, please refer to Figure 4 The plurality of initial stepped blocks 500 are etched to form a plurality of stepped blocks 20 disposed in sequence. The step in the stepped block 20 includes at least two stack pairs 120. Optionally, the step of the stepped block 20 includes two stack pairs 120.

[0045] In this application, by setting that each step of the stepped block 20 includes two stack pairs 120, that is, in the process of etching the stack structure, etching is performed every time with two stack pairs 120 as an etching unit, two stack pairs 120 form a step, and there is no residual material remaining in the corner of the adjacent step. The subsequent operation space of the stepped block 20 is larger. This application improves the technical problem that the operation space of the stepped block 20 is smaller when the residual material in the corner of the step formed by a single stack pair 120 and a plurality of stack pairs 120 (such as three stack pairs 120 and N stack pairs 120) is removed, and the residual material in the corner of the step formed by a single stack pair 120 still exists when the residual material in the corner of the step formed by a plurality of stack pairs 120 (such as three stack pairs 120 and N stack pairs 120) is removed.

[0046] Please refer to Figure 5In one embodiment, the step block 20 includes a first step portion 201 and a second step portion 202, the first step portion 201 and the second step portion 202 are oppositely arranged, and the steps in the first step portion 201 and the steps in the second step portion 202 are staggered. For example, the steps in the first step portion 201 are 1, 3, 5, 7, and 9, and the steps in the second step portion 202 are 4, 6, 8, 10, and 12. The steps in the first step portion 201 and the steps in the second step portion 202 are staggered. The steps in the step block 20 form continuous steps. It can be understood that the first initial portion 501 of the initial step block 500 forms the first step portion 201 after etching, and the second initial portion 502 of the initial step block 500 forms the second step portion 202 after etching. The first step portion 201 and the second step portion 202 form continuous steps in the middle portion.

[0047] In one embodiment, in the first direction, the step block 20 includes a first step block and a second step block adjacent to each other, and the starting step of the second step block is at least one height of a stack pair 120 higher than the ending step of the first step block. Alternatively, the starting step of the second step block is one height of a stack pair 120 higher than the ending step of the first step block. For example, in the first step block, the steps in the first step portion 201 are 1, 3, 5, 7, and 9, and the steps in the second step portion 202 are 4, 6, 8, 10, and 12. In the second step block, the steps in the first step portion 201 are 11, 13, 15, 17, and 19, and the steps in the second step portion 202 are 14, 16, 18, 20, and 22. The step 11 of the second step block forms continuous steps with the steps 10 and 12 in the first step block. The starting step of the second step block is at least one height of a stack pair 120 higher than the ending step of the first step block, so that the steps in the two adjacent step blocks 20 form continuous steps, which facilitates the leading out of all the steps.

[0048] Please continue to refer to Figure 3 In one embodiment, the first initial portion 501 of the initial step block 500 is three heights of a stack pair 120 higher than the second initial portion 502. It can be understood that the first initial portion 501 is an edge flush structure, and no steps are formed on the first initial portion 501. The second initial portion 502 is an edge flush structure, and no steps are formed on the second initial portion 502. It can be understood that before the initial step block 500 is formed, a barrier layer 801 is formed on the stack structure on the sub-connection region 101, and the exposed part of the stack structure is Figure 13In the middle, the barrier layer 801 on the sub-connection region 101 is in the shape of spaced strips, so that part of the stacked structure of the sub-connection region 101 can be exposed. After etching the stacked structure with the barrier layer 801 as a mask, the initial step block 500 can be formed.

[0049] In this application, by setting the first initial portion 501 of the initial step block 500 to be three stacked pairs 120 higher than the second initial portion 502, the steps in the first step portion 201 and the steps in the second step portion 202 of the subsequently formed step block 20 can be staggered. Furthermore, by etching two stacked pairs 120 at a time on the initial step block 500, the formation of a single stacked pair 120 step is avoided. No residue remains in the corners of the steps in this application, and the subsequent operation space of the step block 20 is larger.

[0050] In one specific embodiment, "etching multiple initial step blocks 500 to form multiple sequentially arranged step blocks 20" includes:

[0051] Please see Figure 8 Multiple initial step blocks 500 are etched using at least two stacked pairs 120 as etching units to form multiple intermediate step blocks 520. The first initial portion 501 of the initial step block 500 is etched to form the first step portion 201 of the intermediate step block 520. The second initial portion 502 of the initial step block 500 is etched to form the second step portion 202 of the intermediate step block 520. The first step portion 201 and the second step portion 202 of the intermediate step block 520 are arranged opposite to each other, and the steps of the first step portion 201 and the steps of the second step portion 202 of the intermediate step block 520 are staggered. The first step portion 201 is three stacked pairs 120 higher than the second step portion 202. It is understandable that in this step, both the first initial portion 501 and the second initial portion 502 of the initial step block 500 are etched. After the first initial portion 501 is etched to form a step, the first step portion 201 of the intermediate step block 520 is formed. After the second initial portion 502 is etched to form a step, the second step portion 202 of the intermediate step block 520 is formed.

[0052] Please see Figure 2 and Figure 9 In one specific embodiment, the first connection region 10 further includes a first top gate region 102 and a second top gate region 103, and a plurality of sub-connection regions 101 are connected between the first top gate region 102 and the second top gate region 103 in a first direction; before etching the stacked structure on the plurality of sub-connection regions 101, the fabrication method further includes:

[0053] The stacked structure on the first top gate region 102 is etched using a stack height of 120 as the etching unit to form the first top selection gate step block 70. (See also...)Figure 12 It can be understood that, before etching, a barrier layer 801 is formed on the stack structure on the first top gate region 102, the barrier layer 801 is etched, and the stack structure on the first top gate region 102 is etched with the etched barrier layer 801 as a mask to form the first top select gate step block 70. The first top select gate step block 70 can be a symmetrical structure, and the first top select gate step block 70 can also be an asymmetrical structure with more steps on one side than on the other side. Figure 6 It can be understood that, before etching, a barrier layer 801 is formed on the stack structure on the first top gate region 102, the barrier layer 801 is etched, and the stack structure on the first top gate region 102 is etched with the etched barrier layer 801 as a mask to form the first top select gate step block 70. The first top select gate step block 70 can be a symmetrical structure, and the first top select gate step block 70 can also be an asymmetrical structure with more steps on one side than on the other side. Figure 7 It can be understood that, before etching, a barrier layer 801 is formed on the stack structure on the first top gate region 102, the barrier layer 801 is etched, and the stack structure on the first top gate region 102 is etched with the etched barrier layer 801 as a mask to form the first top select gate step block 70. The first top select gate step block 70 can be a symmetrical structure, and the first top select gate step block 70 can also be an asymmetrical structure with more steps on one side than on the other side.

[0054] And / or, the stack structure on the second top gate region 103 is etched with one stack pair 120 as an etching unit to form the second top select gate step block. Please refer to Figure 12 It can be understood that, before etching, a barrier layer 801 is formed on the stack structure on the first top gate region 102, the barrier layer 801 is etched, and the stack structure on the first top gate region 102 is etched with the etched barrier layer 801 as a mask to form the first top select gate step block 70. The first top select gate step block 70 can be a symmetrical structure, and the first top select gate step block 70 can also be an asymmetrical structure with more steps on one side than on the other side.

[0055] Wherein, the starting step of the top step block 20 is at least one stack pair 120 higher than the tail end step of the first top select gate step block 70 and / or the second top select gate step block. Optionally, the starting step of the top step block 20 is one stack pair 120 higher than the tail end step of the first top select gate step block 70 and / or the second top select gate step block. It can be understood that, the steps of the first top select gate step block 70 and / or the second top select gate step block can be continuous steps, such as steps can be 1, 2, 3, 4, 5, 6, ….

[0056] In this application, the discontinuous steps of the top step block 20 can be supplemented by the steps in the first top select gate step block 70 and / or the second top select gate step block.

[0057] In a specific embodiment, the stack structure further includes a second connection area 30 and a third connection area 40, in the first direction, the second connection area 30 is located on the side of the first array area 50 away from the first connection area 10, and the third connection area 40 is located on the side of the second array area 60 away from the first connection area 10, the second connection area 30 includes a first bottom gate region 130, and the third connection area 40 includes a second bottom gate region 140; after forming the middle step block 520 and before forming the step block 20, the preparation method further includes:

[0058] The stack structure on the first bottom gate region 130 is etched by taking one height of the stack pair 120 as an etching unit to form a first initial bottom select gate step block;

[0059] The stack structure on the second bottom gate region 140 is etched by taking one height of the stack pair 120 as an etching unit to form a second initial bottom select gate step block;

[0060] The bottom end step of the intermediate step block 520 is at least four heights of the stack pair 120 higher than the tail end step of the first initial bottom select gate step block and / or the second initial bottom select gate step block. It can be understood that the stack structure on the first bottom gate region 130 is etched by 7 stack pairs 120 to form the first initial bottom select gate step block, and / or the stack structure on the second bottom gate region 140 is etched by 7 stack pairs 120 to form the second initial bottom select gate step block.

[0061] Please refer to Figure 2 In a specific embodiment, after forming the intermediate step block 520, the first initial bottom select step block and / or the second initial bottom select step block, and before forming the step block 20, the preparation method further comprises:

[0062] Performing an etching process on the plurality of intermediate step blocks 520 to form a plurality of sequentially arranged step blocks 20;

[0063] And performing an etching process on the first initial bottom select gate step block to form a first bottom select gate step block;

[0064] And / or performing an etching process on the second initial bottom select gate step block to form a second bottom select gate step block;

[0065] The top end step of the first bottom select gate step block and / or the second bottom select gate step block is at least one height of the stack pair 120 higher than the tail end step of the bottom located step block 20.

[0066] Understandably, after the first initial bottom selection step block, the second initial bottom selection step block, and the intermediate step block 520 are formed, the etching process is performed simultaneously on the first initial bottom selection step block, the second initial bottom selection step block, and the intermediate step block 520. Since the tail step of the intermediate step block 520 is at least four stack pairs 120 higher than the tail step of the first initial bottom selection gate step block and / or the second initial bottom selection gate step block, the first initial bottom selection gate step block and / or the second initial bottom selection gate step block are etched to the bottom first. That is, the first initial bottom selection gate step block and / or the second initial bottom selection gate step block are etched to the bottom first. At a preset position, such as etching to the substrate 110, the bottom step of the bottommost step block 20 is four stack pairs 120 higher than the substrate 110. Since the step of the step block 20 includes the height of two stack pairs 120, the first step portion 201 of the bottommost step block 20 can be 7, 9, 11, 13, or 15, and the second step portion 202 can be 4, 6, 8, 10, or 12. The steps of the first bottom selected gate step block and / or the second bottom selected gate step block can be 1, 2, 3, 4, 5, 6, or 7. The step 5 of the first bottom selected gate step block and / or the second bottom selected gate step block can supplement the missing steps of the intermediate step blocks 5204 and 6.

[0067] In this application, discontinuous steps in the bottom step block 20 can be supplemented by steps in the first bottom selection gate step block and / or the second bottom selection gate step block.

[0068] In other words, the missing step of the topmost step block 20 in the plurality of step blocks 20 of this application can be supplemented by the steps of the first top selection gate step block 70 and / or the second top selection gate step block, and the missing step of the bottommost step block 20 can be supplemented by the steps of the first bottom selection gate step block and / or the second bottom selection gate step block, and the steps of the step blocks 20 between the topmost and the bottommost complement each other to form a continuous step.

[0069] like Figure 4 middle, Figure 4 The first connecting area 10 has 12 step blocks 20, and each step block 20 has a first step portion 201 with 13 steps. The first step portion 201 is 3 stacked pairs 120 higher than the second step portion 202. Figure 9As shown, the steps of the first step part 201 of the step block 20B from top to bottom are 280, 278, 276, 274, 272, 270, 268, 266, 264, 262, 260, 258, 256, 254; the steps of the second step part 202 of the step block 20B from bottom to top are 257, 259, 261, 263, 265, 267, 269, 271, 273, 275, 277, 379, 381, 383. According to the first step part 201 and the second step part 202 of the step block 20B, it can be known that the step block 20B lacks the step 255 and the step 279, and the step 280 exists.

[0070] The step block 20 adjacent to the step block 20B is the step block 20A and the step block 20C. The steps of the first step part 201 of the step block 20A from top to bottom are 308, 306, 304, 302, 300, 298, 296, 294, 292, 290, 288, 286, 284, 282; the steps of the second step part 202 of the step block 20A from bottom to top are 279, 281, 283, 285, 287, 289, 291, 293, 295, 297, 299, 301, 303, 305. According to the first step part 201 and the second step part 202 of the step block 20A, it can be known that the step block 20A lacks the step 307 and the step 280, and the step 279 exists.

[0071] The steps of the first step part 201 of the step block 20C from top to bottom are 252, 250, 248, 246, 244, 242, 240, 238, 236, 234, 232, 230, 228, 226; the steps of the second step part 202 of the step block 20C from bottom to top are 229, 231, 233, 235, 237, 239, 241, 243, 245, 247, 249, 251, 253, 255. According to the first step part 201 and the second step part 202 of the step block 20C, it can be known that the step block 20C lacks the step 227 and the step 254, and the step 255 layer exists.

[0072] That is, the step 279 missing in the step block 20B can be supplemented by the step 279 of the step block 20A, and the step 255 missing in the step block 20B can be supplemented by the step 255 of the step block 20C.

[0073] Therefore, the present application not only solves the technical problem that the steps of a single stack 120 will have residues in the corner of the steps, so that the subsequent operable space of the step block 20 is smaller. Moreover, the plurality of step blocks 20 of the present application can compensate for each other, and the step structure of the semiconductor device is complete.

[0074] As Figure 9In the embodiment, the step block 20 at the top is step block 20A, the steps of the first step portion 201 of the first top select gate (TSG) step block 70 from top to bottom are 309, 308, 307, 306 in turn, and the steps of the second step portion 202 of the first top select gate (TSG) step block 70 from bottom to top are 306, 307, 308, 309 in turn. That is, the step 307 of the first top select gate (TSG) step block 70 can supplement the missing step 307 of the step block 20A. Of course, the steps of the second top select gate (TSG) step block 20 can also supplement the steps of the step block 20A.

[0075] Therefore, even if the step of the step block 20 at the top is missing, it can be supplemented by any one of the first top select gate (TSG) step block 70 and the second top select gate (TSG) step block 20, and the integrity of the step structure of the semiconductor device is achieved.

[0076] As shown in FIG. 1, the semiconductor device includes a substrate 110, a plurality of step blocks 20, a first array region 50, and a second array region 60. Figure 10 In the embodiment, the steps of the first step portion 201 of the step block 20E at the bottom from top to bottom are 33, 31, 29, 27, 25, 23, 21, 19, 17, 15, 13, 11, 9, 7 in turn, and the steps of the second step portion 202 of the step block 20E at the bottom from bottom to top are 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 in turn. The two missing steps of the step block 20E at the bottom are step 5 and step 33, and the steps of the first bottom select gate (BSG) step block 90 and the second bottom select gate (BSG) step block 20 can be 0, 1, 2, 3, 4, 5, 6, 7. The step 5 of the first bottom select gate (BSG) step block 90 and the second bottom select gate (BSG) step block 20 can supplement the step 5 of the step block 20E at the bottom. The step 33 of the step block E at the bottom can be supplemented by the step block 20 adjacent to the step block E at the bottom.

[0077] Therefore, even if the step of the bottom step block 20E at the bottom is missing, it can be supplemented by any one of the first bottom select gate (BSG) step block 90 and the second bottom select gate (BSG) step block 20, and the integrity of the step structure of the semiconductor device is achieved.

[0078] In a specific embodiment, after the step block 20 is formed, the preparation method further includes:

[0079] Forming a channel structure in the stack structure on the first array region 50 and the stack structure on the second array region 60, wherein the channel structure penetrates into the substrate 110 through the plurality of stack pairs 120. It can be understood that the first array region 50 and the second array region 60 are mainly used for storage.

[0080] Please refer to Figure 11In one embodiment, the stack structure further comprises a plurality of bridge regions 802, the bridge regions 802 being located between the sub-connection regions 101 in the second direction; before etching the stack structure on the plurality of sub-connection regions 101, the method further comprises:

[0081] forming a mask layer 320 on the stack structure, wherein the mask layer 320 covers the stack structure on the plurality of bridge regions 802. It can be understood that the second direction Y is perpendicular to the first direction X. The plurality of step blocks 20 are located in the space between the bridge structures, the first array region 50 is connected to the step block 20 through the bridge structure, and the second array region 60 is connected to the step block 20 through the bridge structure. The word lines in the bridge structure bridge the word line contacts on the step block 20 and the array region (the first array region 50 and the second array region 60) so as to realize a bidirectional word line driving scheme. As shown in Figure 14 In the embodiment, the first array region 50 and the second array region 60 can be formed by the mask layer 320, and the bridge structure can be formed by the mask layer 320. Figure 2 In the embodiment, the bridge structure is a first bridge structure 170 and a second bridge structure 180 respectively. The first top select gate (TSG) step block 70 and the second top select gate (TSG) step block 20 can be formed in the gap 330 between the mask layers 320. The step block 20 can be formed in the gap 340 between the mask layers 320.

[0082] In one embodiment, the method further comprises:

[0083] forming a separation structure in the first direction X through the second connection region 30, the first array region 50, the first connection region 10, the second array region 60 and the third connection region 40, wherein the separation structure extends into the substrate 110. It can be understood that the separation structure is used to separate the stack structure into at least two memory blocks. Figure 2 In the embodiment, the separation structure is a first separation structure 210, a second separation structure 220 and a third separation structure 230 respectively. The structure between the first separation structure 210 and the second separation structure 220 is a first memory block, and the structure between the second separation structure 220 and the third separation structure 230 is a second memory block. The plurality of step blocks 20 can be separated into a first connection step block 240 and a second connection step block 250 by the second separation structure 220. The first connection step block 240 is connected to the first array region 50 through the first bridge structure 170, and the second connection step block 250 is connected to the second array region 60 through the second bridge structure 180. The separation structure (for example, the first separation structure 210) can be formed in the dashed line 350 in Figure 14 Therefore, a plurality of memory blocks can be defined by the separation structure.

[0084] Please refer to Figure 3In addition to the method for manufacturing the semiconductor device, the embodiment of the present application also provides a semiconductor device. The semiconductor device and the method for manufacturing the semiconductor device can realize the advantages of the present application, and can be used together, or can be used separately, and the present application does not have special limitations. In a specific embodiment, the semiconductor device is manufactured by the method for manufacturing the semiconductor device. Optionally, the semiconductor device is a three-dimensional memory.

[0085] The semiconductor device comprises: a substrate 110; and a plurality of step blocks 20 arranged in sequence on the substrate 110, wherein each step in the step block 20 comprises at least two stack pairs 120.

[0086] In the present application, each step of the step block 20 comprises two stack pairs 120, that is, during etching of the stack structure, etching is performed in two stack pairs 120 as an etching unit each time, two stack pairs 120 form a step, and there is no residual material remaining in the corner of the adjacent step. The subsequent operation space of the step block 20 is larger. The present application improves the technical problem that the step formed by a single stack pair 120 and a plurality of stack pairs 120 (such as three stack pairs 120 and N stack pairs 120) has a smaller subsequent operation space, that is, when the residual material in the corner of the step is removed, the residual material in the corner of the step formed by the plurality of stack pairs 120 (such as three stack pairs 120 and N stack pairs 120) is completely removed, and the residual material in the corner of the step formed by the single stack pair 120 still exists.

[0087] In a specific embodiment, the step block 20 comprises a first step portion 201 and a second step portion 202, the first step portion 201 and the second step portion 202 are arranged opposite to each other, and the steps in the first step portion 201 and the steps in the second step portion 202 are arranged in a staggered manner. The steps in the first step portion 201 and the steps in the second step portion 202 are arranged in a staggered manner, so that the steps in the step block 20 form continuous steps.

[0088] In a specific embodiment, in the first direction, the step block 20 comprises a first step block and a second step block adjacent to each other, and the starting step of the second step block is at least one height of a stack pair 120 higher than the tail end step of the first step block. The starting step of the second step block is at least one height of a stack pair 120 higher than the tail end step of the first step block, so that the steps in the two adjacent step blocks 20 form continuous steps, and it is convenient to lead out all the steps.

[0089] In one embodiment, the semiconductor device further includes a first top select gate step block 70 and a second top select gate step block, the plurality of step blocks 20 are located between the first top select gate step block 70 and the second top select gate step block in the first direction; the initial step of the top located step block 20 is at least one height of the stack pair 120 higher than the tail step of the first top select gate step block 70 and / or the second top select gate step block. In this application, the discontinuous step of the top located step block 20 can be supplemented by the step in the first top select gate step block 70 and / or the second top select gate step block. It can be understood that the first top select gate (TSG) step block 70, the plurality of step blocks 20 and the second top select gate (TSG) step block 20 are arranged in sequence along the first direction X direction. The first top select gate (TSG) step block 70, the plurality of step blocks 20 and the second top select gate (TSG) step block 20 are also arranged between the first bridge structure 170 and the second bridge structure 180 along the second direction Y direction of the substrate 110. The first top select gate (TSG) step block 70 and the second top select gate (TSG) step block 20 can be formed in the second group of stack pairs 120, for example, in one or more top word line layers and top insulating layers. In addition, each of the plurality of step blocks 20 can be formed in the corresponding word line layer and insulating layer of the plurality of stack pairs 120.

[0090] In one embodiment, the semiconductor device further includes a first bottom select gate step block and a second bottom select gate step block, the first bottom select gate step block is located on the side of the first top select gate step block 70 away from the step block 20, and the second bottom select gate step block is located on the side of the second top select gate step block away from the step block 20; the top step of the first bottom select gate step block and / or the second bottom select gate step block is at least one height of the stack pair higher than the tail step of the bottom located step block. It can be understood that the first bottom select gate (BSG) step block 90 is formed in the stack pair 120 adjacent to the substrate 110, for example, in one or more bottommost word line layers and bottommost insulating layers adjacent to the substrate 110. Similarly, the second bottom select gate (BSG) step block 20 can also be formed in the first group of stack pairs 120 adjacent to the substrate 110.

[0091] In this application, the discontinuous step of the bottom located step block 20 can be supplemented by the step in the first bottom select gate step block and / or the second bottom select gate step block.

[0092] In one specific embodiment, the semiconductor device further includes a first memory array between the first bottom select gate step block and the first top select gate step block 70, and a second memory array between the second bottom select gate step block and the second top select gate step block, each of the first and second memory arrays having a channel structure formed thereon, the channel structure extending into the substrate 110 through the plurality of stack pairs 120. The first and second memory arrays are configured to store. Each of the channel structures 150 can further include a channel layer, a tunnel layer surrounding the channel layer, a charge trap layer surrounding the tunnel layer, and a blocking layer surrounding the charge trap layer. Further, the channel structures 150 can be in direct contact with the word line layers.

[0093] In one specific embodiment, the semiconductor device further includes a plurality of bridge structures, the plurality of bridge structures being spaced apart in the second direction, the plurality of step blocks 20 being located between the plurality of bridge structures. The word lines in the bridge structures are bridged to the word line contacts on the step blocks 20 and the array regions (the first array region 50 and the second array region 60) to enable a bidirectional word line driving scheme.

[0094] The semiconductor device can include a first separation structure 210. The first separation structure 210 can extend into the substrate 110 through the plurality of stack pairs 120 and extend along the first direction X.

[0095] The semiconductor device can further have a second separation structure 220. The second separation structure 220 can be formed along the first direction X and extend into the substrate 110 through the plurality of stack pairs 120. In some embodiments, the plurality of step blocks 20 can be separated into a first connection step 240 and a second connection step 250 by the second separation structure 220. The second separation structure 220 can further divide the first bottom select gate (BSG) step block 90 into a first sub-BSG step block 901 and a second sub-BSG step block 902. The second separation structure 220 can further divide the first top select gate (BSG) step block 70 into a first sub-TSG step block 701 and a second sub-TSG step block 702.

[0096] The semiconductor device can include a third separation structure 230. The third separation structure 230 can further extend into the substrate 110 through the plurality of stack pairs 120 and extend along the first direction X.

[0097] In some embodiments, the first separation structure 210, the second separation structure 220, and the third separation structure 230 can be gate line and space (GLS) structures. In some embodiments, the GLS structures can be made of a conductive material and positioned on an array common source (ACS) region to function as a contact, where the ACS region is formed in the substrate 110 to function as a common source. In some embodiments, the GLS structures can be made of a dielectric material to function as a separation structure. In some embodiments, a semiconductor device is formed using a gate-last manufacturing technique. Thus, the GLS structures are formed to help remove a sacrificial word line layer (also referred to as a sacrificial layer) as well as form a true gate.

[0098] In some embodiments, two memory blocks can be formed in the memory array region 120, where a first memory block can be defined between the first separation structure 210 and the second separation structure 220, and a second memory block can be defined between the second separation structure 220 and the third separation structure 230. For example, as shown in FIG. 1, the first bridge structure 170, the first connection step block 240, and the first sub-BSG step block 901 are included in the first memory block. The second bridge structure 180, the second connection step block 250, and the second sub-BSG step block 902 are included in the second memory block. Figure 2 Figure 2 In some embodiments, two memory blocks can be formed in the memory array region 120, where a first memory block can be defined between the first separation structure 210 and the second separation structure 220, and a second memory block can be defined between the second separation structure 220 and the third separation structure 230. For example, as shown in FIG. 1, the first bridge structure 170, the first connection step block 240, and the first sub-BSG step block 901 are included in the first memory block. The second bridge structure 180, the second connection step block 250, and the second sub-BSG step block 902 are included in the second memory block.

[0099] The above disclosure is merely preferred embodiments of the application and thus cannot limit the scope of the application. Those skilled in the art can understand that all or part of the above-mentioned processes can be implemented, and equivalent changes can be made according to the claims of the application, which still fall within the scope of the application.​

Claims

1. A method of manufacturing a semiconductor device, characterized by, Comprising: providing a substrate; forming a stack structure on the substrate, the stack structure comprising a plurality of stack pairs, wherein the stack structure comprises a first array region, a second array region, and a first connection region disposed between the first array region and the second array region, the first connection region comprising a plurality of sub-connection regions disposed in sequence in a first direction; the first connection region further comprising a first top gate region and a second top gate region, the plurality of sub-connection regions being connected between the first top gate region and the second top gate region in the first direction; etching the stack structure on the first top gate region with one stack pair as an etching unit to form a first top selection gate step block, and / or etching the stack structure on the second top gate region with one stack pair as an etching unit to form a second top selection gate step block; wherein the starting step of the top step block is at least one stack pair higher than the tail end step of the first top selection gate step block and / or the second top selection gate step block; etching the stack structure on the plurality of sub-connection regions to form a plurality of initial step blocks, each of the initial step blocks comprising a first initial portion and a second initial portion, the first initial portion and the second initial portion having a height difference; etching the plurality of initial step blocks with at least two stack pairs as an etching unit to form a plurality of intermediate step blocks, the first initial portion of the initial step block being three stack pairs higher than the second initial portion, the first initial portion of the initial step block forming a first step portion of the intermediate step block after etching, the second initial portion of the initial step block forming a second step portion of the intermediate step block after etching, the first step portion and the second step portion of the intermediate step block being oppositely disposed, and the steps of the first step portion and the second step portion of the intermediate step block being staggered, the first step portion being three stack pairs higher than the second step portion, each of the step blocks comprising at least two stack pairs.

2. The production method according to claim 1, characterized by, The step block comprises a first step portion and a second step portion, the first step portion and the second step portion being oppositely disposed, and the steps of the first step portion and the second step portion being staggered.

3. The preparation method according to claim 1, characterized in that, In the first direction, the step block comprises a first step block and a second step block adjacent to each other, the starting step of the second step block being at least one stack pair higher than the tail end step of the first step block.

4. The production method according to claim 1, characterized by, The stack structure further comprises a second connection region and a third connection region, the second connection region being located on a side of the first array region away from the first connection region, and the third connection region being located on a side of the second array region away from the first connection region in the first direction, the second connection region comprising a first bottom gate region, and the third connection region comprising a second bottom gate region; after forming the intermediate step blocks and before forming the step blocks, the preparation method further comprises: etching the stack structure on the first bottom gate region with one stack pair as an etching unit to form a first initial bottom selection gate step block; and / or, etching the stack structure on the second bottom gate region with a height of one stack pair to form a second initial bottom select gate step block; wherein the bottom end step of the intermediate step block is at least four heights of one stack pair higher than the tail end step of the first initial bottom select gate step block and / or the second initial bottom select gate step block.

5. The preparation method according to claim 4, characterized in that, After forming the intermediate step block, the first initial bottom select gate step block and / or the second initial bottom select gate step block, and before forming the step block, the preparation method further comprises: performing an etching process on a plurality of the intermediate step blocks to form a plurality of the step blocks arranged in sequence; and performing an etching process on the first initial bottom select gate step block to form a first bottom select gate step block; and / or, performing an etching process on the second initial bottom select gate step block to form a second bottom select gate step block; wherein the top end step of the first bottom select gate step block and / or the second bottom select gate step block is at least one height of one stack pair higher than the tail end step of the step block at the bottom.

6. The preparation method according to claim 1, characterized in that, After forming the step block, the preparation method further comprises: forming a channel structure within the stack structure on the first array region and the stack structure on the second array region, wherein the channel structure penetrates into the substrate through a plurality of the stack pairs.

7. The preparation method according to claim 1, characterized in that, The stack structure further comprises a plurality of bridge regions between the sub-connection regions in the second direction; Before etching the stack structure on a plurality of the sub-connection regions, the preparation method further comprises: forming a mask layer on the stack structure, wherein the mask layer covers the stack structure on a plurality of the bridge regions.

8. A semiconductor device, characterized by Comprise: a substrate; a plurality of step blocks arranged in sequence on the substrate, each of the step blocks comprising at least two stack pairs; a first top select gate step block and a second top select gate step block, a plurality of the step blocks being between the first top select gate step block and the second top select gate step block in a first direction; the starting step of the step block at the top being at least one height of one stack pair higher than the tail end step of the first top select gate step block and / or the second top select gate step block.

9. The semiconductor device of claim 8, wherein, The step block comprises a first step portion and a second step portion, the first step portion and the second step portion being oppositely arranged, and the steps in the first step portion and the steps in the second step portion being staggered.

10. The semiconductor device of claim 8, wherein, In the first direction, the step block comprises a first step block and a second step block adjacent to each other, the starting step of the second step block being at least one height of one stack pair higher than the tail end step of the first step block. The step block comprises a first step portion and a second step portion, the first step portion and the second step portion being oppositely arranged, and the steps in the first step portion and the steps in the second step portion being staggered. In the first direction, the step block comprises a first step block and a second step block adjacent to each other, the starting step of the second step block being at least one height of one stack pair higher than the tail end step of the first step block.

11. The semiconductor device of claim 8, wherein, The semiconductor device further comprises a first bottom select gate step block and a second bottom select gate step block, the first bottom select gate step block is located at a side of the first top select gate step block away from the step block, and the second bottom select gate step block is located at a side of the second top select gate step block away from the step block; a top end step of the first bottom select gate step block and / or the second bottom select gate step block is at least one height of a stack pair higher than a tail end step of the step block located at a bottom.

12. The semiconductor device of claim 11, wherein, The semiconductor device further comprises a first storage array and a second storage array, the first storage array is located between the first bottom select gate step block and the first top select gate step block, and the second storage array is located between the second bottom select gate step block and the second top select gate step block; a channel structure is formed on the first storage array and the second storage array, and the channel structure penetrates into the substrate through a plurality of stack pairs.

13. The semiconductor device of claim 8, wherein, The semiconductor device further comprises a plurality of bridge structures, in a second direction, a plurality of the bridge structures are arranged at intervals, and a plurality of the step blocks are located between a plurality of the bridge structures.

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