A method for improving the process window for polysilicon etching and dielectric layer filling in Nor Flash.

Abstract

The application discloses a method for improving the process window of Nor Flash polysilicon etching and dielectric layer filling. The method is characterized by coating a bottom anti-reflection coating before etching the polysilicon layer and reducing the polysilicon layer of the Nor Flash storage area by using a back etching process, and simultaneously reducing the height difference at the junction of the Nor Flash storage area and the peripheral area. The application can not only avoid the polysilicon etching residue caused by the excessive height difference during the polysilicon layer etching, expand the etching process window, but also reduce the height of the control gate (CG) and the aspect ratio between the control gates, and expand the process window of the dielectric layer filling.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for improving the process window of polysilicon etching and dielectric layer filling in Nor Flash. Background Technology

[0002] As chip process nodes continue to shrink, the gate spacing of the polysilicon in the Nor Flash memory region becomes increasingly smaller, leading to insufficient filling capacity of the subsequent dielectric layer, which easily forms voids and causes failure. Simultaneously, because the polysilicon layer in the memory region is thicker than the surrounding circuitry, residual polysilicon is more likely to remain after etching.

[0003] Please see Figures 3(a) to 3(d) , Figures 3(a) to 3(d) The diagram shows a structure in which polysilicon residue is generated on a silicon substrate after etching of the existing polysilicon layer. The Nor Flash includes a silicon substrate 10, a shallow trench isolation structure 11 formed in the silicon substrate 10, a gate oxide layer 121, a floating gate 122, an ONO dielectric layer 123 located in the storage region 12 of the Nor Flash, and a polysilicon layer 14 located in the storage region 12 and the peripheral region 13.

[0004] Due to the different functions of the storage region (cell) 12 and the peripheral region (peripheral) 13 in the Nor flash polysilicon process, the film thickness of the polysilicon layer 14 varies in different regions. The storage region 12 and the peripheral region 13 differ in height by approximately 600–800 Å before etching. This height difference creates a deep depression at the interface, resulting in a thicker BARC layer at the depression during the bottom anti-reflective layer coating. This makes incomplete etching of the subsequent polysilicon layer more likely, leading to polysilicon residue and a smaller etching process window.

[0005] The search for a method that can not only effectively avoid polysilicon etching residue caused by excessive height difference during polysilicon layer etching and expand the etching process window, but also reduce the control gate (CG) height, decrease the aspect ratio between control gates, and expand the dielectric layer filling process window has become one of the technical problems that urgently need to be solved by those skilled in the art.

[0006] Therefore, in view of the problems existing in the prior art, the designer of this case, based on years of experience in this industry, actively researched and improved the technology, and thus came up with the present invention, a method for improving the process window of polysilicon etching and dielectric layer filling in Nor Flash. Summary of the Invention

[0007] This invention addresses the shortcomings of conventional polysilicon layer etching, where the presence of step height causes deep depressions at the interface. This results in a thicker BARC layer at the depressions during the coating process, leading to incomplete etching of the polysilicon layer, leaving polysilicon residue. Consequently, the etching process window is smaller, and the subsequent dielectric layer has insufficient filling capacity, easily forming voids and causing poor performance. This invention provides a method to improve the etching and dielectric layer filling process window for Nor Flash polysilicon.

[0008] To achieve the objective of this invention, this invention provides a method for improving the process window of polysilicon etching and dielectric layer filling in Nor Flash. The method improves the process window of polysilicon etching and dielectric layer filling in Nor Flash by applying an underlayer anti-reflection coating before etching the polysilicon layer and using a back-etching process to reduce the polysilicon layer of the Nor Flash memory area, while reducing the height difference at the boundary between the Nor Flash memory area and the peripheral area.

[0009] Optionally, the method for improving the process window for polysilicon etching and dielectric layer filling in Nor Flash includes:

[0010] Step S1: Before etching the polysilicon layer of the Nor Flash, an underlayer anti-reflection coating is applied to the polysilicon layer of the storage area and the peripheral area of ​​the Nor Flash to achieve surface planarization.

[0011] Step S2: Coat a photoresist layer on the bottom anti-reflection coating of the Nor Flash, and develop and expose the photoresist layer of the Nor Flash storage area. The photoresist layer located in the peripheral area of ​​the Nor Flash protects the peripheral area.

[0012] Step S3: Harden the bottom anti-reflective coating of the storage area using a plasma process;

[0013] Step S4: Etch the surface of the hardened bottom anti-reflective coating;

[0014] Step S5: Further cure the bottom anti-reflective coating after etching, and form a cured protective layer in the recessed area of ​​the NorFlash;

[0015] Step S6: Use a mixture of sulfur hexafluoride gas, nitrogen gas, carbon tetrafluoride gas, and helium gas to etch and open the oxide layer on the surface of the polycrystalline silicon layer;

[0016] Step S7: Etch back the polysilicon layer of the Nor Flash memory region to reduce the thickness of the polysilicon layer of the Nor Flash memory region;

[0017] Step S8: Remove the bottom anti-reflective coating and the photoresist layer of the outer periphery of the Nor Flash recessed area to obtain a flattened interface.

[0018] Optionally, in step S3, the plasma process gas used to harden the bottom anti-reflective coating is hydrogen bromide gas with a flow rate of 50–150 sccm, the power provided by the energy source is 800–1200 W, and the surface hardening treatment time is 5–10 s.

[0019] Optionally, in step S4, the process gas used for etching the surface of the bottom anti-reflective coating is carbon tetrafluoride gas with a flow rate of 50-100 sccm, a power source providing 200-300 W, a bias voltage of 200-300 V, and an etching time of 15-20 s.

[0020] Optionally, in step S5, the bottom anti-reflective coating after etching is further cured. The plasma process gas is hydrogen bromide gas with a flow rate of 50-150 sccm, the power provided by the energy source is 800-1200W, and the surface hardening treatment time is 5-10s.

[0021] Optionally, in step S6, the flow rate of sulfur hexafluoride gas is 10-15 sccm, the flow rate of nitrogen gas is 10-15 sccm, the flow rate of carbon tetrafluoride gas is 50-100 sccm, the flow rate of helium gas is 300-500 sccm, the power provided by the plasma process energy source is 150-200W, the bias voltage is 100-200V, and the etching time is 5s.

[0022] Optionally, in step S7, a dry plasma process is used to etch the polycrystalline silicon layer. The process gases for the dry plasma process are hydrogen bromide gas with a flow rate of 100-150 sccm, oxygen gas with a flow rate of 2-6 sccm, and chlorine gas with a flow rate of 30-50 sccm. The power provided by the plasma process energy source is 200-300W, the bias voltage is 50-100V, and the etching time is 10-15s.

[0023] Optionally, in step S8, oxygen is used to remove the bottom anti-reflective coating and the photoresist layer in the peripheral area of ​​the Nor Flash recessed region.

[0024] In summary, the method of improving the process window for polysilicon etching and dielectric layer filling in Nor Flash according to the present invention involves applying an anti-reflective coating before etching the polysilicon layer and using a back-etching process to reduce the polysilicon layer in the Nor Flash memory region. At the same time, it reduces the height difference at the boundary between the Nor Flash memory region and the peripheral region. This not only avoids polysilicon etching residue caused by excessive height difference during polysilicon layer etching and expands the etching process window, but also reduces the aspect ratio between control gates by lowering the control gate (CG) height, thus expanding the process window for dielectric layer filling. Attached Figure Description

[0025] Figure 1 The diagram shows a flowchart of the method for improving the process window of polysilicon etching and dielectric layer filling in Nor Flash according to the present invention.

[0026] Figures 2(a) to 2(d) The diagram shows a phased structure of the method for improving the process window of polysilicon etching and dielectric layer filling in Nor Flash according to the present invention.

[0027] Figures 3(a) to 3(d) The diagram shows a structure in which polysilicon residue is generated on a silicon substrate after etching of an existing polysilicon layer. Detailed Implementation

[0028] To explain in detail the technical content, structural features, objectives, and effects of this invention, the following will provide a detailed description in conjunction with embodiments and accompanying drawings.

[0029] Please see Figure 1 , Figure 1 The diagram shows a flowchart of the method for improving the process window of polysilicon etching and dielectric layer filling in Nor Flash according to the present invention. In this invention, the method for improving the process window of polysilicon etching and dielectric layer filling in Nor Flash involves applying an underlayer anti-reflection coating before etching the polysilicon layer and using a back-etching process to reduce the thickness of the polysilicon layer in the Nor Flash memory region, while simultaneously reducing the height difference at the boundary between the Nor Flash memory region and the peripheral region. Clearly, by using a back-etching process to reduce the thickness of the polysilicon layer in the Nor Flash memory region, not only can polysilicon etching residue be avoided due to excessive height difference during polysilicon layer etching, thus expanding the etching process window, but the reduction in the control gate (CG) height also decreases the aspect ratio between control gates, further expanding the process window for dielectric layer filling.

[0030] Please continue reading. Figure 1 and in conjunction with reference Figures 2(a) to 2(d) , Figures 2(a) to 2(d)The diagram shows a phased structural schematic of the method for improving the polysilicon etching and dielectric layer filling process window of Nor Flash according to the present invention. The Nor Flash includes a silicon substrate 10, a shallow trench isolation structure 11 formed within the silicon substrate 10, a gate oxide layer 121, a floating gate 122, and an ONO dielectric layer 123 located in the storage region 12 of the Nor Flash, and a polysilicon layer 14 located in the storage region 12 and the peripheral region 13. All structural layers are fabricated using conventional processes and will not be described in detail here. The method for improving the polysilicon etching and dielectric layer filling process window of Nor Flash includes:

[0031] Step S1: Before etching the polysilicon layer 14 of the Nor Flash, an underlayer anti-reflection coating 15 is applied to the polysilicon layer 14 of the storage area 12 and the peripheral area 13 of the Nor Flash to achieve surface planarization.

[0032] Step S2: A photoresist layer 16 is coated on the bottom anti-reflection coating 15 of the Nor Flash, and the photoresist layer of the storage area 12 of the Nor Flash is developed and exposed. The photoresist layer 16 located in the peripheral area 13 of the Nor Flash protects the peripheral area 13.

[0033] Step S3: Harden the bottom anti-reflective coating 15 of the storage area 12 using a plasma process;

[0034] In this embodiment, the process gas for the plasma process is hydrogen bromide gas, and the flow rate of the hydrogen bromide gas is 50-150 sccm. With the energy source of the plasma process providing 800-1200W of power, the hydrogen bromide gas is converted into bromide ions and hydrogen ions. The bromide ions and hydrogen ions bombard the surface of the bottom anti-reflective coating 15, and the surface of the anti-reflective coating 15 is hardened for 5-10 seconds.

[0035] Step S4: Etch the surface of the hardened bottom anti-reflective coating 15;

[0036] In this embodiment, the process gas used in the etching process is carbon tetrafluoride gas, the flow rate of the carbon tetrafluoride gas is 50-100 sccm, the power provided by the plasma process energy source is 200-300W, the bias voltage is 200-300V, and the etching time is 15-20s.

[0037] Step S5: Further cure the bottom anti-reflective coating 15 after etching, and form a cured protective layer 151 in the recessed area 17 of the Nor Flash;

[0038] In this embodiment, the cured protective layer 151 further protects the recessed area 17 of the Nor Flash. The process gas used in the plasma process is hydrogen bromide gas, with a flow rate of 50–150 sccm. With the plasma process energy source providing 800–1200 W of power, the hydrogen bromide gas is converted into bromide ions and hydrogen ions. These bromide ions and hydrogen ions bombard the surface of the bottom anti-reflective coating 15, and the surface of the anti-reflective coating undergoes a hardening treatment for 5–10 seconds.

[0039] Step S6: Using a mixture of sulfur hexafluoride gas, nitrogen gas, carbon tetrafluoride gas, and helium gas, the surface oxide layer of the polycrystalline silicon layer 14 is etched open.

[0040] In this embodiment, the flow rate of sulfur hexafluoride gas is 10-15 sccm, the flow rate of nitrogen gas is 10-15 sccm, the flow rate of carbon tetrafluoride gas is 50-100 sccm, the flow rate of helium gas is 300-500 sccm, the power provided by the plasma process energy source is 150-200W, the bias voltage is 100-200V, and the etching time is 5s.

[0041] Step S7: The polysilicon layer 14 of the Nor Flash memory region 12 is etched back to reduce the thickness of the polysilicon layer 14 of the Nor Flash memory region 12;

[0042] In this embodiment, the polycrystalline silicon layer 14 is etched using a dry plasma process. The process gases used in the dry plasma process are hydrogen bromide gas with a flow rate of 100-150 sccm, oxygen gas with a flow rate of 2-6 sccm, and chlorine gas with a flow rate of 30-50 sccm. The power provided by the plasma process energy source is 200-300W, the bias voltage is 50-100V, and the etching time is 10-15s.

[0043] Step S8: Remove the bottom anti-reflective coating 15 and the photoresist layer 16 of the outer periphery of the Nor Flash recessed area 17 to obtain a flattened interface.

[0044] In this embodiment, oxygen is used to remove the bottom anti-reflective coating 15 and the photoresist layer 16 of the outer periphery of the Nor Flash recessed region 17.

[0045] In summary, the method of improving the process window for polysilicon etching and dielectric layer filling in Nor Flash according to the present invention involves applying an anti-reflective coating before etching the polysilicon layer and using a back-etching process to reduce the polysilicon layer in the Nor Flash memory region. At the same time, it reduces the height difference at the boundary between the Nor Flash memory region and the peripheral region. This not only avoids polysilicon etching residue caused by excessive height difference during polysilicon layer etching and expands the etching process window, but also reduces the aspect ratio between control gates by lowering the control gate (CG) height, thus expanding the process window for dielectric layer filling.

[0046] Those skilled in the art will understand that various modifications and variations can be made to this invention without departing from its spirit or scope. Therefore, if any modification or variation falls within the scope of the appended claims and their equivalents, the invention is considered to cover such modifications and variations.

Claims

1. A method for improving the process window for polysilicon etching and dielectric layer filling in Nor Flash, characterized in that, The method for improving the process window of polysilicon etching and dielectric layer filling in Nor Flash involves coating an underlayer anti-reflection coating before etching the polysilicon layer and using a back-etching process to reduce the polysilicon layer in the Nor Flash memory area, while reducing the height difference at the junction of the Nor Flash memory area and the peripheral area. The method for improving the polysilicon etching and dielectric layer filling process window of Nor Flash includes: performing step S1: before etching the polysilicon layer of Nor Flash, coating an underlayer anti-reflection layer on the polysilicon layer of the storage region and the peripheral region of Nor Flash to achieve surface planarization; performing step S2: coating a photoresist layer on the underlayer anti-reflection layer of Nor Flash, and developing and revealing the photoresist layer of the storage region of Nor Flash, with the photoresist layer located in the peripheral region of Nor Flash protecting the peripheral region; performing step S3: using a plasma process to harden the bottom anti-reflection coating of the storage region; Step S4: Etch the surface of the hardened bottom anti-reflective coating; Step S5: Further cure the etched bottom anti-reflective coating and form a cured protective layer in the recessed area of ​​the Nor Flash; Step S6: Use a mixed gas of sulfur hexafluoride, nitrogen, carbon tetrafluoride, and helium to etch and open the oxide layer on the surface of the polysilicon layer; Step S7: Etch back the polysilicon layer of the Nor Flash storage area to reduce the thickness of the polysilicon layer of the Nor Flash storage area; Step S8: Remove the bottom anti-reflective coating and the photoresist layer in the peripheral area of ​​the Nor Flash recessed area to obtain a planarized interface.

2. The method for improving the process window of polysilicon etching and dielectric layer filling in Nor Flash as described in claim 1, characterized in that, In step S3, the plasma process gas used to harden the bottom anti-reflective coating is hydrogen bromide gas with a flow rate of 50-150 sccm, the power provided by the energy source is 800-1200W, and the surface hardening treatment time is 5-10s.

3. The method for improving the process window of polysilicon etching and dielectric layer filling in Nor Flash as described in claim 1, characterized in that, In step S4, the process gas used for etching the surface of the bottom anti-reflective coating is carbon tetrafluoride gas with a flow rate of 50-100 sccm, a power source of 200-300W, a bias voltage of 200-300V, and an etching time of 15-20s.

4. The method for improving the process window of polysilicon etching and dielectric layer filling in Nor Flash as described in claim 1, characterized in that, In step S5, the bottom anti-reflective coating after etching is further cured. The plasma process gas is hydrogen bromide gas with a flow rate of 50-150 sccm. The power provided by the energy source is 800-1200W. The surface hardening treatment time is 5-10s.

5. The method for improving the process window of polysilicon etching and dielectric layer filling in Nor Flash as described in claim 1, characterized in that, In step S6, the flow rate of sulfur hexafluoride gas is 10-15 sccm, the flow rate of nitrogen gas is 10-15 sccm, the flow rate of carbon tetrafluoride gas is 50-100 sccm, the flow rate of helium gas is 300-500 sccm, the power provided by the plasma process energy source is 150-200W, the bias voltage is 100-200V, and the etching time is 5s.

6. The method for improving the process window of polysilicon etching and dielectric layer filling in Nor Flash as described in claim 1, characterized in that, In step S7, the polycrystalline silicon layer is etched using a dry plasma process. The process gases for the dry plasma process are hydrogen bromide gas with a flow rate of 100-150 sccm, oxygen gas with a flow rate of 2-6 sccm, and chlorine gas with a flow rate of 30-50 sccm. The power provided by the plasma process energy source is 200-300W, the bias voltage is 50-100V, and the etching time is 10-15s.

7. The method for improving the process window of polysilicon etching and dielectric layer filling in Nor Flash as described in claim 1, characterized in that, In step S8, oxygen is used to remove the bottom anti-reflective coating and the photoresist layer in the outer area of ​​the Nor Flash recessed region.

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