biquad filter

Abstract

The present invention relates to a biquad filter capable of independently adjusting each parameter. In the biquad filter of the embodiment, an output terminal of a first integrator is connected to an input terminal of a negative side of a second integrator, the output terminal of the first integrator is connected to a first input of a negative side of an adder via an inverting amplifier, an output terminal of the second integrator is connected to a second input terminal of the negative side of the adder, an input terminal for inputting an input signal is connected to a third input terminal of the negative side of the first adder, and an output terminal of the adder is connected to an input terminal of a negative side of the first integrator.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2020-148331 (filed on September 3, 2020). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] The embodiments of the present invention relate to a dual second-order filter. Background Technology

[0003] In recent years, filters have been developed for use in communication equipment and other applications to remove unwanted signals.

[0004] In traditional bi-second-order filters, parameters such as center frequency, cutoff frequency, sharpness, or pass gain are adjusted by changing the capacitance values ​​of the capacitors and the resistance values ​​of the resistors included in the bi-second-order filter.

[0005] However, given the need to reduce chip area in semiconductor integrated circuits, it is preferable to adjust the parameters solely by the resistance value of the resistors. However, when adjusting parameters solely by the resistance value of the resistors, a problem arises where changing the resistance value associated with a specified parameter (e.g., frequency) causes other parameters (e.g., sharpness) to also change. Summary of the Invention

[0006] This embodiment provides a dual second-order filter that can independently adjust each parameter.

[0007] One embodiment of a dual second-order filter includes: a first integrator including a first operational amplifier, a first variable resistor and a first capacitor connected to the first operational amplifier; a second integrator including a second operational amplifier, a second variable resistor and a second capacitor connected to the second operational amplifier; an adder including a third operational amplifier and a plurality of resistors connected to the third operational amplifier; and an inverting amplifier with a gain of 1x. The output terminal of the first integrator is connected to the input terminal on the negative side of the second integrator, the output terminal of the first integrator is connected to the first input terminal on the negative side of the adder via the inverting amplifier, the output terminal of the second integrator is connected to the second input terminal on the negative side of the adder, an input terminal for inputting an input signal is connected to the third input terminal on the negative side of the adder, and the output terminal of the adder is connected to the input terminal on the negative side of the first integrator. Attached Figure Description

[0008] Figure 1 This is a circuit diagram showing the dual second-order filter of implementation method 1.

[0009] Figure 2This is a diagram used to illustrate the operation of the double second-order filter as a bandpass filter in Embodiment 1.

[0010] Figure 3 This is a diagram used to illustrate the operation of the double second-order filter as a low-pass filter in Embodiment 1.

[0011] Figure 4 This is a diagram used to illustrate the operation of the double second-order filter as a high-pass filter in Embodiment 1.

[0012] Figure 5 (A) and (B) are circuit diagrams representing the variable resistor and its regulator.

[0013] Figure 6 This is a circuit diagram illustrating another configuration example of the dual second-order filter in Embodiment 1.

[0014] Figure 7 This is a circuit diagram representing the dual second-order filter of implementation method 2. Detailed Implementation

[0015] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, the disclosed examples are merely illustrative, and appropriate modifications that maintain the spirit of the invention will readily occur to those skilled in the art, and are of course included within the scope of the present invention. In addition, to make the description clearer, the drawings sometimes schematically show the width, thickness, shape, etc. of various parts compared to the actual form, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and the various drawings, sometimes the same symbols are used for elements that are the same as those described with respect to previously presented figures, and detailed descriptions are appropriately omitted.

[0016] Hereinafter, a detailed description of one embodiment of a bi-second-order filter will be provided with reference to the accompanying drawings.

[0017] [Implementation Method 1]

[0018] Figure 1 This is a circuit diagram showing the dual second-order filter of implementation method 1. Figure 1 The dual second-order filter FC shown has operational amplifiers OP1, OP2, OP3, resistors R1, R2, R3, R4, R5, R6, capacitors C1 and C2, and an inverting amplifier ROP with a gain of 1. Figure 1 The dual second-order filter FC shown has an input terminal VI, an output terminal VB of a bandpass filter, an output terminal VL of a low-pass filter, and an output terminal VH of a high-pass filter.

[0019] The dual second-order filter FC in this embodiment includes a first integrator ITG1, a second integrator ITG2, an adder ADD, and an inverting amplifier ROP with a gain of 1. Figure 1 In the dual second-order filter FC shown, the first integrator ITG1 includes operational amplifier OP1, resistor R3, and capacitor C1. The second integrator ITG2 includes operational amplifier OP2, resistor R2, and capacitor C2. The adder ADD includes operational amplifier OP3 and multiple resistors, specifically resistors R1, R4, R5, and R6.

[0020] The output terminal Toi1 of the first integrator ITG1 is connected to the output terminal VB. The output terminal Toi1 of the first integrator ITG1 is connected to the input terminal Tiin2 on the negative side of the second integrator ITG2. The output terminal Toi1 of the first integrator ITG1 is connected to the first input terminal Tian1 on the negative side of the adder ADD via the inverting amplifier ROP.

[0021] The output terminal Toi2 of the second integrator ITG2 is connected to the output terminal VL. The output terminal Toi2 of the second integrator ITG2 is connected to the second input terminal Tian2 on the negative side of the adder ADD.

[0022] The input terminal VI, used for inputting input signals, is connected to the third input terminal Tian3 on the negative side of the adder ADD. The output terminal Toa of the adder ADD is connected to the output terminal VH. The output terminal Toa of the adder ADD is connected to the input terminal Tiin1 on the negative side of the first integrator ITG1.

[0023] The positive input terminal Tip1 of the first integrator ITG1, the positive input terminal Tip2 of the second integrator ITG2, and the positive input terminal Tip of the adder ADD are grounded.

[0024] exist Figure 1 In the illustrated dual second-order filter FC, resistors R1, R2, R3, R4, R5, and R6 are variable resistors. The resistance values ​​of resistors R2 and R3 vary based on an external control signal CT1. The resistance value of resistor R1 varies based on an external control signal CT2. The resistance value of resistor R4 varies based on an external control signal CT3. The resistance values ​​of resistors R5 and R6 vary based on an external control signal CT4.

[0025] Alternatively, only resistors R2 and R3 can be variable resistors, while the other resistors, namely R1, R4, R5, and R6, are fixed resistors. Details will be discussed later.

[0026] In this embodiment, operational amplifier OP1, variable resistor R3, and capacitor C1 are sometimes referred to as the first operational amplifier, the first variable resistor, and the first capacitor, respectively. Operational amplifier OP2, variable resistor R2, and capacitor C2 are sometimes referred to as the second operational amplifier, the second variable resistor, and the second capacitor, respectively. Operational amplifier OP3 is sometimes referred to as the third operational amplifier. The resistors R1, R5, and R4 of adder ADD are sometimes referred to as the third resistor, the fourth resistor, and the fifth resistor, or the first resistor, the second resistor, and the third resistor of adder ADD, respectively.

[0027] In the following description, the resistance values ​​of resistors R1, R2, R3, R4, R5, and R6 are set as resistance values ​​R1, R2, R3, R4, R5, and R6, respectively. Similarly, the capacitance values ​​of capacitors C1 and C2 are set as capacitance values ​​C1 and C2, respectively.

[0028] Specifically, the output terminal Ot1 of operational amplifier OP1 is connected to one terminal of capacitor C1, one terminal of resistor R2, output terminal VB, and the input terminal of inverting amplifier ROP. The negative input terminal In1 of operational amplifier OP1 is connected to the other terminal of capacitor C1 and one terminal of resistor R3. The positive input terminal Ip1 of operational amplifier OP1 is grounded.

[0029] The output terminal Ot2 of operational amplifier OP2 is connected to one terminal of capacitor C2, one terminal of resistor R5, and the output terminal VL. The negative input terminal In2 of operational amplifier OP2 is connected to the other terminal of resistor R2 and the other terminal of capacitor C2. The positive input terminal Ip2 of operational amplifier OP2 is grounded.

[0030] The output terminal Ot3 of operational amplifier OP3 is connected to one terminal of resistor R6, the other terminal of resistor R3, and the output terminal VH. The input terminal In3 on the negative side of operational amplifier OP3 is connected to the other terminal of resistor R6, the other terminal of resistor R5, one terminal of resistor R4, and one terminal of resistor R1. The input terminal Ip3 on the positive side of operational amplifier OP3 is grounded.

[0031] The output terminal of the inverting amplifier ROP is connected to the other terminal of resistor R1.

[0032] The other terminal of resistor R4 is connected to input terminal VI.

[0033] The output terminal Toi1 of the first integrator ITG1 is connected to the output terminal Ot1 of operational amplifier OP1, one terminal of capacitor C2, one terminal of resistor R2, the input terminal of inverting amplifier ROP, and the output terminal VB. The negative input terminal Tiin1 of the first integrator ITG1 includes the other terminal of resistor R3 and is connected to the negative input terminal In1 of operational amplifier OP1 via resistor R3.

[0034] The output terminal Toi2 of the second integrator ITG2 is connected to the output terminal Ot2 of the operational amplifier OP2, one terminal of capacitor C2, one terminal of resistor R5, and the output terminal VL. The input terminal Tiin2 on the negative side of the second integrator ITG2 includes one terminal of resistor R2 and is connected to the input terminal In2 on the negative side of the operational amplifier OP2 via resistor R2.

[0035] The output terminal Toa of adder ADD is connected to the output terminal Ot3 of operational amplifier OP3, one terminal of resistor R6, the other terminal of resistor R3, and the output terminal VH. The first input terminal Tian1 on the negative side of adder ADD includes the other terminal of resistor R1. The second input terminal on the negative side of adder ADD includes one terminal of resistor R5. The third input terminal on the negative side of adder ADD includes the other terminal of resistor R4. The first input terminal Tian1, the second input terminal Tian2, and the third input terminal Tian3 on the negative side of adder ADD are connected to the input terminal In3 on the negative side of operational amplifier OP3 via resistors R1, R5, and R4, respectively.

[0036] Furthermore, it can be said that the output terminals Toi1 of the first integrator ITG1, Toi2 of the second integrator ITG2, and Toa of the adder ADD respectively correspond to the output terminals Ot1 of operational amplifier OP1, Ot2 of operational amplifier OP2, and Ot3 of operational amplifier OP3. This is because the signals output from the output terminals of the first integrator ITG1, the second integrator ITG2, and the adder ADD are equivalent to the signals output from the output terminals of operational amplifier OP1, operational amplifier OP2, and operational amplifier OP3, respectively. Figure 2 This is a diagram illustrating the operation of the dual second-order filter FC as a bandpass filter in Embodiment 1. Figure 1 In the above, when the signal input to the input terminal VI is set as vI and the signal output from the output terminal VB is set as vB, the transfer function of the bandpass filter becomes (Equation 1).

[0037]

[0038] In Equation 1, ω0 represents the center frequency, Q represents the sharpness, and H represents the pass gain.

[0039] In Equation 1, when C1 = C2 = C12, R2 = R3 = R23, R5 = R6 = R56, the transfer function, center frequency ω0, sharpness Q, and parameters through gain H can be represented by Equation 2.

[0040]

[0041]

[0042] The frequency characteristics based on the transfer function shown in (Equation 2) are... Figure 2 This is represented by curve PL1. Figure 2 In the diagram, the horizontal axis represents angular frequency ω, and the horizontal axis represents gain Gain.

[0043] Here, we consider the case where the center frequency ω0 is adjusted by changing the value of resistor R23. The resistor value R23 is not included in the sharpness Q and gain H shown in Equation 2. Figure 2 The curve PL2 represents the frequency response when only the center frequency ω0 is adjusted.

[0044] Figure 2 The resistance value R23 in curve PL2 is, for example, smaller than the resistance value R23 in curve PL1. When comparing curve PL1 with resistance value R23a and curve PL2 with resistance value R23b, the center frequency ω0 in curve PL2 shifts towards the higher frequency side. That is, when the resistance value R23 is decreased, the center frequency ω0 shifts towards the higher frequency side.

[0045] As shown in curve PL2, adjusting only the center frequency ω0 does not affect other parameters (sharpness Q, pass gain H). That is, the center frequency ω0 can be adjusted independently.

[0046] Similarly, when adjusting the sharpness Q, changing the value of resistor R1 does not affect the center frequency ω0 or the parameters of gain H. Figure 2 Curve PL3 represents the frequency response when the sharpness Q is adjusted. The resistance value R1 in curve PL3 is, for example, greater than the resistance value R1 in curve PL1. As shown in curve PL3, the sharpness Q can be adjusted independently.

[0047] Similarly, when adjusting the gain H, changing the resistance value R4 does not affect the parameters of center frequency ω0 and sharpness Q. Figure 2Curve PL4 represents the frequency response with the gain H adjusted. The resistance value R4 in curve PL4 is, for example, smaller than the resistance value R4 in curve PL1. As shown in curve PL4, the gain H can be adjusted independently.

[0048] exist Figure 1 In the above, when the signal input to the input terminal VI is set as vI and the signal output from the output terminal VL is set as vL, the transfer function of the low-pass filter becomes (Equation 3).

[0049]

[0050] In Equation 3, ω0 represents the cutoff frequency, Q represents the sharpness, and H represents the pass gain.

[0051] In Equation 3, when C1 = C2 = C12, R2 = R3 = R23, R5 = R6 = R56, the transfer function, cutoff frequency ω0, sharpness Q, and parameters through gain H can be represented by Equation 4.

[0052]

[0053]

[0054] Figure 3 This is a diagram used to illustrate the operation of the dual second-order filter FC as a low-pass filter in Embodiment 1.

[0055] Here, we consider the case where the cutoff frequency ω0 is adjusted by changing the resistance value R23. Figure 3 Curve PL2 represents the frequency response when only the cutoff frequency ω0 is adjusted. The resistance value R23 in curve PL2 is, for example, smaller than the resistance value R23 in curve PL1. The resistance value R23 is not included in the formulas for sharpness Q and gain H. Therefore, it does not affect these parameters, and the cutoff frequency ω0 can be adjusted independently.

[0056] Similarly, when adjusting the sharpness Q, by changing the resistance value R1, the sharpness Q can be adjusted independently without affecting the cutoff frequency ω0 or the parameters of the gain H. Figure 3 Curve PL3 represents the frequency response when the sharpness Q is adjusted. The resistance value R1 in curve PL3 is, for example, greater than the resistance value R1 in curve PL1. As shown in curve PL3, the sharpness Q can be adjusted independently.

[0057] Similarly, when adjusting the pass gain H, by changing the resistance value R4, the pass gain H can be adjusted independently without affecting the parameters of cutoff frequency ω0 and sharpness Q. Figure 3Curve PL4 represents the frequency response with the gain H adjusted. The resistance value R4 in curve PL4 is, for example, smaller than the resistance value R4 in curve PL1. As shown in curve PL4, the gain H can be adjusted independently.

[0058] exist Figure 1 In the above, when the signal input to the input terminal VI is set as vI and the signal output from the output terminal VH is set as vH, the transfer function of the high-pass filter becomes (Equation 5).

[0059]

[0060] In Equation 5, ω0 represents the cutoff frequency, Q represents the sharpness, and H represents the pass gain.

[0061] In Equation 5, when C1 = C2 = C12, R2 = R3 = R23, R5 = R6 = R56, the parameters of the transfer function, cutoff frequency ω0, sharpness Q, and pass gain H can be represented by Equation 6.

[0062]

[0063]

[0064] Figure 4 This is a diagram used to illustrate the operation of the dual second-order filter FC as a high-pass filter in Embodiment 1.

[0065] Here, we consider the case where the cutoff frequency ω0 is adjusted by changing the resistance value R23. The resistance value R23 is not included in the formulas for sharpness Q and gain H. Therefore, it does not affect these parameters, and the cutoff frequency ω0 can be adjusted independently. Figure 4 Curve PL2 represents the frequency response when only the cutoff frequency ω0 is adjusted. The resistance value R23 in curve PL2 is, for example, smaller than the resistance value R23 in curve PL1. The resistance value R23 is not included in the formulas for sharpness Q and gain H. Therefore, it does not affect these parameters, and the cutoff frequency ω0 can be adjusted independently.

[0066] Similarly, when adjusting the sharpness Q, by changing the resistance value R1, the sharpness Q can be adjusted independently without affecting the cutoff frequency ω0 or the parameters of the gain H. Figure 4 Curve PL3 represents the frequency response when the sharpness Q is adjusted. The resistance value R1 in curve PL3 is, for example, greater than the resistance value R1 in curve PL1. As shown in curve PL3, the sharpness Q can be adjusted independently.

[0067] Similarly, when adjusting the pass gain H, by changing the value of resistor R4, the parameters of cutoff frequency ω0 and sharpness Q can be adjusted independently. Figure 4 Curve PL4 represents the frequency response with the gain H adjusted. The resistance value R4 in curve PL4 is, for example, smaller than the resistance value R4 in curve PL1. As shown in curve PL4, the gain H can be adjusted independently.

[0068] Here, we will explain the variable resistor and its regulator that change the resistance value according to the control signal CT. Figure 5 This is a circuit diagram representing a variable resistor and its regulator. Figure 5 (A) represents a variable resistor and its regulator when resistors are connected in series. Figure 5 (B) represents a variable resistor and its regulator when resistors are connected in parallel.

[0069] exist Figure 5 In the example shown in (A), the variable resistor VRa has resistors Ra0, Ra1, Ra2 to Raz. For each of the series-connected resistors Ra1, Ra2 to Raz, there are switches Swa1, Swa2 to Swaz connected in parallel. Here, switches Swa1, Swa2 to Swaz are used as regulator ADJ. When a control signal CT is input to regulator ADJ, the switch corresponding to the control signal CT becomes closed.

[0070] For example, when switches SWA1 and SWA2 are in the open state and other switches are in the closed state, Figure 5 In the example shown in (A), the combined resistance value SRa of the variable resistor VRa is SRa=Ra0+Ra1+Ra2. Thus, by controlling the on and off states of the regulator ADJ according to the control signal CT, the combined resistance value of the variable resistor VRa can be changed.

[0071] exist Figure 5 In the example shown in (B), as described above, resistors Rb0, Rb1, Rb2 to Rbz are connected in parallel. For each of resistors Rb1, Rb2 to Rbz, switches Swb1, Swb2 to Swbz are connected in series. Figure 5 Similarly, in (A), switches Swb1, Swb2 to Swbz are used as regulator ADJ. When a control signal CT is input to regulator ADJ, the switch corresponding to the control signal CT becomes closed.

[0072] For example, when switches SWb1 and SWb2 are in the ON state and the other switches are in the OFF state, Figure 5In the example shown in (B), the combined resistance value SRb of the variable resistor VRb satisfies (1 / SRb) = (1 / Rb0) + (1 / Rb1) + (1 / Rb2). Therefore, the combined resistance value SRb becomes SRb = (Rb0 × Rb1 × Rb2) / {(Rb1 × Rb2) + (Rb0 × Rb2) + (Rb0 × Rb1)}. Thus, by controlling the on and off states of the regulator ADJ according to the control signal CT, the combined resistance value of the variable resistor VRb can be changed.

[0073] In addition, Figure 5 In (A) and (B), the cases of connecting resistors in series and the cases of connecting resistors in parallel are described separately, but the variable resistor in this embodiment is not limited to these. The variable resistor in this embodiment may also include resistors connected in series and in parallel, and their regulators.

[0074] In the dual second-order filter of this embodiment, when adjusting parameters such as frequency ω0 (cutoff frequency ω0 or center frequency ω0), sharpness Q, and pass gain H by changing predetermined resistor values, it is not necessary to change the resistance values ​​of resistors that are not directly related to the parameters to be adjusted. Therefore, each parameter can be adjusted independently.

[0075] <Example of composition>

[0076] Figure 6 This is a circuit diagram illustrating another configuration example of the dual second-order filter in Embodiment 1. Figure 6 The difference in the configuration example shown is that a portion of the variable resistors are set as fixed resistors.

[0077] exist Figure 6 In the double second-order filter FC shown, Figure 1 Resistors R1, R4, R5, and R6 shown have been replaced with fixed resistors. That is, resistors R2 and R3 are variable resistors.

[0078] exist Figure 6 The example shown is suitable for cases where the frequency ω0 (center frequency, cutoff frequency) is adjusted primarily and independently. As mentioned above, the frequency ω0 can be adjusted by changing resistors R2 and R3 (R2 and R3). That is, in Figure 6 In the example shown, the frequency ω0 can be adjusted without changing the resistance value of the resistors that are related to other parameters.

[0079] [Implementation Method 2]

[0080] Figure 7 This is a circuit diagram illustrating the dual second-order filter of implementation method 2. Figure 7 In the double second-order filter shown, with Figure 1Compared to the dual second-order filter shown, the difference is that the whole is configured as a differential filter without an inverting amplifier.

[0081] The dual second-order filter FC has a fully differential operational amplifier DOP1, a fully differential operational amplifier DOP2, a fully differential operational amplifier DOP3, resistors R1A, R2A, R3A, R4A, R5A, R6A, R1B, R2B, R3B, R4B, R5B, R6B, capacitors C1A, C2A, C1B, and C2B.

[0082] The dual second-order filter FC has an input terminal VI1 on the positive side, an input terminal VI2 on the negative side, an output terminal VB1 on the positive side and an output terminal VB2 on the negative side of the bandpass filter, an output terminal VL1 on the positive side and an output terminal VL2 on the negative side of the low-pass filter, an output terminal VH1 on the positive side and an output terminal VH2 on the negative side of the high-pass filter.

[0083] The dual second-order filter FC of this embodiment includes a first integrator ITG1, a second integrator ITG2, and an adder ADD. The first integrator ITG1 includes a fully differential operational amplifier DOP1, resistors R3A and R3B, and capacitors C1A and C1B. The second integrator ITG2 includes a fully differential operational amplifier DOP2, resistors R2A and R2B, and capacitors C2A and C2B. The adder ADD includes a fully differential operational amplifier DOP3, resistors R1A, R4A, R5A, R6A, R1B, R4B, R5AB, and R6A.

[0084] The output terminal Toip1 on the positive side of the first integrator ITG1 is connected to the output terminal VB1. The output terminal Toip1 on the positive side of the first integrator ITG1 is connected to the input terminal Tiin2 on the negative side of the second integrator ITG2. The output terminal Toip1 on the positive side of the first integrator ITG1 is connected to the first input terminal Tip1 on the positive side of the adder ADD.

[0085] The output terminal Toin1 on the negative side of the first integrator ITG1 is connected to the output terminal VB2. The output terminal Toin1 on the negative side of the first integrator ITG1 is connected to the input terminal Tiip2 on the positive side of the second integrator ITG2. The output terminal Toin1 on the negative side of the first integrator ITG1 is connected to the first input terminal Tian1 on the negative side of the adder ADD.

[0086] The positive output terminal Toip2 of the second integrator ITG2 is connected to the output terminal VL1. The positive output terminal Toip2 of the second integrator ITG2 is connected to the second input terminal Tian2 of the negative side of the adder ADD.

[0087] The negative output terminal Toin2 of the second integrator ITG2 is connected to the output terminal VL2. The negative output terminal Toin2 of the second integrator ITG2 is connected to the second input terminal Tip2 of the positive side of the adder.

[0088] The input terminal VI1, which receives either the positive or negative phase of the differential input signal, is connected to the third input terminal Tian3 on the negative side of the adder ADD. The input terminal VI2, which receives the other phase of the differential input signal, is connected to the third input terminal Tip3 on the positive side of the adder ADD. Sometimes, input terminals VI1 and VI2 are also referred to as the first and second input terminals of the dual second-order filter FC, respectively.

[0089] The positive output terminal Toap of adder ADD is connected to the output terminal VH1. The positive output terminal Toap of adder ADD is connected to the negative input terminal Tiin1 of the first integrator ITG1. The negative output terminal Toan of adder ADD is connected to the output terminal VH2. The negative output terminal Toan of adder ADD is connected to the positive input terminal Tiip1 of the first integrator ITG1.

[0090] In the dual second-order filter FC, resistors R1A, R2A, R3A, R4A, R5A, R6A, R1B, R2B, R3B, R4B, R5B, and R6B are variable resistors. The resistance values ​​of resistors R2A, R3A, R2B, and R3B vary based on control signal CT1. The resistance values ​​of resistors R1A and R1B vary based on control signal CT2. The resistance values ​​of resistors R4A and R4B vary based on control signal CT3. The resistance values ​​of resistors R5A, R6A, R5B, and R6B vary based on control signal CT4.

[0091] In this embodiment, the fully differential operational amplifier DOP1 is referred to as the first fully differential operational amplifier. Resistors R3A and R3B, which are variable resistors, are collectively referred to as the first variable resistor. Capacitors C1A and C1B are collectively referred to as the first capacitor.

[0092] The fully differential operational amplifier DOP2 is referred to as the second fully differential operational amplifier. Resistors R2A and R2B, which are variable resistors, are collectively referred to as the second variable resistors. Capacitors C2A and C2B are collectively referred to as the second capacitors.

[0093] The fully differential operational amplifier DOP3 is referred to as the third fully differential operational amplifier. Sometimes, resistors R1A and R1B are collectively referred to as the first resistor of the adder ADD, resistors R5A and R5B are collectively referred to as the second resistor of the adder ADD, resistors R4A and R4B are collectively referred to as the third resistor of the adder ADD, and resistors R6A and R6B are collectively referred to as the fourth resistor of the adder ADD.

[0094] Sometimes, the positive output terminal VB1 and the negative output terminal VB2 of a bandpass filter are collectively referred to as the output terminals of the bandpass filter. Similarly, the positive output terminal VL1 and the negative output terminal VL2 of a low-pass filter are sometimes collectively referred to as the output terminals of the low-pass filter. And sometimes, the positive output terminal VH1 and the negative output terminal VH2 of a high-pass filter are collectively referred to as the output terminals of the high-pass filter.

[0095] However, when it is necessary to differentiate between resistors, capacitors, or output terminals, for example, resistor R3A can be designated as the first variable resistor and resistor R3B as the third variable resistor. Regarding resistors R2A and R2B, resistor R2A can be designated as the second variable resistor and resistor R2B as the fourth variable resistor. Similarly, capacitors C1A and C2A can be designated as the first and second capacitors, respectively, and capacitors C1B and C2B as the third and fourth capacitors, respectively.

[0096] Sometimes, resistors R1A, R5A, R4A, R6A, R4B, R5B, R1B, and R6B are designated as the 5th, 6th, 7th, 8th, 9th, 10th, 11th, and 12th resistors, respectively.

[0097] Specifically, the positive output terminal Op1 of the fully differential operational amplifier DOP1 is connected to one terminal of resistor R2A, one terminal of capacitor C1A, one terminal of resistor R1B, and the output terminal VB1. The negative output terminal On1 of the fully differential operational amplifier DOP1 is connected to one terminal of resistor R2B, one terminal of capacitor C1B, one terminal of resistor R1A, and the output terminal VB2.

[0098] The positive input terminal Ip1 of the fully differential operational amplifier DOP1 is connected to the other terminal of capacitor C1B and one terminal of resistor R3B. The negative input terminal In1 of the fully differential operational amplifier DOP1 is connected to the other terminal of capacitor C1A and one terminal of resistor R3A.

[0099] The positive output terminal Op2 of the fully differential operational amplifier DOP2 is connected to the output terminal VL1, one terminal of capacitor C2A, and one terminal of resistor R5A. The negative output terminal On2 of the fully differential operational amplifier DOP2 is connected to the output terminal VL2, one terminal of capacitor C2B, and one terminal of resistor R5B.

[0100] The positive input terminal Ip2 of the fully differential operational amplifier DOP2 is connected to the other terminal of capacitor C2B and the other terminal of resistor R2B. The negative input terminal In2 of the fully differential operational amplifier DOP2 is connected to the other terminal of capacitor C2A and the other terminal of resistor R2A.

[0101] The positive output terminal Op3 of the fully differential operational amplifier DOP3 is connected to output terminal VH1, one terminal of resistor R6A, and the other terminal of resistor R3A. The negative output terminal On3 of the fully differential operational amplifier DOP3 is connected to output terminal VH2, one terminal of resistor R6B, and the other terminal of resistor R3B.

[0102] The positive input terminal Ip3 of the fully differential operational amplifier DOP3 is connected to the other terminals of resistors R1B, R5B, R4B, and R6B. The negative input terminal In3 of the fully differential operational amplifier DOP3 is connected to the other terminals of resistors R1A, R5A, R4A, and R6A.

[0103] The other terminal of resistor R4A is connected to input terminal VI1. The other terminal of resistor R4B is connected to input terminal VI2.

[0104] The positive output terminal Toip1 of the first integrator ITG1 is connected to the positive output terminal Op1 of the fully differential operational amplifier DOP1, one terminal of resistor R2A, one terminal of capacitor C1A, one terminal of resistor R1B, and the output terminal VB1. The negative output terminal Toin1 of the first integrator ITG1 is connected to the negative output terminal On1 of the fully differential operational amplifier DOP1, one terminal of resistor R2B, one terminal of capacitor C1B, one terminal of resistor R1A, and the output terminal VB2.

[0105] The positive input terminal Tiip1 of the first integrator ITG1 includes another terminal of resistor R3B and is connected to the positive input terminal Ip1 of the fully differential operational amplifier DOP1 via resistor R3B. The negative input terminal Tiin1 of the first integrator ITG1 includes another terminal of resistor R3A and is connected to the negative input terminal In1 of the fully differential operational amplifier DOP1 via resistor R3A.

[0106] The positive output terminal Toip2 of the second integrator ITG2 is connected to the positive output terminal Op2, output terminal VL1, one terminal of capacitor C2A, and one terminal of resistor R5A of the fully differential operational amplifier DOP2. The negative output terminal Toin2 of the second integrator ITG2 is connected to the negative output terminal On2, output terminal VL2, one terminal of capacitor C2B, and one terminal of resistor R5B of the fully differential operational amplifier DOP2.

[0107] The positive input terminal Tiip2 of the second integrator ITG2 includes one terminal of resistor R2B, and is connected to the positive input terminal Ip2 of the fully differential operational amplifier DOP2 via resistor R2B. The negative input terminal Tiin2 of the second integrator ITG2 includes one terminal of resistor R2A, and is connected to the negative input terminal In2 of the fully differential operational amplifier DOP2 via resistor R2A.

[0108] The positive output terminal Toap of adder ADD is connected to the positive output terminal Op3, output terminal VH1, one terminal of resistor R6A, and the other terminal of resistor R3A of fully differential operational amplifier DOP3.

[0109] The output terminal Toan on the negative side of adder ADD is connected to the output terminal On3 on the negative side of fully differential operational amplifier DOP3, output terminal VH2, one terminal of resistor R6B, and the other terminal of resistor R3B.

[0110] The first input terminal Tip1 on the positive side of adder ADD includes one terminal of resistor R1B and is connected to the positive input terminal Ip3 of fully differential operational amplifier DOP3 via resistor R1B. The second input terminal Tip2 on the positive side of adder ADD includes one terminal of resistor R5B and is connected to the positive input terminal Ip3 of fully differential operational amplifier DOP3 via resistor R5B. The third input terminal Tip3 on the positive side of adder ADD includes the other terminal of resistor R4B and is connected to the positive input terminal Ip3 of fully differential operational amplifier DOP3 via resistor R4B.

[0111] The first input terminal Tian1 on the negative side of adder ADD includes one terminal of resistor R1A and is connected to the input terminal In3 on the negative side of fully differential operational amplifier DOP3 via resistor R1A. The second input terminal Tian2 on the negative side of adder ADD includes one terminal of resistor R5A and is connected to the input terminal In3 on the negative side of fully differential operational amplifier DOP3 via resistor R5A. The third input terminal Tian3 on the negative side of adder ADD includes the other terminal of resistor R4A and is connected to the input terminal In3 on the negative side of fully differential operational amplifier DOP3 via resistor R4A.

[0112] In addition, it can be said that the output terminal Toip1 on the positive side of the first integrator ITG1, the output terminal Toip2 on the positive side of the second integrator ITG2, and the output terminal Toap on the positive side of the adder ADD respectively include the output terminal Op1 on the positive side of the fully differential operational amplifier DOP1, the output terminal Op2 on the positive side of the fully differential operational amplifier DOP2, and the output terminal Op3 on the positive side of the fully differential operational amplifier DOP3.

[0113] It can be said that the output terminal Toin1 on the negative side of the first integrator ITG1, the output terminal Toin2 on the negative side of the second integrator ITG2, and the output terminal Toan on the negative side of the adder ADD respectively include the output terminal On1 on the negative side of the fully differential operational amplifier DOP1, the output terminal On2 on the negative side of the fully differential operational amplifier DOP2, and the output terminal On3 on the negative side of the fully differential operational amplifier DOP3.

[0114] The reason is that the signals output from the positive and negative terminals of the first integrator ITG1, the second integrator ITG2, and the adder ADD are equivalent to the signals output from the positive and negative terminals of the fully differential operational amplifiers DOP1, OP2, and DOP3, respectively.

[0115] exist Figure 7 In this code, the differential signal between the signal input to input terminal VI1 and the signal input to input terminal VI2 is defined as vI. The differential signal between the signal output from output terminal VB1 and the signal output from output terminal VB2 is defined as vB. The differential signal between the signal output from output terminal VL1 and the signal output from output terminal VL2 is defined as vL. The differential signal between the signal output from output terminal VH1 and the signal output from output terminal VH2 is defined as vH.

[0116] Furthermore, when R1A = R1B = R1, R2A = R2B = R2, R3A = R3B = R3, R4A = R4B = R4, R5A = R5B = R5, R6A = R6B = R6, C1A = C1B = C1, and C2A = C2B = C2, the transfer function as a bandpass filter is the same as that shown in embodiment (Equation 1). The transfer function as a low-pass filter is the same as that in embodiment (Equation 3). The transfer function as a high-pass filter is the same as that in embodiment (Equation 5).

[0117] As described above, in this embodiment, similar to Embodiment 1, when adjusting the parameters of frequency ω0, sharpness Q, and gain H by changing the specified resistance value, it is possible to adjust each parameter independently without changing the resistance value of a resistor that is not directly related to the parameter to be adjusted.

[0118] Hereinafter, an example of a double second-order filter obtained according to the configuration disclosed in this specification will be noted.

[0119] (1) A dual second-order filter, comprising:

[0120] The first integrator includes a first operational amplifier, a first variable resistor and a first capacitor connected to the first operational amplifier;

[0121] The second integrator includes a second operational amplifier, a second variable resistor and a second capacitor connected to the second operational amplifier;

[0122] The adder includes a third operational amplifier and a plurality of resistors connected to the third operational amplifier; and

[0123] Inverting amplifier, with a gain of 1x.

[0124] The output terminal of the first integrator is connected to the input terminal on the negative side of the second integrator.

[0125] The output terminal of the first integrator is connected to the first input terminal on the negative side of the adder via the inverting amplifier.

[0126] The output terminal of the second integrator is connected to the second input terminal on the negative side of the adder.

[0127] The input terminal used for inputting input signals is connected to the third input terminal on the negative side of the adder described above.

[0128] The output terminal of the adder is connected to the input terminal on the negative side of the first integrator.

[0129] (2) In the double second-order filter described in (1), the output terminal of the first integrator is connected to the output terminal of the bandpass filter.

[0130] (3) In the double second-order filter described in (1), the output terminal of the second integrator is connected to the output terminal of the low-pass filter.

[0131] (4) In the double second-order filter described in (1), the output terminal of the adder is connected to the output terminal of the high-pass filter.

[0132] (5) In any of the two second-order filters described in (1) to (4), the plurality of resistors of the adder are variable resistors.

[0133] (6) In the double second-order filter described in (1), the adder includes a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor.

[0134] The output terminal of the first operational amplifier is connected to one terminal of the first capacitor, one terminal of the second variable resistor, the input terminal of the inverting amplifier, and the output terminal of the bandpass filter.

[0135] The negative input terminal of the first operational amplifier is connected to the other terminal of the first capacitor and one terminal of the first variable resistor.

[0136] The output terminal of the second operational amplifier is connected to one terminal of the second capacitor, one terminal of the fourth resistor, and the output terminal of the low-pass filter.

[0137] The negative input terminal of the second operational amplifier is connected to another terminal of the second variable resistor and another terminal of the second capacitor.

[0138] The output terminal of the third operational amplifier is connected to one terminal of the sixth resistor, the other terminal of the first variable resistor, and the output terminal of the high-pass filter.

[0139] The negative input terminal of the aforementioned third operational amplifier is connected to another terminal of the aforementioned sixth resistor, another terminal of the aforementioned fourth resistor, one terminal of the aforementioned fifth resistor, and one terminal of the aforementioned third resistor.

[0140] The output terminal of the aforementioned inverting amplifier is connected to the other terminal of the aforementioned third resistor.

[0141] The other terminal of the fourth resistor is connected to the input terminal used to input the input signal.

[0142] (7) In the dual second-order filter described in (6), the output terminals of the first integrator, the second integrator, and the adder respectively include the output terminals of the first operational amplifier, the second operational amplifier, and the third operational amplifier.

[0143] The input terminal on the negative side of the first integrator includes another terminal of the first variable resistor.

[0144] The input terminal on the negative side of the second integrator includes one terminal of the second variable resistor.

[0145] The first input terminal on the negative side of the adder includes the other terminal of the third resistor, the second input terminal on the negative side of the adder includes one terminal of the fourth resistor, and the third input terminal on the negative side of the adder includes the other terminal of the fifth resistor.

[0146] (8) In the dual second-order filter described in (1), the input terminal on the positive side of the first integrator, the input terminal on the positive side of the second integrator, and the input terminal on the positive side of the adder are grounded.

[0147] (9) A dual second-order filter, comprising:

[0148] The first integrator includes a first fully differential operational amplifier, a first variable resistor connected to the first fully differential operational amplifier, and a first capacitor connected to the first fully differential operational amplifier.

[0149] The second integrator includes a second fully differential operational amplifier, a second variable resistor connected to the second fully differential operational amplifier, and a second capacitor connected to the second fully differential operational amplifier; and

[0150] The adder includes a third fully differential operational amplifier and multiple resistors connected to the aforementioned third fully differential operational amplifier.

[0151] The output terminal on the positive side of the first integrator is connected to the input terminal on the negative side of the second integrator.

[0152] The output terminal on the positive side of the second integrator is connected to the first input on the positive side of the adder.

[0153] The output terminal on the negative side of the first integrator is connected to the input terminal on the positive side of the second integrator.

[0154] The output terminal on the negative side of the first integrator is connected to the first input terminal on the negative side of the adder.

[0155] The output terminal on the positive side of the second integrator is connected to the second input terminal on the negative side of the adder.

[0156] The output terminal on the negative side of the second integrator is connected to the second input terminal on the positive side of the adder.

[0157] The first input terminal, which is either the positive or negative phase of the differential input signal, is connected to the third input terminal on the negative side of the adder.

[0158] The second input terminal, which is applied to either the positive or negative phase of the aforementioned differential input signal, is connected to the third input terminal on the positive side of the adder.

[0159] The output terminal on the positive side of the adder is connected to the input terminal on the negative side of the first integrator.

[0160] The output terminal on the negative side of the adder is connected to the input terminal on the positive side of the first integrator.

[0161] (10) In the dual second-order filter described in (9), the output terminal on the positive side and the output terminal on the negative side of the first integrator are connected to the output terminal of the bandpass filter.

[0162] (11) In the dual second-order filter described in (9), the output terminal on the positive side and the output terminal on the negative side of the second integrator are connected to the output terminal of the low-pass filter.

[0163] (12) In the double second-order filter described in (9), the output terminal on the positive side and the output terminal on the negative side of the adder are connected to the output terminal of the high-pass filter.

[0164] (13) In any of the two second-order filters described in (9) to (12), the plurality of resistors of the adder are variable resistors.

[0165] (14) In the dual second-order filter described in (9), the first integrator includes a third capacitor and a third variable resistor.

[0166] The second integrator described above includes a fourth capacitor and a fourth variable resistor.

[0167] The adder described above includes resistors 5, 6, 7, 8, 9, 10, 11, and 12.

[0168] The output terminal on the positive side of the first fully differential operational amplifier is connected to one terminal of the second variable resistor, one terminal of the first capacitor, one terminal of the eleventh resistor, and the output terminal on the positive side of the bandpass filter.

[0169] The output terminal on the negative side of the first fully differential operational amplifier is connected to one terminal of the fourth variable resistor, one terminal of the third capacitor, one terminal of the fifth resistor, and the output terminal on the negative side of the bandpass filter.

[0170] The positive input terminal of the first fully differential operational amplifier is connected to the other terminal of the third capacitor and one terminal of the third resistor.

[0171] The negative input terminal of the aforementioned first fully differential operational amplifier is connected to the other terminal of the aforementioned first capacitor and one terminal of the aforementioned first variable resistor.

[0172] The positive output terminal of the aforementioned second fully differential operational amplifier is connected to one terminal of the aforementioned second capacitor, one terminal of the aforementioned sixth resistor, and the positive output terminal of the low-pass filter.

[0173] The output terminal on the negative side of the aforementioned second fully differential operational amplifier is connected to one terminal of the aforementioned fourth capacitor, one terminal of the aforementioned tenth resistor, and the output terminal on the negative side of the aforementioned low-pass filter.

[0174] The positive input terminal of the second fully differential operational amplifier is connected to the other terminal of the fourth capacitor and the other terminal of the fourth variable resistor.

[0175] The negative input terminal of the aforementioned second fully differential operational amplifier is connected to the other terminal of the aforementioned second capacitor and the other terminal of the aforementioned second variable resistor.

[0176] The output terminal on the positive side of the aforementioned third fully differential operational amplifier is connected to one terminal of the aforementioned eighth resistor, the other terminal of the aforementioned first variable resistor, and the output terminal on the positive side of the high-pass filter.

[0177] The output terminal on the negative side of the aforementioned third fully differential operational amplifier is connected to one terminal of the 12th resistor, the other terminal of the 3rd resistor, and the output terminal on the negative side of the aforementioned high-pass filter.

[0178] The positive input terminal of the aforementioned third fully differential operational amplifier is connected to one terminal of the ninth resistor, another terminal of the tenth resistor, another terminal of the eleventh resistor, and another terminal of the twelfth resistor.

[0179] The negative input terminal of the aforementioned third fully differential operational amplifier is connected to another terminal of the aforementioned fifth resistor, another terminal of the aforementioned sixth resistor, one terminal of the aforementioned seventh resistor, and another terminal of the aforementioned eighth resistor.

[0180] The other terminal of the seventh resistor is connected to the first input terminal applied by either the positive or negative phase of the differential input signal.

[0181] The other terminal of the aforementioned 9th resistor is connected to the aforementioned 2nd input terminal applied by the other of the positive or negative phase of the aforementioned differential input signal.

[0182] (15) In the dual second-order filter described in (14), the output terminals of the positive and negative sides of the first integrator, the output terminals of the positive and negative sides of the second integrator, and the output terminals of the positive and negative sides of the adder respectively include the output terminals of the positive and negative sides of the first fully differential operational amplifier, the output terminals of the positive and negative sides of the second fully differential operational amplifier, and the output terminals of the positive and negative sides of the third fully differential operational amplifier.

[0183] The positive input terminal of the first integrator includes another terminal of the third variable resistor, and the negative input terminal of the first integrator includes another terminal of the first variable resistor.

[0184] The positive input terminal of the second integrator includes one terminal of the fourth variable resistor, and the negative input terminal of the second integrator includes one terminal of the second variable resistor.

[0185] The first input terminal on the positive side of the adder includes one terminal of the 11th resistor, the second input terminal on the positive side of the adder includes one terminal of the 10th resistor, and the third input terminal on the positive side of the adder includes the other terminal of the 9th resistor.

[0186] The first input terminal on the negative side of the adder includes one terminal of the fifth resistor, the second input terminal on the negative side of the adder includes one terminal of the sixth resistor, and the third input terminal on the negative side of the adder includes the other terminal of the seventh resistor.

[0187] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. New embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. The embodiments and their variations are included in the scope and spirit of the invention, and are also included in the scope of the invention as described in the claims and its equivalents.

Claims

1. A biquad filter capable of functioning as a bandpass filter, a lowpass filter, and a highpass filter, comprising: a first integrator including a first operational amplifier, a first variable resistor connected to the first operational amplifier, and a first capacitor connected to the first operational amplifier; a second integrator including a second operational amplifier, a second variable resistor connected to the second operational amplifier, and a second capacitor connected to the second operational amplifier; a summer including a third operational amplifier and a plurality of resistors connected to the third operational amplifier; and an inverting amplifier having an amplification of 1, wherein an output terminal of the first integrator is connected to a negative input terminal of the second integrator, the output terminal of the first integrator is connected to a first input terminal of the summer via the inverting amplifier, an output terminal of the second integrator is connected to a second input terminal of the summer, an input terminal for inputting an input signal is connected to a third input terminal of the summer, an output terminal of the summer is connected to an input terminal of the first integrator, and the output terminal of the summer is connected to an input terminal of the first operational amplifier via the first variable resistor.

2. The biquad filter according to claim 1, wherein In a case where the biquad filter functions as a bandpass filter, the output terminal of the first integrator is connected to an output terminal of the bandpass filter.

3. The biquadratic filter of claim 1, wherein In a case where the biquad filter functions as a lowpass filter, the output terminal of the second integrator is connected to an output terminal of the lowpass filter.

4. The biquadratic filter of claim 1, wherein In a case where the biquad filter functions as a highpass filter, the output terminal of the summer is connected to an output terminal of the highpass filter.

5. The biquadratic filter according to any one of claims 1 to 4, wherein The plurality of resistors of the summer are variable resistors.

6. The biquadratic filter of claim 1, wherein The adder includes a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor, an output terminal of the first operational amplifier is connected to one terminal of the first capacitor, one terminal of the second variable resistor, an input terminal of the inverting amplifier, and an output terminal of the biquad filter operating as a band-pass filter, an input terminal on the negative side of the first operational amplifier is connected to the other terminal of the first capacitor and one terminal of the first variable resistor, an output terminal of the second operational amplifier is connected to one terminal of the second capacitor, one terminal of the fourth resistor, and an output terminal of the biquad filter operating as a low-pass filter, an input terminal on the negative side of the second operational amplifier is connected to the other terminal of the second variable resistor and the other terminal of the second capacitor, an output terminal of the third operational amplifier is connected to one terminal of the sixth resistor, the other terminal of the first variable resistor, and an output terminal of the biquad filter operating as a high-pass filter, an input terminal on the negative side of the third operational amplifier is connected to the other terminal of the sixth resistor, the other terminal of the fourth resistor, one terminal of the fifth resistor, and one terminal of the third resistor, an output terminal of the inverting amplifier is connected to the other terminal of the third resistor, and the other terminal of the fifth resistor is connected between an input terminal for inputting the input signal and a third input terminal on the negative side of the adder.

7. The biquadratic filter according to claim 6, wherein The output terminal of the first integrator, the output terminal of the second integrator, and the output terminal of the adder each include the output terminal of the first operational amplifier, the output terminal of the second operational amplifier, and the output terminal of the third operational amplifier, the input terminal on the negative side of the first integrator includes the other terminal of the first variable resistor, the input terminal on the negative side of the second integrator includes one terminal of the second variable resistor, the first input terminal on the negative side of the adder includes the other terminal of the third resistor, the second input terminal on the negative side of the adder includes one terminal of the fourth resistor, and the third input terminal on the negative side of the adder includes the other terminal of the fifth resistor.

8. The biquadratic filter of claim 1, wherein The input terminal on the positive side of the first integrator, the input terminal on the positive side of the second integrator, and the input terminal on the positive side of the adder are grounded.

9. A dual second-order filter comprising: a first integrator including a first fully differential operational amplifier, a first variable resistor connected to the first fully differential operational amplifier, and a first capacitor connected to the first fully differential operational amplifier; a second integrator including a second fully differential operational amplifier, a second variable resistor connected to the second fully differential operational amplifier, and a second capacitor connected to the second fully differential operational amplifier; and an adder including a third fully differential operational amplifier and a plurality of resistors connected to the third fully differential operational amplifier, wherein the output terminal on the positive side of the first integrator is connected to the input terminal on the negative side of the second integrator, the output terminal on the positive side of the second integrator is connected to the first input terminal on the negative side of the adder, the output terminal on the negative side of the first integrator is connected to the input terminal on the positive side of the second integrator, and the output terminal on the negative side of the first integrator is connected to the input terminal on the positive side of the second integrator. The output terminal of the first integrator is connected to the first input terminal of the negative side of the adder. The output terminal of the positive side of the second integrator is connected to the second input terminal of the negative side of the adder. The output terminal of the negative side of the second integrator is connected to the second input terminal of the positive side of the adder. The first input terminal of either the positive or negative phase of the differential input signal is connected to the third input terminal of the negative side of the adder. The second input terminal of the other positive or negative phase of the differential input signal is connected to the third input terminal of the positive side of the adder. The output terminal of the positive side of the adder is connected to the input terminal of the negative side of the first integrator. The output terminal of the negative side of the adder is connected to the input terminal of the positive side of the first integrator. The output terminal of the adder is connected to the input terminal of the negative side of the first operational amplifier via the first variable resistor.

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