Aging tracking circuit, electronic device and electronic equipment

Abstract

The present application provides an aging tracking circuit, an electronic device and an electronic device, wherein the circuit comprises: a latch and a data pull-down module, wherein the size of a first PMOS transistor in the latch is consistent with the size of a PMOS transistor to be tracked in the original circuit, and is larger than the size of a second PMOS transistor in the latch, and the driving capability of the first PMOS transistor after aging is smaller than the driving capability of the second PMOS transistor; and a data pull-down module, wherein the first end is connected to two data storage points of the latch, the second end is grounded, and the third end is used to access a control signal, and when the original circuit is powered on, the first end is connected to the second end to clear the data in the two data storage points, and after the data in the two data storage points are cleared, the first end is disconnected from the second end. The circuit can simulate the aging of the PMOS transistor to be tracked through the first PMOS transistor, and realize aging tracking of the PMOS transistor to be tracked.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to an aging tracking circuit, an electronic device, and an electronic device. Background Art

[0002] As the size of integrated circuits decreases, reliability issues are becoming increasingly prominent. Aging, as one of the important indicators of device reliability, describes that as the circuit is used for a longer time, the reliability of the device becomes more and more serious. The impact of the aging effect on integrated circuits is mainly reflected in the performance degradation of the devices in the circuit as the circuit is used for a longer time, such as changes in transistor threshold voltage, leakage current, transconductance, etc.

[0003] The most serious factor affecting the aging reliability of integrated circuits is the BTI (Bias Temperature Instability) effect. According to the positive or negative stress voltage, BTI is divided into PBTI (Positive Bias Temperature Instability) and NBTI (Negative Bias Temperature Instability). The BTI effect will cause the transistor threshold voltage to increase and the on-state current to decrease. PBTI occurs in NMOS (Negative channel-Metal-Oxide-Semiconductor) transistors. The aging problem of NMOS transistors caused by PBTI has little effect and can usually be ignored. On the contrary, NBTI occurs in PMOS (positive channel Metal Oxide Semiconductor) transistors. The aging problem of PMOS transistors caused by NBTI is more obvious and is the main cause of device aging.

[0004] The failure mechanism of NBTI is as follows: the PMOS transistor operates under a negative gate bias voltage (i.e., the gate voltage is lower than the source voltage), and the circuit operates under high electric field and high temperature conditions. As the operating time increases, the saturated drain current and transconductance continue to decrease, and the threshold voltage continues to increase, thereby affecting the performance of the PMOS transistor.

[0005] From the failure mechanism of NBTI, we know that in a normally working circuit, the normally open PMOS transistor (the gate-source voltage is always in a negative bias state, that is, the gate voltage is always lower than the source voltage) is more seriously affected by aging than the flipped PMOS transistor (the gate-source voltage changes between positive and negative bias), because the NBTI effect has a partial recovery characteristic. When the gate-source voltage of the aged PMOS transistor is in a positive bias state, the offset threshold voltage can be repaired and the device characteristics are partially restored. This stage is called the NBTI recovery stage. For a flipped PMOS transistor, that is, the gate-source voltage of the PMOS transistor jumps from a negative bias to a positive bias, the PMOS transistor will recover from NBTI under the positive bias, while for a PMOS transistor that has been in a maintained state, the NBTI effect will become more and more obvious, which may eventually cause the PMOS transistor to fail.

[0006] Because NBTI can cause the performance of PMOS transistors to degrade, the driving capability of the aged PMOS transistors will deteriorate, thereby increasing the internal delay of the circuit. If the delay is too large, it will cause timing problems in the circuit, causing the entire circuit to fail to work properly. Summary of the invention

[0007] The purpose of the embodiments of the present application is to provide an aging tracking circuit, an electronic device, and an electronic device, so as to effectively track the aging condition of the circuit.

[0008] The embodiment of the present application provides an aging tracking circuit, including:

[0009] A latch, composed of a cross-coupled first inverter and a second inverter, wherein the first inverter has a first PMOS transistor, and the second inverter has a second PMOS transistor; the size of the first PMOS transistor is consistent with the size of the PMOS transistor to be tracked in the original circuit, and is larger than the size of the second PMOS transistor, and the driving capability of the first PMOS transistor after aging is smaller than the driving capability of the second PMOS transistor;

[0010] A data pull-down module, wherein the first end is connected to the two data storage points of the latch, the second end is grounded, and the third end is used to access a control signal; the first end and the second end are turned on and off under the action of the control signal, wherein when the original circuit is powered on, the first end and the second end are turned on to clear the data in the two data storage points, and after the data in the two data storage points are cleared, the first end is disconnected from the second end.

[0011] In the above-mentioned implementation circuit, since the size of the first PMOS transistor is consistent with the size of the PMOS transistor to be tracked in the original circuit, and during use, since the size of the first PMOS transistor is larger than the size of the second PMOS transistor, the first PMOS transistor can be in a normally open state when in use when it is not aged (this is consistent with the use state of the PMOS transistor to be tracked), so that the first PMOS transistor can effectively simulate the aging condition of the PMOS transistor to be tracked, so that the aging condition of the first PMOS transistor can effectively characterize the aging condition of the PMOS transistor to be tracked.

[0012] When the first PMOS transistor is not aged, the first PMOS transistor is normally open, and its driving capability is greater than that of the second PMOS transistor, so that the data in the second storage data point at the gate of the second PMOS transistor is 1, and the data in the first storage data point at the gate of the first PMOS transistor is 0. When the first PMOS transistor is aged, since the driving capability of the first PMOS transistor is less than that of the second PMOS transistor at this time, after the original circuit is powered on again, the data pull-down module clears the data in the latch, and the second PMOS transistor in the latch becomes normally open, so that the data in the first storage data point is 1, and the data in the second storage data point is 0. Therefore, each time the original circuit is powered on again, based on the data value in any data storage point in the latch, it can be effectively determined whether the PMOS transistor to be tracked in the original circuit is aged, thereby realizing aging tracking of the PMOS transistor to be tracked.

[0013] The above-mentioned circuit has a simple structure and simulates the PMOS transistor to be tracked through the PMOS transistor in the latch. It is applicable to various original circuits with PMOS transistor aging tracking requirements (such as memory, logic circuit, large integrated circuit, etc.), has a wide range of applications, and has high industrial application value.

[0014] Further, the data pull-down module includes a first NMOS transistor and a second NMOS transistor; the two data storage points are a first data storage point and a second data storage point; the drains of the first NMOS transistor and the second NMOS transistor together constitute the first end; wherein, the drain of the first NMOS transistor is connected to the first data storage point, and the drain of the second NMOS transistor is connected to the second data storage point; the sources of the first NMOS transistor and the second NMOS transistor are the second end, both of which are grounded; the gates of the first NMOS transistor and the second NMOS transistor are the third end, both of which are connected to the control signal; wherein, when the original circuit is powered on, the control signal is a high-level signal; after the data in the two data storage points are cleared, the control signal is a low-level signal.

[0015] In the above implementation circuit, two NMOS transistors are used to form a data pull-down module. By grounding the sources of the two NMOS transistors, when a high-level control signal is input to the gate, the gate-source voltage can be positively biased (i.e., the gate voltage is higher than the source voltage), so that the source and drain of the NMOS transistor are turned on, thereby grounding the two data storage points in the latch, clearing the data in the latch, and allowing the latch to re-latch the data. The entire data pull-down module has a simple implementation structure, does not complicate the aging tracking circuit, and is easy to deploy in various electronic components that require aging tracking of PMOS transistors.

[0016] Furthermore, the aging tracking circuit also includes: a signal stabilization module, connected to any one of the two data storage points, and used to output the data in the data storage point as a stable signal.

[0017] It should be understood that in actual applications, the data in the latch may not be a standard "0" signal or "1" signal, which may cause the output of the data to be misidentified. However, through the above implementation structure, the data in the data storage point can be output as a stable signal to ensure the reliability of data reading and output.

[0018] Furthermore, the signal stabilization module is an inverter and / or a buffer.

[0019] In the above implementation scheme, the data in the data storage point is processed and output through the inverter and / or buffer, and will be stabilized to a standard "0" signal or "1" signal in the signal inverter or buffer, thereby ensuring the reliability of data reading and output.

[0020] Furthermore, the aging tracking circuit further includes:

[0021] A circuit repair module, comprising a control end, a first input end, a first output end, a second input end, and a second output end;

[0022] The first input end is used to access the input signal of the original circuit, and the first output end is used to access the input end of the original circuit; the second input end is used to access the output end of the original circuit to receive the output signal of the original circuit;

[0023] The control end is connected to any one of the two data storage points;

[0024] The circuit repair module is used to, based on the signal of the connected data storage point: invert the input signal of the original circuit, output the inverted input signal to the original circuit through the first output terminal, and invert the output signal of the original circuit, and output the inverted output signal through the second output terminal; or output the input signal of the original circuit to the original circuit through the first output terminal, and output the output signal of the original circuit through the second output terminal.

[0025] In the above implementation circuit, since the circuit repair module inverts or does not invert the input signal of the original circuit according to the signal of the data storage point of the latch, after the first PMOS transistor ages, the data in the data storage point will be flipped relative to the data before aging, so that after tracing the aging of the PMOS transistor to be tracked, the signal input into the original circuit through the circuit repair module will also be flipped relative to the signal input into the original circuit before aging, so that the PMOS crystal to be tracked in the original circuit can be NBTI-recovered, achieving the effect of self-repair of the PMOS crystal to be tracked.

[0026] In addition, since the driving capability of the first PMOS transistor is lower than that of the second PMOS transistor after aging, the second PMOS transistor becomes normally open in the latch, while the gate-source voltage of the first PMOS transistor remains in a positive bias state, so that the first PMOS transistor also performs NBTI recovery together with the PMOS crystal to be tracked, ensuring that during the autonomous repair process of the PMOS crystal to be tracked, the first PMOS transistor can still have a good aging tracking effect.

[0027] Further, the circuit repair module includes: an input inverter, an output inverter, a first multiplexer and a second multiplexer; one end of the input inverter is the first input end, and the other end is connected to the first multiplexer; one input end of the first multiplexer is the first input end, and the other input end is connected to the input inverter; the output end of the first multiplexer is the first output end; one end of the output inverter is the second input end, and the other end is connected to the second multiplexer; one input end of the second multiplexer is the second input end, and the other input end is connected to the output inverter; the output end of the second multiplexer is the second output end; the control ends of the first multiplexer and the second multiplexer are both connected to any one of the two data storage points; the first multiplexer and the second multiplexer are used to: select the input inverter and the output inverter according to the signal of the connected data storage point; or, select the input signal of the original circuit and the output signal of the original circuit.

[0028] In the above-mentioned implementation circuit, the circuit repair module is realized by only two inverters and two multiplexers. The circuit structure is very simple, which is conducive to layout in electronic devices without causing significant changes in the size of the electronic devices. It has little effect on the PPA (Performance, Power, Area) of the electronic devices and has high practical application value.

[0029] Further, the first multiplexer and the second multiplexer are specifically used to: when the first PMOS transistor is not aged, enable the input inverter and the output inverter; when the first PMOS transistor is aged, enable the input signal of the original circuit and the output signal of the original circuit.

[0030] In the above implementation scheme, when the first PMOS transistor has not aged, the input inverter and the output inverter are enabled, and when the first PMOS transistor has aged, the input signal of the original circuit and the output signal of the original circuit are enabled. This means that during aging, the path taken by the input signal of the original circuit is reduced by two stages of inverters relative to before aging, thereby reducing the delay of the entire circuit and, to a certain extent, repairing the timing problem caused by the circuit delay caused by the aging of the PMOS transistor to be tracked.

[0031] Further, the two data storage points are a first data storage point and a second data storage point; the first data storage point is a data storage point connected to the gate of the first PMOS transistor; the second data storage point is a data storage point connected to the gate of the second PMOS transistor; the control end is connected to the second data storage point in the latch through a third inverter; the first multiplexer is used to enable the input inverter when a low level is input to the control end, and to enable the input signal of the original circuit when a high level is input to the control end; the second multiplexer is used to enable the output inverter when a low level is input to the control end, and to enable the output signal of the original circuit when a high level is input to the control end.

[0032] In the above implementation process, the third inverter can ensure that the control signal output to the two multiplexers is stable, and can enable the input inverter and the output inverter when the first PMOS transistor is not aged, and enable the input signal of the original circuit and the output signal of the original circuit when the first PMOS transistor is aged, so that the delay of the entire circuit is reduced, thereby repairing the timing problem caused by the circuit delay caused by the aging of the PMOS transistor to be tracked to a certain extent.

[0033] An embodiment of the present application further provides an electronic device, comprising: an original circuit having a PMOS transistor to be tracked, and any one of the above-mentioned aging tracking circuits.

[0034] An embodiment of the present application also provides an electronic device, comprising the above-mentioned electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 A basic structural diagram of an aging tracking circuit provided in an embodiment of the present application;

[0037] Figure 2 A schematic diagram of the aging tracking circuit structure with a detailed data pull-down module provided in an embodiment of the present application;

[0038] Figure 3 A schematic diagram of the structure of an aging tracking circuit with a signal stabilization module provided in an embodiment of the present application;

[0039] Figure 4A schematic diagram of an aging tracking circuit structure with a circuit repair module provided in an embodiment of the present application;

[0040] Figure 5 A schematic diagram of an aging tracking circuit structure with a detailed circuit repair module structure provided in an embodiment of the present application;

[0041] Figure 6 A more detailed schematic diagram of the aging tracking circuit structure provided in an embodiment of the present application;

[0042] Figure 7 A schematic diagram of an exemplary aging tracking circuit structure provided in an embodiment of the present application;

[0043] Figure 8 A schematic diagram of the structure of a 6T SRAM Cell circuit provided in an embodiment of the present application;

[0044] Fig. 9 A timing diagram of a circuit before aging provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0046] Example:

[0047] In order to effectively track the aging of the circuit, an aging tracking circuit is provided in an embodiment of the present application. Figure 1 As shown, Figure 1 This is a basic schematic diagram of an aging tracking circuit provided in an embodiment of the present application, including: a latch 1 and a data pull-down module 2.

[0048] The latch 1 is composed of a cross-coupled first inverter 11 and a second inverter 12. The first inverter has a first PMOS transistor 111, and the second inverter has a second PMOS transistor 112.

[0049] It should be understood that the latch is a storage unit circuit for temporarily storing a signal, and has two data storage points, which are respectively located at the gate of the first PMOS transistor 111 and the gate of the second PMOS transistor 111. For ease of description, in the embodiment of the present application, the data storage point located at the gate of the first PMOS transistor 111 is referred to as the first data storage point K1, and the data storage point located at the gate of the second PMOS transistor 111 is referred to as the second data storage point K2.

[0050] In the embodiment of the present application, the size of the first PMOS transistor 111 should be consistent with the size of the PMOS transistor to be tracked in the original circuit to ensure that the first PMOS transistor 111 can effectively simulate the PMOS transistor to be tracked.

[0051] It should be noted that in the embodiment of the present application, the original circuit refers to a circuit with PMOS transistor aging tracking requirements, which can be a memory, a logic circuit, a large integrated circuit, etc., and is not limited in the embodiment of the present application.

[0052] It should also be noted that, in the embodiment of the present application, in order to ensure that the first PMOS transistor 111 can effectively simulate the PMOS transistor to be tracked, the size of the first PMOS transistor 111 should also be larger than the size of the second PMOS transistor 121, and the driving capability of the first PMOS transistor 111 after aging should be smaller than the driving capability of the second PMOS transistor 121.

[0053] Thus, when the first PMOS transistor 111 is not aged, since the size of the first PMOS transistor 111 is larger than that of the second PMOS transistor 121, the driving capability of the first PMOS transistor 111 is greater than that of the second PMOS transistor 121, so that the first PMOS transistor 111 is normally turned on and is affected by the NBTI effect together with the PMOS transistor to be tracked in the original circuit, while the second PMOS transistor 121 is turned off. At this time, the data in the first storage data point K1 is 0, and the data in the second storage data point K2 is 1.

[0054] When the first PMOS transistor 111 ages, the driving capability of the first PMOS transistor 111 degrades to a level less than the driving capability of the second PMOS transistor 121. At this time, the first PMOS transistor 111 is disconnected, while the second PMOS transistor 121 is normally on. At this time, the data in the first storage data point K1 is 1, and the data in the second storage data point K2 is 0.

[0055] Therefore, based on the data in the first storage data point K1 or the data in the second storage data point K2 , it can be effectively determined whether the first PMOS transistor 111 is aged.

[0056] Since the latch remains unchanged after storing data each time, in the embodiment of the present application, a data pull-down module 2 is used to clear the data stored in the latch 1 after the original circuit is powered on each time, so as to ensure that the latch 1 can store data again, so that the latch 1 can update the data representing whether the first PMOS transistor 111 is aged each time it is powered on, so as to realize aging tracking.

[0057] In order to enable the data pull-down module 2 to clear the data stored in the latch 1, in the embodiment of the present application, the first end of the data pull-down module 2 is connected to the two data storage points K1 and K2 of the latch 1; the second end of the data pull-down module 2 is grounded, and the third end is used to access the control signal DCH. The first end and the second end are turned on and off under the action of the control signal DCH. Among them, when the original circuit is powered on, the first end is turned on and off with the second end, and the data storage points K1 and K2 are directly grounded at this time, so that the data in the two data storage points are cleared. After the data in the two data storage points K1 and K2 are cleared, the first end is disconnected from the second end, so that the latch 1 can work normally again.

[0058] It should be understood that in the embodiment of the present application, the data pull-down module 2 can be implemented by a device with a controlled switch function.

[0059] For example, Figure 2 As shown, the data pull-down module 2 may include a first NMOS transistor 21 and a second NMOS transistor 22. Wherein:

[0060] The drains of the first NMOS transistor 21 and the second NMOS transistor 22 together constitute a first terminal. The drain of the first NMOS transistor 21 is connected to the first data storage point K1, and the drain of the second NMOS transistor 22 is connected to the second data storage point K2.

[0061] The sources of the first NMOS transistor 21 and the second NMOS transistor 22 constitute the second terminal, and are both grounded.

[0062] The gates of the first NMOS transistor 21 and the second NMOS transistor 22 constitute a third terminal, both of which are connected to the control signal DCH.

[0063] The control signal DCH is output as a high level signal when the original circuit is powered on, and is output as a low level signal after the data in the two data storage points K1 and K2 are cleared.

[0064] It should be understood that in the embodiments of the present application, in addition to the above Figure 2 In addition to the structure shown in the figure, other structures can also be used to implement the data pull-down module 2. For example, the NMOS transistor in the above example can be replaced by an NPN transistor. In the embodiment of the present application, as long as the circuit structure can realize the controlled connection and disconnection of the data storage points K1 and K2 with the ground line, it can be adopted as the data pull-down module 2 in the embodiment of the present application.

[0065] It should be understood that in actual application, the data in the latch may not be a standard "0" signal or a "1" signal, which may cause the output of the data to be misidentified. Figure 3 As shown, any one of the data storage points K1 and K2 can be connected to the signal stabilization module 3, so that the signal in the data storage point can be output as a stable signal through the signal stabilization module 3 to ensure the reliability of signal reading and output.

[0066] In the embodiment of the present application, the signal stabilization module 3 can be implemented by a device or a combination of devices with signal stabilization capabilities, such as an inverter, a buffer, etc., but this is not a limitation.

[0067] It should be noted that in order to ensure the tracking effect, in the embodiment of the present application, the aging tracking circuit provided in the embodiment of the present application can be set at the same time as the original circuit is set in the electronic device, thereby ensuring that the first PMOS transistor 111 and the PMOS transistor to be tracked are in the same use environment, thereby ensuring the reliability of the aging tracking effect.

[0068] Optionally, in the embodiments of this application, see Figure 4 As shown, the aging tracking circuit may further include a circuit repair module 4. Among them:

[0069] The circuit repair module 4 includes a control terminal A1, a first input terminal A2, a first output terminal A3, a second input terminal A4 and a second output terminal A5.

[0070] The first input terminal A2 is used to access the input signal DI of the original circuit 5, and the first output terminal A3 is used to access the input terminal of the original circuit 5; the second input terminal A4 is used to access the output terminal of the original circuit to receive the output signal of the original circuit.

[0071] The control terminal A1 is connected to any one of the two data storage points K1 and K2.

[0072] The circuit repair module 4 is used to perform one of the following two operations according to the difference in the signal of the connected data storage point:

[0073] Operation 1: Invert the input signal DI of the original circuit 5, and output the inverted input signal (denoted as DI') to the original circuit 5 through the first output terminal A3, and invert the output signal of the original circuit 5, and output the inverted output signal through the second output terminal A5.

[0074] Operation 2: the input signal DI of the original circuit 5 is directly output to the original circuit 5 through the first output terminal A3, and the output signal of the original circuit 5 is directly output through the second output terminal A5.

[0075] It should be understood that, assuming that the circuit repair module 4 is not added, the input signal of the original circuit 5 is DI, and the output signal is DO.

[0076] After adding the circuit repair module 4, in the above operation one, since the signal input to the original circuit 5 is DI', the signal output from the original circuit 5 to the circuit repair module 4 is the inverted signal DO' of DO, so after the circuit repair module 4 inverts DO', it can be ensured that the output of the circuit repair module 4 is DO. In the above operation two, the signal input to the original circuit 5 is DI, and the signal output from the original circuit 5 to the circuit repair module 4 is DO. Since the inversion operation is not performed in the operation two, the signal output by the circuit repair module 4 is also DO. Therefore, the addition of the above circuit repair module 4 will not cause changes in the signal DO output to other circuits, ensuring that the addition of the circuit repair module 4 will not cause confusion in the circuit signal logic.

[0077] Since the circuit repair module 4 is added, and the circuit repair module 4 inverts or does not invert the input signal of the original circuit according to the signal of the data storage point of the latch 1, then, after the first PMOS transistor 111 ages, the data in the data storage point will be flipped relative to that before aging, so that after tracing the aging of the PMOS transistor to be tracked, the signal input into the original circuit 5 through the circuit repair module 4 will also be flipped relative to the signal input into the original circuit 5 before aging, so that the PMOS crystal to be tracked in the original circuit can be NBTI-recovered, achieving the effect of self-repair of the PMOS crystal to be tracked.

[0078] Exemplarily, assuming that the circuit repair module 4 performs operation 1 when the first PMOS transistor 111 is not aged, then when the first PMOS transistor 111 is not aged, the data in the original circuit 5 is DI', and the PMOS crystal to be tracked remains in a normally open working state. When the first PMOS transistor 111 is aged, the data in the original circuit 5 becomes DI, the data is flipped, the gate-source voltage of the PMOS crystal to be tracked is positively biased, and NBTI recovery is performed, thereby achieving the effect of self-repair of the PMOS crystal to be tracked.

[0079] It should be understood that in the embodiment of the present application, since the driving capability of the first PMOS transistor is lower than that of the second PMOS transistor after aging, the second PMOS transistor in the latch will be normally open, and the gate-source voltage of the first PMOS transistor will remain in a positive biased state, so that the first PMOS transistor will also perform NBTI recovery together with the PMOS crystal to be tracked, thereby ensuring that during the autonomous repair process of the PMOS crystal to be tracked, the first PMOS transistor is also performing autonomous repair, thereby ensuring that the aging condition of the first PMOS transistor can always effectively characterize the aging condition of the PMOS crystal to be tracked, thereby always having a good aging tracking effect.

[0080] For example, see Figure 5 As shown, the circuit repair module 4 may include: an input inverter 41, an output inverter 42, a first multiplexer 43 and a second multiplexer 44. Among them:

[0081] One end of the input inverter 41 is the first input end A2 , and the other end is connected to the first multiplexer 43 .

[0082] One input end of the first multiplexer 43 is also used as the first input end A2, directly connected to the input signal DI of the original circuit 5. The other input end is connected to the input inverter 41. The output end of the first multiplexer 43 is used as the first output end A3, connected to the original circuit 5.

[0083] One end of the output inverter 42 is used as the second input end A4 to receive the input signal DI, and the other end is connected to the second multiplexer 44 .

[0084] One input end of the second multiplexer 44 is also used as the second input end A4 to receive the input signal DI, while the other input end is connected to the output inverter 42. The output end of the second multiplexer 44 is used as the second output end A5 to output the final output signal DO.

[0085] The control terminals A1 of the first multiplexer 43 and the second multiplexer 44 are both connected to any one of the two data storage points K1 and K2.

[0086] The first multiplexer 43 and the second multiplexer 44 are used to select the input inverter and the output inverter 42 according to the signal of the connected data storage point; or select the input signal DI of the original circuit 5 and the output signal of the original circuit 5.

[0087] In this way, the circuit repair module 4 is realized by only two inverters and two multiplexers. The circuit structure is very simple, which is conducive to layout in electronic devices without causing significant changes in the size of the electronic devices. It has little effect on the PPA of the electronic devices and has high practical application value.

[0088] Considering that the aging of the PMOS transistor will also cause the internal delay of the circuit to become larger, and even cause the timing problem of the circuit, thus causing the entire circuit to fail to work properly. To this end, in the embodiment of the present application, the gating mode of the two multiplexers can be set so that when the first PMOS transistor 111 is not aged, the input inverter 41 and the output inverter 42 are gated; when the first PMOS transistor 111 is aged, the input signal DI of the original circuit 5 and the output signal of the original circuit 5 are gated. In this way, when the first PMOS transistor 111 tracks the aging of the PMOS transistor to be tracked, the path taken by the input signal DI of the original circuit is reduced by two stages of inverters (i.e., the input inverter 41 and the output inverter 42 are reduced) relative to before aging, thereby reducing the delay of the entire circuit, and to a certain extent repairing the timing problem caused by the circuit delay caused by the aging of the PMOS transistor to be tracked.

[0089] For example, see Figure 6 As shown, the control terminal is connected to the second data storage point K2 in the latch 1 through the third inverter M. The first multiplexer 43 is used to select the input inverter 41 when the control terminal A1 inputs a low level, and select the input signal DI of the original circuit 5 when the control terminal A1 inputs a high level. The second multiplexer 44 is used to select the output inverter 42 when the control terminal A1 inputs a low level, and select the output signal of the original circuit 5 when the control terminal A1 inputs a high level.

[0090] Thus, when the first PMOS transistor 111 is not aged, the K2 data is 0, and after being inverted by the third inverter M, a high level signal is output to the first multiplexer 43 and the second multiplexer 44. At this time, the input inverter 41 and the output inverter 42 are turned on, and the signal input to the original circuit 5 is DI'.

[0091] When the first PMOS transistor 111 ages, after power is turned on again, the K2 data is 1, and after being inverted by the third inverter M, a low-level signal is output to the first multiplexer 43 and the second multiplexer 44. At this time, the original circuit is directly connected to DI, the signal input to the original circuit 5 is DI, and the output of the original circuit 5 is DO. The above is achieved so that when the first PMOS transistor 111 tracks the aging of the PMOS transistor to be tracked, the path taken by the input signal DI of the original circuit is compared with that before aging, which reduces the effect of the two-stage inverter, and to a certain extent repairs the timing problem caused by the circuit delay caused by the aging of the PMOS transistor to be tracked.

[0092] To facilitate understanding of the solution provided in the embodiments of the present application, a specific example structure is taken as an example below to further illustrate the solution of the present application.

[0093] See also Figure 7As shown, the original circuit 5 is Figure 8 The 6T SRAM Cell (6T static random access memory cell) circuit is shown.

[0094] for Figure 8 In the 6T SRAM Cell circuit shown, assuming that Q is 0 and QB is 1, when no obvious aging occurs, the data read from the Cell is the correct data 0. If Q and QB are always maintained at 0 and 1, the PMOS transistor PUR is always in a negative bias state, and the aging problem becomes more serious over time, causing the Cell to read the opposite data.

[0095] This application Figure 7 The aging tracking circuit shown is before aging of the 6T SRAM Cell circuit:

[0096] When the 6T SRAM Cell circuit starts working, the 6T SRAM Cell circuit is powered on, that is, PowerOK = 1. After PowerOK is stable, a high level signal is input to DCH. Figure 7 The first NMOS transistor 21 and the second NMOS transistor 22 are turned on, and the K1 and K2 points are both pulled down to 0. Then DCH becomes a low level signal, and the first NMOS transistor 21 and the second NMOS transistor 22 are turned off.

[0097] For a circuit that works normally, that is, a circuit that has not aged, because the driving capability of the first NMOS transistor 21 is stronger than that of the second NMOS transistor 22, K1 is pulled up to 1, and finally a stable control signal 0 is generated through the third inverter M. When the first multiplexer 43 receives the control signal 0, the input signal DI is selected to be transmitted to the inside of the 6T SRAMCell circuit through the input inverter 41. Similarly, the second multiplexer 44 also receives the control signal 0, and the data DO finally read out is obtained through the output inverter 42. This method ensures that the read data (DO) and the written data (DI) are consistent, that is, the reading and writing are correct, but the data stored in the 6T SRAM Cell is DI, which is opposite to DI. ’ If the circuit is not aging, every time the power is turned on, Figure 7 The circuit in the above process works normally. The timing diagram of the circuit is as follows: Fig. 9 shown.

[0098] After the 6T SRAM Cell circuit ages: that is, when the circuit works for a long time, the transistors that are in the Keep initial state for a long time have serious aging problems, and the performance of the PMOS transistors inside the 6T SRAM Cell will degrade.

[0099] In latch 1, the 6T SRAM Cell circuit is also kept in the hold state after being powered on, and the first PMOS transistor 111 is in a negative bias state. After being affected by aging for a long time, the pull-up driving capability of the first PMOS transistor 111 is weaker than that of the second PMOS transistor 121. When the circuit is powered on next time, DCH generates a high-level signal, pulls down the data at points K1 and K2 to 0, and then changes to a low-level state. At this time, the pull-up driving capability of the second PMOS transistor 121 is stronger than that of the first PMOS transistor 111, resulting in K1 being pulled up to 1 and K2 being maintained at 0. Finally, K2 generates a stable control signal 1 through the third inverter M. When the first multiplexer 43 receives the control signal 1, the input end of the first multiplexer 43 selects a path without an inverter, and directly inputs DI into the 6T SRAM Cell circuit. Similarly, the second multiplexer 44 also receives the control signal 1, and the output also selects a path without an inverter, directly transmitting the output signal of the 6T SRAM Cell circuit to the outside of the circuit to obtain DO, and the read data DO also remains consistent with the input data DI, and the reading and writing are correct. At this time, the data stored in the 6T SRAM Cell circuit is the same as the input signal DI.

[0100] The data stored in the 6T SRAM Cell circuit before aging is opposite to the data stored after aging, so that the 6T SRAM Cell circuit affected by aging can be restored. In addition, the path taken by DI after aging repair is reduced by two inverters compared to before aging repair, so that the circuit delay caused by aging is also effectively compensated and repaired.

[0101] As for latch 1, the values ​​stored in k1 and k2 are opposite before and after aging repair. During the repair of original circuit 5, the first PMOS transistor 111 of latch 1 itself can also be repaired, thereby ensuring that the entire circuit can continue to work normally.

[0102] An embodiment of the present application also provides an electronic device, which includes an original circuit having a PMOS transistor to be tracked, and any of the aforementioned aging tracking circuits.

[0103] In an embodiment of the present application, the electronic device may have a circuit board, and the above-mentioned original circuit and aging tracking circuit are both arranged in the circuit board.

[0104] In the embodiment of the present application, the electronic device may be, but is not limited to, an electronic device such as a memory, a CPU, etc. that has a PMOS transistor aging tracking requirement.

[0105] The present application also provides an electronic device including the above electronic device. For example, the electronic device may be, but is not limited to, a server, a host, a computer, a mobile phone, etc., which has an electronic device with a PMOS transistor aging tracking requirement.

[0106] The aging tracking circuit, electronic device and electronic device provided in the embodiments of the present application have a first PMOS transistor whose size is consistent with the size of the PMOS transistor to be tracked in the original circuit, and during use, the first PMOS transistor has a size larger than the second PMOS transistor, so that the first PMOS transistor can be in a normally open state when in use when it is not aged (this is consistent with the use state of the PMOS transistor to be tracked), so that the first PMOS transistor can effectively simulate the aging condition of the PMOS transistor to be tracked, so that the aging condition of the first PMOS transistor can effectively represent the aging condition of the PMOS transistor to be tracked.

[0107] When the first PMOS transistor is not aged, the first PMOS transistor is normally open, and its driving capability is greater than that of the second PMOS transistor, so that the data in the second storage data point at the gate of the second PMOS transistor is 1, and the data in the first storage data point at the gate of the first PMOS transistor is 0. When the first PMOS transistor is aged, since the driving capability of the first PMOS transistor is less than that of the second PMOS transistor at this time, after the original circuit is powered on again, the data pull-down module clears the data in the latch, and the second PMOS transistor in the latch becomes normally open, so that the data in the first storage data point is 1, and the data in the second storage data point is 0. Therefore, each time the original circuit is powered on again, based on the data value in any data storage point in the latch, it can be effectively determined whether the PMOS transistor to be tracked in the original circuit is aged, thereby realizing aging tracking of the PMOS transistor to be tracked.

[0108] Moreover, the solution provided in the embodiment of the present application has a simple circuit implementation structure, and simulates the PMOS transistor to be tracked through the PMOS transistor in the latch. It is applicable to various original circuits with PMOS transistor aging tracking requirements (such as memory, logic circuits, large integrated circuits, etc.), has a wide range of applications, and high industrial application value.

[0109] In addition, the solution provided in the embodiment of the present application can, through the circuit repair module, enable the signal input into the original circuit through the circuit repair module after aging of the PMOS transistor to be tracked to be flipped relative to the signal input into the original circuit before aging, so that the PMOS crystal to be tracked in the original circuit can be restored by NBTI, thereby achieving the effect of autonomous repair of the PMOS crystal to be tracked.

[0110] In addition, since the driving capability of the first PMOS transistor is lower than that of the second PMOS transistor after aging, the second PMOS transistor becomes normally open in the latch, while the gate-source voltage of the first PMOS transistor remains in a positive bias state, so that the first PMOS transistor also performs NBTI recovery together with the PMOS crystal to be tracked, ensuring that during the autonomous repair process of the PMOS crystal to be tracked, the first PMOS transistor can still have a good aging tracking effect.

[0111] In addition, the solution provided by the embodiment of the present application can also enable the input inverter and the output inverter when the first PMOS transistor is not aged; and enable the input signal of the original circuit and the output signal of the original circuit when the first PMOS transistor is aged. When the first PMOS transistor is aged, the path taken by the input signal of the original circuit is reduced by two stages of inverters compared to before aging, so that the delay of the entire circuit is reduced, thereby repairing the timing problem caused by the circuit delay caused by the aging of the PMOS transistor to be tracked to a certain extent.

[0112] In the embodiments provided in this application, it should be understood that the disclosed circuit structure can be implemented in other ways. The embodiments described above are merely illustrative.

[0113] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0114] As used herein, a plurality refers to two or more than two.

[0115] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An aging tracking circuit, characterized in that: include: A latch, composed of a cross-coupled first inverter and a second inverter, wherein the first inverter has a first PMOS transistor, and the second inverter has a second PMOS transistor; the size of the first PMOS transistor is consistent with the size of the PMOS transistor to be tracked in the original circuit, and is larger than the size of the second PMOS transistor, and the driving capability of the first PMOS transistor after aging is smaller than the driving capability of the second PMOS transistor; A data pull-down module, wherein the first end is connected to the two data storage points of the latch, the second end is grounded, and the third end is used to access a control signal; the first end and the second end are turned on and off under the action of the control signal, wherein when the original circuit is powered on, the first end and the second end are turned on to clear the data in the two data storage points, and after the data in the two data storage points are cleared, the first end and the second end are disconnected; The data pull-down module includes a first NMOS transistor and a second NMOS transistor; the two data storage points are the first data storage point and the second data storage point; the drains of the first NMOS transistor and the second NMOS transistor together constitute the first end; wherein the drain of the first NMOS transistor is connected to the first data storage point, and the drain of the second NMOS transistor is connected to the second data storage point; the sources of the first NMOS transistor and the second NMOS transistor are the second end, both of which are grounded; the gates of the first NMOS transistor and the second NMOS transistor are the third end, both of which are connected to the control signal; wherein when the original circuit is powered on, the control signal is a high-level signal; after the data in the two data storage points are cleared, the control signal is a low-level signal; Alternatively, the data pull-down module includes a first NPN transistor and a second NPN transistor; the two data storage points are a first data storage point and a second data storage point; the drains of the first NPN transistor and the second NPN transistor together constitute the first end; wherein the drain of the first NPN transistor is connected to the first data storage point, and the drain of the second NPN transistor is connected to the second data storage point; the sources of the first NPN transistor and the second NPN transistor are the second end, both of which are grounded; the gates of the first NPN transistor and the second NPN transistor are the third end, both of which are connected to the control signal; wherein, when the original circuit is powered on, the control signal is a high-level signal; after the data in the two data storage points are cleared, the control signal is a low-level signal.

2. The aging tracking circuit according to claim 1, characterized in that: The aging tracking circuit also includes: The signal stabilization module is connected to any one of the two data storage points and is used to output the data in the data storage point in the form of a stable signal.

3. The aging tracking circuit according to claim 2, characterized in that: The signal stabilization module is an inverter and / or a buffer.

4. The aging tracking circuit according to any one of claims 1 to 3, characterized in that: The aging tracking circuit also includes: A circuit repair module, comprising a control end, a first input end, a first output end, a second input end, and a second output end; The first input end is used to access the input signal of the original circuit, and the first output end is used to access the input end of the original circuit; the second input end is used to access the output end of the original circuit to receive the output signal of the original circuit; The control end is connected to any one of the two data storage points; The circuit repair module is used to invert the input signal of the original circuit according to the signal of the connected data storage point, output the inverted input signal to the original circuit through the first output terminal, and invert the output signal of the original circuit, and output the inverted output signal through the second output terminal; or, output the input signal of the original circuit to the original circuit through the first output terminal, and output the output signal of the original circuit through the second output terminal.

5. The aging tracking circuit according to claim 4, characterized in that: The circuit repair module includes: an input inverter, an output inverter, a first multiplexer and a second multiplexer; One end of the input inverter is the first input end, and the other end is connected to the first multiplexer; One input end of the first multiplexer is the first input end, and the other input end is connected to the input inverter; the output end of the first multiplexer is the first output end; One end of the output inverter is the second input end, and the other end is connected to the second multiplexer; One input end of the second multiplexer is the second input end, and the other input end is connected to the output inverter; the output end of the second multiplexer is the second output end; The control ends of the first multiplexer and the second multiplexer are both connected to any one of the two data storage points; The first multiplexer and the second multiplexer are used to select the input inverter and the output inverter according to the signal of the connected data storage point; or, select the input signal of the original circuit and the output signal of the original circuit.

6. The aging tracking circuit according to claim 5, characterized in that: The first multiplexer and the second multiplexer are specifically used to: when the first PMOS transistor is not aged, enable the input inverter and the output inverter; when the first PMOS transistor is aged, enable the input signal of the original circuit and the output signal of the original circuit.

7. The aging tracking circuit according to claim 5, characterized in that: The two data storage points are a first data storage point and a second data storage point; the first data storage point is a data storage point connected to the gate of the first PMOS transistor; the second data storage point is a data storage point connected to the gate of the second PMOS transistor; The control terminal is connected to the second data storage point in the latch through a third inverter; The first multiplexer is used to select the input inverter when the control terminal inputs a low level, and select the input signal of the original circuit when the control terminal inputs a high level; The second multiplexer is used to select the output inverter when a low level is input to the control end, and to select the output signal of the original circuit when a high level is input to the control end.

8. An electronic device, characterized in that: include: An original circuit having a PMOS transistor to be tracked and an aging tracking circuit as claimed in any one of claims 1 to 7.

9. An electronic device, characterized in that: The electronic device comprising claim 8.

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