Identification of susceptibility to inductive charge leakage

Abstract

Aspects of the present disclosure relate to techniques for identifying susceptibility to inductive charge leakage. In some examples, a susceptibility test sequence that includes a cache line flush instruction is used to repeatedly activate rows of memory cells. The susceptibility test sequence causes inductive charge leakage within rows that are physically adjacent to the activated rows such that a physical adjacency map can be generated. In some other examples, the physical adjacency map is used to identify a set of adjacent rows for a target row. The susceptibility test sequence is used to repeatedly activate the set of adjacent rows, after which the contents of the target row are analyzed to determine whether any bits of the target row have been flipped due to inductive charge leakage. If no flipped bits are identified, an indication that the memory cells are not susceptible to inductive charge leakage is generated.

Description

BACKGROUND OF THE INVENTION

[0001] It is important to maintain the integrity of data stored in a computer memory, both in terms of reliability and for security reasons. However, in some cases, a computer memory may be susceptible to induced charge leakage, which may cause a bit in the memory to "flip" or change from its original value in response to other activity in the memory. Such charge leakage can result in data loss or corruption, or may introduce potential security issues (e.g., if the bit is related to memory access permissions, if the bit is outside of an application sandbox, etc.).

[0002] Embodiments are described with respect to these and other general considerations. Additionally, although relatively specific problems have been discussed, it should be understood that embodiments are not limited to solving the specific problems identified in the background art. SUMMARY OF THE INVENTION

[0003] Aspects of the present disclosure relate to techniques for identifying susceptibility to induced charge leakage. In some examples, a susceptibility test sequence that includes a cache line flush instruction is used to repeatedly activate rows of memory cells. In some cases, a refresh command is suppressed or deactivated, thereby preventing the memory cells from recharging their cells and preventing an increased likelihood of induced charge leakage. The susceptibility test sequence causes induced charge leakage within rows that are physically adjacent to the activated rows. Such rows are identified and used to generate a physical adjacency graph for the memory cells.

[0004] In some other examples, the physical adjacency graph is used to identify a set of adjacent rows for a target row. The susceptibility test sequence is used to repeatedly activate the set of adjacent rows, after which the contents of the target row are analyzed to determine whether any bits of the target row have been flipped due to induced charge leakage. If a flipped bit is identified, an indication that the memory cells are susceptible to induced charge leakage is generated. However, if no flipped bits are identified, an indication that the memory cells are not susceptible to induced charge leakage is generated. As a result of using the physical adjacency graph to determine adjacent rows and correspondingly test the adjacent rows, the likelihood of false negatives is reduced or eliminated because the set of adjacent rows is known to be adjacent to the target row.

[0005] The present summary is provided to introduce some concepts in a simplified form that will be further described in the detailed description below. The present summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Non-limiting and non-exhaustive examples are described with reference to the following figures.

[0007] Figures 1A - 1B Illustrated is an overview of an example computing device for identifying susceptibility to inductive charge leakage.

[0008] Figure 2 Illustrated is an overview of an example susceptibility test engine in accordance with aspects described herein.

[0009] Figure 3A Illustrated is an overview of an example method for generating an adjacency graph for memory addresses of memory cells.

[0010] Figure 3B Illustrated is an overview of an example method for evaluating memory cells according to an adjacency graph to determine susceptibility to inductive charge leakage.

[0011] Figure 4A Illustrated is an overview of an example method for generating a susceptibility test signal.

[0012] Figure 4B Illustrated is an overview of an example method for generating an adjacency graph from the contents of memory cells.

[0013] Figure 5 Is a block diagram of example physical components of a computing device that can be utilized to practice aspects of the present disclosure.

[0014] Figure 6A and Figure 6B Is a simplified block diagram of a mobile computing device that can be utilized to practice aspects of the present disclosure.

[0015] Figure 7 Is a simplified block diagram of a distributed computing system in which aspects of the present disclosure can be practiced.

[0016] Figure 8 Illustrated is a tablet computing device for performing one or more aspects of the present disclosure. Detailed Description

[0017] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific embodiments or examples. These aspects may be combined, other aspects may be utilized, and structural changes may be made without departing from the present disclosure. Embodiments may be practiced as a method, system, or device. Thus, embodiments may take the form of a hardware implementation, a fully software implementation, or an implementation combining software and hardware aspects. Accordingly, the following detailed description should not be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims and their equivalents.

[0018] In some examples, memories may be susceptible to inductive charge leakage. For example, dynamic random access memory (DRAM) uses capacitors to store information, where each bit of information is represented by a capacitor. Capacitors are typically arranged in rows and columns. Repeatedly applying current on one row may induce current on adjacent rows, thereby affecting the charge (and associated bits) of the capacitors in the adjacent rows. Thus, a memory access pattern (e.g., causing a row activation) in one area of the memory has the potential to affect other areas. In some cases, such areas may be otherwise inaccessible to the software that generates the memory access pattern (e.g., due to software protection, processor-level protection, etc.). Thus, inductive charge leakage not only results in the possibility of information loss or corruption, but also poses a security risk in cases where software can avoid or potentially circumvent memory protection. Such issues are also relevant in cloud computing scenarios, where multiple tenants may use the same computing resources (e.g., shared storage, shared processors, shared memories, etc.).

[0019] Accordingly, aspects of the present disclosure relate to techniques for identifying the susceptibility of memory cells to inductive charge leakage. In some examples, the memory cells are dual in-line memory modules (DIMMs), ranks of memory modules, or banks of memory modules, etc. A physical adjacency graph for the memory cells is generated to determine how memory addresses map to associated physical cells in the memory cells. The adjacency graph is used to determine a set of memory rows associated with a target row, and the set of memory rows is used to correspondingly test the memory cells. For example, the testing includes: attempting to use the set of memory rows to induce charge leakage in the target row of the memory cells. The memory cells are analyzed to determine whether any bits have been flipped, thereby determining whether the memory cells are susceptible to inductive charge leakage.

[0020] Accordingly, the aspects described herein enable the detection of memory cells that may pose a threat to computer security or exhibit the possibility of data loss or data corruption and other impairments. Additionally, as a result of generating the physical adjacency graph for the memory cells, the likelihood of false negatives (e.g., not being susceptible) is significantly reduced or eliminated. As used herein, a physical adjacency graph is a data structure by which physically adjacent rows are identified, even though the memory addresses for such rows may not be consecutive. Without using the adjacency graph, it is difficult to determine a set of rows adjacent to the target row in order to properly test the memory cells. Thus, if no flipped bits are identified, it may be the case that the memory cells are not susceptible to inductive charge leakage. However, it may also be the case that the set of rows used to perform the test is not adjacent to the target row and thus has little effect on the target row. In such cases, additional testing or time-consuming techniques may be required in order to ultimately determine the rows adjacent to the target row.

[0021] As used herein, the set of lines includes one or more lines adjacent to a target line (e.g., directly adjacent, separated by one or more intermediate lines, etc.), where the target line is the line being tested for susceptibility to inductive charge leakage. It should be understood that the set can include a single line, or in some other examples, the set includes multiple lines, where at least a sub - portion of each line is adjacent to the target line. For example, half of the first line and half of the second line can each be adjacent to the target line. Although example cell geometries of memory cells are described herein, it should be understood that similar aspects apply to any of a variety of other geometries.

[0022] In some examples, a refresh command is used to cause the memory cells to rewrite the data in each cell. For example, DRAM capacitors are restored to their original charge, thereby preserving the data represented by charged and uncharged capacitors. Thus, the refresh command effectively "resets" any charge leakage experienced by the memory cells, which makes it difficult to sense the charge leakage up to the point where a bit is flipped. Therefore, according to the aspects described herein, in order to sense and identify the flipped bits and generate an adjacency graph, it is preferable to generate a high activation rate (e.g., between refresh commands), and in some cases delay or inhibit the refresh command.

[0023] The susceptibility test sequences disclosed herein produce a relatively high activation rate, which increases the likelihood of sensing charge leakage. It should be understood that while various example test sequences are described herein, other test sequences can be used in other examples without departing from the spirit of the disclosure. For example, certain processor architectures may not implement some of the functionality described herein, or may provide different implementations that may produce different results.

[0024] As an example, the susceptibility test sequence can include a set of cache line flush operations in a loop (e.g., clflush or clflushopt, as implemented by various INTEL processors), where each operation is associated with a row of memory in a memory unit. In an example, an optimized cache line flush operation is used (such as clflushopt), which enables multiple cache lines to be flushed in parallel and / or executed with fewer micro-operations compared to other cache line flush instructions (e.g., clflush). It should be understood that clflushopt is referenced herein as an example of an optimized cache line flush operation (compared to clflush as another example), and different optimized cache line flush operations may be used in other examples. Thus, such an instruction can cause the processor to write the cache line associated with the memory row back to the memory unit and flush the line from the processor cache. In some examples, flushing the line from the cache causes the memory prefetcher to access the row and reload the data from the memory unit into the processor cache (e.g., even in the absence of a subsequent load or store instruction). Such behavior can be performed to efficiently use the processor cache, thereby maintaining a cache with data that may be accessed (e.g., associated with a memory row). As a result of the sequence loop, a large number of activations are generated, thereby generating a memory access pattern that may cause charge leakage.

[0025] In addition, using a susceptibility test sequence that includes cache line flush operations can reduce the impact of out-of-order execution optimizations typically implemented by the processor. Given the similarity of the instructions in the above example susceptibility test sequence, the order of the sequence does not significantly affect its effectiveness. As another example, the test sequence can include a load instruction and a cache line flush instruction for each memory row. The cache line flush instruction of such a sequence is used to reduce the likelihood that the processor uses its cache instead of accessing the memory unit to process subsequent load instructions. However, if the load instruction is executed before the cache line flush instruction is completed, the load instruction may not cause an activation to occur in the memory unit.

[0026] While the above example susceptibility test sequence can produce a relatively high activation rate, other techniques are described herein to increase the likelihood of inducing charge leakage. For example, as an addition or alternative to the above susceptibility test sequence, refresh commands can be suppressed, such that the cells of the memory cells gradually discharge rather than being periodically refreshed. As a result, the effects of the memory activations described herein are increased, such that flipped bits are more likely to manifest in the memory cells. Thus, as described above, one or more rows of the memory cells are repeatedly activated, after which the contents of the memory cells are analyzed to identify one or more affected rows. The affected rows in which the bits are flipped are identified and analyzed to determine their adjacency to other rows (e.g., whether they are fully adjacent, semi-adjacent, etc.). In some examples, such techniques are repeated for different rows in order to generate an adjacency graph in accordance with the aspects described herein.

[0027] In some examples, an interposer is used to suppress refresh commands. The interposer can be connected between the memory cells and the memory controller. The interposer can suppress refresh commands generated by the memory controller such that the refresh commands are not received by the memory cells. In some examples, the interposer suppresses the refresh commands in response to actuation of a physical button on the interposer, or in some other examples, the interposer can receive an indication from software executing on a computing device. For example, the interposer can identify commands associated with a particular memory address to indicate whether to suppress the refresh commands. In some examples, the same particular memory address is used to re-enable the refresh commands, or in other examples, a different memory address is used. In additional examples, the interposer is connected to the computing device using a computer bus, such as a Universal Serial Bus (USB) connection through which the interposer is controlled, as well as other connection techniques (e.g., any one of a variety of other buses, such as I2C or serial, etc.).

[0028] As an example, the interposer can manipulate signals for one or more memory cell pins associated with refresh commands of the memory cells. Using Double Data Rate 4 (DDR4) SDRAM as an example, the command encoding for DDR4 is such that A14 is manipulated to be always low in order to effectively suppress the refresh commands without affecting activation, precharge, or write commands. Conversely, changing A14 from high to low (thereby changing the refresh command to a mode register set command) has the effect of changing a read command to a write command. It should be understood that in some other examples, the interposer can change the signal from low to high. Even so, such a change still enables the susceptibility test sequence to be used on the memory cells. In such examples, additional pins can be manipulated. For example, bus parity can be enabled, and ALERT from the memory cells nThe signal can be suppressed when the refresh command is suppressed, thereby preventing the memory cells from being retrained by the memory controller. Once the susceptibility test sequence is complete, the ALERT n signal can be no longer suppressed, such that it is received by the memory controller, enabling the memory controller to retrain the memory cells (e.g., return the memory cells to a usable state).

[0029] It should be understood that the above DDR4 SDRAM example is provided for illustrative purposes, and in some other examples, other techniques can be used to suppress the refresh command. For example, an intermediary layer can be “active” such that it processes memory signals on the bus and relays them between the memory controller and the memory cells. Such an intermediary layer identifies the refresh command when it is passed from the memory controller to the memory cells, such that it can suppress the command by omitting the command while still relaying other communications between the memory controller and the memory cells. As another example, the refresh rate can be deactivated in software (e.g., by changing instructions executed by the memory controller and / or the processor, etc.).

[0030] To generate an adjacency graph, a predetermined sequence is written to the memory cells. As a result of using the predetermined sequence, the contents of the memory cells can later be evaluated based on the sequence to identify bits that have been flipped. In some other examples, the contents of the memory are read and stored for later comparison. Subsequently, according to the aspects described herein, a susceptibility test sequence is used to repeatedly activate one or more rows of the memory cells. In some examples, the refresh command is delayed or suppressed as discussed above. Once the test sequence is complete, the contents of the memory are analyzed to determine the frequency and location of bits that have been flipped. For example, the contents can be compared to the predetermined sequence, or in some other examples, the contents can be compared to the stored contents. One or more rows that exhibit a higher or highest percentage of flipped bits can be determined to be adjacent to the activated memory rows, such that the adjacency graph can indicate that such rows are adjacent. As an example, the adjacency graph can include a list of memory addresses, where the listed addresses are physically adjacent, even though the logical memory addresses may not be numerically adjacent. Such an evaluation can be iteratively performed for additional rows of the memory cells, thereby forming the adjacency graph.

[0031] In some examples, multiple susceptibility tests are performed in parallel to speed up the rate at which susceptibility tests are performed. For example, multiple memory banks and / or memory arrays of memory cells can be tested simultaneously. In another example, only a subset of the memory rows are evaluated (e.g., a consecutive set of rows, randomly sampled rows, a set of rows programmed based on previous observations, etc.). As another example, multiple susceptibility test sequences can be performed simultaneously, after which the contents of the memory can be evaluated for each row associated with the multiple test sequences. Thus, activation and content evaluation can each be batched and performed serially to reduce the overhead associated with suppressing refresh commands (and in some cases restoring the memory cells to a usable state).

[0032] Once the adjacency graph is generated, a target row is selected. A set of adjacent rows for the target row is determined based on the adjacency graph. A predetermined sequence can be loaded into the target row, or in some other examples, the contents of the target row are read and stored. Then, the set of adjacent rows can be activated using a susceptibility test sequence, after which the target row is evaluated (e.g., according to the predetermined sequence, the stored contents, etc.) to determine if there are flipped bits. In some examples, the evaluation is performed without suppressing or delaying the refresh command to determine if the memory cells are susceptible to inductive charge leakage under normal operating conditions. If no flipped bits are identified, an indication that the memory cells are not susceptible can be generated. In contrast, if flipped bits are identified, an indication that the memory cells are susceptible can be generated. In some examples, multiple such evaluations (e.g., multiple evaluations in a given memory array, multiple evaluations in a given memory bank, etc.) are performed before such an indication is provided. In examples where multiple such evaluations are performed, the indication can include a failure rate (e.g., the percentage of tests indicating that the memory cells are susceptible) and / or a sub - portion of the memory cells identified as susceptible (e.g., a memory array or a memory bank, etc.). In some examples, the adjacency graph for previously observed memory cells is used, which can be the case when the memory cells are manufactured by the same manufacturer, from the same batch, or exhibit the same or similar characteristics as previous memory cells, etc. Thus, adjacency graph generation does not need to be performed before testing each memory cell.

[0033] Figures 1A - 1B An example overview of example computing devices 100 and 110 for identifying susceptibility to inductive charge leakage is illustrated. First, turning to Figure 1A, the computing device 100 is illustrated as including a susceptibility testing engine 102, a processing unit 104, a memory controller 106, and a memory unit 108. In some examples, the computing device 100 is a desktop computing device, a server computing device, a laptop computing device, or a mobile computing device, etc. In some cases, the computing device 100 includes a high-level operating system (e.g., MICROSOFT WINDOWS, LINUX, MAC OS, etc.) in which the susceptibility testing engine 102 is located. In some other examples, the susceptibility testing engine 102 executes on the computing device 100 without such a high-level operating system (e.g., from an Extensible Firmware Interface (EFI) console), thereby removing a potential abstraction layer that may exist for memory addresses. For example, one or more system virtual address tables may be used by the operating system (and, in some cases, a hypervisor). System virtual addresses can be translated into system physical addresses, which in turn can be translated into logical addresses. Finally, the logical addresses can be translated into internal addresses used by the memory unit. Thus, in some examples, one or more such abstraction layers can be omitted.

[0034] The processing unit 104 executes instructions (e.g., the susceptibility testing engine 102) and communicates with the memory unit 108 via the memory controller 106. In some examples, the memory controller 106 is part of the processing unit 104. As discussed above, the memory unit 108 includes cells that store bits. As an example, the memory unit 108 is a DIMM composed of capacitors for storing information bits. In some other examples, the memory unit 108 is a sub-part of a memory module, such as a memory bank or a memory bank, etc. As described above, the memory controller 106 periodically passes a refresh command to the memory unit 108.

[0035] According to aspects described herein, the susceptibility testing engine 102 generates an adjacency graph and tests the susceptibility of the memory unit to inductive charge leakage. The susceptibility testing engine 102 can initialize the memory unit 108 by loading a predetermined sequence. For example, the predetermined sequence may include bits all of "1", bits two-thirds of which are "1" (e.g., 0xB6DB6DB…), bits one-third of which are "1" (e.g., 0x4924924…), or bits all of "0". In another example, the susceptibility testing engine can read and store the content of the memory unit 108. Although example sequences are described herein, it should be understood that any one of a variety of other sequences can be used.

[0036] In some examples, processing unit 104 implements cache line flush operations such as clflush or clflushopt. For example, processing unit 104 may write the cache line indicated by the operation back to memory unit 108 and flush the line from the processor cache. In some cases, the memory prefetcher of processing unit 104 accesses the flushed line and reloads the data from memory unit 108 into the processor cache. As a result of the sequence loop, therefore, a large number of activations are generated by processing unit 104, such that the memory access pattern may induce charge leakage within memory unit 108.

[0037] Accordingly, susceptibility test engine 102 uses a susceptibility test sequence that includes one or more cache line flush operations as discussed above. For example, susceptibility test engine 102 may repeatedly activate a single memory row of memory unit 108, or in some other examples, may activate multiple memory rows (e.g., rows that are considered proximate or adjacent, rows in different banks, etc.). Susceptibility test engine 102 may then evaluate the contents of memory unit 108 to determine the location and frequency of flipped bits. In some examples, the evaluation includes comparing the contents of memory unit 108 to a predetermined sequence or previously stored contents. The location and frequency of the flipped bits are then compared to one or more rows for which the susceptibility test sequence is performed in order to generate a physical adjacency map.

[0038] Susceptibility test engine 102 may use the adjacency map to evaluate a target row. In an example, the adjacency map is generated based on the evaluation of memory unit 108. In some other examples, the characteristics of memory unit 108 are evaluated to determine a pre-existing adjacency map. Example characteristics include but are not limited to the manufacturer, serial number, lot number, capacity, operating frequency, number of banks, and / or manufacturing date, etc. The adjacency map is used to determine a set of adjacent rows for the target row. Susceptibility test engine 102 may load a predetermined bit sequence into the target row, or may read and store the contents of the target row. Susceptibility test engine 102 may perform the susceptibility test sequence for each adjacent row, after which susceptibility test engine 102 evaluates the target row (e.g., compared to a predetermined sequence, stored contents, etc.) to determine if any bits have been flipped. If no flipped bits are identified, susceptibility test engine 102 generates an indication that the memory unit is not susceptible. In contrast, if flipped bits are identified, susceptibility test engine 102 generates an indication that the memory unit is susceptible. It should be understood that this is a simplified example of the aspects described herein. In some other examples and as described above, multiple such evaluations are performed (e.g., multiple rows in the same bank, multiple banks of the same memory unit, etc.).

[0039] Now turning to Figure 1B, the computing device 110 is illustrated as including a susceptibility engine 112, a processing unit 114, a memory controller 116, and a memory unit 118. Such aspects are similar to those discussed above with respect to Figure 1A and are therefore not required to be described in detail again below. The computing device 110 also includes an interposer layer 120. In some examples, the interposer layer 120 is communicatively coupled between the memory unit 118 and the memory controller 116. As discussed above, the interposer layer 120 is used to inhibit the refresh commands generated by the memory controller 116 such that the memory unit 118 does not refresh its cells, thereby increasing the effectiveness of the susceptibility test sequence. In some examples, the interposer layer 120 also inhibits the ALERT n signal from the memory unit 118. It should be understood that, in addition to refresh commands, the interposer layer 120 may also inhibit or manipulate any one of a variety of other signals. In some examples, the interposer layer 120 includes a physical button for toggling refresh command inhibition. In some other examples, the interposer layer 120 identifies specific commands or memory addresses (and other indications) in order to determine whether to inhibit or allow refresh commands. For example, the susceptibility test engine 112 may generate an indication to the interposer layer 120 that refresh commands should be inhibited, after which it may perform a susceptibility test sequence and subsequently generate an indication that normal operation of the interposer layer 120 should resume.

[0040] Figure 2 illustrates an overview of an example susceptibility test engine 200 in accordance with aspects described herein. In some examples, the susceptibility test engine 200 is similar to the susceptibility test engine 102 or the susceptibility test engine 112 in Figure 1A and 1B discussed above. The susceptibility test engine 200 is illustrated as including a memory initializer 202, a susceptibility test signal generator 204, and a memory cell evaluation engine 206.

[0041] The memory initializer 202 initializes the memory unit for susceptibility testing. In some examples, the memory initializer 202 loads a predetermined bit sequence into the memory unit. Example sequences include, but are not limited to, all "1" bits, a repeating variation ratio of "1" and "0" bits (e.g., two to three, one to three, etc.), or all "0" bits. In some other examples, the memory initializer 202 reads and stores at least a portion of the contents of the memory unit. In some examples, the stored contents are compressed. As another example, the memory initializer 202 generates an indication to the interposer layer (e.g., Figure 1B the interposer layer 120 in n) indication. In another example, the memory initializer 202 also enables parity associated with the memory cells.

[0042] The susceptibility test engine 200 also includes a susceptibility test signal generator 204 that performs a susceptibility test sequence in accordance with aspects described herein. In some examples, the susceptibility test signal generator iteratively performs the susceptibility test sequence for different rows of the memory cells. For example, the susceptibility test signal generator 204 may select sequential rows to test, or may determine subsequent rows based on results from previously evaluated rows, and so on. As described above, the susceptibility test signal generator 204 may use one or more cache line flush instructions, such as clflush or clflushopt, to cause the processing unit (e.g., processing unit 104 or processing unit 114 in Figure 1A or Figure 1B ) to prefetch lines from the memory cells (e.g., lines that may be associated with the lines specified by the cache line flush instruction). Thus, the susceptibility test signal generator repeatedly activates one or more rows of the memory cells to sense charge leakage.

[0043] Once the susceptibility test signal generator 204 completes the susceptibility test sequence, the memory cell evaluation engine 206 evaluates the contents of the memory cells. In some examples, the contents are compared to a predetermined sequence or previously stored contents (e.g., contents that may have been loaded or stored by the memory initializer 202). The memory cell evaluation engine 206 identifies the locations and frequencies of the flipped bits compared to the rows tested by the susceptibility test signal generator 204. Thus, the memory cell evaluation engine 206 generates a physical adjacency graph. For example, one or more rows with the highest percentage of flipped bits may be determined to be directly adjacent to the test row. In another example, the row with the second highest percentage of flipped bits may be determined to be indirectly adjacent to the tested row, separated by an intermediate row (e.g., the row with the highest percentage of flipped bits). Thus, one or more rows may be ranked according to the incidence of flipped bits to generate the adjacency graph. In some examples, the rows of the memory address may be split across multiple rows (e.g., half-row adjacency, third-row adjacency, etc.), where multiple tested rows exhibit a smaller percentage of flipped bits. For example, only about half of the cells in a semi-adjacent row may be adjacent to the test row and may thus exhibit flipped bits. The other half is not adjacent and may thus exhibit fewer flipped bits or no flipped bits, such that the maximum percentage of flipped bits for such a row would be about half of the cells.

[0044] In some other examples, the susceptibility test signal generator 204 uses a physical adjacency graph (e.g., which can be generated by the memory evaluation engine 206) to evaluate the target row. As described above, the memory initializer 202 can load a predetermined set of bits into the target row or can store content for later evaluation. The susceptibility test signal generator 204 can determine a set of adjacent rows for the target row and can perform a susceptibility test sequence for the determined set of rows. Then, the memory cell evaluation engine 206 can evaluate the target row to determine whether any bits of the target row have been flipped. It should be understood that such an evaluation can be performed multiple times (e.g., on the same target row, for other rows in the same bank, rows in one or more other banks, etc.).

[0045] Figure 3A FIG. illustrates an overview of an example method 300 for generating an adjacency graph for a memory address of a memory cell. In some examples, aspects of method 300 are performed by a susceptibility test engine, such as susceptibility test engines 102, 112, or 200 in Figure 1A , Figure 1B or Figure 2 respectively. Method 300 begins at operation 302, where the memory cell is initialized for evaluation. In some examples, aspects of operation 302 are performed by a memory initializer, such as memory initializer 202 in Figure 2 . As an example, a predetermined bit sequence is loaded into the memory cell. In some other examples, at least a portion of the content of the memory cell is read and stored. In some examples, the content can be compressed before storage. As another example, a suppress refresh command (and in some examples, an indication to suppress one or more other commands, such as ALERT Figure 1B ) can be provided to an intervening layer (e.g., intervening layer 120 in n ). In another example, parity associated with the memory cell can be enabled.

[0046] At operation 304, a susceptibility test sequence is performed. In an example, aspects of operation 304 are performed by a susceptibility test signal generator, such as Figure 2The susceptibility test signal generator 204 in []. As described above, the susceptibility test sequence may include one or more cache line flush instructions associated with a set of memory rows, including but not limited to clflush or clflushopt. In some examples, in addition to the cache line flush instructions, the susceptibility test sequence may further include one or more load memory instructions. For example, a set of clflushopt instructions may be used in a loop to cause the processor to write the cache line back to the memory cell and flush the line from the processor cache. As a result, the memory prefetcher accesses the line and reloads the data from the memory cell into the processor cache. Operation 304 is depicted with an arrow pointing to itself to indicate that the susceptibility test sequence is repeatedly executed or otherwise executed in a loop to repeatedly activate one or more rows of the memory.

[0047] The process proceeds to operation 306, where the memory cell returns to an available state. Operation 306 is illustrated with a dashed box to indicate that operation 306 is only performed in some examples. For example, if an intervening layer (e.g., Figure 1B the intervening layer 120 in []) is used and the ALERT n signal is suppressed, an indication is generated to instruct the intervening layer to allow the ALERT n instruction to flow between the memory cell and the memory controller, causing the memory controller to recondition the memory cell and restore the memory cell to a normal state. As another example, an indication to the intervening layer that a refresh command is received by the memory cell is generated. It should be understood that any of a variety of other operations may be performed to return the memory cell to a normal state.

[0048] The process proceeds to operation 308, where the memory cell is evaluated to identify flipped bits. Aspects of operation 308 may be performed by a memory cell evaluation engine, such as Figure 2 the memory cell evaluation engine 206 in []. In some examples, the content of the memory cell is compared with a predetermined sequence or previously stored content (e.g., that may have been loaded or stored at operation 302). The evaluation may include determining the location and / or frequency of the flipped bits in the memory cell. As an example, the location may be compared with one or more rows tested by the susceptibility test sequence, as performed at operation 304. Method 300 is illustrated as including an arrow from operation 308 to operation 304 to illustrate that the susceptibility test may be repeatedly executed. For example, the same memory row may be evaluated multiple times and / or different memory rows may be evaluated, and so on. Thus, the process may loop between operation 304 and operation 308.

[0049] Finally, the process reaches operation 310, where a physical adjacency graph is generated based on the flipped bits identified at operation 308. In some examples, aspects of operation 310 are performed by a memory cell evaluation engine, such as Figure 2 the memory cell evaluation engine 206 in As an example, one or more rows identified as having the highest percentage of flipped bits relative to the row being tested can be determined to be directly adjacent to the row being tested. In another example, a row having the second highest percentage of flipped bits can be determined to be indirectly adjacent to the row being tested, separated by an intermediate row (e.g., the row having the highest percentage of flipped bits in the previous example). Thus, one or more rows can be ranked according to the incidence of flipped bits. The ranked list can be processed according to a threshold (e.g., at or above a certain percentage, at or above a position in the ranked list, etc.), where one or more rows above the threshold are determined to be adjacent to the memory row. As discussed above, the rows of a memory address can be split across multiple rows, where multiple rows being tested exhibit a smaller proportion of flipped bits than would be observed in the case of full row adjacency. The process terminates at operation 310.

[0050] Although the operations of method 300 are described above in a particular order, it should be understood that any of a variety of other orders can be utilized. For example, prior to proceeding to operations 306 and 308, multiple memory rows can be processed at operation 304 such that the evaluation at operation 308 is performed for each memory row in the memory rows tested at operation 304. As another example, method 300 can be executed to test the memory rows of multiple banks simultaneously, as discussed in more detail above.

[0051] Figure 3B An overview of an example method 350 is illustrated for evaluating memory cells according to an adjacency graph to determine the susceptibility of the memory cells to inductive charge leakage. In an example, aspects of method 350 are performed by a susceptibility test engine, such as the susceptibility test engine 102, 112, or 200 in Figure 1A , Figure 1B or Figure 2 respectively. Method 350 begins at operation 352, where a set of adjacent rows for a target row is determined based on a physical adjacency graph. In some examples, the physical adjacency graph is according to that described above with respect to Figure 3AAspects of the method 300 under discussion are generated. In some examples, a physical adjacency graph is generated based on memory cells undergoing testing, while in some other examples, the adjacency graph is generated from different memory cells and selected based on an evaluation of characteristics associated with the memory cells. The set of adjacent rows can include a single row, or in some other examples can include multiple rows, where at least a sub - portion of each row is adjacent to the target row. For example, half of the first row and half of the second row can each be adjacent to the target row.

[0052] The process proceeds to operation 354, where a susceptibility test sequence is executed for the set of adjacent rows. In some examples, aspects of operation 354 are performed by a susceptibility test signal generator, such as Figure 2 the susceptibility test signal generator 204 in. In some examples, the target row is initialized with a predetermined bit sequence, or the content of the target row is read and stored, as can be performed by a memory initializer (e.g., Figure 2 the memory initializer 202 in). As described herein, the susceptibility test sequence can include one or more cache line flush instructions for each adjacent row. In some examples, in addition to cache line flush instructions, the susceptibility test sequence can also include one or more load memory instructions. Operation 354 is depicted with an arrow pointing to itself to indicate that the susceptibility test sequence is repeatedly executed or otherwise executed in a loop, thereby repeatedly activating each of the adjacent rows in the memory cells.

[0053] The process proceeds to determination 356, where it is determined whether there are flipped bits in the target row. Aspects of determination 356 can be performed by a memory cell evaluation engine, such as Figure 2 the memory cell evaluation engine 206 in. In some examples, the target row of the memory cell is compared to a predetermined sequence or previously stored content (e.g., that may have been loaded into or stored at the target row at operation 354).

[0054] If it is determined that there are flipped bits, the process branches "yes" to operation 360, where an indication that the memory cell is susceptible is generated. In some examples, the indication includes an indication regarding the memory bank of the memory cell or the number or percentage of bits determined to have been flipped. The process terminates at operation 360.

[0055] However, if it is determined that there are no flipped bits, the process instead branches "no" to operation 362, where an indication that the memory cell is not susceptible is generated. In some examples, the indication includes the number or percentage of bits examined and / or the number of times the test was performed, etc. The process terminates at operation 362.

[0056] It should be understood that the above discussion of method 350 provides a simplified example of aspects described herein. In some other examples and as discussed above, multiple such susceptibility assessments are performed (e.g., multiple times for the same row, multiple rows in the same bank, multiple banks of the same memory cell, etc.). Additionally, multiple target rows can be tested simultaneously.

[0057] Figure 4A FIG. illustrates an overview of an example method 400 for generating a susceptibility test signal. In some examples, aspects of method 400 are performed by a susceptibility test signal generator, such as Figure 2 the susceptibility test signal generator 204 in. In some other examples, aspects of method 400 can be performed separately at Figure 3A or Figure 3B operation 304 or operation 354 in. It should be understood that method 400 is provided as an example, and in other examples, other test sequences can be used without departing from the spirit of the present disclosure. For example, certain processor architectures may not implement some of the functionality described herein, or may provide different implementations of the instructions discussed below, which may produce different results.

[0058] Method 400 begins at operation 402, where a cache line flush instruction for a first memory row is generated. In some examples, the memory row is a memory row for generating a physical adjacency graph, as discussed above with respect to Figure 3A operation 304 in. In another example, the memory row is an adjacent row to a target memory row, as discussed above with respect to Figure 3B operation 354 in. As an example, the cache line flush instruction can be a clflush or clflushopt instruction, as implemented by various INTEL processors. Thus, a processing unit (e.g., the processing unit 104 or the processing unit 114 in Figure 1A or Figure 1B ) can write the cache line associated with the memory row back to the memory cell and flush the line from the processor cache. In response, the memory prefetcher accesses the line from the memory cell and reloads the data into the processor cache.

[0059] In some examples, the process proceeds to operation 404, where a cache line flush instruction for a second memory row is generated. The dashed box is used to illustrate operation 404 to indicate that operation 404 is omitted in some other examples. Specifically, the process loops at operation 402, thereby generating a high rate of memory activations for the first memory row. Operation 404 can be performed in examples that use another adjacent row of the target row. In some other examples, the second memory address is in a different memory bank. Similar to operation 402, a clflush or clflushopt instruction indicating the second memory row can be used. The process is illustrated as looping between operation 402 and operation 404 to generate a high rate of memory activations for both the first memory row and the second memory row. The process eventually terminates, after which the memory contents are evaluated according to the aspects described herein.

[0060] Figure 4B An overview of an example method 450 for generating an adjacency graph from the contents of memory cells is illustrated. In some examples, aspects of method 450 are performed by a memory cell evaluation engine, such as Figure 2 the memory cell evaluation engine 206 in Figure 3A The memory contents evaluated by method 450 may have been generated based on the execution of Figure 4A at least a portion of the method 300 in Figure 3A and / or

[0061] Method 450 begins at operation 452, where a set of memory rows of the memory content are selected based on a target row. In some examples, one or more memory rows are selected based on proximity to the target row. For example, memory rows directly adjacent to the target row may be selected for evaluation. In some other examples, the analysis may evaluate memory rows that are increasingly farther from the target row. As an example, the first row directly adjacent (e.g., plus or minus one row), then the row adjacent but separated by the first row (e.g., plus or minus two rows), and so on. As another example, the memory rows may be selected according to one or more adjacency graphs generated from previously analyzed memory cells. In such a case, it may be determined that for a given target row, one or more predicted rows should be evaluated. The predicted rows may be determined based on which rows have generally been observed to be adjacent to the target row of the previous memory cells. Such an analysis may be performed based on the adjacency graph, for the same vendor, same memory capacity, etc. While example techniques for determining one or more memory rows for evaluation are described herein, it should be understood that any of a variety of other techniques may be used.

[0062] The process proceeds to operation 454, where the flipped bits are identified in the determined set of memory rows. In some examples, the memory content associated with the set of memory rows is evaluated according to a predetermined pattern or the previously stored content for the memory rows, as described above. Method 450 is illustrated with an arrow from operation 454 to operation 452 to indicate that operations 452 and 454 may be performed multiple times, each time for a different memory row of the memory content. For example, the frequency of the flipped bits may be determined for the rows on either side of the target row until a given threshold. As an example, the threshold may be determined based on the number of rows in the memory bank, or based on the average number of rows that are expected or previously observed to exhibit the effect of inductive charge leakage. In some other examples, the process loops between operation 452 and operation 454 until no more flipped bits are identified.

[0063] Move to operation 456, where the proximity of the selected memory row to the target row is determined. In some examples, one or more rows identified as having the highest percentage of flipped bits relative to the target row can be determined to be directly adjacent to the test row. If there are multiple such rows (e.g., rows on either side of the target row), the order of the rows can be determined based on observations for other memory rows. For example, a memory row two rows larger than the target memory row can be observed, such that the memory row between that other memory row and the target memory row is determined to be the row one row larger than the target row. In another example, the row with the second highest percentage of flipped bits can be determined to be indirectly adjacent to the row being tested, separated by an intermediate row (e.g., the row with the highest percentage of flipped bits in the previous example). As discussed above, a memory address for a row can be split across multiple rows, where multiple rows being tested exhibit a smaller proportion of flipped bits than observed in the case of full row adjacency. The process terminates at operation 456.

[0064] Figures 5 - 8 and the associated description provide a discussion of the various operating environments in which aspects of the present disclosure may be practiced. However, the devices and systems Figures 5 - 8 illustrated and discussed are for purposes of example and illustration and do not limit the vast number of computing device configurations that may be used to practice the aspects of the present disclosure described herein.

[0065] Figure 5 is a block diagram illustrating the physical components (e.g., hardware) of a computing device 500 that can be utilized to implement aspects of the present disclosure. The computing device components described below can be suitable for the computing devices described above, including Figure 1A and Figure 1B the computing device 100 and the computing device 110 in

[0066] In a basic configuration, the computing device 500 can include at least one processing unit 502 and a system memory 504. Depending on the configuration and type of the computing device, the system memory 504 can include, but is not limited to, volatile storage (e.g., random access memory), non-volatile storage (e.g., read only memory), flash memory, or any combination of such memories.

[0067] In addition, embodiments of the present disclosure may be practiced in conjunction with a graphics library, other operating systems, or any other application and are not limited to any particular application or system. This basic configuration is illustrated by those components within the dashed line 508 in Figure 5 FIG. The computing device 500 may have additional features or functionality. For example, the computing device 500 may also include additional data storage devices (removable and / or non-removable), such as, for example, magnetic disks, optical disks, or magnetic tapes. Such additional storage devices are illustrated by the removable storage device 509 and the non-removable storage device 510 in Figure 5 FIG.

[0068] As described above, many program modules and data files may be stored in the system memory 504. Although executed on the processing unit 502, the program modules 506 (e.g., applications 520) may perform processes including but not limited to aspects as described herein. Other program modules that may be used in accordance with aspects of the present disclosure may include email and contact applications, word processing applications, spreadsheet applications, database applications, slide presentation applications, drawing or computer-aided applications, and the like.

[0069] In addition, embodiments of the present disclosure may be practiced in an electronic circuit or on a single chip containing electronic components or a microprocessor, the electronic circuit including discrete electronic components, a package or integrated electronic chip containing logic gates, a circuit utilizing a microprocessor. For example, embodiments of the present disclosure may be practiced via a system-on-a-chip (SOC), where Figure 5 each or many of the components illustrated in FIG. may be integrated onto a single integrated circuit. Such SOC devices may include one or more processing units, graphics units, communication units, system virtualization units, and various application functionality, all integrated (or "burned") onto a chip substrate as a single integrated circuit. When operating via an SOC, the functionality described herein with respect to the capabilities of the client-to-switch protocol may be operated via dedicated logic integrated on a single integrated circuit (chip) together with other components of the computing device 500. Embodiments of the present disclosure may also be practiced using technologies capable of performing logical operations such as, for example, AND, OR, and NOT (including but not limited to mechanical, optical, fluidic, and quantum technologies). Additionally, embodiments of the present disclosure may be practiced within a general purpose computer or any other circuit or system.

[0070] The computing device 500 may also have one or more input devices 512, such as a keyboard, a mouse, a pen, a voice or speech input device, a touch or swipe input device, etc. (Multiple) output devices 514, such as a display, a speaker, a printer, etc., may also be included. The foregoing devices are examples and other devices may be used. The computing device 500 may include one or more communication connections 516 that allow communication with other computing devices 550. Examples of suitable communication connections 516 include, but are not limited to, radio frequency (RF) transmitter, receiver, and / or transceiver circuitry; universal serial bus (USB), parallel, and / or serial ports.

[0071] As used herein, the term computer-readable medium may include computer storage media. Computer storage media may include volatile and non-volatile media, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, or program modules. System memory 504, removable storage device 509, and non-removable storage device 510 are all examples of computer storage media (e.g., memory storage devices). Computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical storage devices, magnetic tape cartridges, tapes, magnetic disk storage devices or other magnetic storage devices, or any other article capable of storing information and accessible by the computing device 500. Any such computer storage media may be part of the computing device 500. Computer storage media does not include carrier waves or other propagated or modulated data signals.

[0072] Communication media may be embodied by computer-readable media, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission media, and includes any information delivery media. The term "modulated data signal" may describe a signal having one or more characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media may include wired media such as a wired network or direct wired connection, and wireless media such as acoustic, radio frequency (RF), infrared, and other wireless media.

[0073] Figure 6A and Figure 6B Illustrated is a mobile computing device 600, such as a mobile phone, a smartphone, a wearable computer (such as a smartwatch), a tablet computer, a laptop computer, etc., that may be utilized to practice embodiments of the present disclosure. In some aspects, the client may be a mobile computing device. Referring to Figure 6A, which illustrates one aspect of a mobile computing device 600 for implementing various aspects. In a basic configuration, the mobile computing device 600 is a handheld computer with both input and output components. The mobile computing device 600 typically includes a display 605 and one or more input buttons 610 that allow a user to enter information into the mobile computing device 600. The display 605 of the mobile computing device 600 can also be used as an input device (e.g., a touchscreen display).

[0074] If included, the optional side input component 615 allows additional user input. The side input component 615 can be a rotary switch, a button, or any other type of manual input component. In alternative aspects, the mobile computing device 600 can include more or fewer input components. For example, in some embodiments, the display 605 may not be a touchscreen.

[0075] In yet another alternative embodiment, the mobile computing device 600 is a portable telephone system, such as a cellular phone. The mobile computing device 600 can also include an optional keypad 635. The optional keypad 635 can be a physical keypad or a "soft" keypad generated on a touchscreen display.

[0076] In various embodiments, the output components include a display 605 for presenting a graphical user interface (GUI), visual indicators 620 (e.g., light-emitting diodes), and / or audio transducers 625 (e.g., speakers). In some aspects, the mobile computing device 600 includes a vibration transducer for providing tactile feedback to the user. In yet another aspect, the mobile computing device 600 includes input ports and / or output ports, such as an audio input (e.g., a microphone jack), an audio output (e.g., a headphone jack), and a video output (e.g., an HDMI port), for sending signals to or receiving signals from external devices.

[0077] Figure 6B is a block diagram of an architecture that illustrates one aspect of a mobile computing device. That is, the mobile computing device 600 can include a system (e.g., an architecture) 602 to implement some aspects. In one embodiment, the system 602 is implemented as a "smartphone" capable of running one or more applications (e.g., a browser, email, calendar, contact manager, messaging client, game, and media client / player). In some aspects, the system 602 is integrated as a computing device, such as an integrated personal digital assistant (PDA) and a wireless phone.

[0078] One or more applications 666 may be loaded into the memory 662 and run on or in association with the operating system 664. Examples of applications include a phone dialer, an email program, a personal information management (PIM) program, a word processing program, a spreadsheet program, an Internet browser program, a messaging program, and the like. System 602 also includes a non-volatile storage area 668 within the memory 662. The non-volatile storage area 668 may be used to store persistent information that should not be lost when the system 602 is powered down. The applications 666 may use the information in the non-volatile storage area 668 (such as emails or other messages used by an email application) and store information in the non-volatile storage area 668. A synchronization application (not shown) also resides on the system 602 and is programmed to interact with a corresponding synchronization application residing on a host computer to keep the information stored in the non-volatile storage area 668 synchronized with the corresponding information stored at the host computer. As should be understood, other applications may be loaded into the memory 662 and run on the mobile computing device 60 described herein (e.g., a search engine, an extractor module, a relevance ranking module, an answer scoring module, etc.).

[0079] System 602 has a power source 670, which may be implemented as one or more batteries. The power source 670 may also include an external power source, such as a supplementary battery or an AC adapter or a power supply docking cradle for recharging the battery.

[0080] System 602 may also include a radio interface layer 672 that performs the functions of transmitting and receiving radio frequency communications. The radio interface layer 672 supports wireless connectivity between the system 602 and the "outside world" via a communication carrier or service provider. Transmissions to and from the radio interface layer 672 are under the control of the operating system 664. In other words, communications received by the radio interface layer 672 may be disseminated to the applications 666 via the operating system 664, and vice versa.

[0081] The visual indicator 620 can be used to provide visual notifications, and / or the audio interface 674 can be used to generate audible notifications via the audio transducer 625. In the illustrated embodiment, the visual indicator 620 is a light-emitting diode (LED), and the audio transducer 625 is a speaker. These devices can be directly coupled to the power supply 670 such that when activated, they remain on for a duration indicated by the notification mechanism, even if the processor 660 and other components may power down to conserve battery power. The LED can be programmed to remain on indefinitely until the user takes an action to indicate the on state of the device. The audio interface 674 is used to provide audible signals to the user and receive audible signals from the user. For example, in addition to being coupled to the audio transducer 625, the audio interface 674 can also be coupled to a microphone to receive audible input, such as to support a telephone conversation. According to an embodiment of the present disclosure, the microphone can also act as an audio sensor to support control of notifications, as will be described below. The system 602 can also include a video interface 676 that enables the on-board camera 630 to perform operations such as recording still images, video streams, etc.

[0082] The mobile computing device 600 implementing the system 602 can have additional features or functionality. For example, the mobile computing device 600 can also include additional data storage devices (removable and / or non-removable), such as magnetic disks, optical disks, or magnetic tapes. Such additional storage devices are illustrated in the non-volatile storage area 668 in Figure 6B .

[0083] Data / information generated or captured by the mobile computing device 600 and stored via the system 602 can be stored locally on the mobile computing device 600 as described above, or the data can be stored on any number of storage media that can be accessed by the device via the radio interface layer 672 or via a wired connection between the mobile computing device 600 and a separate computing device associated with the mobile computing device 600 (e.g., a server computer in a distributed computing network such as the Internet). As should be understood, such data / information can be accessed by the mobile computing device 600 via the radio interface layer 672 or via a distributed computing network. Similarly, such data / information can be easily transmitted between computing devices for storage and use according to well-known data / information transfer and storage components, including email and collaborative data / information sharing systems.

[0084] Figure 7FIG. illustrates one aspect of the architecture of a system for processing data received at a computing system from a remote source such as a personal computer 704, a tablet computing device 706, or a mobile computing device 708 as described above. The content displayed at the server device 702 can be stored in different communication channels or other storage types. For example, various documents can be stored using a directory service 722, a web portal 724, a mailbox service 726, an instant messaging repository 728, or a social networking site 730.

[0085] The susceptibility test engine 720 can be employed by a client communicating with the server device 702, and / or the memory unit evaluation engine 721 can be employed by the server device 702. Thus, it should be understood that the memory unit evaluation need not occur on the computing device executing the susceptibility test sequence. Instead, at least a sub - portion of the memory content associated with the evaluation techniques described herein can be passed to the server 702 for processing by the memory unit evaluation engine 721. The server device 702 can provide data to and receive data from client computing devices such as a personal computer 704, a tablet computing device 706, and / or a mobile computing device 708 (e.g., a smart phone). As an example, the computer system described above can be embodied in a personal computer 704, a tablet computing device 706, and / or a mobile computing device 708 (e.g., a smart phone). In addition to receiving graphical data that can be pre - processed at a graphics initiation system or post - processed at a receiving computing system, any of these embodiments of the computing device can obtain content from the repository 716.

[0086] Figure 8 FIG. illustrates an exemplary tablet computing device 800 that can perform one or more aspects disclosed herein. Additionally, the aspects and functions described herein can operate on a distributed system (e.g., a cloud - based computing system) where application functionality, memory, data storage and retrieval, and various processing functions can operate remotely from each other on a distributed computing network such as the Internet or an intranet. The user interface and various types of information can be displayed via an on - board computing device display or via a remote display unit associated with one or more computing devices. For example, the user interface and various types of information can be displayed on a wall surface onto which the user interface and various types of information are projected and can interact with these user interfaces and various types of information. Interaction with many of the computing devices that can be utilized to practice embodiments of the present invention includes keystroke entry, touch - screen entry, voice or other audio entry, gesture entry, etc., where in gesture entry the associated computing device is equipped with detection (e.g., camera) functionality for capturing and interpreting user gestures for controlling the functionality of the computing device.

[0087] As should be understood from the foregoing disclosure, one aspect of the present technology relates to a system including: at least one processor; and a memory storing instructions that, when executed by the at least one processor, cause the system to perform a set of operations including: accessing a physical adjacency graph for a memory cell; determining, based on the physical adjacency graph, a first set of adjacent memory rows for a first target row of the memory cell; activating each memory row in the first set of adjacent memory rows using a susceptibility test sequence; evaluating the first target row to determine whether one or more bits of the first target row have changed; and generating an indication that the memory cell is not susceptible to inductive charge leakage based on determining that one or more bits of the first target row have not changed. In one example, the susceptibility test sequence includes cache line flush instructions for each memory row in the first set of adjacent memory rows. In another example, the cache line flush instructions for each memory row cause the processor to prefetch data from the memory cell, thereby generating an activation for the memory row. In a further example, the susceptibility test sequence further includes at least one of a load instruction or a store instruction for each memory row in the first set of adjacent memory rows. In yet another example, the set of operations further includes: loading a predetermined bit sequence into the first target row, and evaluating the first target row to determine whether one or more bits of the first target row have changed includes: evaluating the first target row based on the predetermined bit sequence. In yet another example, the set of operations further includes: determining, based on the physical adjacency graph, a second set of adjacent memory rows for a second target row of the memory cell, where the second target row of the memory cell is in a different bank of the memory cell than the first target row; activating each memory row in the second set of adjacent memory rows using the susceptibility test sequence; and evaluating the second target row to determine whether one or more bits of the second target row have changed. In another example, the indication that the memory cell is not susceptible to inductive charge leakage is further generated based on determining that one or more bits of the second target row have not changed.

[0088] In another aspect, the present technology relates to a method for generating a physical adjacency map. The method includes: initializing the content of memory cells; using a susceptibility test sequence to activate a first memory row of the memory cells; evaluating the memory cells based on the content to identify one or more rows in which bits of the memory cells are changed; and generating a physical adjacency map based on the evaluation of the one or more rows and the first memory row, the physical adjacency map indicating that at least one of the one or more rows is adjacent to the first memory row. In one example, the method further includes: based on the physical adjacency map, determining a set of adjacent memory rows for a target row of the memory cells; using the susceptibility test sequence to activate each memory row in the set of adjacent memory rows; evaluating the target row to determine whether one or more bits of the target row are changed; and based on determining that one or more bits of the target row are not changed, generating an indication that the memory cells are not susceptible to inductive charge leakage. In another example, the susceptibility test sequence is a sequence selected from the group consisting of: an optimized cache line flush instruction for the first memory row, the instruction causing the first memory row to be prefetched, thereby generating an activation for the first memory row; a load instruction for the first memory row and a cache line flush instruction for the first memory row; and a store instruction for the first memory row and a cache line flush instruction for the first memory row. In a further example, initializing the content of the memory cells includes one of the following: loading a predetermined bit sequence into at least a portion of the memory cells; or storing at least a portion of the memory cell content. In yet another example, initializing the content of the memory cells includes: generating an indication to an interposer to inhibit a refresh command for the memory cells. In yet another example, the method further includes: after activating the first memory row, generating an indication to the interposer to allow a refresh command for the memory cells.

[0089] In a further aspect, the present technology relates to a method for identifying the susceptibility of a memory cell to inductive charge leakage. The method includes: accessing a physical adjacency graph for a memory cell; determining, based on the physical adjacency graph, a first set of adjacent memory rows of a first target row of the memory cell; activating each memory row in the first set of adjacent memory rows using a susceptibility test sequence; evaluating the first target row to determine whether one or more bits of the first target row have changed; and generating an indication that the memory cell is not susceptible to inductive charge leakage based on determining that one or more bits of the first target row have not changed. In one example, the susceptibility test sequence includes a cache line flush instruction for each memory row in the first set of adjacent memory rows. In another example, the cache line flush instruction is an optimized cache line flush instruction. In a further example, the susceptibility test sequence further includes at least one of a load instruction or a store instruction for each memory row in the first set of adjacent memory rows. In yet another example, the method further includes loading a predetermined bit sequence into the first target row, and evaluating the first target row to determine whether one or more bits of the first target row have changed includes: evaluating the first target row based on the predetermined bit sequence. In yet another example, the method further includes: determining, based on the physical adjacency graph, a second set of adjacent memory rows of a second target row of the memory cell, wherein the second target row of the memory cell is in a different bank of the memory cell than the first target row; activating each memory row in the second set of adjacent memory rows using the susceptibility test sequence; and evaluating the second target row to determine whether one or more bits of the second target row have changed. In another example, the indication that the memory cell is not susceptible to charge leakage is further generated based on determining that one or more bits of the second target row have not changed.

[0090] For example, aspects of the present disclosure have been described above with reference to block diagrams and / or operational illustrations of methods, systems, and computer program products according to aspects of the present disclosure. The functions / actions noted in the blocks may be performed in a different order than shown in any flowchart. For example, two blocks shown in succession may in fact be executed substantially simultaneously depending on the functionality / action involved, or the blocks may sometimes be executed in the reverse order.

[0091] The description and illustration of one or more aspects provided in this application are not intended to limit or restrict the scope of the claimed disclosure in any way. The aspects, examples, or details provided in this application are considered sufficient to convey ownership and enable others to make and use the best mode of the claimed disclosure. The claimed disclosure should not be construed as limited to any aspect, example, or detail provided in this application. Various features (both structures and methods), whether shown and described in combination or separately, are intended to be selectively included or omitted to produce embodiments having a particular set of features. Having provided the description and illustration of this application, those skilled in the art can envision variations, modifications, and alternative aspects that fall within the spirit of the broader aspects of the general inventive concept implemented in this application and do not depart from the broader scope of the claimed disclosure.

Claims

1. A system, comprising: at least one processor; and a memory storing instructions that, when executed by the at least one processor, cause the system to perform a set of operations, the set of operations including: accessing a physical adjacency graph for a memory cell; determining, based on the physical adjacency graph, a first set of adjacent memory rows for a first target row of the memory cell; activating each memory row in the first set of adjacent memory rows using a susceptibility test sequence that does not include at least one of a load instruction or a store instruction; evaluating the first target row to determine whether one or more bits of the first target row change; and generating an indication that the memory cell is not susceptible to inductive charge leakage based on determining that one or more bits of the first target row do not change.

2. The system of claim 1, wherein the susceptibility test sequence includes a cache line flush instruction for each memory row in the first set of adjacent memory rows.

3. The system of claim 2, wherein the cache line flush instruction for each memory row causes the processor to prefetch data from the memory cell, thereby generating an activation for the memory row.

4. The system according to claim 1, wherein the set of operations further comprises loading a predetermined bit sequence into the first target row, and wherein evaluating the first target row to determine whether one or more bits of the first target row have changed comprises: Evaluating the first target row based on the predetermined bit sequence.

5. The system of claim 1, wherein the set of operations further includes: determining, based on the physical adjacency graph, a second set of adjacent memory rows for a second target row of the memory cell, wherein the second target row of the memory cell is in a different bank of the memory cell than the first target row; activating each memory row in the second set of adjacent memory rows using the susceptibility test sequence; and evaluating the second target row to determine whether one or more bits of the second target row change.

6. The system of claim 5, wherein the indication that the memory cell is not susceptible to inductive charge leakage is further generated based on determining that the one or more bits of the second target row do not change.

7. The system of claim 1, wherein the accessed physical adjacency graph is identified based on characteristics of the memory cell.

8. A method for generating a physical adjacency graph, comprising: initializing the content of a memory cell; activating a first memory row of the memory cell using a susceptibility test sequence; evaluating the memory cell based on the content to identify one or more rows in which bits of the memory cell change; and generating a physical adjacency graph based on an evaluation of the one or more rows and the first memory row, the physical adjacency graph indicating that at least one of the one or more rows is adjacent to the first memory row.

9. The method of claim 8, further comprising: determining, based on the physical adjacency graph, a set of adjacent memory rows for a target row of the memory cell; activating each memory row in the set of adjacent memory rows using the susceptibility test sequence; evaluating the target row to determine whether one or more bits of the target row change; and Generating an indication that the memory cell is insensitive to inductive charge leakage based on determining that one or more bits of the target row have not changed.

10. The method of claim 8, wherein the susceptibility test sequence is a sequence selected from the group consisting of: An optimized cache line flush instruction for the first memory row, the cache line flush instruction causing the first memory row to be prefetched, thereby generating an activation for the first memory row; A load instruction for the first memory row and a cache line flush instruction for the first memory row; And A store instruction for the first memory row and a cache line flush instruction for the first memory row.

11. The method of claim 8, wherein initializing the content of the memory cell includes one of the following: Loading a predetermined bit sequence into at least a portion of the memory cell; or Storing at least a portion of the content of the memory cell.

12. The method of claim 8, wherein initializing the content of the memory cell includes: Generating an indication to the interposer layer that inhibits a flush command for the memory cell.

13. The method of claim 12, further comprising After activating the first memory row, generating an indication to the interposer layer that permits a flush command for the memory cell.

14. A method for identifying the susceptibility of a memory cell to inductive charge leakage, comprising: Accessing a physical adjacency graph for a memory cell; Based on the physical adjacency graph, determining a first set of adjacent memory rows for a first target row of the memory cell; Using a susceptibility test sequence to activate each memory row in the first set of adjacent memory rows, wherein the susceptibility test sequence does not include a load instruction or a store instruction; Evaluating the first target row to determine whether one or more bits of the first target row have changed; And Generating an indication that the memory cell is insensitive to inductive charge leakage based on determining that one or more bits of the first target row have not changed.

15. The method of claim 14, wherein the susceptibility test sequence includes a cache line flush instruction for each memory row in the first set of adjacent memory rows.

16. The method of claim 15, wherein the cache line flush instruction is an optimized cache line flush instruction.

17. The method according to claim 14, wherein the method further comprises loading a predetermined bit sequence into the first target row, and wherein evaluating the first target row to determine whether one or more bits of the first target row have changed comprises: Evaluating the first target row based on the predetermined bit sequence.

18. The method of claim 14, further comprising: Based on the physical adjacency graph, determining a second set of adjacent memory rows for a second target row of the memory cell, wherein the second target row of the memory cell is in a different bank of the memory cell than the first target row; Using the susceptibility test sequence to activate each memory row in the second set of adjacent memory rows; And Evaluating the second target row to determine whether one or more bits of the second target row have changed.

19. The method according to claim 18, wherein the indication that the memory cell is insensitive to inductive charge leakage is further generated based on determining that one or more bits of the second target row have not changed.

20. The method according to claim 14, wherein the accessed physical adjacency graph is identified based on characteristics of the memory cell.

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