Semiconductor module manufacturing method, electronic device manufacturing method, semiconductor module, and electronic device

Abstract

A chip component (400) including a first electrode (410) and a second electrode (420), a semiconductor device (100) including a first land (130E) and a second land (130G), and a printed wiring board (200) are prepared. First and second solder pastes (P1, P2) are supplied to the printed wiring board (200). The chip component (400) is placed on the printed wiring board such that the first electrode (410) is in contact with the first solder paste (P1) and the second electrode (420) is in contact with the second solder paste (P2). The semiconductor device (100) is placed on the printed wiring board such that the first land (130E) faces the first electrode (410) and the second land (130G) faces the second electrode (420). The solder pastes are melted by heating to bond the first land (130E) and the first electrode (410) and to bond the second land (130G) and the second electrode (420).

Description

TECHNICAL FIELD

[0001] The present application relates to a technology of a semiconductor module having a semiconductor device. BACKGROUND

[0002] An electronic device such as a mobile device includes a semiconductor module including a semiconductor device that communicates with other semiconductor devices such as a memory and a printed wiring board on which the semiconductor device is mounted. The semiconductor device is a semiconductor package including a semiconductor element and a package substrate. The arrangement structure of terminals included in the semiconductor device is, for example, a ball grid array (BGA). In the electronic device, high-speed communication and low-voltage communication of the semiconductor device have been developed, and it is required to reduce noise generated in the semiconductor device. Further, with miniaturization and thinning of the electronic device, it is desired to reduce the pitch between adjacent terminals in the semiconductor device.

[0003] As one of means to reduce noise, it is considered to connect a bypass capacitor between a power terminal and a ground terminal of the semiconductor device. The bypass capacitor is usually mounted on a surface of the printed wiring board adjacent to the semiconductor device by surface mount technology (SMT), or mounted on a surface of the printed wiring board opposite to the surface on which the semiconductor device is mounted. However, in this method, it is required to form a wiring on the printed wiring board that electrically connects the semiconductor device and the capacitor, and the inductance of the wiring contributes to generation of noise that hinders improvement of the communication speed in the semiconductor device. Meanwhile, Patent Literature 1 discloses a technology of directly attaching a bypass capacitor to a power pad and a ground pad of a BGA package by solder.

[0004] LIST OF CITATIONS

[0005] PATENT LITERATURE

[0006] Patent Literature 1: JP 2006-173407 A SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] However, in the technology of Patent Literature 1, it is required to form solder balls on each of a pair of electrodes of the capacitor in advance before the semiconductor device is mounted on the printed wiring board. The capacitor is a compact electronic component. For this reason, it is difficult to form the solder balls on the electrodes of the capacitor in terms of manufacturing. Further, the manufacturing process is increased due to the process of forming the solder balls on the electrodes of the capacitor. Therefore, compared with the prior art, it is required to improve the productivity of the semiconductor module. Such a problem also occurs when a small electronic component (for example, an inductor or a resistor) other than the capacitor is connected to the semiconductor device. Further, when these electronic components are connected to the semiconductor device, joint strength is required.

[0009] Therefore, a technique for improving the productivity of a semiconductor module is desired. Furthermore, a technique for improving the joining strength of an electronic component connected to a semiconductor module is also desired.

[0010] Technical Solution to Problem

[0011] According to a first aspect of the present application, there is provided a semiconductor module manufacturing method including the steps of: preparing a chip component including first and second electrodes arranged at intervals in a predetermined direction, a semiconductor device including first and second lands, and a printed wiring board; supplying first and second solder pastes to the printed wiring board at intervals; placing the chip component on the printed wiring board so that the first electrode is in contact with the first solder paste and the second electrode is in contact with the second solder paste; placing the semiconductor device on the printed wiring board so that the first land faces the first electrode and the second land faces the second electrode; heating and melting the first and second solder pastes; and joining the first land and the first electrode to each other with solder and joining the second land and the second electrode to each other with solder by cooling and solidifying the molten solder that has wet-spreading into each of the first and second lands.

[0012] According to a second aspect of the present application, there is provided a semiconductor module including: a printed wiring board; a semiconductor device including first and second lands, the semiconductor device being mounted on the printed wiring board; a chip component including first and second electrodes spaced from each other in a predetermined direction, the chip component being arranged between the printed wiring board and the semiconductor device; a first solder joint joining the first electrode and the first land to each other; and a second solder joint joining the second electrode and the second land to each other, wherein the printed wiring board includes an insulating substrate and a solder resist arranged on a main surface of the insulating substrate, the chip component faces the solder resist, in a plan view, each of the first and second lands overlaps at least a portion of each of the first and second electrodes, and extends outward in the predetermined direction from the chip component, the first solder joint has a rounded shape, wherein when the first solder joint extends from the solder resist toward the first land, the first solder joint spreads outward in the predetermined direction from the first electrode, and the second solder joint has a rounded shape, wherein when the second solder joint extends from the solder resist toward the second land, the second solder joint spreads outward in the predetermined direction from the second electrode.

[0013] According to a third aspect of the present application, there is provided a semiconductor module including: a printed wiring board; a semiconductor device including a first land and a second land, the semiconductor device being mounted on the printed wiring board; a chip component including a first electrode and a second electrode spaced apart from each other in a predetermined direction, the chip component being disposed between the printed wiring board and the semiconductor device; a first solder joint joining the first electrode and the first land to each other; and a second solder joint joining the second electrode and the second land to each other, wherein the printed wiring board includes an insulating substrate, a third land disposed on a main surface of the insulating substrate and electrically connected to the first land by the first solder joint, and a fourth land disposed on the main surface of the insulating substrate and electrically connected to the second land by the second solder joint, in a plan view, each of the first land and the second land overlaps at least a portion of each of the first electrode and the second electrode, overlaps at least a portion of each of the third land and the fourth land, and extends outward from the chip component in the predetermined direction, the first solder joint has a rounded shape, wherein the first solder joint spreads outward from the first electrode in the predetermined direction as the first solder joint extends from the third land toward the first land, and the second solder joint has a rounded shape, wherein the second solder joint spreads outward from the second electrode in the predetermined direction as the second solder joint extends from the fourth land toward the second land.

[0014] According to a fourth aspect of the present application, there is provided a semiconductor module including: a printed wiring board; a semiconductor device including a first land and a second land, the semiconductor device being mounted on the printed wiring board; a chip component including a first electrode and a second electrode spaced apart from each other in a predetermined direction, the chip component being disposed between the printed wiring board and the semiconductor device; a first solder joint joining the first electrode and the first land to each other; and a second solder joint joining the second electrode and the second land to each other, wherein the printed wiring board includes an insulating substrate and a solder resist disposed on a main surface of the insulating substrate, the solder resist having an opening portion into which a portion of the chip component is inserted, in a plan view, each of the first land and the second land overlaps at least a portion of each of the first electrode and the second electrode, and extends outward from the chip component in the predetermined direction, the first solder joint has a rounded shape, wherein when the first solder joint extends from a portion of the main surface of the insulating substrate exposed by the opening portion of the solder resist toward the first land, the first solder joint diffuses outward from the first electrode in the predetermined direction, and the second solder joint has a rounded shape, wherein when the second solder joint extends from a portion of the main surface of the insulating substrate exposed by the opening portion of the solder resist toward the second land, the second solder joint diffuses outward from the second electrode in the predetermined direction.

[0015] Advantages of the Invention

[0016] According to the present application, the productivity of a semiconductor module is improved.

[0017] Other features and advantages of the present application will become more apparent from the following description of the application taken in conjunction with the accompanying drawings. In the drawings, like or similar components are designated with the same reference numerals. BRIEF DESCRIPTION OF DRAWINGS

[0018] [ Figure 1 ] Figure 1 is a diagrammatic view of an electronic device according to the first embodiment.

[0019] [ Figure 2A ] Figure 2A is a perspective view of a processing module according to the first embodiment.

[0020] [ Figure 2B ] Figure 2B is a schematic cross-sectional view of a processing module according to the first embodiment.

[0021] [ Figure 3 ] Figure 3is an enlarged schematic cross-sectional view of a portion of the processing module according to the first embodiment.

[0022] [ Figure 4A ] Figure 4A is an exploded partial perspective view of the processing module according to the first embodiment.

[0023] [ Figure 4B ] Figure 4B is a schematic view for explaining an arrangement relationship between a semiconductor device, a capacitor, and a printed wiring board according to the first embodiment.

[0024] [ Figure 5A ] Figure 5A is a view for explaining one stage of a processing module manufacturing method according to the first embodiment.

[0025] [ Figure 5B ] Figure 5B is a view for explaining one stage of a processing module manufacturing method according to the first embodiment.

[0026] [ Figure 5C ] Figure 5C is a view for explaining one stage of a processing module manufacturing method according to the first embodiment.

[0027] [ Figure 5D ] Figure 5D is a view for explaining one stage of a processing module manufacturing method according to the first embodiment.

[0028] [ Figure 5E ] Figure 5E is a view for explaining one stage of a processing module manufacturing method according to the first embodiment.

[0029] [ Figure 5F ] Figure 5F is a view for explaining one stage of a processing module manufacturing method according to the first embodiment.

[0030] [ Figure 6 ] Figure 6 is an enlarged schematic cross-sectional view of a portion of the processing module according to the second embodiment.

[0031] [ Figure 7A ] Figure 7A is an exploded partial perspective view of the processing module according to the second embodiment.

[0032] [ Figure 7B ] Figure 7B is a schematic view for explaining an arrangement relationship between a semiconductor device, a capacitor, and a printed wiring board according to the second embodiment.

[0033] [ Figure 8A ] Figure 8AFig. 6 is a diagram for explaining one stage of the process module manufacturing method according to the second embodiment.

[0034] [ Figure 8B ] Figure 8B Fig. 7 is a diagram for explaining one stage of the process module manufacturing method according to the second embodiment.

[0035] [ Figure 8C ] Figure 8C Fig. 8 is a diagram for explaining one stage of the process module manufacturing method according to the second embodiment.

[0036] [ Figure 8D ] Figure 8D Fig. 9 is a diagram for explaining one stage of the process module manufacturing method according to the second embodiment.

[0037] [ Figure 8E ] Figure 8E Fig. 10 is a diagram for explaining one stage of the process module manufacturing method according to the second embodiment.

[0038] [ Figure 8F ] Figure 8F Fig. 11 is a diagram for explaining one stage of the process module manufacturing method according to the second embodiment.

[0039] [ Figure 9 ] Figure 9 Fig. 12 is a diagram for explaining one stage of the process module manufacturing method according to the third embodiment.

[0040] [ Figure 10A ] Figure 10A Fig. 13 is an exploded partial perspective view of the process module according to the third embodiment.

[0041] [ Figure 10B ] Figure 10B Fig. 14 is a diagram for explaining the arrangement relationship between the semiconductor device, the capacitor, and the printed wiring board according to the third embodiment.

[0042] [ Figure 11A ] Figure 11A Fig. 15 is a diagram for explaining one stage of the process module manufacturing method according to the third embodiment.

[0043] [ Figure 11B ] Figure 11B Fig. 16 is a diagram for explaining one stage of the process module manufacturing method according to the third embodiment.

[0044] [ Figure 11C ] Figure 11C Fig. 17 is a diagram for explaining one stage of the process module manufacturing method according to the third embodiment.

[0045] [ Figure 11D ] Figure 11Dis a view for explaining one stage of a processing module manufacturing method according to the third embodiment.

[0046] [ Figure 11E ] Figure 11E is a view for explaining one stage of a processing module manufacturing method according to the third embodiment.

[0047] [ Figure 11F ] Figure 11F is a view for explaining one stage of a processing module manufacturing method according to the third embodiment.

[0048] [ Figure 12A ] Figure 12A is a schematic cross-sectional view of the processing module of Example 1.

[0049] [ Figure 12B ] Figure 12B is a schematic cross-sectional view of the processing module of Example 2.

[0050] [ Figure 12C ] Figure 12C is a schematic cross-sectional view of the processing module of Comparative Example 1.

[0051] [ Figure 13 ] Figure 13 is a graph showing the calculation results of inductance in Example 1, Example 2, and Comparative Example 1. DETAILED DESCRIPTION

[0052] Hereinafter, modes for carrying out the present application will be described in detail with reference to the drawings.

[0053] [First Embodiment]

[0054] Figure 1 is an explanatory view of a digital camera 600 that is an example of an imaging apparatus according to the first embodiment. The digital camera 600 that is an imaging apparatus is an interchangeable lens digital camera, and includes a camera body 601. A lens unit (lens barrel) 602 including a lens is detachable from the camera body 601. The camera body 601 includes a housing 611, and a processing module 300 and a sensor module 900 that are printed circuit boards and are disposed inside the housing 611. The processing module 300 is an example of a semiconductor module. The processing module 300 and the sensor module 900 are electrically connected to each other by a cable 950.

[0055] The sensor module 900 includes a printed wiring board 800 and an image sensor 700 that is an imaging element. The image sensor 700 is mounted on the printed wiring board 800. The image sensor 700 is, for example, a complementary metal-oxide semiconductor (CMOS) image sensor or a charge-coupled device (CCD) image sensor. The image sensor 700 has a function of converting light incident via the lens unit 602 into an electric signal.

[0056] The processing module 300 includes the semiconductor device 100 and the printed wiring board 200 as a first wiring board. The semiconductor device 100 is mounted on the printed wiring board 200. The printed wiring board 200 is a rigid substrate. The semiconductor device 100 is, for example, a digital signal processor, and has a function of acquiring an electric signal from the image sensor 700, performing a correction process on the acquired electric signal, and generating image data.

[0057] Figure 2A is a perspective view of the processing module 300 according to the first embodiment. Figure 2B is a schematic cross-sectional view of the processing module 300 taken along a line IIB-IIB in Figure 2A Figure 3 is a schematic cross-sectional view of the processing module 300 taken along a line IIB-IIB in Figure 2B is an enlarged schematic cross-sectional view of a portion of the processing module 300 shown in Figure 2A Figure 2B and Figure 3 will be given below.

[0058] The semiconductor device 100 is an area array semiconductor package, and is a BGA semiconductor package in the first embodiment. The semiconductor device 100 includes a semiconductor element 101 and a package substrate 102 as a second wiring board. The package substrate 102 is a rigid substrate.

[0059] ​​A semiconductor element 101 is mounted on a package substrate 102. The package substrate 102 includes an insulating substrate 120. The insulating substrate 120 has a main surface 121 and a main surface 122 opposite to the main surface 121. The material of the insulating substrate 120 is, for example, a ceramic such as alumina or an epoxy resin containing glass. The semiconductor element 101 is, for example, a semiconductor chip, and is mounted on the main surface 121 of the insulating substrate 120 in a face-up or face-down manner, in the first embodiment, in a face-down manner. A sealing resin 106 for sealing the semiconductor element 101 is provided on the main surface 121 of the insulating substrate 120. The package substrate 102 has a plurality of lands 130 disposed on the main surface 122 of the insulating substrate 120. The arrangement pattern of the plurality of lands 130 can have a lattice shape, i.e., a matrix shape or a staggered shape. The lands 130 are terminals made of a conductive metal material such as copper or gold, and are, for example, signal terminals, power supply terminals, ground terminals, or dummy terminals. A solder resist 108 is provided on the main surface 122. The solder resist 108 is a film made of a solder resist material. Each of the plurality of lands 130 is exposed through an opening portion formed in the solder resist 108. The lands 130 can be solder mask defined (SMD) or non-solder mask defined (NSMD) lands, but are SMD lands in the first embodiment. Although not shown, a heat sink can be disposed on the upper surface of the semiconductor element 101.

[0060] The semiconductor element 101 includes a plurality of power supply terminals, a plurality of ground terminals, and a plurality of signal terminals, each of which is joined to the package substrate 102 by wire bonding or flip-chip bonding (not shown). Figure 2B and Figure 3 A power supply terminal 111E that is one of the plurality of power supply terminals is shown, and a ground terminal 111G that is one of the plurality of ground terminals is shown. That is, the semiconductor element 101 includes the power supply terminal 111E and the ground terminal 111G.

[0061] The printed wiring board 200 includes an insulating substrate 220. The insulating substrate 220 has a main surface 221 and a main surface 222 opposite to the main surface 221. The printed wiring board 200 has a plurality of lands 230 disposed on the main surface 221 of the insulating substrate 220. The lands 230 are terminals made of a conductive metal material such as copper or gold, and are, for example, signal terminals, power supply terminals, ground terminals, or dummy terminals. The material of the insulating substrate 220 is an insulating material such as an epoxy resin.

[0062] The printed wiring board 200 includes a solder resist 208. The solder resist 208 is a film made of a solder resist material. The solder resist 208 is disposed on the main surface 221. Each of the plurality of lands 230 is exposed through an opening portion formed in the solder resist 208. The lands 230 can be SMD or NSMD lands, but are SMD lands in the first embodiment.

[0063] The plurality of lands 130 includes a land 130E serving as a power terminal and a land 130G serving as a ground terminal. The plurality of lands 130 is arranged at an interval of less than or equal to 0.4 mm. The land 130E is a first land, and the land 130G is a second land. The land 130E is electrically connected to the power terminal 111E of the semiconductor element 101 via a via conductor 112E formed on the insulating substrate 120. The land 130G is electrically connected to the ground terminal 111G of the semiconductor element 101 via a via conductor 112G formed on the insulating substrate 120.

[0064] The plurality of lands 130 includes a land 130S in addition to the lands 130E and 130G. The land 130S is a land serving as a signal terminal, a power terminal, a ground terminal, or a dummy terminal. In the first embodiment, each of the plurality of lands 130S is a fifth land, and each of the plurality of lands 230 is a sixth land. The land 130S and the land 230 are joined to each other by a solder joint 193 that is a third solder joint made of solder. The height of the solder joint 193 is higher than the height of the capacitor 400 described later. Specifically, the height is less than or equal to 1.3 times the height of the capacitor. This is because warping occurs from the center to the outer peripheral edge of the semiconductor element 101 during a thermal joining process.

[0065] The processing module 300 includes a capacitor 400 as an example of a chip component. The capacitor 400 is a passive component and is a chip component. The chip component preferably has a size in a plan view of less than or equal to a 0402 size, such as a 0402 size of 0.4 mm x 0.2 mm or a 0201 size of 0.25 mm x 0.125 mm. The notation such as the 0402 size and the 0201 size conforms to a size notation method (mm notation) for electronic components in Japanese Industrial Standards.

[0066] The capacitor 400 includes an element main body 401 having a substantially rectangular parallelepiped shape extending in a long-side direction (as an example of a predetermined direction), and a pair of electrodes 410 and 420 disposed on both sides of the element main body 401 in the long-side direction. The pair of electrodes 410 and 420 are fixed to the element main body 401 at a certain interval in the long-side direction. The element main body 401 and the pair of electrodes 410 and 420 are made of a ceramic material. Figure 2B and Figure 3In the present embodiment, the long side direction of the capacitor 400 (i.e., the element body 401) is the X direction. The short side direction of the capacitor 400 (i.e., the element body 401) is the Y direction. The Y direction is a width direction orthogonal to the X direction. The vertical direction of the capacitor 400 (i.e., the element body 401) is the Z direction. The Z direction is a direction orthogonal to the X direction and the Y direction. The Z direction is also a direction perpendicular to the main surfaces 121, 122, 221, and 222.

[0067] One of the pair of electrodes 410 and 420 is the first electrode 410, and the other is the second electrode 420. Each of the electrodes 410 and 420 includes a base and an outer film covering the base. The outer film material of the electrodes 410 and 420 is a conductive metal material such as tin.

[0068] The capacitor 400 is a bypass capacitor. The electrode 410 of the capacitor 400 is electrically connected to the land 130E, and the electrode 420 of the capacitor 400 is electrically connected to the land 130G.

[0069] The power supply noise is generated by the inductance of the wiring between the electrode 410 of the capacitor 400 and the power supply terminal 111E and the inductance of the wiring between the electrode 420 of the capacitor 400 and the ground terminal 111G. The power supply noise refers to a voltage fluctuation of the power supply line caused by the operation of the semiconductor device 100. This voltage fluctuation occurs when the power supply current changes due to the parasitic inductance or resistance in the power supply line. In order to reduce the power supply noise by reducing the inductance of the wiring, the capacitor 400 is preferably disposed directly below the semiconductor element 101 so that the wiring between the capacitor 400 and the power supply terminal 111E and the wiring between the capacitor 400 and the ground terminal 111G of the semiconductor device 100 are minimized. That is, it is preferable that the semiconductor element 101 and the capacitor 400 overlap in the plan view of the processing module 300 from the semiconductor device 100 side.

[0070] Therefore, in the first embodiment, the capacitor 400 is disposed on the main surface 221 side of the insulating substrate 220 of the printed wiring board 200, that is, between the semiconductor device 100 and the printed wiring board 200. The electrode 410 of the capacitor 400 is joined to the land 130E through the solder joint 191, which is a first solder joint made of solder. The electrode 420 of the capacitor 400 is joined to the land 130G through the solder joint 192, which is a second solder joint made of solder. Therefore, the electrode 410 of the capacitor 400 is directly electrically connected to the land 130E of the semiconductor device 100 through the solder joint 191 without the printed wiring board 200 interposed therebetween. Therefore, the inductance of the wiring between the electrode 410 of the capacitor 400 and the land 130E can be reduced. Further, the electrode 420 of the capacitor 400 is directly electrically connected to the land 130G of the semiconductor device 100 through the solder joint 192 without the printed wiring board 200 interposed therebetween. Therefore, the inductance of the wiring between the electrode 420 of the capacitor 400 and the land 130G can be reduced. Since the inductance of the wiring is reduced, the generated power noise is reduced, and the communication speed in the semiconductor device 100 can be improved.

[0071] In the first embodiment, the solder joints 191 and 192 are in contact with the solder resist 208 but not in contact with the lands 230 of the printed wiring board 200.

[0072] Figure 4A is an exploded partial perspective view of the processing module 300 according to the first embodiment. Figure 4B is a schematic view for explaining the arrangement relationship of the semiconductor device 100, the capacitor 400, and the printed wiring board 200 when viewed in the Z direction. In Figure 4A and Figure 4B In Figure 4B , the lands 130E and 130G of the semiconductor device are indicated by dotted lines.

[0073] As Figure 4AAs shown, electrode 410 has three side surfaces 411, 412, and 413, an upper surface 414, and a lower surface 415 as electrode surfaces. When viewed from a direction perpendicular to each surface, side surfaces 411, 412, and 413, upper surface 414, and lower surface 415 have a rectangular shape. Among the three side surfaces 411, 412, and 413, two side surfaces 412 and 413 face each other at a certain interval in the Y direction. Upper surface 414 and lower surface 415 face each other at a certain interval in the Z direction. Side surface 411 is orthogonal to and adjacent to side surfaces 412 and 413, upper surface 414, and lower surface 415. Electrode 420 has three side surfaces 421, 422, and 423, an upper surface 424, and a lower surface 425 as electrode surfaces. When viewed from a direction perpendicular to each surface, side surfaces 421, 422, and 423, upper surface 424, and lower surface 425 have a rectangular shape. Of the three side surfaces 421, 422, and 423, two side surfaces 422 and 423 face each other at a certain interval in the Y direction. The upper surface 424 and the lower surface 425 face each other at a certain interval in the Z direction. Side surface 421 is orthogonal to and adjacent to side surfaces 422 and 423, and to the upper surface 424 and the lower surface 425. The side surfaces 411 of electrode 410 and 421 of electrode 420 are arranged to face each other at a certain interval in the X direction. The upper surface 414 of electrode 410 faces the connection pad 130E of semiconductor device 100, and the lower surface 415 of electrode 410 faces the solder resist 208 of printed circuit board 200. The upper surface 424 of electrode 420 faces the connection pad 130G of semiconductor device 100, and the lower surface 425 of electrode 420 faces the solder resist 208 of printed circuit board 200.

[0074] like Figure 4B As shown, connecting disks 130E and 130G are arranged at a certain interval in the X direction. In the plan view (i.e., when viewed in the Z direction), connecting disk 130E overlaps with at least a portion (the entire electrode 410 in the first embodiment) of the electrode 410 of the capacitor 400. When viewed in the Z direction, connecting disk 130G overlaps with at least a portion (the entire electrode 420 in the first embodiment) of the electrode 420 of the capacitor 400. In the first embodiment, when viewed in the Z direction, the area S of connecting disk 130E is... 130E The area S is greater than that of electrode 410 410 When viewed in the Z direction, the area S of the connecting disk 130G is... 130G The area S is greater than that of electrode 420 420 When viewed in the Z direction, connecting disks 130E and 130G extend outward from capacitor 400 along the X direction.

[0075] like Figure 3As shown, each of the solder joints 191 and 192 has a rounded shape in which the outer surface diverges away from the capacitor 400 from the solder resist 208 toward each of the lands 130E and 130G. More specifically, the solder joint 191 has a rounded shape in which, as the solder joint 191 extends from the solder resist 208 toward the land 130E, the solder joint 191 expands outward in the X direction (i.e., in the XI direction) from the electrode 410. The solder joint 192 has a rounded shape in which, as the solder joint 192 extends from the solder resist 208 toward the land 130G, the solder joint 192 expands outward in the X direction (i.e., in the X2 direction) from the electrode 420. The XI direction is a direction in the X direction away from the electrode 410. The X2 direction is a direction in the X direction opposite the XI direction and is a direction away from the electrode 420. As a result, the joint strength between each of the lands 130E and 130G and each of the electrodes 410 and 420 is increased. In addition, as shown, each of the solder joints 191 and 192 is prevented from having a convex shape in the X direction, and each of the solder joints 191 and 192 is prevented from shorting with the adjacent solder joint 193. Figure 2B

[0076] As shown, each of the lands 130E and 130G has a rectangular shape when viewed in the Z direction, but is not limited thereto. For example, the lands 130E and 130G can have any shape, such as a polygonal shape, a circular shape, or an elliptical shape, when viewed in the Z direction. Figure 4B

[0077] Next, a method of manufacturing the processing module 300 will be described. Figures 5A to 5F is a schematic view of a method of manufacturing the processing module 300 according to the first embodiment. As shown, Figure 5A the printed wiring board 200 is prepared (step S1). In step S1, the semiconductor device 100 and the capacitor 400 are also prepared. Next, as shown, Figure 5B the solder paste P1 as the first solder paste, the solder paste P2 as the second solder paste, and the solder paste P3 as the third solder paste are supplied to the printed wiring board 200 at intervals (step S2). In the first embodiment, in step S2, the solder paste P1 and the solder paste P2 are supplied to the solder resist 208. In step S2, the solder paste P3 is supplied to the land 230 of the printed wiring board 200.

[0078] ​​The solder pastes P1, P2, and P3 contain solder powder. The solder pastes P1, P2, and P3 can also contain flux components necessary for soldering. In the present embodiment, the solder pastes P1, P2, and P3 are all the same material, but are not limited to the same material, as long as the melting points of the solder pastes P1, P2, and P3 are close. In step S2, the solder pastes P1, P2, and P3 are supplied to the printed wiring board 200 by screen printing using the metal mask 23. The method of supplying the solder pastes P1, P2, and P3 is not limited thereto. For example, the solder pastes P1, P2, and P3 can be supplied to the printed wiring board 200 by a dispenser.

[0079] Next, as shown in FIG. 4, the capacitor 400 prepared in step S1 is placed on the printed wiring board 200 so that the electrode 410 is in contact with the solder paste P1 and the electrode 420 is in contact with the solder paste P2 (step S3). As a result, the lower surface 415 of the electrode 410 is in contact with the solder paste P1, and the lower surface 425 of the electrode 420 is in contact with the solder paste P2. It is not necessary to attach solder balls to the electrodes 410 and 420 of the capacitor 400 in advance. In step S3, the capacitor 400 is mounted on the printed wiring board 200 using a mounter (not shown). At this time, the capacitor 400 is aligned and placed on the printed wiring board so that the electrode 410 and the solder paste P1 face each other and the electrode 420 and the solder paste P2 face each other. Figure 5C Next, as shown in FIG. 4, the capacitor 400 prepared in step S1 is placed on the printed wiring board 200 so that the electrode 410 is in contact with the solder paste P1 and the electrode 420 is in contact with the solder paste P2 (step S3). As a result, the lower surface 415 of the electrode 410 is in contact with the solder paste P1, and the lower surface 425 of the electrode 420 is in contact with the solder paste P2. It is not necessary to attach solder balls to the electrodes 410 and 420 of the capacitor 400 in advance. In step S3, the capacitor 400 is mounted on the printed wiring board 200 using a mounter (not shown). At this time, the capacitor 400 is aligned and placed on the printed wiring board so that the electrode 410 and the solder paste P1 face each other and the electrode 420 and the solder paste P2 face each other.

[0080] Figure 5D Next, as shown in FIG. 4, the capacitor 400 prepared in step S1 is placed on the printed wiring board 200 so that the electrode 410 is in contact with the solder paste P1 and the electrode 420 is in contact with the solder paste P2 (step S3). As a result, the lower surface 415 of the electrode 410 is in contact with the solder paste P1, and the lower surface 425 of the electrode 420 is in contact with the solder paste P2. It is not necessary to attach solder balls to the electrodes 410 and 420 of the capacitor 400 in advance. In step S3, the capacitor 400 is mounted on the printed wiring board 200 using a mounter (not shown). At this time, the capacitor 400 is aligned and placed on the printed wiring board so that the electrode 410 and the solder paste P1 face each other and the electrode 420 and the solder paste P2 face each other. Figure 5D In step S4, the semiconductor device 100 is placed on the printed wiring board 200 so that the solder ball B formed on the connecting pad 130S is in contact with the solder paste P3. In this case, the upper surface 414 of the electrode 410 and the connecting pad 130E do not contact each other, and the upper surface 424 of the electrode 420 and the connecting pad 130G do not contact each other, but they can contact each other.

[0081] ​In step S4, the positional relationship between the printed wiring board 200, the capacitor 400, and the semiconductor device 100 when viewed from the Z direction is as shown in FIG. 4. When the capacitor 400 is placed on the printed wiring board 200, each of the lands 130E and 130G of the semiconductor device 100 overlaps at least a portion of each of the electrodes 410 and 420 when viewed in the Z direction, and extends outward in the X direction from the capacitor 400. Figure 4B

[0082] Next, in a state in which the semiconductor device 100 and the capacitor 400 are placed on the printed wiring board 200, the printed wiring board 200 is transported to a reflow furnace (not shown). Then, in step S5-1 shown in FIG. 5, the temperature of the atmosphere in the reflow furnace is adjusted to a temperature equal to or higher than the melting point of the solder, and the solder paste P1, P2, P3, and the solder balls B are melted as shown in FIG. 6. Figure 5E Figure 5D Figure 5E

[0083] After step S5-1, in step S5-2 shown in FIG. 5, heating is continued to cause the molten solders M1 and M2 to flow. Since the electrodes 410 and 420 have better wettability of the molten solder than the solder resist 208, the molten solders M1 and M2 climb up the side surfaces 411 and 421 in the upward direction indicated by the arrow Z1 as shown in FIG. 7. Thereafter, the molten solders M1 and M2 move to the upper surfaces 414 and 424 due to the wet-spreading property as shown in FIG. 8. Although not shown in FIG. 6, the molten solders M1 and M2 also climb up the side surfaces 412 and 413 of the electrode 410 and the side surfaces 422 and 423 of the electrode 420 in the upward direction indicated by the arrow Z1. Figure 5F Figure 5E Figure 5F Figure 5E

[0084] Furthermore, the capacitor 400 is pushed upward by the molten solders M1 and M2 toward the semiconductor device 100, the distance between the upper surface 414 of the electrode 410 and the land 130E narrows, and the distance between the upper surface 424 of the electrode 420 and the land 130G narrows. The molten solders M1 and M2 that reach the upper surfaces 414 and 424 come into contact with the lands 130E and 130G, wet-spreading occurs on the lands 130E and 130G, and have a rounded shape in which the skirt portion widens as it moves from the solder resist 208 toward the lands 130E and 130G.

[0085] ​​​​​​​​Thereafter, the molten solders Ml and M2 wetting-diffused to each corner of the lands 130E and 130G are cooled and solidified. As a result, the molten solder Ml is cooled and solidified in a rounded shape on the land 130E. The molten solder M2 is cooled and solidified in a rounded shape on the land 130G. Meanwhile, the molten solder M3 is also cooled and solidified. As a result, as shown in FIG. 18, the solder joint 191 is formed in which the land 130E and the electrode 410 are joined by solder, and the solder joint 192 is formed in which the land 130G and the electrode 420 are joined by solder. In addition, the solder joint 193 is formed in which the land 130S and the land 230 are joined by solder. As described above, the processing module 300 shown in FIG. 18 is manufactured. Figure 3 Figure 3 The processing module 300 shown in FIG. 18 is manufactured.

[0086] Thereafter, Figure 3 The processing module 300 shown in FIG. 18 is housed in the housing 611 shown in FIG. 19, whereby the camera body 601, i.e., the digital camera 600 is manufactured. Figure 1

[0087] As described above, by melting the solder pastes Pl and P2 supplied to the printed wiring board 200, it is possible to supply solder to the lands 130E and 130G of the semiconductor device 100 via the electrodes 410 and 420 of the capacitor 400. As a result, it is not necessary to form solder balls in advance on the electrodes 410 and 420 of the capacitor 400, and it is possible to reduce the manufacturing process of the processing module 300. Therefore, since it is possible to easily manufacture the processing module 300, the productivity of the processing module 300 is improved.

[0088] Here, when the solder wettability in the lands 130E and 130G of the semiconductor device 100 is Fl, and the solder wettability in the electrodes 410 and 420 of the capacitor 400 is F2, it is preferable that the relation Fl > F2 is satisfied. For example, by using gold as the surface material of the lands 130, i.e., the surface material of the lands 130E and 130G, the relation Fl > F2 is established, and the molten solders Ml and M2 easily wetting-diffuse in the lands 130E and 130G. As a result, the solder joints 191 and 192 tend to have rounded shapes on the lands 130E and 130G. Therefore, even if the amount of solder in the solder joints 191 and 192 is reduced, it is possible to reliably connect the lands 130E and 130G of the semiconductor device 100 to the electrodes 410 and 420 of the capacitor 400. Therefore, even when the lands 130 of the semiconductor device 100 are arranged at a high density, it is possible to prevent a joining failure from occurring.

[0089] [Second Embodiment]

[0090] A second embodiment will be described. Figure 6 ​​is a schematic cross-sectional view that enlarges a part of the processing module according to the second embodiment. Figure 6 A cross section of the processing module 300A according to the second embodiment is schematically shown. In the following description, components that are the same as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0091] The processing module 300A according to the second embodiment includes the semiconductor device 100 and the printed wiring board 200A that have the same configuration as that of the first embodiment. Like the first embodiment, the land 130E that is the first land, the land 130G that is the second land, and the land 130S that is the fifth land are disposed on the main surface 122 of the insulating substrate 120 included in the semiconductor device 100.

[0092] The printed wiring board 200A includes the insulating substrate 220 that is similar to that in the first embodiment. The insulating substrate 220 has a main surface 221 and a main surface 222 that is opposite to the main surface 221. The printed wiring board 200A includes the land 230E that is the third land, the land 230G that is the fourth land, and the land 230S that is the sixth land, which are disposed on the main surface 221 of the insulating substrate 220.

[0093] The lands 230E, 230G, and 230S are terminals formed of an electrically conductive metal material such as copper or gold. The land 230E is a power supply terminal, and the land 230G is a ground terminal. The land 230S is a signal terminal, a power supply terminal, a ground terminal, or a dummy terminal. The via conductor 212E formed on the insulating substrate 220 is connected to the land 230E. The via conductor 212G formed on the insulating substrate 220 is connected to the land 230G.

[0094] The printed wiring board 200A includes a solder resist 208A. The solder resist 208A is a film made of a solder resist material. The solder resist 208A is disposed on the main surface 221. The land 230S is exposed through an opening portion formed in the solder resist 208A. The land 230E and the land 230G are exposed through one opening portion HA formed in the solder resist 208A. Note that each of the land 230E and the land 230G can be exposed through each of two opening portions independently formed.

[0095] The land 130E and the land 230E are joined to each other by a solder joint 191A that is a first solder joint made of solder. The land 130G and the land 230G are joined by a solder joint 192A that is a second solder joint made of solder. The land 130S and the land 230S are joined to each other by a solder joint 193A that is a third solder joint made of solder.

[0096] As in the first embodiment, the processing module 300A includes the capacitor 400 serving as a bypass capacitor. The capacitor 400 is disposed on the main surface 221 side of the insulating substrate 220 of the printed wiring board 200A, that is, between the semiconductor device 100 and the printed wiring board 200A. The electrode 410 of the capacitor 400 is joined to the land 130E by the solder joint 191A. The electrode 420 of the capacitor 400 is joined to the land 130G by the solder joint 192A. Thus, the electrode 410 of the capacitor 400 is directly electrically connected to the land 130E of the semiconductor device 100 through the solder joint 191A. Accordingly, the inductance of the wiring between the electrode 410 of the capacitor 400 and the land 130E can be reduced. Further, the electrode 420 of the capacitor 400 is directly electrically connected to the land 130G of the semiconductor device 100 through the solder joint 192A. Accordingly, the inductance of the wiring between the electrode 420 of the capacitor 400 and the land 130G can be reduced. Since the inductance of the wiring is reduced, the generated power noise is reduced, and the communication speed in the semiconductor device 100 can be improved.

[0097] In the second embodiment, the land 230E is electrically connected to the land 130E by the solder joint 191A. The land 230G is electrically connected to the land 130E by the solder joint 192A. As in the first embodiment, Figure 6 A power supply IC (not shown) electrically connected to the via conductors 212E and 212G shown is mounted on the printed wiring board 200A. The power supply IC can supply power to the semiconductor element 101 of the semiconductor device 100 via the solder joint 191A and the solder joint 192A.

[0098] Figure 7A is an exploded partial perspective view of the processing module 300A according to the second embodiment. Figure 7B is a schematic view for explaining the arrangement relationship of the semiconductor device 100, the capacitor 400, and the printed wiring board 200A when viewed in the Z direction. In Figure 7A and Figure 7B , the illustration of the solder joints 191A and 192A is omitted. In Figure 7B , the lands 130E and 130G of the semiconductor device are indicated by broken lines.

[0099] As shown in Figure 7A , the upper surface 414 of the electrode 410 faces the land 130E of the semiconductor device 100, and the lower surface 415 of the electrode 410 faces the land 230E of the printed wiring board 200A. The upper surface 424 of the electrode 420 faces the land 130G of the semiconductor device 100, and the lower surface 425 of the electrode 420 faces the land 230G of the printed wiring board 200A.

[0100] like Figure 7B As shown, connecting disks 130E and 130G are arranged at a certain interval in the X direction. When viewed in the Z direction, connecting disk 130E overlaps with at least a portion (the entire electrode 410 in the second embodiment) of the electrode 410 of the capacitor 400. When viewed in the Z direction, connecting disk 130G overlaps with at least a portion (the entire electrode 420 in the second embodiment) of the electrode 420 of the capacitor 400. Connecting disks 230E and 230G are arranged at a certain interval in the X direction. When viewed in the Z direction, connecting disk 230E overlaps with at least a portion (the entire electrode 410 in the second embodiment) of the electrode 410 of the capacitor 400. When viewed in the Z direction, connecting disk 230G overlaps with at least a portion (the entire electrode 420 in the second embodiment) of the electrode 420 of the capacitor 400. Furthermore, when viewed in the Z direction, connecting disk 130E overlaps with at least a portion (the entire connecting disk 230E in the second embodiment). Furthermore, when viewed in the Z direction, connecting disk 130G overlaps with at least a portion (in the second embodiment, the entire connecting disk 230G). In the second embodiment, when viewed in the Z direction, the area S of connecting disk 130E is... 130E The area S is greater than that of electrode 410 410 When viewed in the Z direction, the area S of the connecting disk 130G is... 130G The area S is greater than that of electrode 420 420 When viewed in the Z direction, connecting disks 130E and 130G extend outward from capacitor 400 along the X direction.

[0101] In the second embodiment, as Figure 7B As shown, when viewed in the Z direction, the area S of the connecting disk 130E is... 130E The area S is greater than that of the 230E connecting disk. 230E When viewed in the Z direction, the area S of the connecting disk 130G is... 130G The area S is greater than the 230G of the connecting disk. 230G Furthermore, when viewed in the Z direction, the area S of the opening HA is... HA Area S greater than 400 of capacitor 400 .

[0102] like Figure 6As shown, each of the solder joints 191A and 192A has a rounded shape, in which, when each of the solder joints 191A and 192A extends from each of the lands 230E and 230G toward each of the lands 130E and 130G, an outer surface expands away from the capacitor 400. More specifically, the solder joint 191A has a rounded shape, in which, when the solder joint 191A extends from the land 230E toward the land 130E, the solder joint 191A expands outward in the X direction (i.e., in the XI direction) from the electrode 410. The solder joint 192A has a rounded shape, in which, when the solder joint 192A extends from the land 230G toward the land 130G, the solder joint 192A expands outward in the X direction (i.e., in the X2 direction) from the electrode 420. The XI direction is a direction in the X direction away from the electrode 410. The X2 direction is a direction in the X direction opposite to the XI direction and is a direction away from the electrode 420. As a result, the joint strength between each of the lands 130E and 130G and each of the electrodes 410 and 420 is increased. Further, each of the solder joints 191A and 192A is prevented from having a convex shape in the X direction, and each of the solder joints 191A and 192A is prevented from short-circuiting with the adjacent solder joint 193A.

[0103] As shown, each of the lands 230E and 230G has a rectangular shape when viewed in the Z direction, but is not limited thereto. For example, each of the lands 230E and 230G can have any shape, such as a polygonal shape, a circular shape, or an elliptical shape, when viewed in the Z direction. Figure 7B

[0104] Next, a method of manufacturing the processing module 300A will be described. Figures 8A to 8F is a schematic view of a method of manufacturing the processing module 300A according to the second embodiment. As shown in Figure 8A The printed wiring board 200A is prepared (step S11). In step S11, the semiconductor device 100 and the capacitor 400 are also prepared. Next, as shown in Figure 8B The solder paste P1 as the first solder paste, the solder paste P2 as the second solder paste, and the solder paste P3 as the third solder paste are supplied to the printed wiring board 200A at certain intervals (step S12). In the second embodiment, in step S12, the solder paste P1 is supplied to the land 230E exposed by the opening portion HA formed in the solder resist 208A. Further, the solder paste P2 is supplied to the land 230G exposed by the opening portion HA formed in the solder resist 208A. In step S12, the solder paste P3 is supplied to the land 230S of the printed wiring board 200A.

[0105] ​In step S12, the solder pastes P1, P2, and P3 are supplied to the printed wiring board 200A by screen printing using the metal mask 23. The method of supplying the solder pastes P1, P2, and P3 is not limited thereto. For example, the solder pastes P1, P2, and P3 can be supplied to the printed wiring board 200A by a dispenser.

[0106] Next, as shown in Figure 8C , the capacitor 400 prepared in step Sll is placed on the printed wiring board 200A so that the electrode 410 is in contact with the solder paste P1 and the electrode 420 is in contact with the solder paste P2 (step S13). As a result, the lower surface 415 of the electrode 410 is in contact with the solder paste P1, and the lower surface 425 of the electrode 420 is in contact with the solder paste P2. It is not necessary to attach solder balls to the electrodes 410 and 420 of the capacitor 400 in advance.

[0107] Next, as shown in Figure 8D , the semiconductor device 100 prepared in step Sll is mounted on the printed wiring board 200A so that the land 130E faces the electrode 410 and the land 130G faces the electrode 420 (step S14). In step S14, the semiconductor device 100 is placed on the printed wiring board 200A so that the solder ball B serving as a ball terminal provided on the land 130S is in contact with the solder paste P3. In Figure 8D , the upper surface 414 of the electrode 410 and the land 130E do not contact each other, and the upper surface 424 of the electrode 420 and the land 130G do not contact each other, but they can contact each other.

[0108] In step S14, the positional relationship among the printed wiring board 200A, the capacitor 400, and the semiconductor device 100 when viewed from the Z direction is as shown in Figure 7B When the capacitor 400 is placed on the printed wiring board 200A, each of the land 130E and the land 130G of the semiconductor device 100 overlaps at least a portion of each of the electrode 410 and the electrode 420 when viewed in the Z direction, and extends outward in the X direction from the capacitor 400.

[0109] Next, the printed wiring board 200A is transported to a reflow furnace (not shown) in a state where the semiconductor device 100 and the capacitor 400 are placed on the printed wiring board 200A. Then, in step S15-1 shown in Figure 8E , the atmosphere temperature in the reflow furnace is adjusted to a temperature equal to or higher than the melting point of the solder, and the solder paste P1, P2, P3, and the solder ball B are reflowed as shown in Figure 8D Figure 8E ​The solder paste P1 is melted to form a flowable molten solder M1, and the solder paste P2 is melted to form a flowable molten solder M2. When the solder paste P3 and the solder ball B are melted, a flowable molten solder M3 is obtained.

[0110] After the step S15-1, the heating is continued in a step S15-2 to make the molten solders M1 and M2 flow. As shown in Figure 8F Figure 8E The molten solders M1 and M2 climb up the side surfaces 411 and 421 in an upward direction indicated by arrows Z1. Thereafter, as shown in Figure 8F Figure 8E The molten solders M1 and M2 also climb up the side surfaces 412 and 413 of the electrode 410 and the side surfaces 422 and 423 of the electrode 420 in the upward direction indicated by the arrows Z1, although not shown in

[0111] Furthermore, the capacitor 400 is pushed upward by the molten solders M1 and M2, the distance between the upper surface 414 of the electrode 410 and the land 130E narrows, and the distance between the upper surface 424 of the electrode 420 and the land 130G narrows. The molten solders M1 and M2 that reach the upper surfaces 414 and 424 come into contact with the lands 130E and 130G, wets spread on the lands 130E and 130G, and have a rounded shape in which a skirt portion widens as it moves from the solder resist 208 toward the lands 130E and 130G.

[0112] Thereafter, the molten solders M1 and M2 that wet spread to each corner of the lands 130E and 130G are cooled and solidified. As a result, the molten solder M1 is cooled and solidified in a rounded shape on the land 130E. The molten solder M2 is cooled and solidified in a rounded shape on the land 130G. At the same time, the molten solder M3 is also cooled and solidified. As a result, as shown in Figure 6 Figure 6 The processing module 300A shown above is manufactured.

[0113] Thereafter, Figure 6 The processing module 300A shown above is housed in Figure 1 the housing 611 shown above, thereby manufacturing a camera body of a digital still camera as an example of an electronic device.

[0114] ​​​As described above, by melting the solder paste P1 and P2 supplied to the printed wiring board 200A, the solder can be supplied to the lands 130E and 130G of the semiconductor device 100 via the electrodes 410 and 420 of the capacitor 400. As a result, it is not necessary to form solder balls in advance on the electrodes 410 and 420 of the capacitor 400, and it is possible to reduce the manufacturing process of the processing module 300A. Therefore, since the processing module 300A can be easily manufactured, the productivity of the processing module 300A is improved.

[0115] Furthermore, the land 130E and the land 230E are electrically connected by the solder joint 191A, and the land 130G and the land 230G are electrically connected by the solder joint 192A. As a result, the solder joints 191A and 192A for joining the capacitor 400 to the semiconductor device 100 can be used as power supply lines for supplying power to the semiconductor element 101 of the semiconductor device 100. This increases the degree of freedom of circuit design in the processing module 300A.

[0116] In the second embodiment, as Figure 7B shown, the area S 130E of the land 130E and the area S 130G of the land 130G are larger than the area S 230E of the land 230E and the area S 230G of the land 230G when viewed in the Z direction. Since the molten solders M1 and M2 easily wet and spread in the lands 130E and 130G, it is possible to promote more of the molten solders M1 and M2 to move to the lands 130E and 130G by utilizing this property. As a result, even if there is a variation in the amount of the solder paste P1 and P2 supplied, the allowable amount of variation of the solder paste P1 and P2 increases as the areas of the lands 130E and 130G widen. Therefore, it is possible to prevent the generation of side balls and the like in the solder joints 191A and 192A, and as a result, it is possible to prevent shorting defects in the solder joints 191A and 192A.

[0117] [Third Embodiment]

[0118] A third embodiment will be described. Figure 9 is a schematic cross-sectional view that enlarges a portion of a processing module according to the third embodiment. Figure 9 A cross section of a processing module 300B according to the third embodiment is schematically shown. In the following description, components that are the same as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0119] The processing module 300B according to the third embodiment includes the semiconductor device 100 and the printed wiring board 200B having the same configuration as that of the first embodiment. Like the first embodiment, the land 130E as the first land, the land 130G as the second land, and the land 130S as the fifth land are disposed on the main surface 122 of the insulating substrate 120 included in the semiconductor device 100.

[0120] The printed wiring board 200B has the insulating substrate 220 similar to that in the first embodiment. The insulating substrate 220 has a main surface 221 and a main surface 222 opposite to the main surface 221. Like the first embodiment, the land 230 is disposed on the main surface 221 of the insulating substrate 220.

[0121] The printed wiring board 200B includes the solder resist 208B. The solder resist 208B is a film made of a solder resist material. The solder resist 208B is disposed on the main surface 221. The land 230 is exposed through an opening portion formed in the solder resist 208B.

[0122] Like the first embodiment, the processing module 300B includes the capacitor 400 serving as a bypass capacitor. The capacitor 400 is disposed on the main surface 221 side of the insulating substrate 220 of the printed wiring board 200B, that is, between the semiconductor device 100 and the printed wiring board 200B. The electrode 410 of the capacitor 400 is joined to the land 130E through the solder joint 191B as a first solder joint made of solder. The electrode 420 of the capacitor 400 is joined to the land 130G through the solder joint 192B as a second solder joint made of solder. Thus, the electrode 410 of the capacitor 400 is directly electrically connected to the land 130E of the semiconductor device 100 through the solder joint 191B. Thus, the inductance of the wiring between the electrode 410 of the capacitor 400 and the land 130E can be reduced. The electrode 420 of the capacitor 400 is directly electrically connected to the land 130G of the semiconductor device 100 through the solder joint 192B. Thus, the inductance of the wiring between the electrode 420 of the capacitor 400 and the land 130G can be reduced. Since the inductance of the wiring is reduced, the generated power noise is reduced, and the communication speed in the semiconductor device 100 can be improved.

[0123] The land 130S and the land 230 are joined to each other through the solder joint 193B as a third solder joint made of solder. In the third embodiment, the solder resist 208B has an opening portion HB exposing a portion 221B of the main surface 221.

[0124] Figure 10A is an exploded partial perspective view of the processing module 300B according to the third embodiment. Figure 10Bis a schematic view for illustrating the arrangement relationship of the semiconductor device 100, the capacitor 400, and the printed wiring board 200B when viewed in the Z direction. In Figure 10A and Figure 10B the soldered portions 191B and 192B are not shown. In Figure 10B the land 130E and the land 130G of the semiconductor device are indicated by dotted lines.

[0125] As shown in Figure 10A , the upper surface 414 of the electrode 410 faces the land 130E of the semiconductor device 100, and the lower surface 415 of the electrode 410 faces the portion 221B of the main surface 221 of the printed wiring board 200B. The upper surface 424 of the electrode 420 faces the land 130G of the semiconductor device 100, and the lower surface 425 of the electrode 420 faces the portion 221B of the printed wiring board 200B.

[0126] As shown in Figure 10B , the land 130E and the land 130G are arranged at a certain interval in the X direction. In the plan view, i.e., when viewed in the Z direction, the land 130E overlaps at least a portion of the electrode 410 of the capacitor 400 (the entire electrode 410 in the third embodiment). When viewed in the Z direction, the land 130G overlaps at least a portion of the electrode 420 of the capacitor 400 (the entire electrode 420 in the third embodiment). In the third embodiment, when viewed in the Z direction, the area S 130E of the land 130E is larger than the area S 410 of the electrode 410. When viewed in the Z direction, the area S 130G of the land 130G is larger than the area S 420 of the electrode 420. When viewed in the Z direction, the land 130E and the land 130G extend outward in the X direction from the capacitor 400.

[0127] As shown in Figure 9As shown, each of the solder joints 191B and 192B has a rounded corner shape, wherein, as each of the solder joints 191B and 192B extends from the portion 221B exposed by the opening HB toward each of the connecting pads 130E and 130G, the outer surface extends away from the capacitor 400. More specifically, solder joint 191B has a rounded corner shape, and as solder joint 191B extends from the portion 221B exposed by the opening HB toward the connecting pad 130E, solder joint 191B extends outward from the electrode 410 in the X direction (i.e., in the X1 direction). Solder joint 192B has a rounded corner shape, and as solder joint 192B extends from the portion 221B exposed by the opening HB toward the connecting pad 130G, solder joint 192B extends outward from the electrode 420 in the X direction (i.e., in the X2 direction). The X1 direction is the direction away from the electrode 410 in the X direction. The X2 direction is the opposite direction to the X1 direction in the X direction and is away from the electrode 420. As a result, the bonding strength between each of the connecting pads 130E and 130G and each of the electrodes 410 and 420 is increased. In addition, it prevents each of the solder joints 191B and 192B from having a convex shape in the X direction, and prevents each of the solder joints 191B and 192B from short-circuiting with the adjacent solder joint 193B.

[0128] In the third embodiment, as Figure 10B As shown, when viewed in the Z direction, the area S of the opening HB is... HB That is, the area S of the portion 221B exposed by the opening HB. 221B Area S greater than 400 of capacitor 400 Therefore, as Figure 9 As shown, a portion of the capacitor 400 in the Z direction is inserted into the opening HB, and the distance between the semiconductor device 100 and the printed circuit board 200B is narrowed.

[0129] Next, the method for manufacturing the processing module 300B will be described. Figures 11A to 11F This is an explanatory diagram of a method according to the manufacturing processing module 300B of the third embodiment. (See diagram for reference.) Figure 11A As shown, a printed circuit board 200B is prepared (step S21). In step S21, a semiconductor device 100 and a capacitor 400 are also prepared. Next, as... Figure 11B As shown, solder paste P1 (as the first solder paste), solder paste P2 (as the second solder paste), and solder paste P3 (as the third solder paste) are supplied to the printed circuit board 200B at intervals (step S22). In the third embodiment, in step S22, solder pastes P1 and P2 are supplied at intervals to the portion 221B exposed by the opening HB formed in the solder resist 208B. In step S22, solder paste P3 is supplied to the connector pad 230 of the printed circuit board 200B.

[0130] In step S22, the solder paste Pl, P2, and P3 is supplied to the printed wiring board 200B by screen printing using the metal mask 23. The method of supplying the solder paste Pl, P2, and P3 is not limited thereto. For example, the solder paste Pl, P2, and P3 can be supplied to the printed wiring board 200B by a dispenser.

[0131] Next, as shown in Figure 11C Fig. 23, the capacitor 400 prepared in step S21 is placed on the printed wiring board 200B so that the electrode 410 is in contact with the solder paste Pl and the electrode 420 is in contact with the solder paste P2 (step S23). As a result, the lower surface 415 of the electrode 410 is in contact with the solder paste Pl, and the lower surface 425 of the electrode 420 is in contact with the solder paste P2. It is not necessary to attach solder balls to the electrodes 410 and 420 of the capacitor 400 in advance.

[0132] Next, as shown in Figure 11D Fig. 24, the semiconductor device 100 prepared in step S21 is mounted on the printed wiring board 200B so that the land 130E faces the electrode 410 and the land 130G faces the electrode 420 (step S24). In step S24, the semiconductor device 100 is placed on the printed wiring board 200B so that the solder ball B serving as a ball terminal provided on the land 130S is in contact with the solder paste P3. In Figure 11D step S24, the upper surface 414 of the electrode 410 and the upper surface 424 of the electrode 420 are not in contact with each other, but they can be in contact with each other.

[0133] In step S24, the positional relationship among the printed wiring board 200B, the capacitor 400, and the semiconductor device 100 viewed in the Z direction is as shown in Figure 10B When the capacitor 400 is placed on the printed wiring board 200B, each of the land 130E and the land 130G of the semiconductor device 100 viewed in the Z direction overlaps at least a portion of each of the electrode 410 and the electrode 420, and extends outward in the X direction from the capacitor 400.

[0134] Next, the printed wiring board 200B is transported to a reflow furnace (not shown) in a state where the semiconductor device 100 and the capacitor 400 are placed on the printed wiring board 200B. Next, in Figure 11E step S25-1 shown in Fig. 25, the atmosphere temperature in the reflow furnace is adjusted to a temperature equal to or higher than the melting point of the solder, and the Figure 11D solder paste Pl, P2, P3, and the solder ball B in Figure 11EThe solder paste P1 is melted to form a flowable molten solder M1, and the solder paste P2 is melted to form a flowable molten solder M2. When the solder paste P3 and the solder ball B are melted, a flowable molten solder M3 is obtained.

[0135] After the step S25-1, the heating is continued to flow the molten solders M1 and M2 in the step S25-2 shown below. Figure 11F Figure 11E As shown, the molten solders M1 and M2 climb up the side surfaces 411 and 421 in an upward direction indicated by an arrow Z1. Thereafter, as shown, Figure 11F Figure 11E As shown, the molten solders M1 and M2 move to the upper surfaces 414 and 424. Although

[0136] Furthermore, the capacitor 400 is pushed upward by the molten solders M1 and M2, the distance between the upper surface 414 of the electrode 410 and the land 130E becomes narrow, and the distance between the upper surface 424 of the electrode 420 and the land 130G becomes narrow. The molten solders M1 and M2 that reach the upper surfaces 414 and 424 come into contact with the lands 130E and 130G, wet spread on the lands 130E and 130G, and have a rounded shape in which a skirt portion becomes wide as it moves from the solder resist 208 toward the lands 130E and 130G.

[0137] Thereafter, the molten solders M1 and M2 that wet spread to the lands 130E and 130G are cooled and solidified. As a result, the molten solder M1 is cooled and solidified in a rounded shape on the land 130E. The molten solder M2 is cooled and solidified in a rounded shape on the land 130G. At the same time, the molten solder M3 is also cooled and solidified. As a result, as shown, Figure 9 Figure 9 As described above, the processing module 300B shown is manufactured.

[0138] Thereafter, Figure 9 The processing module 300B shown is housed in the housing 611 shown, thereby manufacturing a camera body of a digital still camera as an example of an electronic device. Figure 1

[0139] ​​​​As described above, by melting the solder paste P1 and P2 supplied to the printed wiring board 200B, the solder can be supplied to the lands 130E and 130G of the semiconductor device 100 via the electrodes 410 and 420 of the capacitor 400. As a result, it is not necessary to form solder balls in advance on the electrodes 410 and 420 of the capacitor 400, and it is possible to reduce the manufacturing process of the processing module 300B. Therefore, since the processing module 300B can be easily manufactured, the productivity of the processing module 300B is improved.

[0140] In the third embodiment, since a part of the capacitor 400 is inserted into the opening portion HB, the height of the solder joints 191B, 192B, and 193B in the Z direction, that is, the interval between the semiconductor device 100 and the printed wiring board 200B in the Z direction can be narrowed. Therefore, it is possible to reduce the amount of solder in the solder joints 191B, 192B, and 193B, and it is possible to reduce the manufacturing cost of the processing module 300B.

[0141] (Example 1)

[0142] Example 1 corresponding to the first embodiment will be described. In Figure 3 In the semiconductor device 100 illustrated, the minimum interval of the solder balls B Figure 5D ) as two adjacent unjoined ball terminals is 0.4 [mm]. The material of the lands 130 is copper. The material of each of the solder joints 191, 192, and 193 is tin-3.0% silver 0.5% copper. From Figure 4B The area S 400 of the capacitor 400 viewed in the Z direction illustrated is 0.4 [mm] x 0.2 [mm]. That is, the capacitor 400 is a 0402 chip component.

[0143] According to the minimum interval of the solder balls B and the size of the capacitor 400, the metal mask 23 used in the manufacturing process of the processing module 300 Figure 5B The thickness of the metal mask 23 illustrated is set to 0.08 [mm], and the solder balls B are ball terminals before joining of two adjacent in the semiconductor device 100.

[0144] In Figure 5E and Figure 5F In the steps S5-1 and S5-2 illustrated, the solder pastes P1, P2, and P3 are melted at the peak temperature of the atmosphere in the reflow furnace at 230°C or higher. Thereafter, the molten solders M1, M2, and M3 are cooled and solidified. It is confirmed that the capacitor 400 is joined to the semiconductor device 100 by the solder joints 191 and 192. The solder joints 191 and 192 have a round shape on the lands 130E and 130G.

[0145] The movement of the molten solders Ml, M2 and M3 in steps S5-1 and S5-2 is confirmed by observation as follows. First, the solder paste P3 and the solder ball B are entirely melted. At this time, the semiconductor device 100 is moved toward the printed wiring board 200 by the rounded molten solder M3. At the same time, since the molten solders Ml and M2 are not in contact with the lands of the printed wiring board 200, the molten solders Ml and M2 move to the electrodes 410 and 420 of the capacitor 400 and reach the upper surfaces 414 and 424 along the side surfaces 411 and 412. The capacitor 400 is raised with respect to the surface of the solder resist 208 by the molten solders Ml and M2. The amount of the raising depends on the amounts of the solder pastes Pl and P2, but is about 0.01 to 0.015 [mm] in Example 1. As a result, the upper surfaces 414 and 424 of the capacitor 400 are brought close to the lands 130E and 130G. The molten solders Ml and M2 that have reached the upper surfaces 414 and 424 come into contact with the lands 130E and 130G and spread wetly over the lands 130E and 130G. The movement of the molten solders Ml, M2 and M3 as described above forms the solder joints 191 and 192 having a rounded shape on the lands 130E and 130G.

[0146] (Example 2)

[0147] Example 2 corresponding to the second embodiment will be described. In Figure 6 The minimum distance of the solder balls B Figure 8D ) that are two adjacent unjoined ball terminals in the semiconductor device 100 shown is 0.4 [mm]. The material of the lands 130 is copper. The solder joints 191A, 192A and 193A are made of tin-3.0% silver 0.5% copper. The area S Figure 7B of the capacitor 400 viewed in the Z direction shown is 0.4 [mm] x 0.2 [mm]. That is, the capacitor 400 is a 0402 chip component. 400

[0148] The size of the lands 130E and 130G in the semiconductor device 100 viewed in the Z direction is set to 0.6 [mm] x 0.22 [mm]. The size of the lands 230E and 230G in the printed wiring board 200A viewed in the Z direction is set to 0.5 [mm] x 0.2 [mm]. The area S 130E of the land 130E and the area S 130G of the land 130G are 0.132 mm 2 . The area S 230E of the land 230E and the area S 230G of the land 230G are 0.1 mm 2 . As described above, the area S 130E of the land 130E and the area S 130G ​the area S of the land 230E 230E and the area S of the land 230G 230G is set to S 230E and S 230G <S 130E and S 130G .

[0149] Compared to Example 1, the amounts of the solder pastes P1 and P2 are increased, and in order to confirm the round shape, the thickness of the metal mask 23 used in Step S12 shown in FIG. 12 is set to 0.10 [mm] which is thicker than 0.08 [mm]. Figure 8B

[0150] Since the area S of the land 130E 130E and the area S of the land 130G 130G are larger than the area S of the land 230E 230E and the area S of the land S230G 230G , in Steps S15-1 and S15-2, the molten solders M1 and M2 wet and spread to the large-area lands 130E and 130G. Therefore, in Example 2, it is confirmed that the generation of side balls and the expansion of round corners are prevented in the solder joints 191A and 192A, and the short defect is prevented.

[0151] (Example 3)

[0152] Next, a third example will be described. Example 3 corresponds to the first embodiment, but the materials of the lands 130E and 130G are different from those of Example 1.

[0153] The wettability of the molten solder in the lands 130E and 130G of the semiconductor device 100 is Fl, and the wettability of the molten solder in the electrodes 410 and 420 of the capacitor 400 is F2. In Example 3, the materials of the lands 130E and 130G of the semiconductor device 100 and the electrodes 410 and 420 of the capacitor 400 are selected to satisfy the relationship of Fl ≥ F2. The wettability of the molten solder refers to the ease of assembly of the molten solder.

[0154] In order for the molten solder to wet and spread on the surfaces of the electrodes 410 and 420 of the capacitor 400 and the surfaces of the lands 130E and 130G of the semiconductor device 100, it is important that the surfaces of the molten solder and the object metal are not contaminated. The cleaner the surfaces of the molten solder and the metal, the closer the interatomic distance between them, and the molten solder wets and spreads on the metal surface, thereby coming into close contact with the metal surface. For this reason, the lands 130E and 130G of the semiconductor device 100 are subjected to gold plating which is difficult to oxidize. In addition, the electrodes 410 and 420 of the capacitor 400 are plated with tin which is easy to oxidize and has a low reduction rate.

[0155] ​Figure 5B The thickness of the metal mask 23 shown is set to 0.05 [mm]. The supply amounts of the solder pastes P1, P2, and P3 are smaller than those in Example 1. The sizes of the semiconductor device 100 and the capacitor 400 are the same as in Example 1.

[0156] In steps S5-1 and S5-2 in Figure 5E and Figure 5F In steps S5-1 and S5-2 in

[0157] (Calculation of inductance)

[0158] Next, the inductance of the wiring between the semiconductor element and the capacitor was calculated for Example 1, Example 2, and Comparative Example 1. Figure 12A is a schematic cross-sectional view of the processing module 300 of Example 1. Figure 12B is a schematic cross-sectional view of the processing module 300A of Example 2. Figure 12C is a schematic cross-sectional view of the processing module 300X of Comparative Example 1.

[0159] Figure 12C The processing module 300X of Comparative Example 1 shown includes the semiconductor device 100, the capacitor 400, and the printed wiring board 200X. The semiconductor device 100 includes the semiconductor element 101 and the package substrate 102. The semiconductor element 101 is mounted on the package substrate 102. The package substrate 102 includes the land 130E and the land 130G.

[0160] The printed wiring board 200 includes the insulating substrate 220X. The insulating substrate 220X has one main surface and another main surface opposite to the one main surface. The land 230EX and the land 230GX are disposed on the one main surface of the insulating substrate 220X. The land 130E and the land 230EX are joined by the solder joint 191X. The land 130G and the land 230GX are joined by the solder joint 192X.

[0161] The capacitor 400 is disposed on the other main surface side of the insulating substrate 220X of the printed wiring board 200X. A land 240EX solder-joined to the electrode 410 of the capacitor 400 and a land 240GX solder-joined to the electrode 420 of the capacitor 400 are disposed on the other main surface of the insulating substrate 220X. The land 230EX and the land 240EX are electrically connected by a via conductor 291X formed in the insulating substrate 220X. The land 230GX and the land 240GX are electrically connected by a via conductor 292X formed in the insulating substrate 220X.

[0162] The calculation conditions are shown below. In the semiconductor device 100 that is a BGA semiconductor package, the pitch between two adjacent ball terminals is set to 0.4 [mm]. The thickness of the package substrate 102 is set to 0.4 [mm]. Each of the solder joints 193, 193A, 191X, and 192X has a height of 0.220 [mm] and a width of 0.250 [mm]. The capacitor 400 is a 0402 size chip capacitor. The thickness of each of the printed wiring boards 200, 200A, 200X is set to 0.8 [mm]. For the calculation of the inductance, a calculation formula of the inductance in a parallel wire is used.

[0163] The calculation results of Example 1 shown in FIG. 12 will be described. Figure 12A The inductance value of each of the via conductors 112E and 112G in the package substrate 102 is 266 pH. Each of the inductance value between the electrode 410 of the capacitor 400 and the land 130E and the inductance value between the electrode 420 of the capacitor 400 and the land 130G is 180 pH. Therefore, each of the inductance value between the power supply terminal 111E of the semiconductor element 101 and the electrode 410 of the capacitor 400 and the inductance value between the ground terminal 111G of the semiconductor element 101 and the electrode 420 of the capacitor 400 is 466 pH. Figure 12B The calculation results of Example 2 shown in FIG. 13 are similar to those of Example 1.

[0164] The calculation results of Example 3 shown in FIG. 14 will be described. Figure 12CThe calculation results of Comparative Example 1 are shown. The inductance value of each of the via conductors 112E and 112G in the package substrate 102 is 266 pH. The inductance value of each of the solder joints 191X and 192X is 42 pH. The inductance value of each of the via conductors 291X and 292X in the printed wiring board 200X is 545 pH. Each of the inductance value between the electrode 410 of the capacitor 400 and the land 240EX and the inductance value between the electrode 420 of the capacitor 400 and the land 240GX is 180 pH. Therefore, each of the inductance value between the power supply terminal 111E of the semiconductor element 101 and the electrode 410 of the capacitor 400 and the inductance value between the ground terminal 111G of the semiconductor element 101 and the electrode 420 of the capacitor 400 is 1033 pH.

[0165] Figure 13 The calculation results of the inductance in Example 1, Example 2, and Comparative Example 1 are shown. As shown in Figure 13 in Examples 1 and 2, the inductance values are smaller than the inductance value of Comparative Example 1. As a result, the generated power supply noise is reduced, and high-speed communication can be achieved in the semiconductor device 100. In Example 2, as shown in Figure 12B the semiconductor device 100 and the printed wiring board 200A are connected via the capacitor 400 through the solder joints 191A and 192A. As a result, the semiconductor element 101 can be supplied with power via the solder joints 191A and 192A. Therefore, the land 130S can be used for a purpose other than the power supply line, and the degree of freedom of circuit design is increased.

[0166] As described above, a processing module that achieves high-speed communication can be manufactured without increasing the manufacturing process.

[0167] Note that the present application is not limited to the above-described embodiments, and many modifications can be made within the technical idea of the present application. In addition, the effects described in the embodiments are merely illustrative of the most appropriate effects produced by the present application, and the effects of the present application are not limited to those described in the embodiments.

[0168] In the above-described embodiments, the case where the electronic component is the capacitor 400 has been described, but the present application is not limited thereto. The electronic component can be a passive component such as a resistor or an inductor.

[0169] In the above-described embodiments, the semiconductor device 100 to which the solder balls B are disposed on the lands 230S is prepared in advance, but the present application is not limited thereto. That is, in the step of preparing the semiconductor device 100, the solder balls S can be disposed on the lands 230S.

[0170] [Industrial Applicability]

[0171] The present application can be implemented in a semiconductor module mounted on various electronic devices including a digital camera.

[0172] The present application is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the present application. Therefore, the claims are appended so as to disclose the scope of the present application.

[0173] [List of reference numerals]

[0174] 100 semiconductor device

[0175] 130E connection pad (first connection pad)

[0176] 130G connection pad (second connection pad)

[0177] 200 printed wiring board

[0178] 300 processing module (semiconductor module)

[0179] 400 capacitor (electronic component)

[0180] 410 electrode (first electrode)

[0181] 420 electrode (second electrode)

Claims

1. A semiconductor module manufacturing method comprising the steps of: preparing a chip component including a first electrode and a second electrode arranged at intervals in a predetermined direction, a semiconductor device including a first land and a second land, and a printed wiring board, the wettability of the first land having molten solder being higher than the wettability of the first electrode having molten solder; supplying a first solder paste and a second solder paste to the printed wiring board at intervals; placing the chip component on the printed wiring board so that the first electrode is in contact with the first solder paste and the second electrode is in contact with the second solder paste; placing the semiconductor device on the printed wiring board so that the first land faces the first electrode and the second land faces the second electrode; heating and melting the first solder paste and the second solder paste; and joining the first land and the first electrode to each other with solder and joining the second land and the second electrode to each other with solder by cooling and solidifying the molten solder wet-spreading into each of the first land and the second land.

2. The semiconductor module manufacturing method according to claim 1, in the step of placing the semiconductor device, each of the first land and the second land overlaps at least a portion of each of the first electrode and the second electrode in a plan view, and extends outward from the chip component in the predetermined direction. wherein 3. The semiconductor module manufacturing method according to claim 1, in the step of joining, the wet-spreading molten solder obtained by melting the first solder paste is cooled and solidified in a rounded shape on the first land, and wherein the wet-spreading molten solder obtained by melting the second solder paste is cooled and solidified in a rounded shape on the second land.

4. The semiconductor module manufacturing method according to any one of claims 1 to 3, the printed wiring board includes an insulating substrate and a solder resist arranged on a main surface of the insulating substrate, and wherein the first solder paste and the second solder paste are supplied onto the solder resist.

5. The semiconductor module manufacturing method according to any one of claims 1 to 3, the printed wiring board includes an insulating substrate and a third land and a fourth land arranged on a main surface of the insulating substrate, and wherein in the step of supplying, the first solder paste is supplied onto the third land and the second solder paste is supplied onto the fourth land.

6. The semiconductor module manufacturing method according to claim 5, in a plan view, the area of the first land is larger than the area of the third land, and the area of the second land is larger than the area of the fourth land. wherein 7. The semiconductor module manufacturing method according to any one of claims 1 to 3, the printed wiring board includes an insulating substrate and a solder resist arranged on a main surface of the insulating substrate, wherein the solder resist has an opening portion exposing a portion of the main surface of the insulating substrate, and the first solder paste and the second solder paste are supplied to the opening portion. The first solder paste and the second solder paste are supplied to portions exposed through the opening portions on the main surface of the insulating substrate.

8. The semiconductor module manufacturing method according to any one of claims 1 to 3, wherein, The semiconductor device includes a fifth land provided with a solder ball, and the printed wiring board includes a sixth land, The semiconductor module manufacturing method further includes the steps of: In a case where the first solder paste and the second solder paste are supplied in the printed wiring board, a third solder paste is supplied onto the sixth land; The semiconductor device is placed on the printed wiring board so that the solder ball contacts the third solder paste; The third solder paste and the solder ball are heated and melted together with the first solder paste and the second solder paste; and The fifth land and the sixth land are joined to each other with solder by cooling and solidifying the molten solder.

9. The semiconductor module manufacturing method according to any one of claims 1 to 3, wherein The semiconductor device is a BGA semiconductor package.

10. An electronic device manufacturing method including the steps of: manufacturing a semiconductor module by the manufacturing method according to any one of claims 1 to 3; and arranging the semiconductor module inside a housing.

11. A semiconductor module including: a printed wiring board; a semiconductor device including a first land and a second land, the semiconductor device being mounted on the printed wiring board; a chip component including a first electrode and a second electrode spaced apart from each other in a predetermined direction, the chip component being arranged between the printed wiring board and the semiconductor device; a first solder joint joining the first electrode and the first land to each other; and a second solder joint joining the second electrode and the second land to each other, wherein the printed wiring board includes an insulating substrate and a solder resist arranged on a main surface of the insulating substrate, the chip component faces the solder resist, in a plan view, each of the first land and the second land overlaps at least a portion of each of the first electrode and the second electrode, and extends outward from the chip component in the predetermined direction, the first solder joint has a rounded shape in which, when the first solder joint extends from the solder resist toward the first land, the first solder joint spreads outward in the predetermined direction from the first electrode, and wherein wettability of the first land with molten solder is higher than wettability of the first electrode with molten solder.

12. A semiconductor module including: a printed wiring board; a semiconductor device including a first land and a second land, the semiconductor device being mounted on the printed wiring board; a chip component including a first electrode and a second electrode spaced apart from each other in a predetermined direction, the chip component being arranged between the printed wiring board and the semiconductor device; a first solder joint joining the first electrode and the first land to each other; and a second solder joint joining the second electrode and the second land to each other, wherein the printed wiring board includes an insulating substrate and a solder resist arranged on a main surface of the insulating substrate, the chip component faces the solder resist, in a plan view, each of the first land and the second land overlaps at least a portion of each of the first electrode and the second electrode, and extends outward from the chip component in the predetermined direction, the first solder joint has a rounded shape in which, when the first solder joint extends from the solder resist toward the first land, the first solder joint spreads outward in the predetermined direction from the first electrode, and wherein wettability of the first land with molten solder is higher than wettability of the first electrode with molten solder. a second solder joint that joins the second electrode and the second land to each other, wherein the printed wiring board includes an insulating substrate, a third land that is disposed on a main surface of the insulating substrate and electrically connected to the first land by the first solder joint, and a fourth land that is disposed on the main surface of the insulating substrate and electrically connected to the second land by the second solder joint, each of the first land and the second land overlaps at least a portion of each of the first electrode and the second electrode, overlaps at least a portion of each of the third land and the fourth land, and extends outward from the chip component in the predetermined direction in a plan view, the first solder joint has a round shape, wherein the first solder joint spreads outward from the first electrode in the predetermined direction when the first solder joint extends from a portion of the main surface of the insulating substrate exposed by the opening of the solder resist toward the first land, and wherein wettability of the first land with molten solder is higher than wettability of the first electrode with molten solder.

13. A semiconductor module comprising: a printed wiring board; a semiconductor device including a first land and a second land, the semiconductor device being mounted on the printed wiring board; a chip component including a first electrode and a second electrode that are spaced apart from each other in a predetermined direction, the chip component being disposed between the printed wiring board and the semiconductor device; a first solder joint that joins the first electrode and the first land to each other; and a second solder joint that joins the second electrode and the second land to each other, wherein the printed wiring board includes an insulating substrate and a solder resist that is disposed on a main surface of the insulating substrate, the solder resist has an opening portion into which a portion of the chip component is inserted, each of the first land and the second land overlaps at least a portion of each of the first electrode and the second electrode, and extends outward from the chip component in the predetermined direction in a plan view, the first solder joint has a round shape, wherein the first solder joint spreads outward from the first electrode in the predetermined direction when the first solder joint extends from a portion of the main surface of the insulating substrate exposed by the opening of the solder resist toward the first land, and wherein wettability of the first land with molten solder is higher than wettability of the first electrode with molten solder.

14. The semiconductor module according to any one of claims 11 to 13, wherein, the first land is a power supply terminal, and the second land is a ground terminal.

15. The semiconductor module according to any one of claims 11 to 13, wherein the chip component is a chip component of 0402 size or less.

16. The semiconductor module according to any one of claims 11 to 13, wherein, the chip component is a capacitor.

17. The semiconductor module according to any one of claims 11 to 13, wherein, The semiconductor device is a BGA semiconductor package in which a distance between lands is less than or equal to 0.4 mm.

18. The semiconductor module according to any one of claims 11 to 13, wherein, The semiconductor device includes a semiconductor element, and In a plan view of the semiconductor module, the semiconductor element and the chip component overlap each other.

19. The semiconductor module according to any one of claims 11 to 13, further comprising a third solder joint that joins a fifth land and a sixth land, wherein The semiconductor device includes the fifth land, The printed wiring board includes the sixth land on a main surface of the insulating substrate, and A height of the third solder joint is higher than a height of the chip component.

20. An electronic device comprising: a housing; and The semiconductor module according to any one of claims 11 to 13 is disposed inside the housing.

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