A transistor test circuit and control method

Abstract

The present application belongs to the field of semiconductor testing, and specifically provides a test circuit for a transistor and a control method for the circuit. The test circuit for the transistor includes: a power branch composed of at least two power sub-branches connected in parallel; a switch branch composed of a first diode and a first switch connected in parallel; a protection branch composed of a second diode, an inductor and a fourth switch connected in parallel; a transistor to be tested; and a third diode; wherein the positive terminal of the power branch is connected to the negative terminal of the switch branch; the positive terminal of the switch branch is connected to the negative terminal of the protection circuit; the positive terminal of the protection circuit is connected to the collector of the transistor to be tested; the emitter of the transistor to be tested is respectively connected to the negative terminal of the power branch and the negative terminal of the third diode; the positive terminal of the third diode is connected to the negative terminal of the power branch. Based on the technical solution provided by the present invention, the test of the transistor under the condition of changing the bus voltage can be quickly realized without replacing the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor measurement technology, and in particular to a transistor test circuit and a control method. Background Art

[0002] In the power conversion system, transistors are widely used, for example, they can be used in high-voltage inverters, high-voltage static VAR generators, locomotive traction inverters, and wind power converters. As transistors are so widely used, there are more and more types and manufacturers of transistors, so the performance test of transistors becomes particularly important.

[0003] In the transistor product manual, the parameters used to describe the performance of the transistor include static parameters and dynamic parameters. The measurement of static parameters is relatively simple, but the test of dynamic parameters (such as turn-on delay time Tdon, current rise time Tr, turn-off delay time Tdoff, current fall time Tf, turn-on loss Eon, and turn-off loss Eoff, etc.) is more complicated. In the current common transistor test equipment, in order to improve the current carrying capacity, the bus capacitor capacity is generally set to be relatively large. Therefore, the bus voltage cannot be changed quickly during the test. In the case where the bus voltage needs to be changed during the test, it takes a long time to complete, resulting in low test efficiency. Summary of the invention

[0004] In view of the above problems in the prior art, the present invention provides a transistor test circuit, which can quickly change the bus voltage during the test process and improve the test efficiency.

[0005] To achieve the above-mentioned purpose, the first aspect of the present invention provides a transistor test circuit, comprising: a power supply branch composed of at least two power supply sub-branches connected in parallel; a power supply branch composed of at least two power supply sub-branches connected in parallel; a switch branch composed of a first diode and a first switch connected in parallel; a protection branch composed of a second diode, an inductor and a fourth switch connected in parallel; a transistor to be tested; and a third diode; wherein the positive terminal of the power supply branch is connected to the negative terminal of the switch branch; the positive terminal of the switch branch is connected to the negative terminal of the protection branch; the positive terminal of the protection branch is connected to the collector of the transistor to be tested; the emitter of the transistor to be tested is respectively connected to the negative terminal of the power supply branch and the negative electrode of the third diode; and the positive electrode of the third diode is connected to the negative terminal of the power supply branch.

[0006] From the above, by designing a power branch composed of at least two power sub-branches connected in parallel, the voltage can be changed by changing the access state of the at least two power sub-branches to simulate the bus voltage change process during the test, thereby improving the test efficiency. In addition, by designing the first diode and the third diode, the parasitic inductance in the entire test circuit can be reduced.

[0007] As a possible implementation manner of the first aspect, the power sub-branch includes: a power supply and a capacitor connected in parallel, and a switch for controlling the on and off of the power supply and the capacitor connected in parallel.

[0008] From the above, the corresponding switch in the power sub-branch can be controlled to control whether the sub-branch is connected to the test circuit, so as to achieve the purpose of voltage variation.

[0009] As a possible implementation of the first aspect, it also includes: a control branch, used to control the on-off of the power branch, the switch branch, the protection branch, and the transistor to be tested; wherein the control branch controls the on-off of the power branch by controlling the switch in the power sub-branch; the control branch controls the on-off of the switch branch by controlling the first switch in the switch branch; the control branch controls the on-off of the protection branch by controlling the fourth switch in the protection branch; the control branch controls the on-off of the transistor to be tested by controlling the gate of the transistor to be tested.

[0010] From the above, the control branch can emit control pulses to achieve control of the controllable devices in the test circuit.

[0011] As a possible implementation manner of the first aspect, the control branch is further used to control the size of the power supply in the power supply branch.

[0012] As a possible implementation manner of the first aspect, the method further includes: in the at least two power sub-branches, voltages of the power sub-branches are different.

[0013] As described above, by setting the voltages in the power sub-branches to different voltages, the diversity of voltages is enriched, and testing in multiple voltage modes can be achieved.

[0014] A second aspect of the present application provides a control method for a test circuit, wherein the test circuit includes the circuit described in any one of claims 1 to 5, and is characterized in that the control method includes: controlling the switch in the power sub-branch with a lower voltage in the power branch to close, and controlling the first switch in the switch branch to close; when the collector current in the transistor to be tested remains stable and is 0, controlling the switch in the power sub-branch with a lower voltage in the power branch to open, controlling the switch in the power sub-branch with a higher voltage in the power branch to close, and controlling the fourth switch in the protection branch to close; when the collector current in the transistor to be tested remains stable and is 0 again, controlling the switch in the power sub-branch with a higher voltage in the power branch to open; until the circuit is stable, controlling the first switch in the switch branch and the fourth switch in the protection branch to open.

[0015] Through the control method, a fast variable voltage test of the transistor is achieved without replacing the device, thereby improving the test efficiency.

[0016] These and other aspects of the invention will become apparent from the following description of the embodiment(s). BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A circuit diagram of a transistor test circuit provided by an embodiment of the present invention;

[0018] Figure 2 A schematic diagram of control timing in a control method for a test circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The words "first, second, third, etc." or module A, module B, module C and the like in the specification and claims are used only to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that the specific order or sequence can be interchanged where permitted so that the embodiments of the invention described herein can be implemented in an order other than that illustrated or described herein.

[0020] In the following description, the numbers representing the steps, such as S110, S120, etc., do not necessarily mean that the steps must be executed in this manner. If permitted, the order of the previous and next steps can be interchanged, or they can be executed simultaneously.

[0021] The term "comprising" as used in the description and claims should not be interpreted as being limited to what is listed thereafter; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the mentioned features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components and groups thereof. Therefore, the expression "a device comprising means A and B" should not be limited to a device consisting of components A and B only.

[0022] References to "one embodiment" or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places in this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. In addition, in one or more embodiments, the particular features, structures, or characteristics can be combined in any appropriate manner, as would be apparent to one of ordinary skill in the art from this disclosure.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. In the event of any inconsistency, the meanings described in this specification or derived from the contents recorded in this specification shall prevail. In addition, the terms used herein are only for the purpose of describing the embodiments of the present invention and are not intended to limit the present invention.

[0024] Referring to the figures below, a transistor test circuit provided in the present application is described in detail.

[0025] like Figure 1 As shown, it is a circuit structure diagram of the test circuit of the transistor provided in the embodiment of the present application. In this embodiment, the test circuit of the transistor includes a power branch 110, a switch branch 120, a protection branch 130, a transistor DUT to be tested, and a third diode D3. Among them, the positive terminal of the power branch 110 is connected to the negative terminal of the switch branch 120, the positive terminal of the switch branch 120 is connected to the negative terminal of the protection branch 130, the positive terminal of the protection branch 130 is connected to the collector of the transistor DUT to be tested, and the emitter of the transistor DUT to be tested is respectively connected to the negative terminal of the power branch 110 and the negative terminal of the third diode D3; the positive electrode of the third diode D3 is connected to the negative terminal of the power branch 110. Among them, the transistor can be an insulated gate bipolar transistor (IGBT), and can also be a metal-oxide-semiconductor field-effect transistor (MOSFET), etc.

[0026] In this embodiment, the power branch 110 includes a plurality of power sub-branches 111, which are connected in parallel. The power sub-branch 111 includes a parallel power supply and a capacitor, and a switch for controlling the on / off of the power sub-branch. Figure 1 POW1 is shown as the power supply, Figure 1The C1 is a capacitor, and the power supply POW1 is connected in parallel with the capacitor C1, and then connected to the switch K2 to form a power sub-branch. Similarly, the power supply POW2 is connected in parallel with the capacitor C2, and then connected to the switch K3 to form another power sub-branch. A plurality of such power sub-branches are connected in parallel to form a power branch 110. In this embodiment, the switch in each power sub-branch 111 can be controlled to control whether the sub-branch is connected to the test circuit, so as to quickly change the voltage connected to the test circuit, thereby improving the test efficiency. The switch branch 120 includes a first diode D1 and a first switch K1, and the first diode D1 and the first switch K1 are connected in parallel. The switch branch 120 is used to control the on and off of the entire test circuit. The protection branch 130 includes a second diode D2, an inductor L, and a fourth switch K4, and the second diode D2, the inductor L, and the fourth switch K4 are connected in parallel.

[0027] In this embodiment, the test circuit may further include a control branch 140 for controlling the on / off of the power branch 110, the switch branch 120, the protection branch 130, and the transistor DUT to be tested. Specifically, the control branch 140 may control the on / off of the power sub-branch by controlling the switch in the power sub-branch in the power branch 110, for example, by controlling Figure 1 The K2 and / or K3 shown are used to control the corresponding power sub-branch. The control branch 140 can control the on-off of the switch branch 120 by controlling the first switch K1 in the switch branch 120. The control branch 140 can control the on-off of the protection branch 130 by controlling the fourth switch K4 in the protection branch 130. The control branch 140 can control the on-off of the transistor DUT under test by controlling the gate g of the transistor DUT under test.

[0028] It should be understood that in this embodiment, the voltages of each power sub-branch can be different or the same. In this embodiment, the voltages of the two power sub-branches are set to be different. For example, the power supply POW1 is set to 500V and the power supply POW2 is set to 1000V.

[0029] like Figure 2 As shown, a control method for a test circuit is provided in an embodiment of the present application. Figure 2 The working principle of the test circuit in this embodiment is further described. In this embodiment, the test circuit is the test circuit of the transistor in the above embodiment, so the circuit structure is not described in detail in this embodiment.

[0030] like Figure 2As shown, the waveform corresponding to the control pulse of K1 is the control pulse of the first switch K1 in the switch branch described in the above embodiment, the waveform corresponding to the control pulse of K2 is the control pulse corresponding to the switch K2 in the power sub-branch described in the above embodiment, the waveform corresponding to the control pulse of K3 is the control pulse corresponding to the power sub-branch K3 in the above embodiment, and the waveform corresponding to the control pulse of K4 is the control pulse of the fourth switch K4 in the protection branch described in the above embodiment. DUT is the waveform corresponding to the transistor DUT to be tested in the above embodiment at different control moments, including the voltage Vge between the gate and the emitter, the voltage Vce between the collector and the emitter, and the current Ic of the collector. In this embodiment, t0 is the start time of the test, at which time it is necessary to control switches K2 and K1 to be closed. When the current Ic in the transistor DUT to be tested remains stable and is 0, that is, Figure 2 At time t5 in the figure, the control switch K2 is opened, the control switch K3 is closed, and the control switch K4 is closed. In the subsequent period of time, the current Ic will continue to fluctuate until the current Ic in the transistor DUT under test is stable and 0 again, that is, Figure 2 At t8 in the circuit, the control switch K3 is disconnected. After all parameters in the circuit are stable, the test is completed. At this time, the control switches K1 and K4 are disconnected, corresponding to Figure 2 Mid t9 moment.

[0031] Based on the transistor test circuit and control method provided by the present application, a power supply branch composed of at least two power supply sub-branches connected in parallel is designed to change the access voltage of the test circuit by changing the access state of each power supply sub-branch, thereby achieving the purpose of fast voltage change and greatly improving the test efficiency. In addition, a first diode and a third diode are also arranged in the test circuit of the present application. By designing these two diodes, the parasitic inductance in the test circuit is reduced to improve the test accuracy.

[0032] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention is described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present invention, all of which belong to the protection scope of the present invention.

Claims

1. A transistor test circuit, characterized in that: include: A power branch consisting of at least two power sub-branches connected in parallel; A switch branch consisting of a first diode and a first switch connected in parallel; A protection branch composed of a second diode, an inductor and a fourth switch connected in parallel; The transistor to be tested; as well as The third diode; Wherein, the positive terminal of the power supply branch is connected to the negative terminal of the switch branch; the positive terminal of the switch branch is connected to the negative terminal of the protection branch; the positive terminal of the protection branch is connected to the collector of the transistor to be tested; the emitter of the transistor to be tested is respectively connected to the negative terminal of the power supply branch and the negative terminal of the third diode; the positive terminal of the third diode is connected to the negative terminal of the power supply branch; The power sub-branch comprises: A power supply and a capacitor connected in parallel, and a switch for controlling the on and off of the power supply and the capacitor connected in parallel.

2. The circuit according to claim 1, characterized in that Also includes: A control branch, used for controlling the on and off of the power supply branch, the switch branch, the protection branch, and the transistor to be tested; Among them, the control branch controls the on-off of the power branch by controlling the switch in the power sub-branch; the control branch controls the on-off of the switch branch by controlling the first switch in the switch branch; the control branch controls the on-off of the protection branch by controlling the fourth switch in the protection branch; the control branch controls the on-off of the transistor to be tested by controlling the gate of the transistor to be tested.

3. The circuit according to claim 2, characterized in that The control branch is also used to control the power supply in the power supply branch.

4. The circuit according to claim 1, characterized in that Also includes: In the at least two power supply sub-branches, voltages of the power supply sub-branches are different.

5. A control method for a test circuit, the test circuit comprising the circuit according to any one of claims 1 to 4, characterized in that: The control method comprises: Controlling the switch in the power sub-branch with a lower voltage in the power branch to close, and controlling the first switch in the switch branch to close; When the collector current in the transistor to be tested remains stable and is 0, the switch in the power sub-branch with a lower voltage in the power branch is controlled to be disconnected, the switch in the power sub-branch with a higher voltage in the power branch is controlled to be closed, and the fourth switch in the protection branch is controlled to be closed; When the collector current in the transistor to be tested remains stable and is 0 again, controlling the switch in the power sub-branch with a higher voltage in the power branch to be disconnected; After the circuit is stable, the first switch in the switch branch and the fourth switch in the protection branch are controlled to be disconnected.

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