Wiring method, device, electronic equipment and storage medium of programmable device

Abstract

The application discloses a wiring method and device of a programmable device, electronic equipment and a storage medium, and belongs to the field of integrated circuit design. It comprises the following steps: acquiring a wired node and a to-be-wired node in user-designed circuit wiring; judging whether the to-be-wired node is a key wiring node in the user-designed circuit wiring to obtain a node judgment result; acquiring a reverse target node of the to-be-wired node according to the node judgment result, wherein the reverse target node comprises a wiring starting point of the user-designed circuit wiring and a wired node near the to-be-wired node; and reversely executing a wiring algorithm process with the to-be-wired node as a starting point and the reverse target node as an ending point. The application does not need to allocate a wiring path in advance, thereby making subsequent wiring operation more flexible, and can make the wiring speed faster, the wiring time shorter and the user experience better.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuit design, and relates to a field programmable logic device (referred to as a programmable device) integrated circuit software tool design technology, in particular to a wiring method and device of a programmable device, an electronic equipment and a storage medium. BACKGROUND

[0002] In the wiring module of a super large programmable device, a high fan-out user design circuit connection line generally refers to a user design connection line with only one wiring source and m wiring sinks, and the number m of wiring sinks is usually large (more than 1000).

[0003] When a wiring algorithm process needs to be performed on a high fan-out user design circuit connection line in a super large programmable device, the wiring operation is from the wiring source to the wiring sink, and when wiring is performed on a new wiring sink, a suitable intermediate node needs to be selected from the already expanded path as a new wiring source.

[0004] Most existing programmable devices do not distinguish between ordinary fan-out user design circuit connection lines and high fan-out user design circuit connection lines when selecting a suitable intermediate node, and the programmable device uses a wiring algorithm process based only on PathFinder and A* expansion to obtain the intermediate node. This wiring algorithm process based only on PathFinder and A* expansion has a slow wiring speed, a long wiring time and a poor user experience when wiring a high fan-out user design circuit connection line.

[0005] Although a small part of existing programmable devices distinguish between ordinary user design circuit connection lines and high fan-out user design circuit connection lines when selecting a suitable intermediate node, the programmable device uses a pre-wiring method to obtain the intermediate node, which is equivalent to directly designating certain wiring nodes as intermediate nodes in the high fan-out user design circuit connection line before performing the wiring algorithm process on the high fan-out user design circuit connection line, and classifying different wiring sinks into different new wiring sources. This method of obtaining the intermediate node through pre-wiring is equivalent to pre-allocating a wiring path, which makes the subsequent wiring operation less flexible, has a slow wiring speed, a long wiring time and a poor user experience. SUMMARY

[0006] The wiring method and device of the programmable device, the electronic equipment and the storage medium provided by the embodiments of the present application not only do not need to pre-allocate a wiring path, but also have a fast wiring speed, a short wiring time and a good user experience.

[0007] The technical scheme of the present application is to provide a wiring method for a programmable device, which comprises: obtaining a wired node and a to-be-wired node in a user-designed circuit connection; determining whether the to-be-wired node is a key wiring node in the user-designed circuit connection to obtain a node determination result; obtaining a reverse target node of the to-be-wired node according to the node determination result, wherein the reverse target node comprises a wiring starting point of the user-designed circuit connection and a wired node near the to-be-wired node; and reversely executing a wiring algorithm process with the to-be-wired node as a starting point and the reverse target node as a terminal point.

[0008] Preferably, before the step of obtaining the wired node and the to-be-wired node in the user-designed circuit connection, the method further comprises: determining whether the user-designed circuit connection is a high-fanout user-designed circuit connection; if not, executing a wiring algorithm process; and if yes, executing the step of obtaining the wired node and the to-be-wired node in the user-designed circuit connection.

[0009] Preferably, the step of determining whether the to-be-wired node is a key wiring node in the user-designed circuit connection to obtain a node determination result comprises: obtaining a preset timing analysis result of the user-designed circuit connection; determining whether the to-be-wired node is marked with a key node according to the preset timing analysis result; if yes, the to-be-wired node is a key wiring node; and if not, the to-be-wired node is not a key wiring node.

[0010] Preferably, the step of obtaining a reverse target node of the to-be-wired node according to the node determination result comprises: if the node determination result is yes, taking a wiring starting point in the user-designed circuit connection as the reverse target node; if the node determination result is no, determining whether there is a wired node near the to-be-wired node according to a preset diamond search algorithm process with the to-be-wired node as a center; if not, taking the wiring starting point in the user-designed circuit connection as the reverse target node; and if yes, taking the wired node as the reverse target node.

[0011] Preferably, the step of determining whether there is a wired node near the to-be-wired node according to a preset diamond search algorithm process with the to-be-wired node as a center comprises: obtaining a preset diamond algorithm threshold of the diamond search algorithm process; searching the wiring nodes from the center to the periphery according to the preset diamond algorithm threshold with the to-be-wired node as the center to obtain a plurality of wiring nodes; and determining whether the wired node exists in the plurality of wiring nodes.

[0012] Preferably, the method further comprises: marking each routing node traversed by the to-be-routed node when the to-be-routed node performs the preset diamond search algorithm as a diamond search node; marking each routing node traversed by the to-be-routed node when the to-be-routed node reversely performs the routing algorithm procedure as a routed state; marking each routing node in the diamond search node without the routed state as a discarded node; and correspondingly, the method further comprises: clearing the discarded node after the to-be-routed node reversely performs the routing algorithm procedure.

[0013] Preferably, the plurality of to-be-routed nodes share one reverse target node.

[0014] Another technical scheme of the present application provides a fast routing device of a programmable device, which comprises: a node acquisition module, configured to acquire routed nodes and to-be-routed nodes in user-designed circuit connection; a key node judgment module, configured to judge whether the to-be-routed node is a key routing node in the user-designed circuit connection, and obtain a node judgment result; a reverse target acquisition module, configured to acquire a reverse target node of the to-be-routed node according to the node judgment result, wherein the reverse target node comprises a routing starting point of the user-designed circuit connection and a routed node near the to-be-routed node; and a reverse routing module, configured to reversely execute the routing algorithm procedure with the to-be-routed node as a starting point and the reverse target node as a terminal point.

[0015] Another technical scheme of the present application provides a computer device, which comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the routing method of the programmable device.

[0016] Another technical scheme of the present application provides a computer readable storage medium, which stores a computer program, wherein the computer program is executable on a processor to implement the steps of the routing method of the programmable device.

[0017] Compared with the prior art, the present application has the following advantages:

[0018] 1、The application, when executing the algorithm process, takes the reverse target node as the intermediate node, which is the source of the user-designed circuit net or the routed node near the to-be-routed node. The source and the routed node are both known routed nodes (or called as the routed path node) in the user-designed circuit net. Therefore, the application does not need to specify some routing sources in advance before executing the algorithm process, so that the application does not need to allocate the routing path in advance, thereby making the subsequent routing operation more flexible. Meanwhile, the application takes the reverse target node as the intermediate node and reversely executes the routing algorithm process, thereby connecting the routing nodes in the user-designed circuit net together, reducing the time for executing the routing algorithm process of the high fan-out user-designed circuit net, thereby reducing the compilation time of the user design, making the routing speed faster, the routing time shorter, and improving the user experience.

[0019] 2、The application solves the problem of slow routing time caused by selecting the existing path node in the iteration process of the path search of the high fan-out user-designed circuit net (design net) using the traditional routing expansion algorithm (the routing algorithm based on the PathFinder and A* expansion). The routing algorithm complexity of the high fan-out user-designed circuit net (design net) is reduced from the default 0(n*n) to 0(n), thereby reducing the routing time of the high fan-out user-designed circuit net (design net) and improving the user experience. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the application. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0021] Figure 1 is a flowchart of the routing method of the programmable device according to the first embodiment of the application;

[0022] Figure 2 is a structural schematic diagram of the fast routing device of the programmable device according to the second embodiment of the application;

[0023] Figure 3 is a structural schematic diagram of the programmable device according to the first embodiment of the application when executing the preset diamond search algorithm;

[0024] Figure 4is a structure schematic diagram of the programmable device in the first embodiment of the present application when performing the reverse routing algorithm process;

[0025] Figure 5 is a structure schematic diagram of the path tree formed after the reverse backtracking path is integrated into the original path tree in the first embodiment of the present application;

[0026] Figure 6 is a structure schematic diagram of an electronic device of the third embodiment of the present application;

[0027] Figure 7 is a structure schematic diagram of a storage medium of the fourth embodiment of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of the present application.

[0029] The terms "first", "second", "third" in the present application are only used for description purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", "third" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise explicitly and specifically limited. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between the components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0030] When performing the routing algorithm process, the routing algorithm process is performed from the routing source to each routing sink in sequence in the high-fanout user design circuit connection in the super-large programmable device, and when performing the routing algorithm process on a new routing sink, a suitable intermediate node is selected from the already expanded path (performing the routing algorithm process) as a new routing source.

[0031] When selecting a suitable intermediate node as a new routing source, the programmable device needs to first traverse all the already routed nodes in the current user design circuit connection, and estimate the path delay to the destination (sink) in turn. Finally, it selects a suitable intermediate node as a new routing source according to the priority queue of the path delay.

[0032] The aforementioned method of obtaining intermediate nodes significantly increases the runtime of the routing algorithm. Furthermore, the time complexity of the routing algorithm for this programmable device is O(n*n), where n refers to the number of nodes extended to the path. When the number of routing endpoints, m, exceeds 10,000, for a single user-designed circuit connection, the routing time will largely be concentrated on selecting suitable intermediate nodes as new routing sources and choosing appropriate starting paths.

[0033] Figure 1 This is a schematic flowchart illustrating the wiring method of a programmable device according to a first embodiment of the present invention. It should be noted that if substantially the same result is achieved, the method of the present invention is not necessarily identical. Figure 1 The illustrated process sequence is limited. For example... Figure 1 As shown, the wiring method for this programmable device includes the following steps:

[0034] S1. Obtain the wired nodes and unwired nodes in the user-designed circuit wiring;

[0035] In this step, when routing is required for a very large-scale programmable device, since the programmable device contains both ordinary fan-out user design nets (hereinafter referred to as connection lines) and high fan-out user design nets, the programmable device can determine whether to use the methods described in steps S1 to S4 throughout the entire routing operation, or only use the methods described in steps S1 to S4 for high fan-out user design nets.

[0036] To further accelerate routing speed and improve user experience, this application, when executing the routing algorithm for user-designed circuit connections, will call different routing processes based on the fan-out behavior of the connecting lines (i.e., user-designed circuit connections):

[0037] If it is a common fan-out connection line, the general routing algorithm (A* extended routing algorithm process or PathFinder algorithm process) is still called, and if it is a high fan-out connection line, the routing process of the high fan-out line is called (i.e. steps S1-S4), which is specifically as follows: judging whether the user design circuit connection line is a high fan-out user design circuit connection line; if not, executing the routing algorithm process; if yes, executing steps S1-S4.

[0038] In actual work, the routing algorithm process of the present application is the A* extended routing algorithm process or the PathFinder algorithm process, both of which are prior art in the field and will not be described here.

[0039] In this step, the routed node is a routed node in the user design circuit connection line that has executed the routing algorithm process, and the to-be-routed node is a routed node in the user design circuit connection line that has not executed the routing algorithm process. The routed node can be fused into a path tree, which is specifically as follows:

[0040] S11, marking all routed nodes in the user design circuit connection line that have executed the routing algorithm process as having been routed;

[0041] S12, marking all to-be-routed nodes in the user design circuit connection line that have not executed the routing algorithm process as not having been routed;

[0042] S13, marking the routed nodes traversed by the to-be-routed node when the routing algorithm process is executed in reverse as having been routed;

[0043] S14, marking the extended path formed by all routed nodes marked as having been routed as a path tree;

[0044] Further, as shown in Figure 2 , the present application regards all routed nodes in the user design circuit connection line on the path tree as routed nodes. When routing, the present application further includes the following steps: judging whether there are routed nodes in the user design circuit connection line on the path tree; if yes, the routed nodes not on the path tree are to-be-routed nodes; if not, the routing algorithm process ends.

[0045] As shown in Figure 4As shown, all the functional blocks (nodes) in the user-designed circuit connection can be collectively referred to as wiring nodes, that is, the wiring end points sink1-sink5, the wiring start point source, and the nodes n1-n16 can be collectively referred to as wiring nodes, the wiring end points sink1-sink4, the wiring start point source, and the nodes n1-n9 in dark color represent wired nodes, the above wired nodes form a path node tree (that is, a wired path tree), the wiring end point sink5 and the nodes n10-n16 are to-be-wired nodes, and the wiring end point sink5 is the starting point of the reverse execution of the wiring algorithm flow, and the wiring end point sink5 also forms a path tree (that is, a reverse backtracking path tree).

[0046] The wiring scheme (steps S1-S4) described in the present application is a strategy for completely adjusting the wiring (especially the high-fanout user-designed circuit connection), all the wired nodes in the wired path tree are marked in dark color, all the to-be-wired nodes are marked in white color, and the forward expansion general wiring method (A* expansion algorithm and PathFinder algorithm) is changed into a completely reverse expansion wiring method.

[0047] Further, the to-be-wired nodes of the present application can be multiple, and the multiple to-be-wired nodes share the same reverse target node, so that even if there are many candidate points in the forward expansion, there is only one target point (reverse target node) in the reverse expansion. In this way, all the wiring end points (sinks) of the present application can sequentially find a reverse wiring path, and all the wiring end points (sinks) have only one target point, so that the present application avoids the overhead of selecting the best starting point in the wiring starting stage.

[0048] In the current wiring process of the user-designed circuit connection (design net), the already expanded path forms a path tree (that is, a wired path tree), which is completely saved in the memory during the wiring process and continues until all the wiring end points (sinks) of the current user-designed circuit connection (design net) are wired.

[0049] S2, judging whether the to-be-wired node is a key wiring node in the user-designed circuit connection, to obtain a node judgment result;

[0050] In this step, the step of obtaining the node judgment result specifically includes:

[0051] S21, obtaining a preset timing analysis result of the user-designed circuit connection;

[0052] S22, judging whether there is a key node mark on the to-be-wired node according to the preset timing analysis result;

[0053] S23, if yes, the to-be-routed node is a critical routing node; if no, the to-be-routed node is not a critical routing node.

[0054] In actual work, before starting routing, the application needs to perform timing analysis on the user design circuit connection, and after the timing analysis is completed, it can be known which routing nodes on the user design circuit connection are important and which routing nodes are unimportant. At this time, the application only needs to mark the important routing nodes as critical nodes.

[0055] S3, obtaining a reverse target node of the to-be-routed node according to the node judgment result, the reverse target node including a routing start point of the user design circuit connection and a routed node near the to-be-routed node;

[0056] In actual work, the reverse target node in this step is the intermediate node described in the background section of the application. The intermediate node is named as the reverse target node because the reverse target node needs to perform a reverse routing algorithm process (i.e., a reverse A* extended routing algorithm process and / or a PathFinder algorithm process).

[0057] In the application, since the routing start point (source) and the routed node as the reverse target node are both routed nodes in the routed path tree in step S1, the reverse target node (intermediate node) of the application is not directly specified outside the routed path tree, but is obtained in the routing algorithm process. The step of obtaining the reverse target node of the to-be-routed node includes:

[0058] S31, if the node judgment result is yes, the routing start point in the user design circuit connection is taken as the reverse target node;

[0059] S32, if the node judgment result is no, whether there is a routed node near the to-be-routed node is determined according to a preset diamond search algorithm process with the to-be-routed node as the center;

[0060] S33, if no, the routing start point in the user design circuit connection is taken as the reverse target node; if yes, the routed node is taken as the reverse target node.

[0061] In the application, for a high fan-out user design circuit connection (design net), when the timing criticality is high, all routing end points (sinks) are reversely routed to the routing start point (source) for delay estimation and extension. Each routing end point (sink) of the application is reversely routed to the routing start point (source) in the shortest path as possible, so that the timing of the application is better.

[0062] In actual work, if the timing priority level of the user-designed circuit connection net is not high, but more routing nodes are used in the application, thereby causing resource waste, the application can adjust the reverse target node of each routing sink according to the preset timing critical level.

[0063] The reverse target node of the application can be multiple, when routing is needed for a routing sink, the application can traverse multiple routing nodes (functional block tile units) near the current routing sink by the diamond search algorithm process, select the nearest routed node as the target expansion node (that is, the reverse target node) of the current routing sink expansion, which can improve the node reuse rate of routing.

[0064] As shown in Figure 3 When the preset diamond search algorithm process is executed, each grid point can represent a routing node (such as a functional block tile unit) or a combination of multiple routing nodes (functional block tiles) in a programmable device (such as an FPGA architecture). Such a search can be completed in constant time. When placing, since the multiple routing sinks will be placed as close as possible in actual work, when using approximate nearest neighbor search in four directions (that is, diamond search), the nearby routed node can be quickly found. The routed node found in this way is used as a new routing source, which can avoid excessive use of long lines to expand to the original routing source in online, and improve the overall routing node reuse rate.

[0065] As shown in Figure 3 The step of judging whether there is a routed node near the to-be-routed node includes: S321, obtaining a preset diamond algorithm threshold of the diamond search algorithm process; S322, searching the routing nodes from the center to the periphery according to the preset diamond algorithm threshold with the to-be-routed node as the center, to obtain multiple routing nodes; S323, judging whether there is a routed node in the obtained multiple routing nodes.

[0066] S4, reversely executing the routing algorithm process with the to-be-routed node as the starting point and the reverse target node as the terminal point.

[0067] In the process of routing to a specific sink, when a node in the existing path tree (i.e. a reverse target node) is encountered, the path tree formed by the specific sink (e.g. sink 5) is fused with the original path tree that has been routed into a new path tree, and the irrelevant routing nodes are discarded. The path tree formed by the specific sink (e.g. sink 5) is the reverse backtracking path tree, and the original path tree that has been routed is the path tree formed by the routed nodes (e.g. sink 1-sink 4). After reverse backtracking, the white nodes that are discarded are automatically deleted. The present application combines Figure 5 The step of fusing the reverse backtracking path into the original path tree is described as follows:

[0068] Figure 5 The structure of the path tree formed after the reverse backtracking path is fused into the original path tree in the first embodiment of the present application is shown in the structure diagram. When the reverse routing algorithm flow is executed, the present application should start from the sink 5, and when the routed node n8 on the path tree that has been routed is encountered, the path tree generated by the current sink 5 is backtracked in reverse from bottom to top (from the sink 5 to the routed node n8), and the routed nodes (n8, n12, n9, n10, sink 5) that have been passed through are marked. These paths (the paths formed by n8, n9, n10, n12, and sink 5) are fused into the above-mentioned path tree (the path tree formed by sink 1-sink 4).

[0069] In actual work, in the process of fusing the reverse backtracking path into the original path tree, other branch nodes that have not been traversed (e.g. n11, n13-n16) are automatically cleaned up in the backtracking process, as follows:

[0070] S41, the routed nodes traversed by the to-be-routed node when the preset diamond search algorithm is executed are all marked as diamond search nodes;

[0071] S42, the routed nodes traversed by the to-be-routed node when the reverse routing algorithm flow is executed are all marked as routed nodes;

[0072] S43, the routed nodes in the diamond search nodes that do not have the routed node state mark are marked as discarded nodes (e.g. the routed nodes marked by the dashed line in FIG. 6); Figure 5

[0073] S44, accordingly, after the reverse routing algorithm flow is executed, it further includes: cleaning up the discarded nodes.

[0074] In actual work, each routed node on the path tree that has been routed has a set address (id), which identifies the above-mentioned each set address as a root tree, for example Figure 5 ​The dark nodes in the figure mark the signal addresses (sink id) of the nodes (n8, n10) on the expanded tree for a specific routing end point (sink5). In the process of merging the reverse trace path into the original path tree, the required routing nodes (n9, n10) are merged into the root tree, and the node addresses (id) on the path tree expanded by sink5 are modified to the root tree. The addresses (id) of the other routing nodes (n11-n16) not traversed are still the original signal addresses (sink id), but at this time, since the routing end point sink5 has been routed, these routing nodes (n11-n16) automatically become abandoned nodes.

[0075] In actual work, when routing the next routing end point (sink6, not shown in the figure), these abandoned nodes (n13-n16) are directly used as unused normal nodes.

[0076] Figure 2 A structure diagram of a fast routing device of a programmable device according to a second embodiment of the present application is shown in FIG. 2. As shown in the figure, the fast routing device of the programmable device comprises: Figure 2

[0077] A node obtaining module 21 is configured to obtain routed nodes and to-be-routed nodes in user-designed circuit connection lines.

[0078] A key node judging module 22 is configured to judge whether the to-be-routed node is a key routing node in the user-designed circuit connection lines, to obtain a node judgment result.

[0079] A reverse target obtaining module 23 is configured to obtain a reverse target node of the to-be-routed node according to the node judgment result, the reverse target node being either a routing start point of the user-designed circuit connection lines or a routed node near the to-be-routed node.

[0080] A reverse routing module 24 is configured to execute a reverse routing algorithm process with the to-be-routed node as a starting point and the reverse target node as an end point.

[0081] In actual work, specific limitations of the fast routing device of the programmable device can refer to the limitations of the routing method of the programmable device described above, and will not be repeated here. Each module in the fast routing device of the programmable device described above can be realized by software, hardware, or a combination thereof. Each module described above can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to each module.

[0082] Figure 6 ​is a structural schematic diagram of an electronic device of a third embodiment of the present application. As shown in Figure 6 The electronic device 30 comprises a processor 31 and a memory 32 coupled with the processor 31.

[0083] The memory 32 stores program instructions for implementing the wiring method of the programmable device of any of the above embodiments.

[0084] The processor 31 is configured to execute the program instructions stored in the memory 32 to perform the fast wiring process of the programmable device.

[0085] The processor 31 can also be referred to as a CPU (Central Processing Unit). The processor 31 can be an integrated circuit chip with signal processing capability. The processor 31 can also be a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application-Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0086] Referring to Figure 7 , Figure 7 is a structural schematic diagram of a storage medium of a fourth embodiment of the present application. The storage medium 40 of the fourth embodiment of the present application stores program instructions 41 capable of implementing all the above methods. The program instructions 41 can be stored in the above storage medium in the form of a software product, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the method of each embodiment of the present application. The above storage medium includes a U disk, a mobile hard disk, a ROM (Read-Only Memory), a RAM (Random Access Memory), a magnetic disk or an optical disk, and various media capable of storing program codes, or a terminal device such as a computer, a server, a mobile phone, a tablet, etc.

[0087] In the several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only schematic. The division of the units is only a logical function division. There can be another division manner in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or in other forms.

[0088] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit. The above is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process conversion, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

[0089] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile and / or volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. Any reference to memory, storage, database or other medium used in each embodiment provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0090] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the present application is only exemplified by the above-mentioned division of each functional unit and module. In actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the above-described functions.

Claims

1. A wiring method of a programmable device, characterized by, The wiring method comprises: Obtaining a wired node and a to-be-wired node in a user-designed circuit connection; Determining whether the to-be-wired node is a key wiring node in the user-designed circuit connection to obtain a node determination result; Obtaining a reverse target node of the to-be-wired node according to the node determination result, wherein the reverse target node comprises a wiring starting point of the user-designed circuit connection and a wired node near the to-be-wired node; Reversely executing a wiring algorithm process with the to-be-wired node as a starting point and the reverse target node as an ending point.

2. The wiring method of a programmable device according to claim 1, wherein, Before the step of obtaining the wired node and the to-be-wired node in the user-designed circuit connection, the method further comprises: Determining whether the user-designed circuit connection is a high-fanout user-designed circuit connection; If not, a wiring algorithm process is executed; If yes, the step of obtaining the wired node and the to-be-wired node in the user-designed circuit connection is executed.

3. The wiring method of a programmable device according to claim 2, wherein, The step of determining whether the to-be-wired node is a key wiring node in the user-designed circuit connection to obtain a node determination result comprises: Obtaining a preset timing analysis result of the user-designed circuit connection; Determining whether the to-be-wired node is marked with a key node according to the preset timing analysis result; If yes, the to-be-wired node is a key wiring node; if not, the to-be-wired node is not a key wiring node.

4. The wiring method of a programmable device according to claim 1 or 2 or 3, characterized by, The step of obtaining a reverse target node of the to-be-wired node according to the node determination result comprises: If the node determination result is yes, a wiring starting point in the user-designed circuit connection is taken as the reverse target node; If the node determination result is no, it is determined whether there is a wired node near the to-be-wired node according to a preset diamond search algorithm process with the to-be-wired node as a center; If no, a wiring starting point in the user-designed circuit connection is taken as the reverse target node; If yes, the wired node is taken as the reverse target node.

5. The wiring method of a programmable device according to claim 4, wherein, The step of determining whether there is a wired node near the to-be-wired node according to a preset diamond search algorithm process with the to-be-wired node as a center comprises: Obtaining a preset diamond algorithm threshold of the diamond search algorithm process; Searching the wiring nodes from the center to the periphery according to the preset diamond algorithm threshold with the to-be-wired node as the center to obtain a plurality of wiring nodes; Determining whether there is the wired node in the plurality of wiring nodes.

6. The wiring method of a programmable device according to claim 5, wherein, The method further comprises: Marking all the wiring nodes traversed by the to-be-wired node when the preset diamond search algorithm is executed as diamond search nodes; Marking all the wiring nodes traversed by the to-be-wired node when the wiring algorithm process is reversely executed as wired states; Marking the wiring nodes in the diamond search nodes without the wired state mark as abandoned nodes; Correspondingly, the method further comprises: Clearing the abandoned nodes after the wiring algorithm process is reversely executed.

7. The wiring method of a programmable device according to claim 6, wherein, All the to-be-wired nodes are multiple, and the multiple to-be-wired nodes share one reverse target node.

8. A wiring device for a programmable device, characterized by, The method comprises: A node obtaining module is configured to obtain a wired node and a to-be-wired node in a user-designed circuit connection; A key node judging module is configured to judge whether the to-be-routed node is a key routing node in the user-designed circuit connection, and obtain a node judging result. A reverse target obtaining module is configured to obtain a reverse target node of the to-be-routed node according to the node judging result, wherein the reverse target node includes a routing starting point of the user-designed circuit connection and a routed node near the to-be-routed node. A reverse routing module is configured to execute a reverse routing algorithm process with the to-be-routed node as a starting point and the reverse target node as a terminal point.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the routing method of the programmable device according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, the computer program comprising instructions that, when executed by a computer, cause the computer to perform the method of any one of claims 1 to 9. The computer program is executed by the processor to implement the steps of the routing method of the programmable device according to any one of claims 1 to 7.

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