Memory device and method for determining memory system read voltage

Abstract

The present disclosure provides a method, device and system for determining a read voltage of a memory system. In one aspect of the present disclosure, a memory device includes a memory cell array, an accumulation circuit and a controller. Each memory cell is coupled to a corresponding word line among a plurality of word lines and a corresponding bit line among a plurality of bit lines. The accumulation circuit is configured to accumulate read signals of a plurality of memory cells in a page to generate an output value of each accumulated read signal corresponding to the read voltage when data stored in a page is read by applying a respective read voltage among a plurality of read voltages to a bit line corresponding to the page. The controller is configured to determine a calibrated read voltage of the page based on the read voltages and the respective output values ​​associated with the read voltages.

Description

Technical Field

[0001] The present disclosure describes a system and method for determining a read voltage of a memory system, such as a three-dimensional non-volatile memory (NVM) system, and particularly a system having an on-chip analog-to-digital converter (ADC) circuit, which can quickly and efficiently determine a calibrated read voltage for reading memory data, thereby improving the performance of the memory system. Background Art

[0002] When a data storage device, such as memory cells in a memory system, is programmed, data is read from the memory cells by comparing the cell threshold voltage to one or more read voltages to sense the programming state of each memory cell. However, the cell threshold voltage may change due to one or more factors, such as read disturbance or data retention, which may cause the sensed programming state to be different from the written programming state, resulting in a bit failure in the data read output. Some existing systems and technologies use the same verify read voltage regardless of changes in the cell threshold voltage.

[0003] One technique for compensating for cell threshold voltage changes involves storing a lookup table with preset read voltages and priorities. If the error correction technique fails, the system will re-read at a different read voltage according to the priorities set in the lookup table. Another technique is to use a voltage calibration technique where the number of bits (or memory cells) that are turned on are counted at successive voltages to find a "valley," i.e., the voltage with the smallest change in the bit count.

[0004] Public Content

[0005] One aspect of the present disclosure is characterized in that a memory device includes: a memory cell array, each memory cell is coupled to a corresponding word line among a plurality of word lines, and a corresponding bit line among a plurality of bit lines; an accumulation circuit is coupled to the memory cell array and is configured to: when data stored in a page is read by applying each of a plurality of read voltages to a bit line corresponding to the page, accumulate the read signals of each of the memory cells in the page to generate an output value of each accumulated read signal corresponding to the read voltage; and a controller is coupled to the accumulation circuit and is configured to determine a calibrated read voltage for the page based on the read voltage and the output value related to the read voltage.

[0006] In some embodiments, the accumulation circuit includes an analog-to-digital converter configured to convert the accumulated read signal into an output value.

[0007] In some embodiments, the readout signal includes at least a current or a voltage.

[0008] In some embodiments, at least one accumulation circuit or controller is configured to record respective output values.

[0009] In some embodiments, a memory device includes a control circuit coupled to a memory cell array. The control circuit can be configured to apply a read voltage to a word line in a manner that a read voltage is applied continuously over a sequence of read voltage values.

[0010] In some embodiments, the controller and the accumulation circuit may be implemented in an integrated circuit.

[0011] In some embodiments, the control circuit is configured to iteratively increase or decrease the read voltage. A first amount between first adjacent read voltage values ​​may be different from a second amount between second adjacent read voltage values. The first amount between first adjacent read voltage values ​​may be the same as the second amount between second adjacent read voltage values.

[0012] In some embodiments, the control circuit is configured to: determine whether a read voltage having a first read voltage value is lower than a threshold voltage; in response to determining that the read voltage having the first read voltage value is not greater than the threshold voltage, increase or decrease the read voltage to have a second read voltage value to apply the second read voltage value to a subsequent read operation on the page; and in response to determining that the read voltage having the first read voltage value is lower than the threshold voltage, start the controller to determine a calibration read voltage for the page.

[0013] In some embodiments, the controller is configured to: for at least two read voltage values ​​in the read voltage sequence, determine a difference between an output value of each read voltage in the read voltage sequence and a second read voltage value immediately preceding the read voltage value, thereby providing a difference sequence.

[0014] In some embodiments, the controller is configured to identify a specific read voltage value from at least two read voltage values, the specific read voltage value providing a minimum difference in the difference sequence; and set the calibration read voltage to have the specific read voltage value, and determine the calibration read voltage based on the difference sequence and the read voltage.

[0015] In some embodiments, the controller is configured to: for at least two read voltage values ​​in a read voltage sequence, determine a second difference between the output value of each read voltage in the read voltage value sequence and a second read voltage value immediately preceding the read voltage value, thereby providing a second difference sequence; and determine a calibration voltage value using the second difference sequence and the read voltage.

[0016] In some embodiments, the controller is configured to identify a specific read voltage value from at least one read voltage value, the specific read voltage value providing a minimum difference in the second difference sequence; and set the calibration read voltage to have the specific read voltage value, and determine the calibration read voltage using the second difference sequence and the read voltage.

[0017] In some embodiments, the control circuit is configured to: iteratively change the read voltage from an initial voltage value to a first read voltage value in a first direction, the first direction being one of an increasing direction and a decreasing direction; determine that a difference between a first output value of the first read voltage value and a second output value of a second read voltage value immediately before the first read voltage value is less than a first threshold value; and determine that a first calibration read voltage having the first read voltage value. A difference between a second output value of the second read voltage value and a third output value of a third read voltage value immediately before the second read voltage value may be greater than the first threshold value.

[0018] In some embodiments, the control circuit is configured to: iteratively change the read voltage from an initial voltage value to a third read voltage value in a second direction, the second direction being one of an increasing direction and a decreasing direction; determine that the difference between a third output value of the third read voltage value and a fourth output value of a fourth read voltage value immediately before the third voltage value is less than a second threshold; and determine a second calibrated read voltage having the third read voltage value, wherein the calibrated read voltage is determined based on the first calibrated read voltage and the second calibrated read voltage.

[0019] In some embodiments, a difference between a fourth output value of the fourth read voltage value and a fifth output value of the fifth read voltage value immediately before the fourth read voltage value may be greater than the second threshold.

[0020] In some embodiments, the calibration read voltage is determined to have the following expression:

[0021] V=β(XY)+Y

[0022] Wherein V, X and Y represent the calibration read voltage, the first calibration read voltage and the second calibration read voltage respectively, and β is a constant between the interval [0, 1].

[0023] In some embodiments, the control circuit is configured to: iteratively change the read voltage from an initial voltage value to a third read voltage value in a second direction, the second direction being one of an increasing direction and a decreasing direction; determine a first difference between a third output value of the third read voltage and a fourth output value of a fourth read voltage value immediately before the third voltage value; determine a second difference between an output value of the fourth read voltage value and a fifth output value of a fifth read voltage value immediately before the fourth read voltage value; determine that a difference between the first difference and the second difference is less than a second threshold; and determine a second calibrated read voltage having a second read voltage value; wherein the calibrated read voltage is determined based on the first calibrated read voltage and the second calibrated read voltage.

[0024] In some embodiments, the calibration read voltage is determined to have the following expression:

[0025] V=β(XY)+Y

[0026] Wherein V, X and Y represent the calibration read voltage, the first calibration read voltage and the second calibration read voltage respectively, and β is a constant between the interval [0, 1].

[0027] In some embodiments, the calibration read voltage is a preset value as an initial value in the read voltage value sequence.

[0028] Another aspect of the present disclosure is characterized in that a memory device includes: a memory array including pages of multiple memory cells coupled to multiple corresponding word lines; an analog-to-digital converter circuit coupled to the memory array and configured to: when data stored in a page is read by applying a respective read voltage among a plurality of read voltages to a bit line corresponding to the page, accumulate read signals of each memory cell in the page to generate an output value of each accumulated read signal corresponding to the read voltage; and a controller coupled to the accumulation circuit and configured to determine a calibrated read voltage for the page based on the read voltage and the output value related to the read voltage.

[0029] In some embodiments, the analog-to-digital converter circuit includes a controller.

[0030] In some embodiments, a memory device includes a control circuit coupled to a memory array and configured to apply a read voltage to a word line in a manner that continuously applies a read voltage over a sequence of read voltage values.

[0031] Another aspect of the present disclosure features a method comprising: applying a plurality of read voltages to word lines of a page of memory cells of a memory device; for each of the read voltages, accumulating read signals of a plurality of memory cells in the page to generate an output value of each of the accumulated read signals corresponding to the read voltage; and determining a calibrated read voltage for the page based on the read voltages and the output value associated with the read voltages.

[0032] In some embodiments, determining a calibrated read voltage of a page includes: for at least two read voltages in the read voltages, determining a difference between an output value of each read voltage in a read voltage value sequence and a second read voltage value immediately preceding the read voltage value, thereby providing a difference sequence; and determining a calibration voltage value using a difference sequence and the read voltages.

[0033] In some embodiments, the step of determining the calibration voltage value using a second difference sequence and a read voltage includes: for at least two read voltage values ​​in the read voltage sequence, determining a second difference between an output value of each read voltage in the read voltage value sequence and a second read voltage value immediately preceding the read voltage value, thereby providing a second difference sequence; and determining the calibration voltage value using the second difference sequence and the read voltage.

[0034] The technology in the above embodiments includes methods, systems, computer program products, and computer-readable media. In one example, a method can be executed by a memory, and the method can include the steps performed by the memory described above, such as: the step of determining the non-volatile memory read voltage. In another example, such a computer program product is appropriately embodied in a non-transitory machine-readable medium of instructions executable by one or more processors. The instructions are configured to cause one or more processors to perform the steps described above. Such a computer-readable medium stores instructions, which, when executed by one or more processors, are configured to cause one or more processors to perform the above steps.

[0035] The details of one or more disclosed embodiments are described in the accompanying drawings and the following detailed description. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1A is a schematic diagram of an example system according to one or more embodiments of the present disclosure.

[0037] Figure 1B FIG. 1 is a block diagram of an exemplary memory including an analog-to-digital converter circuit according to one or more embodiments of the present disclosure.

[0038] Figure 1CFIG. 4 is a schematic diagram of an example block of a 2D memory according to one or more embodiments of the present disclosure.

[0039] Figure 1D FIG. 4 is a schematic diagram of an example block of a 3D memory according to one or more embodiments of the present disclosure.

[0040] Figure 2A FIG. 4 is a diagram showing an example of threshold voltage distribution of a multi-level cell (MLC) in different states according to one or more embodiments of the present disclosure.

[0041] Figure 2B FIG. 4 is a diagram showing the relationship between the read output of the counting unit and the read voltage under different program / erase cycles in the present disclosure.

[0042] Figure 3 FIG. 1 is an exemplary diagram of a memory having an analog-to-digital converter determining a memory read voltage according to one or more embodiments of the present disclosure.

[0043] Figure 4 FIG. 1 is an exemplary diagram of combining memory cells with different states in adjacent word lines to represent a new state according to one or more embodiments of the present disclosure.

[0044] Figure 5 The flowchart is a method for determining a read voltage using a valley-tracking diagram using an analog-to-digital converter according to one or more embodiments of the present disclosure.

[0045] Figure 6 The flowchart is another method for determining a read voltage using a valley-tracking diagram with an analog-to-digital converter according to one or more embodiments of the present disclosure.

[0046] Description of Reference Numerals

[0047] 100: System

[0048] 110: Installation

[0049] 112: Device controller

[0050] 113: Processor

[0051] 114: Internal memory

[0052] 116: Memory

[0053] 117: Controller

[0054] 118: Analog-to-digital converter circuit

[0055] 120: Host device

[0056] 130: Memory interface

[0057] 132: Control Logic

[0058] 134: Data buffer

[0059] 140: Error correction code circuit

[0060] 140c: Two-dimensional storage block

[0061] 141, 157: Storage unit

[0062] 142: Encoder

[0063] 142c,152: Unit page

[0064] 143: String selection transistor

[0065] 144: Decoder

[0066] 144c,154: cell string

[0067] 145: Ground selection transistor

[0068] 146,156: string selection line

[0069] 148,158: Ground selection line

[0070] 149,159: Common source line

[0071] 150,410: Memory cell array

[0072] 152: Unit Page

[0073] 160: Sense Amplifier

[0074] 200,250,300,(a)320,(b)340,(c)360,(d)380,400: Chart

[0075] 202,204,206,208,322,324,342,344,350,361,382,384: Curve

[0076] 203: Dashed curve

[0077] 326,346: Line segment

[0078] 362: First positive slope section

[0079] 366: Second positive slope section

[0080] 364: Plane part

[0081] 370: Part

[0082] 402,WL: word line

[0083] 404, BL: bit line

[0084] 500,600: Flowchart

[0085] 502,504,506,508,602,604,606,608,610,612,614,616,618,620: Steps

[0086] A, B, C: Programming status

[0087] BL0, BL1, ..., BL n-1 BL n : Field line

[0088] CSL: Common Source Line

[0089] ER: Erase state

[0090] GSL: Ground Select Line

[0091] GST: Ground Select Transistor

[0092] HVT Initia1 , LVT Initial : Initial threshold voltage distribution

[0093] HVT Retentio , LVT Retention : Threshold voltage distribution

[0094] I sum : Digital current value

[0095] I i ,I i-1 : Analog-to-digital converter output

[0096] LSB: Least Significant Bit

[0097] MSB: Most Significant Bit

[0098] PE0, PE3k, PE5k, PE10k, PE15k, PE20k: Data chart

[0099] SSL: String Select Line:

[0100] SST: String Select Transistor

[0101] V Disturb , V Rd1 , V Rd2 , V Rd3 , V Rdpass,V WLi-1 ,V WLi ,V WLj : Read voltage

[0102] V l0 ,V h0 , V l1 , V h1 , V l2 , V h2 , V 13 , V h3 , : threshold voltage

[0103] V h0’ : Limit voltage

[0104] V PASS : High voltage

[0105] WL0, WL1, ...WL n-1 , WL n :Line

[0106] X: First calibration voltage

[0107] Y: Second calibration voltage

[0108] β: numerical value

[0109] Δ1, Δ2, ..., Δ i-1 , Δ j-1 , Δ j-2 : Voltage interval

[0110] Δ th1 : First threshold voltage

[0111] Δ th2 : Second threshold voltage DETAILED DESCRIPTION

[0112] Due to frequent read and write operations, the memory may experience read disturbance, in which the state of a memory cell, such as an erased state and one or more written states in the memory, may increase or decrease the threshold voltage. Read disturbance may cause a failed bit (or error bit) when reading. The error-correcting code (ECC) decoder can be configured to decode the data read from the memory to detect and debug errors under the error correction capability of the error correction code scheme. The data can be detected by comparing the cell threshold voltage and the read voltage (or reference read voltage) to read the data of the memory cell.

[0113] A major challenge of 3D memory systems such as 3D NAND flash memory is to reduce bit errors and increase read performance. However, the threshold voltage V t The distribution is affected by various conditions, such as layer variation, write / erase times, temperature, retention time, and page address, resulting in the inability to fix the optimal read voltage. The optimal read voltage means obtaining the minimum variation when applying the read voltage, such as the minimum number of error bits.

[0114] In some conventional techniques, a preset read voltage is used to read the data of the memory regardless of the change of the input parameters. However, the preset read voltage may be different from the optimal read voltage, resulting in an additional overhead when decoding the error correction code.

[0115] In another conventional technique, a lookup table storing a plurality of preset read voltages is used, and the preset read voltages are used in a fixed order according to the relative priorities that are independent of the input parameters. The data is first read with the first preset voltage having the highest priority, and if the read output data fails the error correction code test, the second preset voltage having the second highest priority is used. The retry read operation continues until the read output passes the error correction code test. However, the establishment of the lookup table may consume a lot of human resources and R&D time, and engineers may need to fine-tune the optimal read voltage one by one according to the input parameters. The size of the table may become larger and larger due to different process technologies and different operating conditions.

[0116] Machine learning (ML) technology has been proposed to determine the optimal read voltage. For example, offline inference of machine learning can be used to determine the relationship between input parameters and optimal read parameters. However, in order to achieve high accuracy, such offline inference may cause a large amount of memory burden. Online inference may require additional calculation and time burden to reduce read latency.

[0117] Valley search has also been proposed for determining the optimal read voltage. In the valley search technique, bits are counted at successively different voltages and the change in the bit count caused by the change in the read voltage is observed. The voltage with the smallest change in the bit count may correspond to the lowest point of the valley and may provide the optimal read voltage. However, bit counting implemented by hardware circuits takes a long time.

[0118] In general, determining the optimal read voltage is time-consuming and lengthy, and as the number of input parameters considered in the process increases, the calculation time and power consumption may increase. Therefore, it is necessary to develop a technology that can accurately read with a limited read delay time in a time-varying channel and can reduce the burden of the error correction code through the optimal read voltage.

[0119] Embodiments of the present disclosure provide a system, method, and technique for determining a read voltage (e.g., a calibrated read voltage) of a memory system (e.g., a non-volatile memory system). The technique can calibrate (or optimize) the read voltage through an analog-to-digital converter circuit and a valley search method of a memory chip to minimize the number of error bits, thereby reducing the error correction code decoding burden, reducing the additional memory burden, reducing read latency, reducing R&D costs, and improving read accuracy. The term "calibrated read voltage" herein refers to a read voltage calibrated using a valley search method of a memory chip through an analog-to-digital converter circuit. The calibrated read voltage can be an optimal read voltage corresponding to a minimum change, such as a minimum value or a minimum number of error bits.

[0120] In some embodiments, an analog-to-digital converter circuit is implemented in a memory, and the analog-to-digital converter includes an accumulation circuit configured to accumulate a plurality of bits of current to obtain a sum of the currents during a read operation. The accumulation circuit may include an analog-to-digital converter configured to convert an analog signal of the current sum to a digital value. The analog-to-digital converter circuit can achieve a faster counting time, for example, during a valley search, to determine a calibrated read voltage (or an optimized read voltage).

[0121] In some embodiments, the memory stores a predetermined read voltage, for example, determined by the memory manufacturer based on empirical data. The controller may be implemented in the analog-to-digital converter circuit itself or external to the analog-to-digital converter. The predetermined read voltage may be calibrated to be a calibrated read voltage (or optimal read voltage) for a particular page or block, for example, starting with the predetermined read voltage and applying different read voltages successively as part of a valley search. For each test voltage, the analog-to-digital converter circuit accumulates the currents of the word lines corresponding to a plurality of memory cells on the page, obtains the sum of the currents, and converts the sum into a digital value. The controller may compare the output values ​​of the consecutive different read voltages, and determine the calibrated read voltage using the plurality of digital values ​​and the different read voltages. In particular, the read voltage that provides the smallest change in bit count may correspond to the bottom of the valley and may provide the optimal or calibrated read voltage. To improve accuracy, the controller may also compare the first difference between adjacent read voltage digital values ​​or even the second difference between adjacent first differences to determine the bottom of the valley.

[0122] In some embodiments, in addition to operating in current mode, such as accumulating the current of multiple bits in a read operation, the ADC can also be configured to operate in voltage mode, such as accumulating the voltage of multiple bits in a read operation, or a hybrid mode including both current mode and voltage mode.

[0123] Conventional memory devices or systems do not include such analog-to-digital converter circuits or use analog-to-digital conversion circuits in such a manner. Using an analog-to-digital converter circuit can accumulate current and output a digital value to accelerate fast bit counting and reduce bit counting operations with higher energy efficiency and read time. Implementing an analog-to-digital converter in a memory can also allow for the reduction of erroneous bits to achieve higher accuracy and reduce the decoding burden of error correction codes.

[0124] The technology can be applied to a variety of different volatile memories or non-volatile memories, such as NAND flash memory, NOR flash memory, resistive random-access memory (RRAM), phase-change memory (PCM) such as phase-change random-access memory (PCRAM), spin-transfer torque (STT) magnetoresistive random-access memory (MRAM), etc. The technology can also be applied to charge-trapping memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate memory devices. The technology can be applied to two-dimensional memory devices or three-dimensional memory devices. The technology can be applied to various types of memory, such as single-level cell (SLC), multi-level cell (e.g., 2-level cell devices), triple-level cell (TLC), quad-level cell (QLC), or penta-level cell (PLC). Or or even more, the technology can be applied to different types of devices or systems, such as secure digital cards (SD), embedded multimedia cards (eMMC), or solid-state drives (SSD), embedded systems, etc.

[0125] Figure 1A An exemplary system 100 is shown, which includes a device 110 and a host device 120. The device 110 includes a device controller 112 and a memory 116. The device controller 112 includes a processor 113 and an internal memory 114.

[0126] In some embodiments, the device 110 is a storage device. For example, the device 110 can be an embedded multimedia card (eMMC), a secure digital card (SD), a solid state drive (SSD), or other suitable storage methods. In some embodiments, the device 110 is a smart watch, a digital camera, or a media player. In some embodiments, the device 110 is a client device coupled to the host device 120. For example, the device 110 is an SD card in a digital camera or a media player as the host device 120.

[0127] Device controller 112 is a general purpose microprocessor or a special application microprocessor. In some embodiments, device controller 112 is a memory controller of device 110. The following paragraphs describe various techniques based on an embodiment in which device controller 112 is a memory controller. However, the techniques described in the following paragraphs can also be applied to embodiments in which device controller 112 is another controller other than a memory controller.

[0128] The processor 113 is configured to execute instructions and process data, the instructions including framework instructions and / or other programming instructions stored in the second memory in framework code and / or other programming code. The data includes appropriate data such as programming data corresponding to the framework and / or other programming executed by the processor 113. In some embodiments, the processor 113 is a general-purpose processor or a special application processor. The processor 113 can also be a central processing unit (CPU).

[0129] The processor 113 accesses instructions or data in the internal memory 114. In some embodiments, the internal memory 114 is a static random access memory (SRAM) or a dynamic random access memory (DRAM). For example, in some embodiments, when the device 110 is an embedded multimedia card, an SD card or a smart watch, the internal memory 114 is a static random access memory. In some embodiments, when the device 110 is a digital camera or a multimedia player, the internal memory 114 is a dynamic random access memory.

[0130] In some embodiments, the internal memory is a cache memory included in the memory controller 112, such as Figure 1A As shown, the internal memory 114 stores instruction codes corresponding to instructions executed by the processor 113 and / or data required by the processor 113 during operation.

[0131] The device controller 112 transmits the instruction code and / or data from the memory 116 to the internal memory 114. In some embodiments, the memory 116 is a non-volatile memory configured to store instructions and / or data for a long time, such as a NAND flash memory or other suitable non-volatile memory device. In the embodiment where the memory 116 is a NAND flash memory, the device 110 is a flash memory device, such as a flash memory card, and the flash memory 112 is a NAND flash memory controller. For example, in some embodiments, when the device 110 is an embedded multimedia card or an SD card, the memory device 116 is a NAND flash memory; in some embodiments, when the device 110 is a digital camera, the memory 116 is an SD card; and in some embodiments, when the device 110 is a media player, the memory 116 is a hard disk.

[0132] In some embodiments, the device controller 112 is configured to transmit data and instructions to or from the host device 120, and the device controller 112 is further configured to transmit data to and receive data from the memory 116. For example, the device controller 112 is configured to transmit data and a write command to instruct the memory 116 to store data at a specific address. In another example, the device controller 112 is configured to receive a read request (or a read instruction) from the host device 120, and transmit a corresponding read instruction to the memory 116 to read data at a specific address in the memory 116.

[0133] In some embodiments, the device controller 112 includes an ECC circuit 140, which may include an ECC encoder 142 and an ECC decoder 144. The ECC encoder 142 may be configured to receive data to be stored in the memory 116 and generate a codeword, such as encoding the data using an ECC encoding method. The ECC encoder 112 may include a Reed Solomon encoder, a Bose-Chaudhuri-Hocquenghem encoder, a low-density parity check encoder (LDPC encoder), a Turbo Code encoder, or any combination thereof. The ECC decoder 144 may be configured to decode the data read from the memory to detect and debug errors under the error correction capability of the ECC scheme. In some embodiments, the ECC circuit 140 is included in the memory 116. In some embodiments, the device controller 112 includes a first ECC circuit 140 , and the memory 116 includes a second ECC circuit 140 .

[0134] As discussed in further detail below, the device 110 is configured to determine a read voltage for reading data from the memory 116, for example, in response to a read request from the host device 120. The analog-to-digital converter circuit 118 may be integrated into the memory 116, for example, during the production of the memory 116. The result of the analog-to-digital converter 118 may be used to read data from the memory 116. In some embodiments, the analog-to-digital converter circuit 118 may also be integrated into the device controller 112, and the analog-to-digital converter circuit 118 may include an accumulation circuit, and the accumulation circuit may include an analog-to-digital converter. The memory 116 may also include a controller 117 coupled to the analog-to-digital converter circuit and configured to determine the read voltage based on the output of the analog-to-digital converter circuit 118.

[0135] Figure 1B An exemplary configuration of a memory 116 having a memory cell array 150 is shown. The memory cell may include a memory transistor configured as a storage element, and the memory transistor may include a silicon-oxide-nitride-oxide-silicon (SONOS) transistor, a floating gate transistor, a nitride read only memory (NROM) transistor, or any suitable non-volatile memory metal oxide device capable of storing charge. The memory 116 may include an X-direction decoder (or row decoder) and a Y-direction decoder (or column decoder), and each memory cell may be coupled to the X-direction decoder via a respective word line, and coupled to the Y-direction decoder via a respective bit line. Therefore, each memory cell may be selected by the X-direction decoder and the Y-direction decoder via a respective word line and bit line for reading or writing.

[0136] The memory 116 includes a memory interface (input / output port) 130 configured to communicate with the device controller 112. The memory 116 may also include a control logic (or control circuit) 132 coupled to the memory interface 130 and the memory array 150, and configured to control the operation of the memory 116. For example, the control logic 132 may receive a read command from the device controller 112 via the memory interface 130, and read the corresponding data in the memory array. The memory 116 also includes a sense amplifier 160 connected to the Y-direction resolver via a data line, and a data buffer 134 for buffering the output signal from the sense amplifier 160 to the memory interface 130.

[0137] During a write operation, the data register registers input data from the memory interface 130, and the address generator generates a corresponding physical address to store the input data in a specific memory cell in the memory array 150. The address generator is connected to the X-direction decoder and the Y-direction decoder, and the X-direction decoder and the Y-direction decoder are controlled by corresponding word lines and bit lines to select a specified memory cell. The static memory buffer can retain the input data from the data register in its memory when power is supplied. The control logic 132 processes the write signal from the static memory buffer and provides a control signal to a voltage generator that generates a write voltage, and provides the write voltage to the X-direction decoder and the Y-direction decoder. The Y-direction decoder is configured to output a write voltage to a bit line to store the write data to a specific memory cell.

[0138] During a read operation, the control logic 132 provides control signals to the voltage generator and the sense amplifier 160. The voltage generator provides voltages to the X-direction decoder and the Y-direction decoder for selecting a memory cell. The sense amplifier 160 senses a low-power (voltage or current) signal from the bit line representing the data bit (0 or 1) stored in the selected memory cell and amplifies the oscillation of the low-power signal to a recognizable logic level so that the data bit can be properly interpreted by logic outside the memory 116. The data buffer 134 receives the amplified voltage from the sense amplifier 160 and outputs the amplified power signal to the device controller 112 through the memory interface 130.

[0139] In some embodiments, Figure 1B As shown, the memory 116 includes an analog-to-digital converter circuit 118 connected to the memory array 150. The analog-to-digital converter 118 can be coupled to a control logic, such as a controller 117. As discussed in further detail below, the controller 117 can be configured to determine a calibration (or optimal) read voltage during a read operation using the output of the analog-to-digital converter circuit 118. For example, the controller 117 can perform a valley search on the output of the analog-to-digital converter, such as a digital value corresponding to the accumulated current of a plurality of memory cells, at different read voltages to determine the calibration read voltage. The control logic 132 can then provide a control signal to a voltage generator to generate a calibration read voltage. The voltage generator can provide the calibration read voltage to an X-direction decoder and a Y-direction decoder for selecting a memory cell to read data through the sense amplifier 160. The read data can be sent from the memory 116 to the error correction code decoder 144 through the memory interface 130 for decoding and debugging.

[0140] In some embodiments, the controller 117 may be included in the analog-to-digital converter circuit 118. The analog-to-digital converter circuit 118 may determine the calibration read voltage and provide information of the calibration read voltage to the control logic 132 for generating the calibration read voltage. The controller may be a separate component in the memory 116 or distributed among multiple components shown and / or not shown.

[0141] In some embodiments, the memory 116 performs a first read operation by applying a first read voltage to one or more target memory cells of the memory array 150, senses a first output of the first read operation of the analog-to-digital converter circuit 118, and records the first output. The memory 116 performs a second read operation by applying the first read voltage to one or more target memory cells of the memory array 150, senses a second output of the second read operation of the analog-to-digital converter circuit 118, and records the second output. A difference between the first read voltage and the second read voltage may be determined, and in response to the difference between the first output and the second output being substantially equal to zero, the memory 116, such as the analog-to-digital converter circuit 118 or the controller 117, may output the second read voltage as a calibration read voltage.

[0142] Figure 1CAn exemplary configuration of a two-dimensional memory block 140 is shown when the memory 116 is a two-dimensional memory, the block 140 includes memory cells 141 coupled to a series of field lines BL0, BL1, ..., BLn-1 and BLn to form a plurality of cell strings 144, and a series of row word lines WL0, WL1, ..., WLn-1 and WLn to form a plurality of cell pages 142. The cell string 144 may include a plurality of memory cells 141, a string select transistor (SST) 143 and a ground select transistor (GST), which are coupled in series. The gate of the string select transistor 143 is coupled to a string select line (SSL) 146, and the gates of the string select transistors in different string select lines are also coupled to the same string select line. The gates of the memory cells 141 are respectively coupled to word lines WL0, WL1, ..., WLn-1, WLn, and the memory cells 141 are coupled to a common source line (CSL) 149 through a ground selection transistor. The ground selection transistor 145 is coupled to a ground selection line (GSL) 148, and the gates of the ground selection transistors in different strings are also coupled to the same ground selection line. The cell page 142 may include a plurality of memory cells 141. The memory cells 141 in the cell page 142 are coupled in series to corresponding word lines. When an input voltage is applied to the word line, the input voltage is also applied to the gates of the memory cells 141 in the cell page 142. In order to read a specific cell page 142 in the block 140 in a read operation, a lower voltage is applied to the word line corresponding to the specific cell page 142, while a higher voltage is applied to other cell pages in the block 140.

[0143] The device 110 may include a flash translation layer (FTL) to manage read, write, and erase operations. The flash translation layer may be stored in the device controller 112, for example, in the internal memory 114. The flash translation layer uses a logical-to-physical address mapping table to store physical pages in physical blocks mapped to logical pages in logical blocks.

[0144] Figure 1D The example of a three-dimensional memory block 150 when the memory 116 is a three-dimensional memory is shown. The memory cells 157 are arranged in a three-dimensional manner, such as a rectangular coordinate system (XYZ coordinate system), and are coupled to a plurality of word lines to form a plurality of cell pages 152, and are coupled to a plurality of bit lines BL<n>BL<n+1> The cell strings 154 are combined into a plurality of cell strings. The cell string 154 includes a plurality of memory cells 157 coupled in series, wherein a memory cell may be configured as a string selection transistor (SST) coupled to a string selection line (SSL) 156, and a memory cell may be configured as a ground selection transistor (GST) coupled to a ground selection line (GSL) 158. The memory cell 157 is coupled to a common source line (CSL) 159 through the ground selection transistor (GST).

[0145] The memory block 150 may include a plurality of memory layers stacked together, for example, each memory layer may be a two-dimensional plane layer vertically along the Z-axis direction, for example, an XY plane including a plurality of cell pages 152, each cell page 152 can be read and / or programmed individually. In order to read a specific cell page 152 in the memory layer 160 during a read operation, a lower voltage is applied to the word line corresponding to the specific page cell 152, and a lower voltage is also applied to other cell pages 152 in the memory layer, while a higher voltage is applied to other memory layers in the block 150.

[0146] The memory cell can be in a programmed state or an erased state. For example, if the memory cell is a single-level cell (SLC), the memory cell can be programmed to a programmed state of "0" or an erased state of "1". If the memory cell is a multi-level cell (MLC) capable of storing two bits of data, the memory cell can be programmed to one of the programmed states (0, 1), (0, 0), (1, 0), or erased to an erased state of (1, 1).

[0147] Once programmed or erased, the memory cell has a corresponding threshold voltage, which is a characteristic of the memory cell. When a read voltage equal to or greater than the threshold voltage is applied to the gate of the memory cell, the memory cell can be turned on. When a read voltage lower than the threshold voltage is applied to the gate of the memory cell, the memory cell can be turned off. The read action is not a programming or erasing action, nor is it intended to change the state of the memory cell.

[0148] The threshold voltages of multiple memory cells in a block corresponding to the same state, such as an erased state or a programmed state, may have a distribution, such as a range between a lower limit voltage and a higher limit voltage. Memory cells having threshold voltages within the range are considered to be in the corresponding state, in other words, memory cells in the state have threshold voltages within the range.

[0149] Figure 2A A graph 200 is shown showing the distribution of threshold voltages and read voltages of memory cells in different states. The memory cells may be Figure 1C The storage unit 141 in or Figure 1D 157 in the memory cell. The memory cell may be a NAND flash memory. For illustration purposes only, the memory cell is a multi-level cell that can store two bits of data, and the memory cell can be programmed or erased to have one of four states ER, A, B, and C. In some examples, ER is an erased state (1, 1), and A, B, C are programmed states (0, 1), (0, 0), and (1, 0), and the states ER, A, B, and C have gradually increasing read voltages. The multi-level cell NAND flash memory may divide the two bits of each memory cell in a word line into two pages, which are the units of one-time programming. The least significant bits (LSBs) of all memory cells in a word line form the least significant bit page of the word line, and the most significant bits (MSBs) of all memory cells in the word line form the most significant bit page of the word line.

[0150] Once programmed or erased, the memory cell has a corresponding threshold voltage, which is a characteristic of the memory cell. The memory cell may be a floating gate transistor, and when a read voltage higher than or equal to the threshold voltage is applied to the gate of the memory cell, the memory cell may be turned on. When a read voltage lower than the threshold voltage is applied to the gate of the memory cell, the memory cell may be turned off. The read action is not a programming or erasing action, and is not intended to change the state of the memory cell.

[0151] Each state corresponds to a threshold voltage distributed in a range between a lower voltage and a higher voltage. A memory cell having a threshold voltage in the range is considered to be in the corresponding state, in other words, a memory cell in a state has a threshold voltage in the range. For example, if a memory cell has a threshold voltage between V10 and Vh0, the memory cell is in the ER state; if a memory cell has a threshold voltage between Vl1 and Vh1, the memory cell is in the A state; if a memory cell has a threshold voltage between V12 and Vh2, the memory cell is in the B state; and if a memory cell has a threshold voltage between V13 and Vh3, the memory cell is in the C state. Curves 202, 204, 206, and 208 show the respective threshold voltage distributions in states ER, A, B, and C, respectively.

[0152] During a read operation, a read voltage may be applied to the word line coupled to the gate of the selected memory cell to determine whether the selected memory cell is in an on or off state. Rd1 When applied, the memory cell will be turned on in the ER state and turned off in the A, B, and C states. When a read voltage V Rd2 When applied, the memory cell will be turned on in the ER or A state and turned off in the B or C state. When a read voltage V Rd3 When applied, the memory cell is turned on in the ER, A, or B state and turned off in the C state. When a read voltage V Rdpass When applied, the memory cell is turned on regardless of its state.

[0153] During the read operation, a pass voltage V is applied to other memory cells in the same bit line. Rdpass Therefore, if the selected memory cell is at the read voltage V Rd If the selected memory is turned on by the read voltage, the memory cell in the corresponding bit line forms a conductive path and has a current or voltage change that can be detected by the current or voltage sensor coupled to the word line. If the selected memory is turned off by the read voltage, the memory cell in the corresponding bit line does not form a conductive path and does not have a current or voltage change that can be detected by the current or voltage sensor coupled to the word line.

[0154] Due to repeated read and write operations, a read disturbance phenomenon may occur, in which the threshold voltage of a memory cell increases abnormally. Figure 2A As shown, in some examples, the distribution curve 202 of the erased state ER includes a dashed curve 203, and the dashed curve 203 includes a higher threshold voltage. For example, the new higher limit Vh0' is higher than the higher limit voltage Vh0. When the new higher limit voltage Vh0' is within the range of the threshold voltages V11 and Vh1 of the A state, the erased state ER overlaps with the programmed state A. That is, the memory cell has overlapping states. When the read voltage V Disturb When applied, the memory cell with the erased state ER threshold voltage is turned into the off state instead of the on state. Therefore, by detecting whether the memory is on or off with a specific read voltage, it can be determined whether the memory cell is subjected to read disturbance. In some examples, the states with lower threshold voltages in the memory cell, such as ER and A, are more susceptible to read disturbance than the states with higher threshold voltages.

[0155] Figure 2B A data graph 250 shows the relationship between cell count and read voltage for a multi-level cell device with different write / erase times (0, 3000 or 3k, 5000 or 5k, 10000 or 10k, 15000 or 15k, 20000 or 20k) on the memory. Figure 2B The threshold voltage distribution and the optimal read voltage of the display memory cell can be changed according to one or more input parameters (for example, the number of write / erase times of the memory cell). PE0 data, when there is no write / erase times, can correspond to Figure 2A The threshold voltage distribution data shown. The read voltage V1 corresponds to Figure 2A The read voltage V Rd1 , and can be the best read voltage for reading the erased state ER(1,1) of the memory cell. The read voltage V2 corresponds to Figure 2A The read voltage V Rd2 , and can be the best read voltage for reading the erased state (1, 1) and the programmed state (0, 1) of the memory cell. The read voltage V3 corresponds to Figure 2A The read voltage V Rd3 , and the optimal read voltages for the erased state ER (1, 1), the programmed state A (0, 1) and the programmed state B (0, 0) can be read for the memory cells, and the remaining memory cells can be judged to have the programmed state C (1, 0). As the number of write / erase times of the memory increases, the optimal read voltage rises and the data graph becomes shallower.

[0156] Figure 3 An example of determining a memory read voltage by a memory having an analog-to-digital converter circuit according to one or more embodiments of the present disclosure is shown. The memory may be Figure 1A as well as Figure 1B The memory 116 in the embodiment of the present invention, the analog-to-digital converter circuit may be Figure 1A as well as Figure 1B The analog-to-digital converter circuit 118 in the embodiment may be included in the memory. The memory may include a controller, such as Figure 1A as well as Figure 1B The controller 117 in the embodiment is configured to determine the calibration (or optimal) reading voltage based on the output of the analog-to-digital converter. The controller may be included in the control logic, for example Figure 1B The control logic 132 may be in the analog-to-digital converter circuit, or may be separate from the control logic and the analog-to-digital converter. For illustration purposes only, Figure 3 The memory cell of the memory is a single-level cell device (SLC) that can store one bit of data (eg, 0 or 1).

[0157] Graph (a) 320 shows an initial or hypothetical threshold voltage distribution for a memory cell (eg, a single-level cell) state, similar to Figure 2A The threshold voltage distribution of the multi-level cell state is shown. Curve 322 shows the initial threshold voltage distribution LVT in the lower state (eg, the erased state with bit 1). Initial , while curve 324 shows the initial threshold voltage distribution HVT in a higher state (eg, a programming state with bit 0) Initial Line segment 326 shows the preset read voltage V WLd The position is between the lower threshold voltage and the higher threshold voltage, and the preset read voltage V WLd It can be stored in a memory, such as a control logic or an analog-to-digital converter circuit. In some examples, the preset read voltage V WLd The memory manufacturer pre-configures the memory when it is produced. In some examples, the preset read voltage V WLd Determined by one or more memory characteristics (eg, periodically updated).

[0158] As described above, the memory may experience read disturbance or retention, where the states of the memory cells in the memory (e.g., erased state and one or more programmed states) may have increased or decreased threshold voltages. Graph (b) 340 shows an example of the threshold voltage distribution of the states of the memory cells (e.g., single-level cells) in the memory when data retention occurs. In this example, curve 342 shows the threshold voltage distribution LVT in the lower state (e.g., the programmed state with bit 1). Retention The curve 344 shows the change with the preset reading voltage V WLd The threshold voltage distribution HVT in the overlapping higher state (eg, the programming state with bit 0) Retention Therefore, if the preset reading voltage V WLd , a bit that should be in one state (e.g., a higher state with bit 0) is read as being in another state (e.g., a lower state with bit 1). Segment 346 shows the optimal (or calibrated) read voltage V WL , which is located between the threshold voltages of the changed higher state and the lower state (eg, as shown by curves 342 and 344 ).

[0159] In order to determine the position of the best read voltage for reading the memory cell in the memory page, the memory is configured to use an analog-to-digital converter circuit to read the memory page in a read operation. The analog-to-digital converter circuit can accumulate the current of multiple characters of the memory page where the read voltage is to be read, rather than calculating the number of multiple characters of the memory page where the read voltage is to be read. This can greatly increase the reading speed, thereby speeding up the judgment speed.

[0160] Figure 4 FIG. 400 is a schematic diagram of how an analog-to-digital converter circuit accumulates current read from a memory cell according to one or more embodiments. A memory cell array 410 stores a certain number of memory cells, each memory cell is coupled to a corresponding word line 402 and a corresponding bit line 404. Each memory cell is in an erased state corresponding to a character "1" or a programmed state corresponding to a character "0". A page, such as Figure 1C The page 142 is coupled to the word line 402. When a read voltage is applied to the word line, the programming word in the corresponding page can be read out. If the word is 1, a current will flow out. For each read voltage, the analog-to-digital converter circuit will horizontally accumulate the current of the memory cell from left to right (bit 1). Figure 4 As shown, for the first word line 402, there will be 6 bits "1" that can cause current. The analog-to-digital converter circuit can accumulate the current of the 6 programming bits and output a digital current value Isum. The digital current value can be stored in the analog-to-digital converter circuit or the memory. In comparison, the traditional valley search method is to calculate the number of bits including the bit "1", and it needs to be calculated 6 times, which may be slower than using the analog-to-digital converter circuit to calculate the 6-bit digital current value at a time. When the same page is read with a second read current, the analog-to-digital converter can clear the previous current value and accumulate the current of the same page again at the second read voltage. Through this method, a data chart of the output of the analog-to-digital converter circuit (e.g., the digital current value Isum) relative to the read voltage change can be obtained, such as Figure 3 (C) 360 shown in the diagram.

[0161] Back to Figure 3 , graph (C) 360 shows the output I of the analog-to-digital converter circuit as a function of the read voltage, and the curve can be generated by iteratively increasing or decreasing the read voltage, for example: starting from a preset VWLD. At each read voltage, a read operation is performed, and the analog-to-digital converter circuit is used to accumulate the current of the read memory cell, thereby obtaining the sum of the accumulated currents and converting it into a digital value I. As shown in graph (C) 360, curve 350 shows the output I of the analog-to-digital converter circuit as a function of the read voltage of the page of the memory cell in the initial state (as shown in graph (a) 320). It can be seen that the output I of the analog-to-digital converter circuit changes with the data retention of the memory cell. As described above, in all read operations, a high voltage V PASS Applied to word lines outside the page being read.

[0162] As shown in graph (C) 360, curve 361 includes a first positive slope portion 362, a flat portion 364, and a second positive slope portion 366. Below the flat portion 364 and within the first positive slope portion, as fewer bits "1" are read, the output of the analog-to-digital converter circuit decreases, which reduces the output of the analog-to-digital converter, such as the digital value I. Above the flat region 364 and within the second positive slope portion 366, as more programmed bits "0" are erroneously read as bits "1", the output of the analog-to-digital converter circuit increases. Therefore, by placing the read voltage within the flat portion 364, read errors can be reduced, for example, minimized. As shown in graph (C) 360, the flat region 364 is located between the threshold voltage ranges 342, 344. In the flat region 364, the output of the analog-to-digital converter circuit is substantially flat and is a function of the read voltage, which indicates the optimal read voltage V WL Within the planar region 364 .

[0163] To more accurately determine the location of the optimal read voltage, the data in the portion 370 of the curve 361 including the flat region 364 can be further processed. Graph (d) 380 shows the derivative of the analog-to-digital converter output as a function of the read voltage. For example, the curve 382 of graph (c) 380 can be obtained by iteratively reducing the read voltage, for example, using the voltage V WL1 , V WL2 , ..., V WLk-1 、V WLk , and use the calibration step to calculate the continuous (or adjacent) read voltage V WLi-1 、V Wli The difference Δi between the analog-to-digital converter outputs Ii-1 and Ii is, for example, Δi=Ii-Ii-1. When the difference is close to zero or at a minimum value, the bottom of the curve 382 is identified, and the optimal read voltage is determined. That is, the minimum value in the curve 382 (e.g., as close to the minimum value as possible under practical time constraints, operating power, circuit packaging, voltage level size, etc.) provides a calibrated read voltage, such as the optimal read voltage V WL For comparison, curve 384 in FIG. (C) 380 is also generated from portion 370 of curve 350, where the optimal V WL Smaller than the previous best V WL , while the previous best V WL Less than the preset V WLd , which indicates that data retention will gradually reduce the optimal read voltage.

[0164] In some embodiments, a memory, such as a controller, may pre-determine a search range, such as: Figure 3 The search range 386 shown in FIG. 386 can be determined by the initial voltage, for example, the preset voltage V WLd , to a preset threshold voltage, for example: V WLi The read voltage may be gradually increased (e.g., by a voltage interval ΔV) from an initial voltage to a predetermined threshold voltage. If the read voltage is still within the search range, the read voltage is continuously decreased to obtain a new output value of the analog-to-digital converter circuit. If the read voltage is outside the search range or exceeds the predetermined threshold voltage, that is, the read voltage across the entire search range has been used, the memory, such as a controller, may determine a calibrated read voltage for the page using the respective output values ​​of the analog-to-digital converter circuit and a series of read voltages. After determining the calibrated read voltage, the memory may then read the data stored in the page using the calibrated read voltage.

[0165] In some embodiments, the search range may be from an initial voltage to a threshold voltage greater than the initial voltage. In some embodiments, the search range may be from an initial voltage to a threshold voltage less than the initial voltage. In some embodiments, the search range may be between a first and a second threshold voltage, and the initial voltage is greater than the first threshold voltage and less than the second threshold voltage. The memory may change the read voltage first from the initial voltage to the first threshold voltage, and then from the initial voltage to the second threshold voltage. The memory may also change the read voltage first from the initial voltage to the second threshold voltage, and then from the initial voltage to the first threshold voltage.

[0166] Figure 5 A flowchart 500 is shown of a method for determining a calibration read voltage of a memory having an analog-to-digital converter circuit according to one or more embodiments of the present disclosure. The memory may be Figure 1A as well as Figure 1B The memory 116 in the embodiment of the present invention, the analog-to-digital converter circuit may be Figure 1A as well as Figure 1B The analog-to-digital converter circuit 118 in the memory may include a controller, such as Figure 1A as well as Figure 1B The controller 117 in the embodiment is configured to determine a calibrated (or optimal) read voltage based on the output of the analog-to-digital converter circuit. The controller may include control logic in the analog-to-digital converter circuit, such as: Figure 1B The control logic 132 in the memory may be separate from the control logic and the analog-to-digital converter circuit. The process 500 may be executed by a memory. For illustration purposes only, the memory cells in the memory are exemplified by single-level cells (SLC).

[0167] The memory can store data in pages consisting of multiple memory cells. Pages, e.g. Figure 1C Page 142 of Figure 1D The page 152 in corresponds to a word line in the memory. The memory cell can be in different states, for example: an erased state with a bit "1" and a programmed state with a bit "0".

[0168] Process 500 begins, for example, when the memory receives a read request to read data on a page. The memory may then use process 500 to determine a calibrated read voltage for the page to read the data on the page. Process 500 then performs an iterative step that performs a page read (step 502) and records the output value of the analog-to-digital converter circuit (step 504).

[0169] like Figure 3 As shown, iterative page reading can be provided by applying a series of consecutive read voltages to the word lines of the page. Iterative page reading can be started from a preset read voltage, such as a preset read voltage present in the memory. For iterative page reading, the read voltage can be gradually increased or decreased from the preset read voltage, such as by a voltage interval Δ V In some embodiments, the voltage interval Δ V In some embodiments, the voltage interval Δ V is not fixed and can be updated dynamically. For example, if the read operation requires a faster speed, such as: the memory tends to be high-speed, the voltage interval Δ V Can be larger if the reading requires higher accuracy, for example: close to the position of the optimal reading voltage, the voltage interval Δ V Can be smaller.

[0170] As mentioned above Figure 4 As shown, the currents of multiple bits (e.g., bit 1) in each read voltage page are accumulated by the analog-to-digital converter circuit and converted into digital values ​​corresponding to the output of the analog-to-digital converter circuit. After storing the output of the analog-to-digital converter circuit, the memory, such as a controller, determines whether the read voltage exceeds the search range (e.g., Figure 3 The search range 386 in FIG. 500 is a step 506. The search range may be preset, for example, based on empirical data or acceptable read voltage variations. If the read voltage is still within the search range, the read voltage is increased or decreased, for example, by a voltage interval ΔV, and the process 500 returns to step 502. If the read voltage is outside the search range, that is, the read voltages across the entire search range have been used, the memory, for example, a controller, determines a calibration read voltage for the page using the output values ​​of the respective analog-to-digital converter circuits and a series of read voltages (step 508), for example: Figure 3 After determining the calibration read voltage, the process 500 ends, and the memory can then read the data stored in the page with the calibration read voltage.

[0171] In order to find or determine the calibration read voltage, a series of read voltage configurations can be implemented in different ways. In some embodiments, the read voltage is gradually increased from a preset read voltage. In some embodiments, the read voltage is gradually decreased from a preset read voltage. In some embodiments, the read voltage is first gradually decreased from a preset read voltage to a lower voltage, and then increased from a preset read voltage to a higher voltage. In some embodiments, the read voltage is first gradually increased from a preset read voltage to a higher voltage, and then decreased from a preset read voltage to a lower voltage, for example: Figure 6 Further details shown.

[0172] Figure 6 Another exemplary flow chart 600 for determining a calibration read voltage of a memory having an analog-to-digital converter circuit according to one or more embodiments of the present disclosure is shown. The memory may be Figure 1A as well as Figure 1B The analog-to-digital converter circuit may be Figure 1A as well as Figure 1B The analog-to-digital converter circuit 118 in the memory may include a controller, such as Figure 1A as well as Figure 1B The controller 117 in the embodiment is configured to determine the calibration (or optimal) reading voltage based on the output of the analog-to-digital converter circuit. The controller may include control logic in the analog-to-digital converter circuit, such as: Figure 1B The process 600 may be executed by a memory.

[0173] and Figure 5 Similar to the flowchart 500, the process 600 begins, for example, when the memory receives a read request to read the data of the page, the memory can use the initial read voltage V WL_initial Perform initial read and obtain initial read data. If the error correction code, for example: Figure 1A If the error correction code decoder 144 in the memory successfully decrypts the read data, for example, any error bits present in the data can be detected and corrected, then the memory does not need to perform further steps of process 600, which means that the initial read voltage can be used to read the data of the page. However, if the error correction code decodes the read data and fails, the memory can continue to perform process 600 to determine the calibration read voltage for the page to read the data of the page. Process 600 finds the calibration read voltage by first gradually increasing the initial read voltage V WL_initia1 to a higher voltage X in a higher search region, for example, as shown in steps 604, 606, 608, and 610, and then gradually from the initial voltage V WL_initial Decrease to a lower voltage Y in a lower seek region, for example, as shown in steps 612, 614, 616, 618. Next, a calibration read voltage may be determined based on the output of the analog-to-digital converter circuit for the read voltage used during the seek, or based on X and Y.

[0174] Initial reading voltage V WL_initial It can be a preset value, for example, preset by the memory manufacturer based on experience or known memory characteristics. The initial read voltage can also be updated based on a previously known optimal or calibrated read voltage. In some embodiments, since each write / erase operation will initialize the page, the initial read voltage is set to a preset value by the memory manufacturer.

[0175] and Figure 5 Similar to steps 502 and 504, in step 602, the memory is initially read at a voltage V WL_initial If the error correction code decoding fails, the memory triggers the analog-to-digital converter circuit to accumulate the currents of the word lines corresponding to the multiple memory cells in the page to obtain the sum of the currents, which can be converted by the analog-to-digital converter circuit and recorded as a digital current value I1.

[0176] Then read the voltage increase, for example: with a voltage interval of Δ V As described above, the voltage interval can be fixed or dynamically updated based on different criteria. Step 604 is similar to step 602, except that an additional read voltage transformer is used to read the same page. The analog-to-digital converter circuit accumulates the currents of multiple memory cells on the page to obtain the corresponding digital current value Ii.

[0177] In step 606, in order to increase the accuracy of the determination, two consecutive (or adjacent) readings of the voltage V WLi 、V WLi-1 The output digital current value I i ,I i-1 The difference between i-1 is obtained, for example, Δ i-1 =I i -I i-1 , where i is an integer greater than 1. In step 608, the digital current value I is output. i and I i-1 The difference between i-1 and the first preset threshold Δ th1 For example, the first preset threshold is substantially the same as 0. If the difference Δ i-1 is not less than a preset threshold, which indicates that the read voltage has not yet reached the optimal (or calibrated) read voltage, and the read voltage can be further increased, for example, by a voltage interval ΔV. The process 600 then returns to step 604 and performs a new read operation. The voltage interval can be the same as the previous read voltage V WLi The voltage interval may be the same as the previous voltage interval, or may be smaller or larger than the previous voltage interval. Then, the process 600 repeats steps 606 and 608, for example, as shown in FIG. 5 , until the read voltage exceeds the search range.

[0178] If the difference Δ i-1 Less than the preset threshold Δ th1 , which represents the read voltage V WLi Substantially close to the optimal read voltage in the higher voltage search region, in step 610, the memory (eg, controller) determines the first calibration read voltage X and the read voltage V WLi same.

[0179] Process 600 then begins with an initial read voltage and performs a search in the lower voltage search region. The initial read voltage may be gradually reduced, for example, by voltage intervals ΔV, which may be the same or different than those used in the higher voltage search region. In step 612, similar to step 604, the page is read at a reduced read voltage V WLj Read, where j is an integer greater than 1. The analog-to-digital converter circuit is then triggered to accumulate the currents of the word lines corresponding to the plurality of memory cells in the page to obtain the sum of the currents, which can be converted by the analog-to-digital converter circuit and recorded as a digital current value I j In step 614, similar to step 606, two consecutive (or adjacent) read voltages V WLj 、V Wj-1 The output digital current value I j ,I j-1 The difference between j-1 is obtained, for example: Δ j-1 =I j -I j-1 .

[0180] In some embodiments, similar to step 608, the output digital current value I j ,I j-1 The difference between j-1 The difference may be compared to a preset threshold, for example, based on empirical data. If the difference is not less than the preset threshold, the read voltage may be further increased, and process 600 returns to step 612. If the difference is less than the preset threshold, the memory (e.g., analog-to-digital converter circuit or controller) may determine that the read voltage V WLj Substantially close to the optimum read voltage in the lower voltage seek region.

[0181] In some embodiments, to further improve accuracy, such as Figure 6 As shown, in step 616, the first continuous reading voltage V WLj 、V WLj-1 The first difference Δ j-1 and a second continuous read voltage V adjacent to the first continuous read voltage WLj-1 ,V WLj-2 The second difference Δ j-2 The difference between the two is judged as |Δ j-1 -Δ j-2 |. Then the difference |Δ j-1 -Δ j-2 | and can be preset, for example, based on empirical data, the second threshold voltage Δ th2 Make a comparison. If the difference is not less than the second threshold voltage Δ th2 , the read voltage can be further reduced, and the process 600 then returns to step 612. If the difference is less than the second threshold voltage Δ th2 , the memory (e.g., analog-to-digital converter circuit or controller) can determine the read voltage V WLj In step 610, the memory (eg, controller) determines whether the second calibration read voltage Y and the read voltage V WLj In some embodiments, X may also be determined according to steps 616 and 618 for determining Y.

[0182] In step 620, the optimal read voltage is determined by at least one of the first calibration voltage X and the second calibration voltage Y. For example, based on the size of the voltage interval ΔV, Y may be on the left side of the optimal read voltage and X may be on the right side of the optimal read voltage. Figure 6 As shown, the optimal read voltage can be expressed as:

[0183] V WL =β(XY)+Y

[0184] If there is any distortion, β may be 0.4 or 0.6. In some embodiments, if the voltage interval ΔV is small enough, X may be determined as the optimal read voltage and β may be 1, or Y may be determined as the optimal read voltage and β may be 0.

[0185] The contents and embodiments disclosed in the present invention may be applied to one or more computer program products. For example, in a data processing device, one or more computer program instruction modules are encoded in a computer-readable medium to execute or control data processing. The computer-readable medium may be a machine-readable storage device, a computer-readable medium storage substrate, a storage device, or a combination of one or more of the above devices. The term "data processing device" includes all devices, devices and machines used for data processing, such as, but not limited to, a programmable processor, a computer, multiple processors or multiple computers. In addition to hardware, the device may also include coding that provides an execution environment for computer programs, such as: coding that constitutes processor firmware, a protocol stack, a database management system, an executing system, or a combination of one or more of the above.

[0186] The system disclosed in the present invention includes all devices, apparatuses and machines for data processing, such as but not limited to a programmable processor, a computer, multiple processors or multiple computers. In addition to hardware, a system may also include code that provides an execution environment for computer programs, such as code that constitutes processor firmware, a protocol stack, a database management system, an executing system or a combination of one or more of the above.

[0187] The computer program disclosed in the present invention (also referred to as program, software, application software, script or code) can be written in any form of programming language, including coding or decoding language, and can also be deployed in any form, such as: an independently operating program or a module, a component, a subroutine or other unit for a computer computing environment. The computer program disclosed in the present invention does not necessarily correspond to a single file in a file system. A program can be stored in a file containing other programs or data (for example: one or more scripts stored in a markup language file). The file can be a single file dedicated to the program, or multiple files that cooperate with each other (for example: a file storing one or more modules, subroutines or partial codes). The computer program can be deployed to run on one or more computers located in one or more locations connected by a communication network.

[0188] The steps and flowcharts shown in the present invention can be implemented by one or more programmable processors running one or more computer programs to perform the functions described. The instruments of the steps and flowcharts can also be implemented by a special-purpose logic circuit, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0189] Processors suitable for running the computer program include, for example, general or special purpose microprocessors, or one or more processors of one or more digital computers. Generally, the processor receives instructions and data from one or both of a read-only memory or a random access memory. Essential elements of a computer include a processor for executing instructions and one or more storage devices for storing instructions and data. Generally, a computer includes or is coupled to a computer for receiving data and transmitting data to one or more mass storage devices, such as magnetic disks or magneto-optical disks, for data storage, however, the computer does not necessarily require such devices. Computer-readable media suitable for storing computer program instructions and data include various forms of non-volatile memory, media and storage devices, for example semiconductor memory devices, such as erasable programmable read-only memory (EPROM), electronically erasable rewritable read-only memory (EEPROM), flash memory devices and magnetic disks. The processor and memory may be assisted or combined with special purpose logic circuits.

[0190] Although the present invention has been disclosed as above in the form of embodiments, it is only used to describe the technical features in a specific embodiment and is not used to limit the scope of protection of the present invention. The technical features described in individual embodiments can be combined and applied to a single embodiment. Conversely, multiple technical features described in a single embodiment can also be applied to multiple embodiments individually or in sub-combinations. Furthermore, although the initial requirements or operating methods of the above-mentioned technical features show that they need to be combined in a specific manner, one or more technical features required to be combined can be removed therefrom, wherein the required combination may refer to a sub-combination or its related variations. Similarly, although the steps are shown in a specific order in the diagram, it is not required that the step must be performed in a specific step, or that all the steps shown must be performed in full to achieve the described result.

[0191] The above only discloses a number of possible implementation examples, and various changes, modifications and enhancements may be made without departing from the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope of the attached claims.< / n>

Claims

1. A memory device, the memory device comprising: a memory cell array, each memory cell being coupled to a corresponding word line among a plurality of word lines and a corresponding bit line among a plurality of bit lines; An accumulation circuit is coupled to the memory cell array, and the accumulation circuit is configured as follows: When data stored in a page is read by applying each of a plurality of read voltages to a bit line corresponding to the page, a read signal of each of the memory cells in the page is accumulated to generate an output value of each accumulated read signal corresponding to the read voltage; a controller coupled to the accumulation circuit and configured to determine a calibration read voltage of the page based on the read voltages and the output values ​​associated with the read voltages; as well as A control circuit, coupled to the memory cell array, is configured to iteratively increase or decrease the read voltages. 2 . The memory device of claim 1 , wherein the accumulation circuit comprises an analog-to-digital converter configured to convert the accumulated read signal into each of the output values. 3 . The memory device of claim 1 , wherein the read signal comprises at least a current or a voltage. 4 . The memory device of claim 1 , wherein the control circuit is configured to apply each of the read voltages to the word line in a manner of continuously applying the read voltages over a sequence of read voltage values. The memory device of claim 4 , wherein the control circuit comprises the controller.

6. The memory device according to claim 1, wherein the control circuit is configured as: Determining whether the read voltage having a first read voltage value is lower than a threshold voltage; In response to determining that the read voltage having the first read voltage value is not greater than the threshold voltage, increasing or decreasing the read voltage to have a second read voltage value to be applied to a subsequent read operation on the page; as well as In response to determining that the read voltage having the first read voltage value exceeds the threshold voltage, the controller is enabled to determine the calibration read voltage of the page.

7. The memory device according to claim 5, wherein the controller is configured to: For at least two read voltage values ​​in the read voltage sequence, a difference between the output value of each read voltage in the read voltage sequence and the output value of a second read voltage value immediately before the read voltage value is determined to provide a difference sequence.

8. The memory device according to claim 7, wherein the controller is configured to determine the calibration read voltage based on the difference sequence and the read voltages, the steps comprising: identifying a specific read voltage value from the at least two read voltage values, the specific read voltage value providing a minimum difference in the difference sequence; and The calibration read voltage is set to have the specific read voltage value.

9. The memory device according to claim 7, wherein the controller is configured to: For the at least two read voltage values ​​in the read voltage sequence, determining a second difference between the output value of each read voltage in the read voltage sequence and a second read voltage value immediately before the read voltage value, thereby providing a second difference sequence; and A calibration voltage value is determined based on the second difference sequence and the read voltages.

10. The memory device according to claim 1, wherein the control circuit is configured as: Iteratively changing the read voltage from an initial voltage value to a first read voltage value in a first direction, the first direction being one of an increasing direction and a decreasing direction; Determining that a difference between a first output value of the first read voltage value and a second output value of a second read voltage value immediately before the first read voltage value is less than a first threshold; and A first calibration read voltage having the first read voltage value is determined.

11. The memory device according to claim 10, wherein the control circuit is configured as: iteratively changing the read voltage from the initial voltage value to a third read voltage value in a second direction, the second direction being one of the increasing direction and the decreasing direction; Determining that a difference between a third output value of the third read voltage value and a fourth output value of a fourth read voltage value immediately before the third read voltage value is less than a second threshold; and A second calibration read voltage having the third read voltage value is determined, wherein the calibration read voltage is determined based on the first calibration read voltage and the second calibration read voltage.

12. The memory device according to claim 10, wherein the control circuit is configured as: iteratively changing the read voltage from the initial voltage value to a third read voltage value in a second direction, the second direction being one of the increasing direction and the decreasing direction; determining a first difference between a third output value of the third read voltage and a fourth output value of a fourth read voltage value immediately before the third read voltage value; Determining a second difference between the output value of the fourth read voltage value and a fifth output value of a fifth read voltage value immediately before the fourth read voltage value; Determining that a difference between the first difference and the second difference is less than a second threshold; as well as determining a second calibration read voltage having the second read voltage value; The calibration read voltage is determined by the first calibration read voltage and the second calibration read voltage.

13. The memory device of claim 12, wherein the calibration read voltage is determined to have the following expression: Wherein V, X and Y represent the calibration read voltage, the first calibration read voltage and the second calibration read voltage respectively, and β is a constant between the interval [0, 1].

14. A memory device, the memory device comprising: A memory array including a plurality of pages of memory cells coupled to a plurality of corresponding word lines; an analog-to-digital converter circuit coupled to the memory array and configured as follows: When data stored in a page is read by applying a respective read voltage among a plurality of read voltages to a bit line corresponding to the page, a read signal of each of the memory cells in the page is accumulated to generate an output value of an accumulated read signal corresponding to the read voltage; a controller coupled to the analog-to-digital converter circuit and configured to determine a calibrated read voltage for the page based on the read voltages and the output values ​​associated with the read voltages; as well as A control circuit, coupled to the memory cell array, is configured to iteratively increase or decrease the read voltages.

15. The memory device of claim 14, wherein the analog-to-digital converter circuit comprises the controller.

16. The memory device of claim 14, the control circuit being configured to apply the read voltages to the word line in a manner that the read voltages are applied successively over a sequence of read voltage values.

17. A method comprising: Applying a plurality of read voltages to word lines corresponding to a page of a plurality of memory cells of a memory device; For each of the read voltages, accumulating the read signals of the memory cells in the page to generate an output value of the accumulated read signal corresponding to the read voltage; as well as Determining a calibration read voltage for the page based on the read voltages and the output values ​​associated with the read voltages; in, Determining a calibrated read voltage of the page includes: For at least two of the read voltages, determining a difference between the output value of each read voltage in the read voltage value sequence and the output value of a second read voltage value immediately before the read voltage value, thereby providing a difference sequence; as well as The calibration read voltage is determined according to the difference sequence and the read voltages.

18. The method according to claim 17, wherein the step of determining the calibration read voltage using the difference sequence and the read voltages comprises: For the at least two read voltage values ​​in the read voltage sequence, determining a second difference between the output value of each read voltage in the read voltage sequence and the output value of a second read voltage value immediately before the read voltage value, thereby providing a second difference sequence; and The calibration read voltage is determined according to the second difference sequence and the read voltages.

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