Silicon carbide semiconductor device manufacturing method, silicon carbide semiconductor device, and applications thereof

Abstract

The application discloses a silicon carbide semiconductor device preparation method, a silicon carbide semiconductor device and application thereof. A first mask layer is formed on one side of a silicon carbide substrate layer, and a first implantation is performed to form a well region. The silicon carbide substrate layer is of a first conductive type, the well region is of a second conductive type, the first conductive type is opposite to the second conductive type, the thickness of the first mask layer is 0.1-10 microns, and a second implantation of a material of the first conductive type is performed on the well region to form a first source region. The angle between the implantation and the normal is 10-70 degrees. The silicon carbide semiconductor device preparation method forms a required width short channel by adjusting the thickness of the mask layer and the implantation angle. The thickness of the mask layer and the implantation angle can be accurately controlled through the process parameters of the equipment, that is, the required channel length can be controlled by adjusting the process parameters, and the controllability and stability of the prepared channel silicon carbide semiconductor device can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a silicon carbide semiconductor device preparation method, a silicon carbide semiconductor device and an application thereof. BACKGROUND

[0002] Power integrated circuit is a special integrated circuit that integrates power devices, low-voltage control circuits, signal processing and communication interface circuits in the same chip. The application of power integrated circuits not only reduces the size of the whole machine, reduces the wiring, and reduces the parasitic parameters, but also makes the cost lower, the size smaller and the weight lighter, so it is widely used in many fields such as communication and network, computer and consumer electronics, industry and automobile electronics. Power devices have developed rapidly from small power, low frequency and half-controlled to high power, high frequency and fully-controlled. Various structures and materials of power devices have appeared and realized commercialization. However, as the most rapidly developed silicon-based power device, its performance has approached the theoretical limit of silicon material.

[0003] Silicon carbide has attracted much attention due to its excellent material properties. As a switching device with low on-resistance, high reverse voltage and fast switching speed, the application prospect of silicon carbide metal-oxide semiconductor field effect transistor is very broad. However, to further improve the performance of the device, the problem of reducing the channel resistance needs to be solved. The large channel resistance leads to large loss during conduction. To reduce the conduction loss, the on-resistance needs to be reduced. The specific on-resistance of planar metal-oxide semiconductor field effect transistor can be expressed as: R ON,SP = R CH,SP + R DR,SP + W*S(R S + R JFET + R SUB ), wherein R ON,SP represents the specific on-resistance, R CH,SP is the channel resistance, R DR,SP is the drift region resistance, R S represents the sum of the source contact resistance and the n+ source region resistance, R JFET is the JFET region resistance, R SUB is the sum of the substrate resistance and its ohmic contact resistance, and W and S are the width and half-cell length of the cell. To minimize the channel resistance, the channel length needs to be reduced. The important factor affecting the shortening of the channel is the limitation of the manufacturing process.

[0004] There are two methods for making a channel of a conventional silicon carbide metal-oxide semiconductor field effect transistor, i.e., a photoetching method and a self-alignment method. The channel formed by the photoetching method is limited by the precision of the photoetching process and is suitable for making a metal-oxide semiconductor field effect transistor with a long channel. The self-alignment method can make a sub-micron channel, but the stability of the self-alignment method is limited by the stability of the deposition and etching processes. The self-alignment method for making a sub-micron channel includes the following steps: after forming a well region, a mask layer for the well region is reserved, a channel mask layer with different film quality is deposited, and the channel mask layer is etched by using a dry etching method. The dry etching method has anisotropy, so the channel is defined by the channel mask layer left on the sidewall of the well region mask layer. Therefore, the channel made by the method is affected by the morphology of the well region mask layer, the thickness of the channel mask layer and the dry etching method. Any drift of the processes will cause the length and morphology of the final channel to be different. SUMMARY

[0005] Therefore, it is necessary to provide a silicon carbide semiconductor device preparation method with good controllability and stability.

[0006] The present application provides a silicon carbide semiconductor device preparation method, which comprises the following steps:

[0007] S10: a first mask layer is formed on one side of a silicon carbide substrate layer, and a first implantation is performed to form a well region, wherein the surface of the well region is flush with the implantation surface of the silicon carbide substrate layer, the silicon carbide substrate layer is of a first conductivity type, the well region is of a second conductivity type, the first conductivity type is opposite to the second conductivity type, and the thickness of the first mask layer is 0.1-10 microns;

[0008] S20: a second mask layer is formed on the well region, and a first source region is formed on both sides of the first mask layer through the second mask layer and the first mask layer, the first source region is formed by using a material of the first conductivity type to perform a second implantation on the well region, the angle between the implantation direction and the normal line is 10-70 degrees, and the first source region and the silicon carbide substrate layer below the first mask layer form a channel. When the first source region on one side is formed, the second mask layer is left empty in the region close to the first mask layer on the side to leave the positions of the first source region and the channel, and when the first source region on the other side is formed, the second mask layer is left empty in the region close to the first mask layer on the side to leave the positions of the first source region and the channel;

[0009] S30: a second source region is formed by using a material of the second conductivity type to perform a third implantation on the region of the well region except the first source region and the channel, the well region surrounds the first source region and the second source region, and a basic device structure is prepared;

[0010] S40: Activate the basic device structure.

[0011] In one embodiment, the following step is included after step S40:

[0012] S50: A gate is formed on the well region and the silicon carbide substrate layer;

[0013] S60: A source electrode is formed on the source region, wherein the source region includes a first source region and a second source region, the source electrode is in contact with the first source region, and the source electrode is in contact with the second source region;

[0014] S70: A drain is formed on the side of the silicon carbide substrate away from the source region and the gate.

[0015] In one embodiment, in step S20, the angle between the second injection direction and the normal is 40° to 50°.

[0016] In one embodiment, in step S10, the thickness of the first mask layer is 0.5 μm to 5 μm.

[0017] In one embodiment, the silicon carbide substrate layer includes a silicon carbide substrate and a silicon carbide epitaxial layer disposed on the silicon carbide substrate, the first mask layer is disposed on the silicon carbide epitaxial layer, and the silicon carbide epitaxial layer surrounds the well region.

[0018] In one embodiment, the silicon carbide substrate has a thickness of 100 μm to 500 μm and a substrate resistivity of 0.01 Ohm·cm to 0.1 Ohm·cm; and / or

[0019] The thickness of the silicon carbide epitaxial layer is 3μm to 200μm, and the doping concentration is 10. 13 cm -3 ~10 17 cm -3 .

[0020] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type; and / or

[0021] The first conductivity type is P-type, and the second conductivity type is N-type.

[0022] In one embodiment, the first conductivity type is N-type, the second conductivity type is P-type, and in step S10, the material implanted for the first time is aluminum or arsenic, with a doping concentration of 10. 16 cm -3 ~10 19 cm -3 ; and / or

[0023] In step S20, the material implanted for the second time is nitrogen or phosphorus, with a doping concentration of 10. 18 cm -3 ~10 22 cm -3 ; and / or

[0024] In step S30, the material implanted for the third time is aluminum or arsenic, with a doping concentration of 10. 18 cm -3 ~10 22 cm -3 .

[0025] Furthermore, the present invention also provides a silicon carbide semiconductor device, which is obtained by the above-described method for preparing a silicon carbide semiconductor device.

[0026] The present invention further provides an electronic product comprising the aforementioned silicon carbide semiconductor device.

[0027] In the above-mentioned method for fabricating silicon carbide semiconductor devices, a short channel of the required width is formed by adjusting the mask layer thickness and the injection angle. The thickness of the mask layer and the injection angle can be precisely controlled by the process parameters of the equipment. That is, the required channel length can be controlled by adjusting the process parameters. Compared with the traditional photolithography and self-aligned formation methods, it has higher controllability of photolithography and etching accuracy, and can improve the controllability and stability of fabricating the required channel semiconductor device. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the fabrication process for silicon carbide semiconductor devices.

[0029] The symbols in the attached image are explained as follows:

[0030] 100: Silicon carbide semiconductor device; 1010: Silicon carbide substrate; 1011: Silicon carbide epitaxial layer; 102: Well region; 103: First masking layer; 1040: Second masking layer; 1041: Third masking layer; 105: First source region; 106: Second source region; 1071: Gate oxide layer; 1072: Polysilicon layer; 1073: Dielectric layer; 108: Gate metal layer; 109: Source; 110: Drain.

[0031] Figure 2 This is a diagram showing the relationship between the channel width L, injection angle α, and the first mask layer D in step S20. Detailed Implementation

[0032] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0033] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. In the description of the present invention, "a number" means at least one, such as one, two, etc., unless otherwise explicitly specified.

[0034] The terms "preferred," "more preferably," etc., used in this invention refer to embodiments of the invention that provide certain beneficial effects under certain circumstances. However, other embodiments may also be preferred under the same or other circumstances. Furthermore, the description of one or more preferred embodiments does not imply that other embodiments are unavailable, nor is it intended to exclude other embodiments from the scope of this invention.

[0035] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to integers, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are incorporated.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0037] like Figure 1 The present invention illustrates a method for fabricating a silicon carbide semiconductor device 100, comprising the following steps.

[0038] Step S10: As Figure 1(a) A first mask layer 103 is formed on one side of a silicon carbide substrate to form a well region 102 by a first implantation. The surface of the well region 102 is flush with the implantation surface of the silicon carbide substrate. The silicon carbide substrate is of a first conductivity type, and the well region 102 is of a second conductivity type. The conductivity types of the first conductivity type and the second conductivity type are opposite. The thickness of the first mask layer 103 is 0.1 μm to 10 μm.

[0039] Understandably, the above-mentioned injection direction is to inject the first mask layer 103 into the silicon carbide substrate layer from one side of the silicon carbide substrate layer.

[0040] In a specific example, the silicon carbide substrate 103 includes a silicon carbide substrate 1010 and a silicon carbide epitaxial layer 1011 disposed on the silicon carbide substrate, a first mask layer 103 disposed on the silicon carbide epitaxial layer 1011, and the silicon carbide epitaxial layer 1011 surrounding the well region 102.

[0041] In a specific example, the silicon carbide substrate 1010 has a thickness of 100 μm to 500 μm, a substrate resistivity of 0.01 Ohm·cm to 0.1 Ohm·cm, and the substrate impurity is nitrogen.

[0042] Preferably, the thickness of the silicon carbide substrate 1010 can be, but is not limited to, 300 μm to 400 μm.

[0043] Furthermore, the thickness of the silicon carbide epitaxial layer 1011 is 3 μm to 200 μm, and the doping concentration is 10. 13 cm -3 ~10 17 cm -3 .

[0044] Preferably, the thickness of the silicon carbide substrate 1010 can be, but is not limited to, 10 μm to 12 μm, and the doping concentration is 10. 15 cm -3 ~10 16 cm -3 .

[0045] Understandably, the minimum thickness of the first mask layer 103 is determined by the injection requirements of the well region 102.

[0046] Furthermore, the thickness of the first mask layer 103 is preferably 1μm to 3μm, and specifically, it can be, but is not limited to, 0.1μm, 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm or 10μm.

[0047] The material of the first mask layer 103 may be, but is not limited to, selected from at least one of polysilicon, silicon nitride, and silicon dioxide.

[0048] Furthermore, the method for forming the first mask layer 103 described above may be, but is not limited to, chemical vapor deposition.

[0049] Step S20: As Figure 1 As shown in (b) to (f), a second mask layer 1040 is formed on the well region 102. A first source region 105 is formed on both sides of the first mask layer 103 through the second mask layer 1040 and the first mask layer 103. The first source region 105 is formed by a second implantation of a material of a first conductivity type into the well region 102. The angle between the implantation direction and the normal is 10° to 70°. A channel is formed between the first source region 105 and the silicon carbide substrate layer below the first mask layer 103.

[0050] Specifically, when forming the first source region 105 on one side, firstly, as Figure 1 As shown in (b), a second mask layer 1040 is first formed. The second mask layer 1040 is left open in the area adjacent to the first mask layer 103 on this side, to create space for the predetermined first source region 105 and the channel, forming a first source region mask layer 1040a. A first conductivity type material is then implanted into the well region 102 a second time to form the first source region 105 on one side. Figure 1 As shown in (c); then, as Figure 1 (d) Remove the first source region mask layer 1040a mentioned above.

[0051] Similarly, when forming the first source region 105 on the other side, as... Figure 1 As shown in (e), a second mask layer 1040 is formed again. This time, the second mask layer 1040 leaves a gap in the area adjacent to the first mask layer 103 on this side to create space for the predetermined first source region 105 and the channel, forming a second first source region mask layer 1040b. A first conductivity type material is then implanted into the well region 102 a second time to form the first source region 105 on one side, as shown in (e). Figure 1 As shown in (f).

[0052] Understandably, the first source region 105 has a first conductivity type.

[0053] Specifically, a second mask layer 1040 with a thickness of 1 μm to 1.5 μm is deposited. Photoresist is coated on the second mask layer 1040, and a first source region mask layer 1040a is formed using photolithography. Implantation is then performed to form the first source region 105 and the channel on that side. Subsequently, the first source region mask layer 1040a is removed, for example, removing the 1040a made of silicon dioxide. Afterward, the second mask layer 1040 is formed again in the same manner, for example, by depositing another layer of silicon dioxide to cover the well region 102. Photoresist is then coated on the silicon dioxide layer, and a second first source region mask layer 1040b is formed using photolithography. Implantation is then performed to form the first source region 105 and the channel on that side.

[0054] Understandably, the material of the first mask layer 103 is different from that of the second mask layer 1040 to facilitate the removal of the material of the second mask layer 1040. The material of the second mask layer 1040 may be, but is not limited to, silicon dioxide.

[0055] Specifically, the injection angle can be, but is not limited to, 10°, 15°, 20°, 25°, 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65° or 70°, and preferably the injection angle is 40° to 50°.

[0056] Understandably, such as Figure 2 The thickness of the first mask layer is D, the angle with the normal during injection is α, and the channel width is L = D × tanα. That is, the channel width decreases as the thickness D of the first mask layer decreases and as the injection angle α decreases.

[0057] Furthermore, the width of the channel L is 0.1μm to 2μm. It is understood that the above width may be, but is not limited to, 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm, 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm or 2μm.

[0058] Step S30: As Figure 1 (g) A second source region 106 is formed by a third implantation of a material of the second conductivity type into the region of the well region 102 other than the first source region 105 and the channel. The well region 102 surrounds the first source region 105 and the second source region 106 to fabricate a basic device structure.

[0059] Understandably, a third mask layer 1041 is formed on the trap region 102 before the third injection.

[0060] Step S40: Activate the basic device structure.

[0061] Understandably, the activation methods described above may include, but are not limited to, high-temperature annealing, and the purpose of activation may include, but is not limited to, activating the function of donor and acceptor impurities.

[0062] The process includes removing the third mask layer 1041 before step S40.

[0063] In a specific example, the following steps are included after step S40:

[0064] Step S50: As Figure 1 As shown in (h) to (j), a gate is formed on the well region 102 and the silicon carbide substrate. The gate includes a gate dielectric layer and a gate electrode layer. The gate dielectric layer includes a gate oxide layer 1071, a polysilicon layer 1072 and a dielectric layer 1073. The gate oxide layer 1071 is on the channel and the silicon carbide epitaxial layer. The polysilicon layer 1072 is on the gate oxide layer 1071. The dielectric layer 1073 surrounds the oxide layer 1071 and the polysilicon layer 1072. The gate electrode layer includes a gate metal layer 108, which is on the polysilicon layer 1072.

[0065] In a specific example, such as Figure 1 As shown in (h), a gate oxide layer 1071, a polysilicon layer 1072, and a dielectric layer 1073 are sequentially deposited on the channel and the silicon carbide epitaxial layer 1011. The polysilicon layer 1072 is on the gate oxide layer 1071, and the dielectric layer 1073 surrounds the oxide layer 1071 and the polysilicon layer 1072. Electrode openings are then made in the dielectric layer 1073. A gate metal layer 108 is then deposited on the polysilicon layer 1072 as the gate electrode layer.

[0066] Step S60: As Figure 1 (j) shows that a source electrode 109 is formed on the source region, which includes a first source region 105 and a second source region 106. The source electrode 109 is in contact with the first source region 105 and the second source region 106.

[0067] Specifically, such as Figure 1 (i) The source includes an ohmic contact metal (1051 and 1061) and a source metal, with the source metal on top of the ohmic contact metal. The methods for forming the ohmic contact metal and the source metal on the source region include, but are not limited to, chemical vapor deposition, physical vapor deposition or plasma-enhanced chemical vapor deposition.

[0068] Step S70: Form a drain on the side of the silicon carbide substrate away from the source and gate regions.

[0069] Specifically, the methods for forming the drain electrode include, but are not limited to, chemical vapor deposition, physical vapor deposition, or plasma-enhanced chemical vapor deposition of drain electrode metal.

[0070] Furthermore, the aforementioned drain metal may be, but is not limited to, at least one of titanium, nickel, platinum, and gold.

[0071] Understandably, to simplify the fabrication process, the ohmic contact metal layers of the gate region and the source region can be formed simultaneously.

[0072] Furthermore, there is no fixed order in which the source, gate, and drain are fabricated.

[0073] In a specific example, the first conductivity type is N-type, the second conductivity type is P-type; and / or

[0074] The first conductivity type is P-type, and the second conductivity type is N-type.

[0075] In a specific example, the first conductivity type is N-type, the second conductivity type is P-type, and in step S10, the material implanted for the first time is aluminum or arsenic, with a doping concentration of 10. 16 cm -3 ~10 19 cm -3 .

[0076] Specifically, in step S10, the material implanted for the first time is aluminum, and the doping concentration of the material implanted for the first time is 10. 17 cm -3 ~10 18 cm -3 The first multi-step injection was performed using energy ranging from 10 keV to 1000 keV.

[0077] In step S20, the material implanted for the second time is nitrogen or phosphorus, with a doping concentration of 10. 18 cm -3 ~10 22 cm -3 .

[0078] Specifically, in step S20, the material implanted for the second time is nitrogen ions, and the doping concentration of the material implanted for the second time is 10. 21 cm -3 ~10 22 cm -3 A second multi-step injection was performed using energies ranging from 10 keV to 500 keV.

[0079] In step S30, the material implanted for the third time is aluminum or arsenic, with a doping concentration of 10. 18 cm -3 ~10 22 cm -3 .

[0080] Specifically, in step S30, the material implanted for the third time is aluminum ions, and the doping concentration of the material implanted for the third time is 10.21 cm -3 ~10 22 cm -3 A third multi-step injection was performed using energy ranging from 10 keV to 1000 keV.

[0081] Understandably, the above example only uses N-type as the first conductivity type and P-type as the second conductivity type. If the first conductivity type is P-type and the second conductivity type is N-type, the doping material and doping concentration can be conventionally selected according to the actual situation.

[0082] In the above-mentioned method for fabricating silicon carbide semiconductor devices, the method of forming short channels by adjusting the mask layer thickness and the injection angle can be precisely controlled by the process parameters of the equipment. That is, the required channel length can be controlled by adjusting the process parameters. Compared with the existing photolithography and self-aligned formation methods, it has higher controllability of photolithography and etching.

[0083] Furthermore, the present invention also provides a silicon carbide semiconductor device, which is obtained by the above-described method for preparing a silicon carbide semiconductor device.

[0084] The present invention further provides an electronic product comprising the aforementioned silicon carbide semiconductor device.

[0085] Understandably, electronic products include electronic components such as integrated circuits, resistors, and capacitors.

[0086] This invention differs from traditional methods that use large-angle implantation to form channels. Traditional methods involve adjusting the angle during P-well implantation to create a P-well beneath the mask, while N+ implantation has no angle to form the channel. However, this method results in a gradient in channel doping concentration, with the P-well concentration decreasing from N+ to the JFET region, thus affecting threshold voltage stability. In this invention, the desired short channel width is formed by adjusting the mask layer thickness and implantation angle. Both the mask layer thickness and the implantation angle can be precisely controlled through the equipment's process parameters; that is, the required channel length can be controlled by adjusting the process parameters. This method avoids changes in P-well concentration and creates an N- region at the N+ edge, which enhances the short-circuit capability of the MOSFET.

[0087] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The embodiments described above are merely illustrative of several implementations of the present invention, designed to facilitate a detailed understanding of the technical solutions of the present invention, but should not be construed as limiting the scope of protection of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the scope of protection of the present invention. It should be understood that technical solutions obtained by those skilled in the art based on the technical solutions provided by the present invention through logical analysis, reasoning, or limited experimentation are all within the scope of protection of the appended claims. Therefore, the scope of protection of this invention patent should be determined by the content of the appended claims, and the specification and drawings can be used to interpret the content of the claims.

Claims

1. A method for fabricating a silicon carbide semiconductor device, characterized in that, Includes the following steps: S10: A first mask layer is formed on one side of a silicon carbide substrate layer, and a first implantation is performed to form a well region. The surface of the well region is flush with the implantation surface of the silicon carbide substrate layer. The silicon carbide substrate layer is of a first conductivity type, and the well region is of a second conductivity type. The first conductivity type and the second conductivity type are opposite in conductivity type. The thickness of the first mask layer is 0.1 μm to 10 μm. S20: A second mask layer is formed on the well region. First source regions are formed on both sides of the first mask layer through the second mask layer and the first mask layer. The first source regions are formed by a second implantation of a material of a first conductivity type into the well region. The implantation direction is at an angle of 10° to 70° with the normal. A channel is formed between the first source region and the silicon carbide substrate layer below the first mask layer. The thickness of the first mask layer is D, the angle with the normal during implantation is α, and the width of the channel is L = D × tanα. When forming the first source region on one side, the second mask layer leaves a gap in the area adjacent to the first mask layer on one side to leave space for the first source region and the channel on the predetermined side. When forming the first source region on the other side, the second mask layer leaves a gap in the area adjacent to the first mask layer on the other side to leave space for the first source region and the channel on the predetermined other side. S30: Using a material of the second conductivity type, a third implantation is performed into the region of the well region other than the first source region and the channel to form a second source region, the well region surrounding the first source region and the second source region, to fabricate a basic device structure; S40: Activate the basic device structure.

2. The method for fabricating a silicon carbide semiconductor device as described in claim 1, characterized in that, The following steps are included after step S40: S50: A gate is formed on the well region and the silicon carbide substrate layer; S60: A source electrode is formed on the source region, wherein the source region includes a first source region and a second source region, the source electrode is in contact with the first source region, and the source electrode is in contact with the second source region; S70: A drain is formed on the side of the silicon carbide substrate away from the source region and the gate.

3. The method for fabricating a silicon carbide semiconductor device as described in claim 1, characterized in that, In step S20, the angle between the second injection direction and the normal is 40°~50°.

4. The method for fabricating a silicon carbide semiconductor device as described in claim 1, characterized in that, In step S10, the thickness of the first mask layer is 0.5 μm to 5 μm.

5. The method for fabricating a silicon carbide semiconductor device as described in claim 1, characterized in that, The silicon carbide substrate includes a silicon carbide substrate and a silicon carbide epitaxial layer disposed on the silicon carbide substrate, the first mask layer is disposed on the silicon carbide epitaxial layer, and the silicon carbide epitaxial layer surrounds the well region.

6. The method for fabricating a silicon carbide semiconductor device as described in claim 5, characterized in that, The silicon carbide substrate has a thickness of 100 μm to 500 μm and a substrate resistivity of 0.01 Ohm·cm to 0.1 Ohm·cm; and / or The thickness of the silicon carbide epitaxial layer is 3 μm to 200 μm, and the doping concentration is 10. 13 cm -3 ~10 17 cm -3 .

7. The method for fabricating a silicon carbide semiconductor device according to any one of claims 1 to 6, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type; and / or The first conductivity type is P-type, and the second conductivity type is N-type.

8. The method for fabricating a silicon carbide semiconductor device as described in claim 7, characterized in that, The first conductivity type is N-type, the second conductivity type is P-type, and in step S10, the material implanted for the first time is aluminum or arsenic, with a doping concentration of 10. 16 cm -3 ~10 19 cm -3 ; and / or In step S20, the material implanted for the second time is nitrogen or phosphorus, with a doping concentration of 10. 18 cm -3 ~10 22 cm -3 ; and / or In step S30, the material implanted for the third time is aluminum or arsenic, with a doping concentration of 10. 18 cm -3 ~10 22 cm -3 .

9. A silicon carbide semiconductor device, characterized in that, The silicon carbide semiconductor device is obtained by the method of fabrication according to any one of claims 1 to 8.

10. An electronic product, characterized in that, It includes the silicon carbide semiconductor device as described in claim 9.

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