Semiconductor structure and preparation method thereof

Abstract

The present disclosure provides a semiconductor structure and a method for preparing the same. The semiconductor structure has a substrate having a first upper surface. An active region is surrounded by an insulating region in the substrate. An embedded power line and an embedded signal line are disposed within the substrate and in the active region. A first circuit layer is disposed on the first upper surface of the substrate to cover the embedded power line and the embedded signal line. A second circuit layer is disposed on the upper surface of the substrate and is separated from the first circuit layer. A unit cell capacitor is disposed on the first circuit layer and is electrically coupled to the first circuit layer.

Description

Technical Field

[0001] This application claims priority to and the benefit of U.S. regular application No. 17 / 014,282, filed on September 8, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a semiconductor structure having an embedded power line and an embedded signal line and a method for manufacturing the same. Background Art

[0003] Dynamic random access memory (DRAM) is a semiconductor device used to store bits of data in separate cell capacitors within an integrated circuit. DRAM typically takes the form of trench capacitor DRAM cells and stacked capacitor DRAM cells. In stacked capacitor DRAM cells, the cell capacitors are formed above the read / write transistors. An advanced method for fabricating read / write transistors uses a buried gate electrode, which includes a gate electrode and a word line formed in a gate trench within an active region.

[0004] Over the past few decades, with the continuous advancement of semiconductor manufacturing technology, the size of electronic components has also shrunk accordingly. As the size of a cell transistor shrinks to a few nanometers, short-channel effects may occur, which may cause a significant decrease in the performance of the cell transistor.

[0005] To overcome performance issues, it is highly desirable to improve the fabrication methods of the unit cell transistors in semiconductor structures.

[0006] The above description of “prior art” is merely to provide background technology, and does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the Invention

[0007] One embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate having a first upper surface. An active region is surrounded by an insulating region in the substrate. An embedded power line and an embedded signal line are disposed within the substrate and located in the active region. A first circuit layer is disposed on the first upper surface of the substrate and covers the embedded power line and the embedded signal line. A second circuit layer is disposed on the first upper surface of the substrate and is separated from the first circuit layer. A unit cell capacitor is disposed on the first circuit layer and electrically coupled to the first circuit layer.

[0008] In some embodiments, the embedded power line is disposed in a central portion of the active region, and the embedded signal line is disposed in a peripheral portion of the active region.

[0009] In some embodiments, the buried power line is far away from the insulating region, and the buried signal line is close to the insulating region.

[0010] In some embodiments, the semiconductor structure further includes a word line structure disposed on the unit cell capacitor.

[0011] In some embodiments, the semiconductor structure further includes an interlayer dielectric encapsulating the cell capacitor and the word line structure.

[0012] In some embodiments, the semiconductor structure further includes a second conductive material disposed in a through-hole passing through the interlayer dielectric.

[0013] In some embodiments, the semiconductor structure further includes a bit line structure disposed on the interlayer dielectric and above the word line structure.

[0014] In some embodiments, the buried power line, the buried signal line, and the word line structure extend along a first direction, and the bit line structure extends along a second direction, and the second direction is substantially orthogonal to the first direction.

[0015] In some embodiments, the second conductive material in the through-hole extends along a third direction, which is perpendicular to the first direction and the second direction.

[0016] In some embodiments, the embedded power line and the embedded signal line are arranged along the second direction.

[0017] In some embodiments, the word line structure and the bit line structure form a memory array, wherein the memory array has a four square feature size (4F 2 ) a layout.

[0018] In some embodiments, the unit cell capacitor is interposed between the first circuit layer and the word line structure, and the word line structure is interposed between the unit cell capacitor and the bit line structure.

[0019] Another embodiment of the present disclosure provides a method for fabricating a semiconductor structure. The method comprises the following steps: providing a substrate having a first upper surface; forming an insulating region in the substrate to surround an active region; forming a recess in the active region; disposing a first conductive material in the recess to form a buried power line and a buried signal line; forming a first circuit layer and a second circuit layer on the upper surface of the substrate, wherein the first circuit layer covers the buried power line and the buried signal line, and the second circuit layer is disposed separately from the first circuit layer; and forming a unit cell capacitor on the first circuit layer.

[0020] In some embodiments, the fabrication method further includes: forming a word line structure on the unit cell capacitor; and forming an interlayer dielectric to encapsulate the unit cell capacitor and the word line structure.

[0021] In some embodiments, after the interlayer dielectric is formed, a through hole is formed through the interlayer dielectric to partially expose the second circuit layer.

[0022] In some embodiments, after the through-hole is formed, a second conductive material is deposited to fill the through-hole.

[0023] In some embodiments, after forming the second conductive material, a bit line structure is formed on the interlayer dielectric and above the word line structure.

[0024] In some embodiments, the bit line structure is electrically coupled to the word line structure and the cell capacitor.

[0025] In some embodiments, the bit line structure is electrically coupled to the word line structure, the cell capacitor, and the first circuit layer.

[0026] In some embodiments, the second conductive material electrically connects the bit line structure to the second circuit layer.

[0027] The above has provided a fairly broad overview of the technical features and advantages of the present disclosure, allowing for a better understanding of the detailed description of the present disclosure below. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure pertains that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. It should also be understood by those skilled in the art to which the present disclosure pertains that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] A more complete understanding of the disclosure of this application may be obtained by referring to the embodiments and claims in conjunction with the drawings, in which like reference numerals refer to like elements.

[0029] Figure 1A A schematic top view of a portion of a first memory array illustrating some embodiments of the present disclosure, wherein the first memory array has a 6F 2 layout.

[0030] Figure 1B A schematic top view of a portion of a second memory array illustrating some embodiments of the present disclosure, wherein the first memory array has a 4F 2 layout.

[0031] Figure 2 A schematic cross-sectional view of a semiconductor structure illustrating some embodiments of the present disclosure.

[0032] Figure 3 Some embodiments of the present disclosure are based on Figure 2 Schematic diagram of a process for preparing a semiconductor structure.

[0033] Figures 4 to 22 Some embodiments of the present disclosure are based on Figure 3 A schematic cross-sectional view of the manufacturing stages of the preparation method in sequence.

[0034] Figure 23 Some embodiments of the present disclosure are illustrated in Figure 22 Schematic top view of the semiconductor structure in FIG.

[0035] The description of the accompanying drawings is as follows:

[0036] 100: Base

[0037] 102: Pad oxide layer

[0038] 104: Pad nitride layer

[0039] 106: first photoresist pattern

[0040] 110: First dielectric material

[0041] 112: Adulterants

[0042] 114: Impurity region

[0043] 120: Second photoresist pattern

[0044] 130: Isolation pad

[0045] 140: First conductive material

[0046] 150: First circuit layer

[0047] 152: Second circuit layer

[0048] 160: Landing Pad

[0049] 170: Unit cell capacitor

[0050] 180: First conductive plug

[0051] 190: Character Line Structure

[0052] 200: Second conductive plug

[0053] 210: Interlayer dielectric

[0054] 220: Second conductive material

[0055] 230: Bit line structure

[0056] 300: Preparation method

[0057] A1: First memory array

[0058] A2: Second memory array

[0059] AA: Active Area

[0060] AA1: Active area

[0061] BB: insulation zone

[0062] BL1: bit line

[0063] BL2: bit line

[0064] BPL: Buried Power Line

[0065] BSL: buried signal line

[0066] D1: First direction

[0067] D2: Second direction

[0068] D3: Third direction

[0069] O1: First opening

[0070] O2: Second opening

[0071] S1: upper surface

[0072] S2: upper surface

[0073] ST1: Semiconductor structure

[0074] T1: Insulation trench

[0075] T2: Depression

[0076] T3: Perforation

[0077] w1: predetermined distance

[0078] WL1: character line

[0079] WL2: character line

[0080] S101: Steps

[0081] S103: Steps

[0082] S105: Steps

[0083] S107: Steps

[0084] S109: Steps

[0085] S111: Steps

[0086] S113: Steps

[0087] S115: Steps

[0088] S117: Steps

[0089] S119: Steps

[0090] S121: Steps

[0091] S123: Steps

[0092] S125: Steps

[0093] S127: Steps DETAILED DESCRIPTION

[0094] Specific language will now be used to describe the embodiments or examples of the present disclosure shown in the accompanying drawings. It should be understood that the scope of the present disclosure is not intended to be limited thereby. Any modifications or improvements to the described embodiments, as well as any further applications of the principles described in this document, will be considered as generally occurring by those of ordinary skill in the art. Element numbers may be repeated throughout the embodiments, but this does not necessarily mean that the features of one embodiment are applicable to another embodiment, even if they share the same element number.

[0095] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe different elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a "first element," "component," "region," "layer," or "section" discussed below could be referred to as a second element, component, region, layer, or section without departing from the teachings herein.

[0096] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the present invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, the terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0097] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0098] In silicon-on-insulator (SOI) technology, the floating body effect (FBE) is a phenomenon in which the threshold voltage (Vth) of a transistor varies because the body of the transistor does not have a specific fixed voltage value during operation. In other words, the threshold voltage of the transistor depends on its bias voltage and the history of carrier recombination processes. The floating body effect causes voltage fluctuations in the body region of an SOI metal-oxide-semiconductor field-effect transistor (MOSFET), which can have detrimental effects on the operation of many SOI devices. The most common of these detrimental effects are the kink effect and the bipolar effect. As a channel region of a device is partially depleted and a high drain voltage is applied, the electric field generated in the device can lead to impact ionization near a drain region.

[0099] Dynamic random access memory (DRAM) was developed to overcome inherent scaling limitations and improve the cost-effectiveness of mass production. DRAM scaling has been significantly improved by using a trench capacitor structure and a stacked capacitor structure. The size of a unit memory cell with one unit cell transistor and one unit cell capacitor has been reduced by evolving a layout of a memory array from a hexagonal feature size (6F) to a smaller size (6F). 2 ) evolved into a square characteristic size (4F 2 ). In particular, the minimum feature size F shrinks with each new generation, and when the unit cell size is generally αF 2 , α is a coefficient that decreases as the generations progress.

[0100] 6F 2 With 4F 2 The main difference between the layouts is 4F 2 The unit cell structure is realized using vertical pillar transistor (VPT), ​​and the 6F 2 The unit cell structure is implemented using a buried channel array transistor (BCAT). Because of the minimum area of ​​the unit cell, the 4F 2 The unit cell is a promising architecture for cost-effective and scalable DRAM chips. 2 The unit cell can be compared to 6F 2 The VPT element exhibits excellent retention characteristics in static mode, and even in pillar-type channels, the floating body effect can be reduced by using a gradual junction profile.

[0101] To avoid the floating body effect and reduce leakage current in transistors for low-power applications, non-silicon-based materials are being used in 4F 2 Unit cell structures exhibit high potential due to their inherent high band gap. However, high-temperature processes can affect the electrical properties of non-silicon-based materials. For example, many non-silicon-based materials are heat-sensitive and may degrade during high-temperature processes. The fabrication of a unit cell capacitor typically involves numerous high-temperature processes.

[0102] Therefore, when using heat-sensitive non-silicon-based materials in the manufacture of unit cell transistors, the process of unit cell capacitors and unit cell transistors should be separated and a capacitor-first process should be adopted. However, it is not easy to use in practice because at 4F 2 DRAMs with this technology face technical difficulties, as the cell transistors must be vertical. Reducing the area of ​​the cell transistors and capacitors is extremely difficult. For example, due to limited space, metal routing for multiple power lines and multiple signal lines is challenging. Additional metal routing must be designed into multiple additional contact areas.

[0103] In manufacturing 4F 2 In the capacitor-first process of DRAM, the space originally designed for metal wiring is blocked by the unit cell capacitor. Therefore, in the present disclosure, the power line and the signal line are buried in multiple recesses, and the formation method of the recesses is the same as that in the 6F 2 The multiple gate trenches in DRAM manufacturing are identical.

[0104] Figure 1A A schematic top view of a portion of a first memory array A1 illustrating some embodiments of the present disclosure, wherein the first memory array A1 has a 6F 2 Layout. Figure 1A In some embodiments, a plurality of word lines WL1 are orthogonal to a plurality of bit lines BL1. In some embodiments, a width of each word line WL1 and a width of each bit line BL1 are 1F, where F is a minimum feature size. In some embodiments, a distance between any two adjacent word lines WL1 and a distance between any two adjacent bit lines BL1 are also 1F. In 6F 2 In the layout of FIG, the active area AA1 is arranged diagonally relative to the extension direction of the word line WL1 or the bit line BL1. In the active area AA1, a plurality of memory cells (not shown) are located at the intersection of the word line WL1 and the bit line BL1 and are electrically coupled to the word line WL1 and the bit line BL1. Figure 1A The area of ​​a unit memory cell is about 3F×2F=6F 2, as shown by the dotted rectangle.

[0105] Figure 1B A schematic top view of a portion of a second memory array A2 illustrating some embodiments of the present disclosure, wherein the first memory array A2 has a 4F 2 Layout. Figure 1B In some embodiments, the word lines WL2 are orthogonal to the bit lines BL2. In some embodiments, the width of each word line WL2 and the width of each bit line BL2 are 1F. In some embodiments, the distance between any two adjacent word lines WL2 and the distance between any two adjacent bit lines BL2 are also 1F. 2 In the layout of FIG, the active area AA2 is set at the intersection of the word line WL2 and the bit line BL2. In addition, a unit memory cell (not shown) is located in the active area AA2 and is electrically coupled to the word line WL2 and the bit line BL2. Figure 1B The area of ​​the unit memory cell is about 2F×2F=4F 2 , as shown by the square dotted line.

[0106] Figure 2 A schematic cross-sectional view of a semiconductor structure ST1 illustrating some embodiments of the present disclosure is provided. The semiconductor structure ST1 has a substrate 100 having a first upper surface S1. An insulating trench T1 is disposed in the substrate 100 and filled with a first dielectric material 110. The insulating trench T1 filled with the first dielectric material 110 forms an insulating region BB in the substrate 100. An active region AA is surrounded by the insulating region BB. The active region AA is doped to form an impurity region 114. A recess T2 is disposed in the active region AA, wherein the depth of the recess T2 is less than the depth of the insulating trench T1. The impurity region 114 is divided into a plurality of impurity regions 114 by a plurality of recesses T2.

[0107] An isolation liner 130 is conformally disposed within the recess T2. A first conductive material 140 is disposed within the recess T2 and is surrounded by the isolation liner 130. The first conductive material 140 located in a central portion of the active area AA forms a buried power line BPL, while the first conductive material 140 located in a peripheral portion of the active area AA forms a buried signal line BSL. The buried power line BPL and the buried signal line BSL extend along a first direction D1. Furthermore, a plurality of buried power lines BPL and a plurality of buried signal lines BSL are arranged along a second direction D2, which is orthogonal to the first direction D1.

[0108] A first circuit layer 150 and a second circuit layer 152 are disposed on the first upper surface S1 of the substrate 100 and are separated from each other by a predetermined distance w1. The first circuit layer 150 covers the embedded power lines BPL and the embedded signal lines BSL and is electrically coupled to the embedded power lines BPL and the embedded signal lines BSL. The second circuit layer 152 does not cover the embedded power lines BPL or the embedded signal lines BSL.

[0109] A cell capacitor 170 is disposed on a landing pad 160, which is located on the first circuit layer 150. The cell capacitor 170 is electrically coupled to the first circuit layer 150 via the landing pad 160. A word line structure 190 is disposed on a first conductive plug 180, which is disposed on the cell capacitor 170. The word line structure 190 is electrically coupled to the cell capacitor 170 via the first conductive plug 180. The cell capacitor 170 is interposed between the first circuit layer 150 and the word line structure 190. The word line structure 190 extends along a first direction D1. In some embodiments, multiple word line structures 190 are arranged along a second direction D2.

[0110] A second conductive plug 200 is disposed on the wordline structure 200. The stack of the landing pad 160, the cell capacitor 170, the first conductive plug 180, the wordline structure 190, and the second conductive plug 200 extends along a third direction D3, which is substantially orthogonal to both the first direction D1 and the second direction D2. An interlayer dielectric 210 having a second upper surface S2 encapsulates the landing pad 160, the cell capacitor 170, the first conductive plug 180, the wordline structure 190, and the second conductive plug 200.

[0111] A through-hole T3 penetrates the interlayer dielectric 210 and exposes the second circuit layer 152. The through-hole T3 is filled with a second conductive material 220. A bit line structure 230 (having a second upper surface S3) is disposed on the word line structure 190. Furthermore, the word line structure 190 is interposed between the cell capacitor 170 and the bit line structure 230. The bit line structure 230 extends in the second direction D2. The second conductive material 220 deposited in the through-hole T3 substantially forms a bit line contact (BLC) electrically connecting the bit line structure 230 to the second circuit layer 152 and to the impurity region 114. The bit line contact extends in the third direction D3.

[0112] Figure 3 Some embodiments of the present disclosure are based on Figure 2 3 is a flow chart of a method 300 for manufacturing a semiconductor structure ST1. Figures 4 to 22 Some embodiments of the present disclosure are based on Figure 3Schematic cross-sectional view of the manufacturing method 300 in sequence of various manufacturing stages.

[0113] Please refer to Figure 4 ,in accordance with Figure 3 In step S101, a substrate 100 is provided. In some embodiments, substrate 100 may include a single crystal silicon substrate, a compound semiconductor substrate, a silicon-on-insulator (SOI) substrate, or other suitable substrate. The compound substrate may be, for example, a silicon germanium (SiGe) substrate or a gallium arsenide (GaAs) substrate. Substrate 100 has a first top surface S1.

[0114] Please refer to Figures 5 to 9 ,in accordance with Figure 3 In step S103, an active region boundary process is performed on the substrate 100. In some embodiments, the active region boundary process is a shallow trench isolation (STI) formation process. First, please refer to Figure 5 A pad oxide layer 102 and a pad nitride layer 104 are sequentially formed on the first upper surface S1 of the substrate 100. In some embodiments, the pad oxide layer 102 comprises silicon oxide (SiO2), and the pad nitride layer 104 comprises silicon nitride (Si3N4). It should be understood that the pad oxide layer 102 and the pad nitride layer 104 may be replaced by other suitable materials that provide high etching selectivity relative to the substrate 100. In some embodiments, the pad oxide layer 102 may be deposited by an existing deposition process, such as a chemical vapor deposition (CVD) process, or by thermally oxidizing an upper thin portion of the substrate 100 in a furnace. The pad oxide layer 102 may be used to reduce interfacial stress between the substrate 100 and the subsequently formed pad nitride layer 104. In some embodiments, the pad nitride layer 104 may be formed using a low pressure chemical vapor deposition (LPCVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. The pad nitride layer 104 may be used as a barrier layer to prevent water or oxygen molecules from diffusing into the substrate.

[0115] Please refer to Figure 6 A first photoresist pattern 106 is formed on the pad nitride layer 104 to define a location of an insulating region. In some embodiments, the first photoresist pattern 106 has a plurality of first openings O1, each of which exposes the upper surface of the pad nitride layer 104. In particular, forming the first photoresist pattern 106 includes at least sequentially coating a first photoresist layer (not shown) on the pad nitride layer 104, exposing the first photoresist layer to radiation using a first photomask (not shown) and a lithography process, and developing the exposed first photoresist layer.

[0116] Next, please refer to Figure 7The first photoresist pattern 106 is used as an etching mask to etch the substrate 100, the pad oxide layer 102, and the pad nitride layer 104. Specifically, portions of the substrate 100, the pad oxide layer 102, and the pad nitride layer 104 that extend through the first opening O1 are removed. Thus, an insulating trench T1 is formed in the substrate 100. The first photoresist pattern 106 is then removed using an ashing process or a wet stripping process.

[0117] Next, please refer to Figure 8 A wet stripping process is then used to remove the pad oxide layer 102 and the pad nitride layer 104 covering the isolation trench T1. At this time, the first upper surface S1 of the substrate 100 is exposed again.

[0118] Next, please refer to Figure 9 The insulating trench T1 is filled with a first dielectric material 110 using a CVD process or a spin-on coating process. In some embodiments, the first dielectric material 110 includes at least one of silicon oxide (SiO2), tetraethyl orthosilicate (TEOS), boron phosphorussilicate glass (BPSG), and undoped silicate glass (USG). In some embodiments, after the insulating trench T1 is filled with the first dielectric material 110, a chemical mechanical polishing (CMP) process may be performed to planarize a top surface of the first dielectric material 110 so that the top surface of the first dielectric material 110 does not protrude above the top surface S1 of the substrate 100.

[0119] Please still refer to Figure 9 The insulating trench T1 filled with the first dielectric material 110 forms an insulating region BB. In some embodiments, the insulating region BB can be disposed at predetermined intervals in the substrate 100. Furthermore, an active region AA is surrounded by the insulating region BB, and multiple active regions AA can be arranged in the substrate 100 in an alternating manner with the insulating region BB.

[0120] Please refer to Figure 10 ,in accordance with Figure 3In step S105, an ion implantation process is performed on the substrate 100. In particular, the ion implantation process may include one or more doping processes. For example, a dopant 112 may be implanted into the substrate 100 to form an impurity region 114 in the active region AA. The impurity region 114 is surrounded by the insulating region BB, and the lower surface of the impurity region 114 may be located at a predetermined depth from the first upper surface S1 of the substrate 100. In some embodiments, when the dopant 112 includes phosphorus (P) or arsenic (As), the impurity region 114 may be an n-type doped region. In this case, when the dopant 112 includes boron (B), gallium (Ga), or indium (In), the impurity region 114 may be a p-type doped region. In this case, the impurity region 114 has a plurality of electron holes as majority carriers. In some embodiments, an annealing process may be performed to repair damage caused by the ion implantation process and activate the dopants 112 .

[0121] Please refer to Figure 11 and Figure 12 ,in accordance with Figure 3 In step S107, a recess forming process is performed on the substrate 100. First, please refer to Figure 11 A second photoresist pattern 120 is formed on the substrate 100 to define a plurality of recessed locations. In some embodiments, the second photoresist pattern 120 includes a plurality of second openings O2, each of which exposes an upper surface of the impurity region 114. Specifically, forming the second photoresist pattern 120 includes at least sequentially coating a second photoresist layer (not shown) on the active region AA and the insulating region BB, exposing the second photoresist layer to radiation using a second photomask (not shown) and a lithography process (not shown), and developing the exposed second photoresist layer.

[0122] Next, please refer to Figure 12 , using the second photoresist pattern 120 as an etching mask to etch the active area AA. In particular, some portions of the active area AA exposed by the second opening O2 are removed. Therefore, a plurality of recesses T2 are formed in the active area AA, and then the second photoresist pattern 120 is removed using an ashing process or a wet stripping process. In some embodiments, the depth of the recess T2 is less than the depth of the insulating trench T1. In some embodiments, the recess T2 is a linear channel extending in any direction in the active area. Therefore, the impurity region 114 is divided into several impurity regions 114 by the recess T2. In some embodiments, the lower surfaces of the impurity regions 114 are higher than the lower surfaces of the recesses T2.

[0123] Please refer to Figure 13 ,in accordance with Figure 3In step S109, an isolation liner 130 is formed on the substrate 100. In particular, first, the isolation liner 130 is deposited on the active area AA and the insulating area BB, and is conformally formed in the recess T2. Then, a CMP process is performed to remove some portions of the isolation liner 130 located on the first upper surface S1. Therefore, some remaining portions of the isolation liner 130 are arranged in a straight line at each inner sidewall of the recess T2. In some embodiments, the manufacturing technology of the isolation liner 130 includes using a CVD process. Preferably, the manufacturing technology of the isolation liner 130 includes using an atomic layer deposition (ALD) deposition to allow the formation of a highly conformal isolation liner 130 with a more uniform thickness. In some embodiments, the isolation liner 130 includes silicon oxide (SiO2) or other suitable materials.

[0124] Please refer to Figure 14 ,in accordance with Figure 3 In step S111, a first conductive material 140 is formed on the substrate 100. Specifically, the first conductive material 140 is first deposited on the active area AA and the insulating area BB, completely filling the recess T2 aligned with the isolation liner 130. Next, a CMP process is performed to remove the first conductive material 140 on the first top surface S1. As a result, the first conductive material 140 surrounded by the isolation liner 130 remains in the recess T2.

[0125] In some embodiments, the first conductive material 140 is formed using a CVD process, a physical vapor deposition (PVD) process, or an electroplating process. In some embodiments, the first conductive material 140 comprises various metals, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or other suitable materials. In some embodiments, before the first conductive material 140 is deposited on the isolation liner 130, a metal seed layer (not shown) is conformally formed on the isolation liner 130 to facilitate adhesion between the isolation liner 130 and the subsequently formed first conductive material 140. The material of the metal seed layer is selected based on the material used in the first conductive material 140.

[0126] Please still refer to Figure 14 In some embodiments, the first conductive material 140 surrounded by the isolation liner 130 in the substrate 100 forms a signal line or a power line. In particular, the first conductive material 140 located at the center of the active area AA forms a buried power line BPL, and the first conductive material 140 located at the periphery of the active area AA forms a buried signal line BSL. In other words, the buried power line BPL is far away from the insulating area BB, and the buried signal line BSL is close to the insulating area BB. In some embodiments, as Figure 14As shown, the embedded power lines BPL and embedded signal lines BSL extend in a first direction D1. Furthermore, multiple embedded power lines BPL and multiple embedded signal lines BSL extend along a second direction D2, which is orthogonal to the first direction D1. The embedded power lines BPL can provide a supply voltage (Vcc) to power the electronic components subsequently formed thereon. The embedded signal lines BSL can be electrically coupled to multiple signal transmission pins (not shown), which are used to transmit various data signals (DQ) or data strobe signals (DQS).

[0127] Please refer to Figure 15 ,in accordance with Figure 3 In step S113, a first circuit layer 150 and a second circuit layer 152 are formed on the substrate 100. In particular, the first circuit layer 150 and the second circuit layer 152 are disposed on the first upper surface S1 of the substrate 100 and are separated from each other by a predetermined distance w1. In some embodiments, the first circuit layer 150 covers a plurality of buried power lines BPL and a plurality of buried signal lines BSL, and the first circuit layer 150 is electrically coupled to the buried power lines BPL and the buried signal lines BSL. The second circuit layer 152 does not cover the buried power lines BPL or the buried signal lines BSL. In some embodiments, the first circuit layer 150 and the second circuit layer 152 can function as a sense amplifier (SA) circuit or a sub-word line driver (SWD) circuit. The first circuit layer 150 and the second circuit layer 152 will be electrically coupled to a plurality of electronic components subsequently formed thereon.

[0128] Please refer to Figure 16 ,in accordance with Figure 3 In step S115, a plurality of unit cell capacitors 170 are formed on the substrate 100. In particular, the unit cell capacitors 170 are electrically coupled to the first circuit layer 150 via a plurality of landing pads 160, wherein one unit cell capacitor 170 is disposed on each landing pad 160 formed on the first circuit layer 150. In addition, the unit cell capacitors 170 are electrically coupled to the impurity region 114. The unit cell capacitors 170 are used to store a charge, which is a bit representing information. The formation of the landing pads 160 may include at least one lithography process, an etching process, and a deposition process well known in the art. In some embodiments, the material of the landing pads 160 includes tungsten (W), copper (Cu), aluminum (Al), or an alloy thereof, but is not limited thereto.

[0129] It should be understood that Figure 16The illustrated unit cell capacitor 170 is for illustration purposes only and does not illustrate the detailed structure of the unit cell capacitor 170. In some embodiments, the unit cell capacitor 170 includes at least a lower electrode, an upper electrode, and a capacitor dielectric material, wherein the capacitor dielectric material is surrounded by the lower electrode and the upper electrode. The lower electrode and the upper electrode can be a conductor, such as a metal, an alloy, or polysilicon. The capacitor dielectric material can include one or more high-k dielectric materials, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), or the like. In some embodiments, the unit cell capacitor 170 can have any shape known in the art for capacitors. For example, the unit cell capacitor 170 can have a simple shape, such as a rectangle, or a complex shape, such as concentric cylinders or stacked disks.

[0130] Please refer to Figure 17 ,in accordance with Figure 3 In step S117, a plurality of word line structures 190 are formed on the substrate 100. In particular, the word line structures 190 are electrically coupled to the unit cell capacitors 170 via a plurality of first conductive plugs 180, wherein each word line structure 190 is disposed on a first conductive plug 180 formed on a unit cell capacitor 170. In some embodiments, the unit cell capacitor 170 is interposed between the first circuit layer 150 and the word line structures 190.

[0131] The formation of the first conductive plug 180 may include at least one lithography process, an etching process, and a deposition process known in the art. In some embodiments, the first conductive plug 180 is a conductor, such as metal, alloy, or polysilicon. It should be understood that Figure 17 The word line structure 190 shown is for illustration only, and the detailed structure of the word line structure 190 is not shown.

[0132] In some embodiments, wordline structure 190 includes at least a gate dielectric material, a gate electrode, and a gate spacer. The gate electrode is disposed on the gate dielectric material and the gate spacer. The gate dielectric material is surrounded by the gate spacer. In some embodiments, the gate dielectric material comprises silicon oxide or other suitable materials. In some embodiments, the gate electrode is a metal gate or a polysilicon gate, and the metal gate comprises tungsten, aluminum, copper, titanium, or other materials with an appropriate work function.

[0133] In some embodiments, the gate spacer is an insulator, which may include nitride, low-k dielectric, or other suitable materials. In some embodiments, the word line structure 190 may include a non-silicon-based material or a thermally sensitive material. In some embodiments, such as Figure 17As shown, the word line structures 190 extend in a first direction D1. In addition, the word line structures 190 are arranged along a second direction D2, which is perpendicular to the first direction D1.

[0134] Please refer to Figure 18 ,in accordance with Figure 3 In step S119, a plurality of second conductive plugs 200 are formed on the wordline structure 190. In particular, each second conductive plug 200 is disposed on a wordline structure 190. The formation of the second conductive plugs 200 may include at least one lithography process, an etching process, and a deposition process as is known in the art. In some embodiments, the second conductive plugs 200 are a conductor, such as a metal, an alloy, or polysilicon.

[0135] In some embodiments, the stack of landing pad 160, cell capacitor 170, first conductive plug 180, word line structure 190, and second conductive plug 200 extends along a third direction D3, which is substantially orthogonal to both first direction D1 and second direction D2. In some embodiments, the gate electrode in word line structure 190 can serve as a gate terminal of a cell capacitor, which is used to control word line structure 190. The first conductive plug 180 and the second conductive plug 200 immediately below and above word line structure 190 can serve as a source terminal and a drain terminal of the cell capacitor. The cell transistor serves as a switch for cell capacitor 170. That is, the cell transistor controls the charging and discharging of cell transistor 170.

[0136] Please refer to Figure 19 ,in accordance with Figure 3 In step S121, an interlayer dielectric 210 is formed on the substrate 100. In particular, the interlayer dielectric 210 covers the first circuit layer 150, the second circuit layer 152, and a portion of the impurity region 114. Furthermore, the interlayer dielectric 210 encapsulates the landing pad 160, the cell capacitor 170, the first conductive plug 180, the word line structure 190, and the second conductive plug 200.

[0137] In some embodiments, the interlayer dielectric 210 primarily comprises an oxide, such as silicon oxide or other suitable materials, and its fabrication technique includes a CVD process. In some embodiments, the interlayer dielectric 210 may include multiple steps. For example, in a first step, the interlayer dielectric 210 may be deposited to a level that is flush with the upper surface of the cell capacitor 170. In a second step, the interlayer dielectric 210 may be deposited to a level that is flush with the upper surface of the wordline structure 190. In a third step, the interlayer dielectric 210 may be deposited to completely cover the second conductive plug 200. After the third step, a CMP process is performed to planarize the interlayer dielectric 210, thereby exposing the upper surface of the second conductive plug 200. At this point, the interlayer dielectric 210 has a flat second upper surface S2 that is coplanar with the upper surface of the second conductive plug 200.

[0138] Please refer to Figure 20 ,in accordance with Figure 3 In step S123, a plurality of through-holes T3 are formed to pass through the interlayer dielectric 210. In particular, the formation of the through-holes T3 includes at least forming a photoresist pattern (not shown) on the interlayer dielectric 210, etching the interlayer dielectric 210 until the second circuit layer 152 is exposed, and then removing the photoresist pattern.

[0139] Please refer to Figure 21 ,in accordance with Figure 3 In step S125, a second conductive material 220 is formed on the substrate 100. Specifically, the second conductive material 220 is first deposited on the interlayer dielectric 210 and completely fills the through-hole T3. Next, a CMP process is performed to remove the second conductive material 220 located on the second top surface S2. As a result, the second conductive material 220 remains in the through-hole T3 surrounded by the interlayer dielectric 210. In some embodiments, the second conductive material 220 is formed using a CVD process, a PVD process, or an electroplating process. In some embodiments, the second conductive material 220 includes various metals, such as aluminum, copper, tungsten, titanium, or other suitable materials.

[0140] Please refer to Figure 22 ,in accordance with Figure 3In step S127 of the embodiment, a bit line structure 230 is formed on the interlayer dielectric 210. In particular, the bit line structure 230 is disposed on the word line structure 190. In some embodiments, the word line structure 190 is interposed between the unit cell capacitor 170 and the bit line structure 230. In some embodiments, the manufacturing technology of the bit line structure 230 includes using a CVD process, a PVD process, or an electroplating process. In some embodiments, the bit line structure 230 is a conductor, such as a metal or polysilicon. Preferably, the bit line structure 230 is a metal alloy, such as tungsten silicide (SiW). In some embodiments, as Figure 22 As shown, the bit line structure 230 extends in the second direction D2. At this time, a semiconductor structure ST1 is generally formed, wherein the semiconductor structure ST1 mainly includes a memory array.

[0141] In some embodiments, the bit line structure 230 is electrically coupled to the word line structure 190 and the cell capacitor 170. The bit line structure 230 can be used to transmit a signal to the cell capacitor 170 so that data stored in the cell capacitor 170 can be read, or a signal can be stored as data or written to the cell capacitor 170. In some embodiments, the second conductive material 220 deposited in the through hole T3 is substantially a bit line contact (BLC), which electrically connects the bit line structure 230 to the second circuit layer 152 and to the impurity region 114. In some embodiments, the bit line contact extends in the third direction D3.

[0142] Figure 23 Some embodiments of the present disclosure are illustrated in Figure 22 Please refer to the top view of the semiconductor structure ST1. Figure 23 The buried power lines BPL, buried signal lines BSL, and word line structures 190 extend in a first direction D1, and the bit line structures 230 extend in a second direction D2, which is substantially perpendicular to the first direction D1. Thus, the multiple word line structures 190 and the multiple bit line structures 230 form the rows and columns of a memory array. Compared to the buried power lines BPL and buried signal lines BSL within the substrate 100, the word line structures 190 are dispersed within the substrate 100, so that the word line structures 190 are spatially higher than the buried power lines BPL and buried signal lines BSL.

[0143] However, the word line structure 190, the buried power line BPL and the buried signal line BSL are basically arranged along the second direction D2. The bit line structure 230 is more dispersed in the substrate 100 than the word line structure 190, so that the bit line structure 230 is higher in space than the word line structure 190. Figure 23A cell capacitor 170 is shown located at the intersection of each word line structure 190 and each bit line structure 230. In some embodiments, the word line structure 190 and the bit line structure 230 generally form a 4F 2 layout.

[0144] In the present disclosure, multiple power lines and multiple signal lines are embedded in the substrate, while multiple main components of a memory array are disposed on the substrate, such as word line structures, bit line structures, and unit cell capacitors. In addition, when heat-sensitive non-silicon-based materials are used in the manufacture of the unit cell transistors, a capacitor-first process is used to manufacture the 4F 2 Due to the minimized area of ​​multiple unit memory cells, the space available for metal wiring becomes limited, and metal wiring is an arrangement including multiple power lines and multiple signal lines adjacent to the main components. The present disclosure utilizes multiple recesses, which are generally used to accommodate the 6F 2 Multiple buried wordline structures are provided in the layout to accommodate the power lines and the signal lines. The advantages of placing the power lines and the signal lines in the recesses include saving space that would otherwise be used for metal wiring above the substrate. Therefore, there is no need to reserve space adjacent to the cell transistors or cell capacitors for metal wiring. Furthermore, the additional space allows for optimal adjustment of the configuration of the wordline structure, bitline structure, or cell capacitors disposed above the substrate.

[0145] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the processes described above.

[0146] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with this disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this application.

Claims

1. A semiconductor structure comprising: a substrate having a first upper surface; an active region surrounded by an insulating region in the substrate; An embedded power line and an embedded signal line are disposed in the substrate and located in the active area; a first circuit layer, disposed on the first upper surface of the substrate and covering the embedded power line and the embedded signal line; a second circuit layer disposed on the first upper surface of the substrate and separated from the first circuit layer, wherein the second circuit layer does not cover the embedded power line and the embedded signal line; and A unit cell capacitor is disposed on the first circuit layer and electrically coupled to the first circuit layer. 2 . The semiconductor structure according to claim 1 , wherein the buried power line is disposed in a central portion of the active region, and the buried signal line is disposed in a peripheral portion of the active region. 3 . The semiconductor structure as claimed in claim 1 , wherein the buried power line is farther from the insulating region than the buried signal line is from the insulating region. 4 . The semiconductor structure as claimed in claim 1 , further comprising a word line structure disposed on the unit cell capacitor. 5 . The semiconductor structure of claim 4 , further comprising an interlayer dielectric encapsulating the unit cell capacitor and the word line structure. 6 . The semiconductor structure of claim 5 , further comprising a second conductive material disposed in a through-hole passing through the interlayer dielectric. 7 . The semiconductor structure of claim 6 , further comprising a bit line structure disposed on the interlayer dielectric and above the word line structure. 8 . The semiconductor structure of claim 7 , wherein the buried power line, the buried signal line, and the word line structure extend along a first direction, and the bit line structure extends along a second direction, and the second direction is orthogonal to the first direction. 9 . The semiconductor structure according to claim 8 , wherein the second conductive material in the through-hole extends along a third direction, and the third direction is perpendicular to the first direction and the second direction. 10 . The semiconductor structure as claimed in claim 8 , wherein the buried power line is arranged along the second direction.

11. The semiconductor structure of claim 10, wherein the word line structure and the bit line structure form a memory array, wherein the memory array has a layout with four square feature sizes. 12 . The semiconductor structure of claim 10 , wherein the unit cell capacitor is interposed between the first circuit layer and the word line structure, and the word line structure is interposed between the unit cell capacitor and the bit line structure.

13. A method for preparing a semiconductor structure, comprising: Providing a substrate having a first upper surface; forming an insulating region in the substrate to surround an active region; forming a recess in the active region; Disposing a first conductive material in the recess to form an embedded power line and an embedded signal line; forming a first circuit layer and a second circuit layer on the upper surface of the substrate, wherein the first circuit layer covers the embedded power line and the embedded signal line, and the second circuit layer is disposed separately from the first circuit layer, wherein the second circuit layer does not cover the embedded power line and the embedded signal line; and A unit cell capacitor is formed on the first circuit layer.

14. The method for preparing a semiconductor structure according to claim 13, further comprising: forming a word line structure on the unit cell capacitor; as well as An interlayer dielectric is formed to encapsulate the unit cell capacitor and the word line structure. 15 . The method for fabricating a semiconductor structure according to claim 14 , wherein after the interlayer dielectric is formed, a through hole is formed to pass through the interlayer dielectric and partially expose the second circuit layer. 16 . The method for fabricating a semiconductor structure as claimed in claim 15 , wherein after the through-hole is formed, a second conductive material is deposited to fill the through-hole. 17 . The method for fabricating a semiconductor structure according to claim 16 , wherein after forming the second conductive material, a bit line structure is formed on the interlayer dielectric and above the word line structure. 18 . The method for fabricating a semiconductor structure according to claim 17 , wherein the bit line structure is electrically coupled to the word line structure and the unit cell capacitor. 19 . The method for fabricating a semiconductor structure according to claim 17 , wherein the bit line structure is electrically coupled to the word line structure, the unit cell capacitor, and the first circuit layer. 20 . The method for fabricating a semiconductor structure according to claim 17 , wherein the second conductive material electrically connects the bit line structure to the second circuit layer.

Images