Doherty power amplifier and radio frequency front end module

Abstract

The application discloses a Doherty power amplifier and a radio frequency front end module. The Doherty power amplifier comprises a carrier amplification circuit, a peak value amplification circuit, a bias circuit and a first gain adjustment circuit. The bias circuit is configured to output a first bias signal to the carrier amplification circuit or the peak value amplification circuit. The first gain adjustment circuit is configured to extract at least part of a current signal from the bias circuit to reduce the first bias signal output to the carrier amplification circuit or the peak value amplification circuit when the gain of the Doherty power amplifier shows an upward trend. The technical solution can improve the linearity of the Doherty power amplifier.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of radio frequency technology, and in particular to a Doherty power amplifier and a radio frequency front-end module. BACKGROUND

[0002] In recent years, 5G technology has become a research hotspot in the field of radio frequency technology. In the 5G communication system, one of the most critical components is the radio frequency power amplifier (PA). Because the 5G communication system has a high requirement for linearity, the Doherty power amplifier technology is generally used to greatly improve the efficiency of the radio frequency power amplifier.

[0003] The Doherty power amplifier (Doherty PA) is widely used because it can support a large modulation bandwidth and only requires a low baseband digital signal processing overhead. However, at present, the Doherty power amplifier cannot simultaneously obtain high efficiency and good linearity, resulting in poor overall performance of the Doherty power amplifier. SUMMARY

[0004] Embodiments of the present application provide a Doherty power amplifier and a radio frequency front-end module to solve the problem of poor linearity of the Doherty power amplifier.

[0005] A Doherty power amplifier includes a carrier amplification circuit, a peak amplification circuit, a bias circuit, and a first gain adjustment circuit.

[0006] The bias circuit is configured to output a first bias signal to the carrier amplification circuit or the peak amplification circuit.

[0007] The first gain adjustment circuit is configured to extract at least part of a current signal from the bias circuit to reduce the first bias signal output to the carrier amplification circuit or the peak amplification circuit when the gain of the Doherty power amplifier is in an upward trend.

[0008] Further, the first gain adjustment circuit is configured to extract at least part of a current signal from the bias circuit to reduce the first bias signal output to the carrier amplification circuit or the peak amplification circuit when a first gain difference value is less than a first threshold value; wherein the first gain difference value refers to the difference between the downward amplitude of the gain of the carrier amplification circuit and the upward amplitude of the gain of the peak amplification circuit in the same time period.

[0009] Further, the bias circuit includes a bias transistor; a first end of the bias transistor is configured to receive a signal source signal, a second end of the bias transistor is connected to a first power supply end, and a third end of the bias transistor is coupled to an input node of the carrier amplification circuit or the peak amplification circuit.

[0010] Further, the first gain adjustment circuit is configured to draw at least part of the current signal from the first end or the third end of the bias transistor to reduce the first bias signal output to the carrier amplification circuit or the peak amplification circuit when the Doherty power amplifier gain is in an upward trend.

[0011] Further, the bias circuit comprises a peak bias circuit configured to provide a peak bias signal to the peak amplification circuit.

[0012] Further, the bias circuit comprises a carrier bias circuit configured to provide a carrier bias signal to the carrier amplification circuit.

[0013] Further, the first gain adjustment circuit comprises a first transistor and a first bias power supply end, a second end of the first transistor is connected to the first bias power supply end, a first end of the first transistor is coupled to the bias circuit, and a third end of the first transistor is grounded.

[0014] When the Doherty power amplifier gain is in an upward trend, the first bias power supply end outputs a first bias current to the first transistor, so that the first transistor draws at least part of the current signal from the bias circuit to reduce the first bias signal output to the carrier amplification circuit or the peak amplification circuit.

[0015] Further, the first gain adjustment circuit further comprises a first resistor.

[0016] A first end of the first resistor is connected to the first bias power supply end and the first end of the first transistor, and a second end of the first resistor is grounded.

[0017] Further, the bias circuit further comprises a second resistor, and the third end of the bias transistor is coupled to an input node of the carrier amplification circuit or the peak amplification circuit through the second resistor.

[0018] Further, the Doherty power amplifier further comprises a feedback circuit, one end of the feedback circuit is connected to a carrier signal transmission path in the carrier amplification circuit, and the other end is coupled to an output end of the peak bias circuit and configured to turn on the peak bias circuit under a selected condition; wherein the selected condition is that the power of the carrier signal in the carrier amplification circuit is greater than a preset power, and the preset power indicates that the carrier amplification circuit is in or close to a saturation state.

[0019] A Doherty power amplifier, comprising a carrier amplification circuit, a peak amplification circuit, a bias circuit and a first gain adjustment circuit.

[0020] The bias circuit is configured to output a first bias signal to the carrier amplification circuit or the peak amplification circuit through a bias output node;

[0021] The first gain adjustment circuit is coupled to the bias output node and is configured to draw at least part of the first bias signal from the bias circuit when turned on.

[0022] Further, the first gain adjustment circuit is configured to draw at least part of the current signal from the bias circuit to reduce the first bias signal output to the carrier amplification circuit or the peak amplification circuit when a first gain difference value is less than a first threshold value, wherein the first gain difference value refers to a difference between a falling amplitude of the gain of the carrier amplification circuit and a rising amplitude of the gain of the peak amplification circuit in the same time period.

[0023] Further, the first gain adjustment circuit includes a first transistor and a first bias power supply end, a second end of the first transistor is connected to the first bias power supply end, a first end of the first transistor is coupled to the bias circuit, and a third end of the first transistor is grounded.

[0024] When the gain of the Doherty power amplifier shows an upward trend, the first bias power supply end outputs a first bias current to the first transistor, so that the first transistor draws at least part of the current signal from the bias circuit to reduce the first bias signal output to the carrier amplification circuit or the peak amplification circuit.

[0025] A radio frequency front-end module includes the Doherty power amplifier described above.

[0026] The Doherty power amplifier described above and the radio frequency front-end module, the Doherty power amplifier includes a carrier amplification circuit, a peak amplification circuit, a bias circuit, and a first gain adjustment circuit; the bias circuit is configured to output a first bias signal to the carrier amplification circuit or the peak amplification circuit; the first gain adjustment circuit is configured to draw at least part of a current signal from the bias circuit to reduce the first bias signal output to the carrier amplification circuit or the peak amplification circuit when the gain of the Doherty power amplifier shows an upward trend; this embodiment draws at least part of the current signal from the bias circuit to reduce the first bias signal output to the carrier amplification circuit or the peak amplification circuit when the gain of the Doherty power amplifier starts to show an upward trend by accessing the first gain adjustment circuit, thereby avoiding the phenomenon of gain expansion of the Doherty power amplifier, improving the gain flatness of the Doherty power amplifier, and further achieving the purpose of improving the linearity of the Doherty power amplifier. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description only some of the embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor under the premise of these drawings.

[0028] Figure 1 is a circuit schematic diagram of a Doherty power amplifier in an embodiment of the present application;

[0029] Figure 2 is another circuit schematic diagram of a Doherty power amplifier in an embodiment of the present application;

[0030] Figure 3 is another circuit schematic diagram of a Doherty power amplifier in an embodiment of the present application;

[0031] Figure 4 is a gain curve schematic diagram of a Doherty power amplifier in an embodiment of the present application.

[0032] In the figure: 10, carrier amplification circuit 10; 20, peak amplification circuit 20; 30, bias circuit 30; 40, first gain adjustment circuit; 50, feedback circuit. DETAILED DESCRIPTION

[0033] The following will combine the drawings in the embodiments of the present application, and the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0034] It should be understood that the present application can be implemented in different forms, and should not be interpreted as being limited to the embodiments presented here. On the contrary, these embodiments are provided to make the disclosure complete and complete, and to fully convey the scope of the present application to those skilled in the art. In the drawings, the size and relative size of the layers and regions may be exaggerated for clarity. The same reference signs represent the same elements throughout the drawings.

[0035] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0036] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] For a thorough understanding of the present application, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0039] The present embodiment provides a Doherty power amplifier, asFigure 1 As shown, the Doherty power amplifier includes a carrier amplification circuit 10, a peak amplification circuit 20, a bias circuit 30 and a first gain adjustment circuit 40. The bias circuit 30 is configured to output a first bias signal to the carrier amplification circuit 10 or the peak amplification circuit 20. The first gain adjustment circuit 40 is configured to extract at least part of the current signal from the bias circuit 30 to reduce the first bias signal output to the carrier amplification circuit 10 or the peak amplification circuit 20 when the gain of the Doherty power amplifier is in an upward trend.

[0040] In one embodiment, the first gain adjustment circuit 40 is a circuit for adjusting the gain of the Doherty power amplifier when the gain of the Doherty power amplifier is in an upward trend. In one embodiment, the gain of the Doherty power amplifier is dependent on the gain of the carrier amplification circuit 10 and the gain of the peak amplification circuit 20. Therefore, the gain of the Doherty power amplifier is in an upward trend means that the gain amplitude of the carrier amplification circuit 10 and the gain amplitude of the peak amplification circuit 20 are superimposed in an upward trend at the same time period.

[0041] In one embodiment, the Doherty power amplifier includes a carrier amplification circuit 10 and a peak amplification circuit 20. The carrier amplification circuit 10 is configured to amplify a carrier signal and output a carrier amplification signal. The peak amplification circuit 20 is configured to amplify a peak signal and output a peak amplification signal.

[0042] In one embodiment, the Doherty power amplifier further includes a bias circuit 30 configured to output a first bias signal to the carrier amplification circuit 10 or the peak amplification circuit 20 in the Doherty power amplifier. Optionally, the bias circuit 30 can be a peak bias circuit configured to output the first bias signal to the peak amplification circuit 20. The bias circuit 30 can be a carrier bias circuit configured to output the first bias signal to the carrier amplification circuit 10.

[0043] In one specific embodiment, in the Dougherty power amplifier, when the power of the carrier amplifier circuit 10 reaches a preset power, for example, when the carrier amplifier circuit 10 approaches or reaches saturation, it is determined that the power of the carrier amplifier circuit 10 has reached the preset power. At this time, the peak amplifier circuit 20 starts to work. At this time, due to the connection of the peak amplifier circuit 20, the overall impedance presented by the Dougherty power amplifier decreases, causing the gain of the Dougherty power amplifier to begin to decrease, that is, the gain of the Dougherty power amplifier shows a decreasing trend. As the power of the peak amplifier circuit 20 gradually increases, the gain of the Dougherty power amplifier begins to show an increasing trend. Therefore, the Dougherty power amplifier in this embodiment also includes a first gain adjustment circuit 40. When the gain of the Dougherty power amplifier shows an increasing trend, the first gain adjustment circuit 40 extracts at least a portion of the current signal from the bias circuit 30 to reduce the first bias signal output to the carrier amplifier circuit 10 or the peak amplifier circuit 20, thereby avoiding the phenomenon of gain expansion of the Dougherty power amplifier and improving the gain flatness of the Dougherty power amplifier. It should be noted that at least part of the current signal can be the signal output from the bias signal source terminal received by the bias circuit 30, or it can be the signal that is amplified by the bias transistor in the bias circuit 30 and then input to the carrier amplifier circuit 10 or the peak amplifier circuit 20.

[0044] In this embodiment, the Dougherty power amplifier includes a carrier amplifier circuit 10, a peak amplifier circuit 20, a bias circuit 30, and a first gain adjustment circuit 40. The bias circuit 30 is configured to output a first bias signal to the carrier amplifier circuit 10 or the peak amplifier circuit 20. The first gain adjustment circuit 40 is configured to extract at least a portion of the current signal from the bias circuit 30 when the gain of the Dougherty power amplifier begins to rise, thereby reducing the first bias signal output to the carrier amplifier circuit 10 or the peak amplifier circuit 20. This embodiment, by incorporating the first gain adjustment circuit 40, ensures that when the gain of the Dougherty power amplifier begins to rise, at least a portion of the current signal is extracted from the bias circuit 30 to reduce the first bias signal output to the carrier amplifier circuit 10 or the peak amplifier circuit 20. This avoids gain expansion in the Dougherty power amplifier, improves the gain flatness of the Dougherty power amplifier, and ultimately improves the linearity of the Dougherty power amplifier.

[0045] In one embodiment, such as Figure 1 As shown, the first gain adjustment circuit 40 is configured to extract at least a portion of the first bias signal from the bias circuit 30 when the first gain difference is less than the first threshold. The first gain difference refers to the difference between the decrease in the gain of the carrier amplifier circuit 10 and the increase in the gain of the peak amplifier circuit 20 within the same time period.

[0046] The first threshold is a value customized by the user according to actual needs. In a specific embodiment, in order to ensure the gain flatness of the Dougherty power amplifier and to ensure that the first gain adjustment circuit 40 can extract the first bias signal from the bias circuit 30 within a suitable time period, the first threshold should not be set too large.

[0047] In this embodiment, the first gain difference refers to the difference between the decrease in gain of the carrier amplifier circuit 10 and the increase in gain of the peak amplifier circuit 20 within the same time period. If the first gain difference is less than the first threshold, it indicates that the decrease in gain of the carrier amplifier circuit 10 and the increase in gain of the peak amplifier circuit 20 are close within the same time period, and the overall gain of the Dougherty power amplifier tends to flatten. In a specific embodiment, when the carrier amplifier circuit 10 and the peak amplifier circuit 20 work together, the gain of the carrier amplifier circuit 10 begins to decrease, and the gain of the peak amplifier circuit 20 begins to increase. Initially, because the decrease in gain of the carrier amplifier circuit 10 is greater than the increase in gain of the peak amplifier circuit 20, the overall gain of the Dougherty power amplifier still shows a decreasing trend. However, as the power of the peak amplifier circuit 20 gradually increases, the decrease in gain of the carrier amplifier circuit 10 and the increase in gain of the peak amplifier circuit 20 will reach a balance / equal at a certain moment. Subsequently, the decrease in gain of the carrier amplifier circuit 10 gradually becomes less than the increase in gain of the peak amplifier circuit 20, causing the overall gain of the Dougherty power amplifier to begin to increase. In this embodiment, when the first gain difference is less than the first threshold, that is, when the decreasing trend of the gain of the carrier amplifier circuit 10 and the increasing trend of the peak amplifier circuit 20 gradually become the same, and the decreasing trend of the gain of the carrier amplifier circuit 10 begins to be less than the increasing trend of the peak amplifier circuit 20, indicating that the gain of the Dougherty power amplifier is about to or has begun to increase, the first gain adjustment circuit 40 extracts at least a portion of the first bias signal from the bias circuit 30 to reduce the first bias signal output to the carrier amplifier circuit 10 or the peak amplifier circuit 20, thereby avoiding the phenomenon of gain expansion in the Dougherty power amplifier, improving the gain flatness of the Dougherty power amplifier, and thus achieving the purpose of improving the linearity of the Dougherty power amplifier.

[0048] In one embodiment, such as Figure 1 and Figure 3 As shown, the bias circuit 30 includes a bias transistor 31; the first terminal of the bias transistor 31 is configured to receive a signal source signal, the second terminal of the bias transistor 31 is connected to the first power supply terminal VCC, and the third terminal of the bias transistor 31 is coupled to the input node of the carrier amplifier circuit 10 or the peak amplifier circuit 20.

[0049] In an embodiment, the biasing circuit 30 comprises a biasing transistor 31. Optionally, the biasing transistor 31 can be a field effect transistor or a HBT transistor. Preferably, the biasing transistor 31 is a HBT transistor.

[0050] As an example, the biasing transistor 31 comprises a base, a collector and an emitter, the base of the biasing transistor 31 is configured to receive a signal source signal, the collector of the biasing transistor 31 is connected to the first power supply terminal VCC, and the emitter of the biasing transistor 31 is coupled to the input node of the carrier amplifier circuit 10 or the peak amplifier circuit 20.

[0051] Optionally, the Doherty power amplifier further comprises a first signal source S31, i.e. a biasing signal source terminal, the output terminal of the first signal source S31 is connected to the input terminal of the biasing circuit 30, and is configured to output the signal source signal to the base of the biasing transistor 31.

[0052] Optionally, the biasing circuit 30 further comprises a biasing voltage dividing circuit for stabilizing the static working point of the biasing transistor 31. The biasing voltage dividing circuit comprises a first voltage dividing transistor D31 and a second voltage dividing transistor D32, and preferably, the first voltage dividing transistor D31 and the second voltage dividing transistor D32 are both HBT transistors. The collector of the first voltage dividing transistor D31 is connected to the base of the first transistor M41 and the base of the biasing transistor 31, the emitter of the first voltage dividing transistor D31 is connected to the collector of the second voltage dividing transistor D32, the collector of the second voltage dividing transistor D32 is connected to the base of the second voltage dividing transistor D32, and the emitter of the second voltage dividing transistor D32 is grounded.

[0053] In the embodiment, the biasing circuit 30 comprises a biasing transistor 31; the first terminal of the biasing transistor 31 is configured to receive a signal source signal, the second terminal of the biasing transistor 31 is connected to the first power supply terminal VCC, and the third terminal of the biasing transistor 31 is coupled to the input node of the carrier amplifier circuit 10 or the peak amplifier circuit 20, so as to output a first biasing signal to the input node of the carrier amplifier circuit 10 or the peak amplifier circuit 20.

[0054] In an embodiment, as shown in Figure 1 and Figure 3 the first gain adjusting circuit 40 is configured to extract at least part of the current signal from the first terminal or the third terminal of the biasing transistor 31 when the gain of the Doherty power amplifier shows an upward trend, so as to reduce the first biasing signal output to the carrier amplifier circuit 10 or the peak amplifier circuit 20.

[0055] In one embodiment, the first gain adjustment circuit 40 is configured to draw at least part of the current signal from the first terminal of the bias transistor 31 when the gain of the Doherty power amplifier is in an upward trend, for example, the drawn current signal can be the signal source received by the base of the bias transistor 31, so as to reduce the first bias signal output to the carrier amplification circuit 10 or the peak amplification circuit 20, thereby avoiding the gain expansion phenomenon of the Doherty power amplifier, and improving the gain flatness of the Doherty power amplifier.

[0056] In one embodiment, the first gain adjustment circuit 40 is configured to draw at least part of the current signal from the third terminal of the bias transistor 31 when the gain of the Doherty power amplifier is in an upward trend, for example, the drawn current signal can be the first bias signal output by the third terminal of the bias transistor 31, so as to reduce the first bias signal output to the carrier amplification circuit 10 or the peak amplification circuit 20, thereby avoiding the gain expansion phenomenon of the Doherty power amplifier, and improving the gain flatness of the Doherty power amplifier.

[0057] In the embodiment, by configuring the first gain adjustment circuit 40 to draw at least part of the current signal from the first terminal or the third terminal of the bias transistor 31 when the gain of the Doherty power amplifier is in an upward trend, the purpose of reducing the first bias signal output to the carrier amplification circuit 10 or the peak amplification circuit 20 can be achieved, so as to improve the linearity of the Doherty power amplifier.

[0058] In one embodiment, as shown in FIG. 4, the first gain adjustment circuit 40 includes a first transistor M41 and a first bias power supply terminal S41, the second terminal of the first transistor M41 is connected to the first bias power supply terminal S41, the first terminal of the first transistor M41 is coupled to the input terminal of the bias circuit 30 or the output terminal of the bias circuit 30, and the third terminal of the first transistor M41 is grounded. When the gain of the Doherty power amplifier is in an upward trend, the first bias power supply terminal S41 outputs a first bias current to the first transistor M41, so that the first transistor M41 draws at least part of the current signal from the bias circuit 30, so as to reduce the first bias signal output to the carrier amplification circuit 10 or the peak amplification circuit 20. Figure 3 In one embodiment, the first gain adjustment circuit 40 includes a first transistor M41 and a first bias power supply terminal S41. Optionally, the first transistor M41 can be a field effect transistor or an HBT transistor. Preferably, the first transistor M41 is an HBT transistor.

[0059]

[0060] ​In one specific embodiment, the base of the first transistor M41 is connected to the first bias power supply terminal S41, the collector of the first transistor M41 is coupled to the input terminal or the output terminal of the bias circuit 30, and the emitter of the first transistor M41 is grounded. In this example, when the gain of the Dougherty power amplifier is increasing, the first bias power supply terminal S41 is controlled to output a first bias current. The base of the first transistor M41 receives the first bias current output by the first bias power supply terminal S41. Under the action of this first bias current, the first transistor M41 is turned on. After being turned on, the first transistor M41 extracts at least a portion of the current signal from the bias current, such as the signal source signal received at the input terminal of the bias circuit 30 or the first bias signal output by the output terminal of the bias circuit 30, thereby reducing the first bias signal output to the carrier amplifier circuit 10 or the peak amplification current. It is understood that the magnitude of the first bias current output by the first bias power supply terminal S41 must be sufficient to turn on the first transistor M41.

[0061] In another specific embodiment, when the gain of the Dougherty power amplifier has not yet shown an upward trend, the first bias power supply terminal S41 will not output the first bias current, or the first bias power supply terminal S41 will be controlled to output a first bias current with a small current value. The first bias current with a small current value is insufficient to turn on the first transistor M41. At this time, the first transistor M41 is in the off state and cannot extract a current signal from the bias current.

[0062] In this embodiment, the first gain adjustment circuit 40 includes a first transistor M41 and a first bias power supply terminal S41. The first terminal of the first transistor M41 is connected to the first bias power supply terminal S41, the second terminal of the first transistor M41 is coupled to the input terminal or the output terminal of the bias circuit 30, and the third terminal of the first transistor M41 is grounded. When the gain of the Dougherty power amplifier is increasing, the first bias power supply terminal S41 outputs a first bias current to the first transistor M41, turning on the first transistor M41 to extract at least a portion of the current signal from the bias circuit 30, thereby reducing the first bias signal output to the carrier amplifier circuit 10 or the peak amplifier circuit 20, avoiding the phenomenon of gain expansion in the Dougherty power amplifier, improving the gain flatness of the Dougherty power amplifier, and thus achieving the purpose of improving the linearity of the Dougherty power amplifier.

[0063] In one embodiment, such as Figure 3 As shown, the first gain adjustment circuit 40 also includes a first resistor R41; the first end of the first resistor R41 is connected to the first bias power supply terminal S41 and the first end of the first transistor M41, and the second end of the first resistor R41 is grounded.

[0064] In the embodiment, the first gain adjusting circuit 40 further comprises a first resistor R41, by connecting a first end of the first resistor R41 to the first bias power supply end S41 and a first end of the first transistor M41, and connecting a second end of the first resistor R41 to ground, when the gain of the Doherty power amplifier is in an upward trend, the first bias current outputted by the first bias power supply end S41 flows through the first resistor R41, so that the first end of the first resistor R41 forms an open voltage. When the open voltage is equal to or greater than the turn-on voltage of the first transistor M41, the first transistor M41 is turned on. Specifically, according to actual needs, the size of the open voltage can be adjusted by adjusting the first bias current and the resistance value of the first resistor R41, so that the open voltage is equal to or greater than the turn-on voltage of the first transistor M41.

[0065] Optionally, as shown in Figure 3 , the first gain adjusting circuit 40 further comprises a transistor protection circuit 401 arranged between the second end of the first transistor M41 and the input end of the bias circuit 30 or the output end of the bias circuit 30, for large current / voltage protection of the first transistor M41. Optionally, the transistor protection circuit can be a circuit formed by a resistor, an inductor, or a combination of a resistor and an inductor.

[0066] In an embodiment, as shown in Figure 3 , the peak bias circuit further comprises a second resistor R31, and the third end of the peak bias transistor 31 is coupled to the input node of the peak amplification circuit 20 through the second resistor R31.

[0067] In the embodiment, the peak bias circuit further comprises a second resistor R31, by connecting the second resistor R31 between the third end of the peak bias transistor 31 and the input node coupled to the peak amplification circuit 20, the size of the first bias signal outputted to the peak amplification circuit 20 can be adjusted by configuring the resistance value of the second resistor R31. As a preferred, the second resistor R31 is an adjustable resistor.

[0068] In an embodiment, as shown in Figure 2 , the Doherty power amplifier further comprises a feedback circuit 50, one end of the feedback circuit 50 is connected to a carrier signal transmission path in the carrier amplification circuit 10, and the other end is coupled to the output end of the peak bias circuit, and is configured to enable the peak bias circuit under a selected condition; wherein the selected condition is that the power of the carrier signal in the carrier amplification circuit 10 is greater than a preset power, and the preset power indicates that the carrier amplification circuit 10 is in or close to a saturation state.

[0069] The selected condition is that the carrier amplification circuit 10 is in or close to a saturated state. Alternatively, the selected condition is that the power of the carrier signal in the carrier amplification circuit 10 is greater than a preset power, which indicates that the carrier amplification circuit 10 is in or close to a saturated state. Alternatively, the selected condition is that the voltage of the carrier signal in the carrier amplification circuit 10 is greater than a preset voltage, which indicates that the carrier amplification circuit 10 is in or close to a saturated state. The preset power can be any power value defined in advance. The preset voltage can be any voltage value defined in advance. For example, as the carrier amplification circuit 10 starts to saturate (e.g., reaches gain compression), the amplification capability of the carrier amplification transistor deteriorates, resulting in a rapid increase in the base current. Therefore, when the carrier amplification circuit 10 is in or close to a saturated state, it is determined that the power of the carrier signal of the carrier amplification circuit 10 is greater than the preset power.

[0070] In an embodiment, one end of the feedback circuit 50 is connected to the carrier signal transmission path in the carrier amplification circuit 10, and the other end is coupled to the output end of the peak bias circuit. For example, the carrier signal transmission path can be the input node or the output node of the carrier amplification circuit 10. In this embodiment, when the power of the carrier signal is greater than the preset power, the gain of the carrier amplification circuit 10 gradually decreases, resulting in a decrease in the overall output efficiency of the Doherty power amplifier. Although the peak amplification circuit 20 starts to work at this time, the output power of the peak amplification circuit 20 is low at the beginning, and the gain of the Doherty power amplifier shows a downward trend. As the output power of the peak amplification circuit 20 gradually increases, the gain of the Doherty power amplifier shows an upward trend, as shown by curve 1 in Figure 4 .

[0071] Therefore, in order to improve the overall output efficiency and linearity of the Doherty power amplifier, one end of the feedback circuit 50 is connected to the carrier signal transmission path in the carrier amplification circuit 10, and the other end is coupled to the output end of the peak bias circuit. When the power of the carrier signal is greater than the preset power, the feedback circuit 50 extracts sufficient carrier signal from the carrier amplification circuit 10 and feeds it to the output end of the peak bias circuit, so that the peak bias circuit is turned on. The peak bias circuit provides a peak bias signal to the peak amplification circuit 20 in the turned-on state, so that the peak amplification circuit 20 works normally, amplifies the received peak signal, and outputs a peak amplification signal, to make up for the gain loss of the output carrier amplification signal of the carrier amplification circuit 10 in a saturated state, as shown by curve 2 in Figure 4The curve 2 shown can improve the overall output efficiency of the Doherty power amplifier, and at the same time, due to the first gain adjustment circuit 40 configured to draw at least part of the current signal from the bias circuit 30 to reduce the first bias signal output to the carrier amplification circuit 10 or the peak amplification circuit 20 when the gain of the Doherty power amplifier shows an upward trend, the upward trend of the Doherty power amplifier is reduced, as shown in the curve 1. Figure 4 The curve 2 shown can also improve the linearity of the Doherty power amplifier, as shown in the curve 3. Figure 4 The curve 3 shown is a gain curve of the Doherty power amplifier under the joint action of the feedback circuit 50 and the first gain adjustment circuit 40.

[0072] In the embodiment, the Doherty power amplifier further comprises a feedback circuit 50, by connecting one end of the feedback circuit 50 to the carrier signal transmission path in the carrier amplification circuit 10, and the other end is coupled to the output end of the peak bias circuit, and the first gain adjustment circuit 40 is configured to draw at least part of the current signal from the bias circuit 30 to reduce the first bias signal output to the carrier amplification circuit 10 or the peak amplification circuit 20 when the gain of the Doherty power amplifier shows an upward trend, which can compensate for the gain loss of the output carrier amplification signal of the carrier amplification circuit 10 in the saturation state, improve the overall output efficiency of the Doherty power amplifier, and at the same time, due to the first gain adjustment circuit 40 configured to draw at least part of the current signal from the bias circuit 30 to reduce the first bias signal output to the carrier amplification circuit 10 or the peak amplification circuit 20 when the gain of the Doherty power amplifier shows an upward trend, the linearity of the Doherty power amplifier is improved, and the overall performance of the Doherty power amplifier is improved.

[0073] Optionally, the feedback circuit 50 comprises a feedback capacitor and a feedback resistor connected in series. For example, the capacitance of the feedback capacitor can be set according to the power of the carrier signal at the input end of the carrier amplification circuit 10, or the capacitance of the feedback capacitor and the resistance of the feedback resistor can be set according to the power of the carrier signal at the output end of the carrier amplification circuit 10. As an example, the greater the power of the carrier signal at the input end of the carrier amplification circuit 10 or the power of the carrier signal at the output end of the carrier amplification circuit 10, the smaller the capacitance of the feedback capacitor, and the greater the resistance of the feedback resistor. When the power of the carrier signal in the carrier amplification circuit 10 is greater than the preset power, the feedback capacitor and the feedback resistor connected in series form an RC feedback circuit 50, which provides an alternating current feedback signal to the output end of the peak bias circuit to control the peak bias circuit to be turned on.

[0074] The embodiment provides a Doherty power amplifier, as shown in Figure 1 and as shown in Figure 3As shown, the Doherty power amplifier includes a carrier amplification circuit 10, a peak amplification circuit 20, a bias circuit 30, and a first gain adjustment circuit 40. The bias circuit 30 is configured to output a first bias signal to the carrier amplification circuit 10 or the peak amplification circuit 20 through a bias output node. The first gain adjustment circuit 40 is coupled to the bias output node and is configured to draw at least part of the first bias signal from the bias circuit 30 when turned on.

[0075] In one embodiment, the first gain adjustment circuit 40 is a circuit for adjusting the gain of the Doherty power amplifier when the gain of the Doherty power amplifier is in an upward trend. In one embodiment, the gain of the Doherty power amplifier is dependent on the gain of the carrier amplification circuit 10 and the gain of the peak amplification circuit 20. Therefore, the gain of the Doherty power amplifier is in an upward trend means that the gain amplitude of the carrier amplification circuit 10 and the gain amplitude of the peak amplification circuit 20 are superimposed in an upward trend at the same time period.

[0076] In one embodiment, the Doherty power amplifier includes a carrier amplification circuit 10 and a peak amplification circuit 20. The carrier amplification circuit 10 is configured to amplify a carrier signal and output a carrier amplified signal. The peak amplification circuit 20 is configured to amplify a peak signal and output a peak amplified signal.

[0077] In one embodiment, the Doherty power amplifier further includes a bias circuit 30 configured to output a first bias signal to the carrier amplification circuit 10 or the peak amplification circuit 20 in the Doherty power amplifier. Optionally, the bias circuit 30 can be a peak bias circuit configured to output the first bias signal to the peak amplification circuit 20. The bias circuit 30 can be a carrier bias circuit configured to output the first bias signal to the carrier amplification circuit 10.

[0078] In a specific embodiment, in the Doherty power amplifier, when the power of the carrier amplification circuit 10 reaches the preset power, for example, when the carrier amplification circuit 10 approaches or reaches saturation, it is determined that the power of the carrier amplification circuit 10 reaches the preset power, and the peak amplification circuit 20 starts to work. At this time, due to the access of the peak amplification circuit 20, the overall impedance of the Doherty power amplifier decreases, so that the gain of the Doherty power amplifier starts to decrease, that is, the gain of the Doherty power amplifier shows a downward trend. As the power of the peak amplification circuit 20 gradually increases, the gain of the Doherty power amplifier starts to show an upward trend. The gain of the Doherty power amplifier decreases during the process of changing from the downward trend to the upward trend, which reduces the linearity of the Doherty power amplifier. Therefore, the Doherty power amplifier in the embodiment further includes a first gain adjustment circuit 40. When the gain of the Doherty power amplifier shows an upward trend, at least part of the current signal is extracted from the bias circuit 30 through the first gain adjustment circuit 40 to reduce the first bias signal output to the carrier amplification circuit 10 or the peak amplification circuit 20, so as to avoid the phenomenon of gain expansion of the Doherty power amplifier, and to improve the gain flatness of the Doherty power amplifier. It should be noted that the at least part of the current signal can be the signal output by the bias signal source end in the bias circuit 30, or the signal input to the carrier amplification circuit 10 or the peak amplification circuit 20 after being amplified by the bias transistor in the bias circuit 30.

[0079] In the embodiment, the Doherty power amplifier includes a carrier amplification circuit 10, a peak amplification circuit 20, a bias circuit 30, and a first gain adjustment circuit 40. The bias circuit 30 is configured to output a first bias signal to the carrier amplification circuit 10 or the peak amplification circuit 20. The first gain adjustment circuit 40 is configured to extract at least part of the current signal from the bias circuit 30 when the gain of the Doherty power amplifier shows an upward trend, so as to reduce the first bias signal output to the carrier amplification circuit 10 or the peak amplification circuit 20. In the embodiment, by accessing the first gain adjustment circuit 40, at least part of the current signal is extracted from the bias circuit 30 when the gain of the Doherty power amplifier starts to show an upward trend, so as to reduce the first bias signal output to the carrier amplification circuit 10 or the peak amplification circuit 20, thereby avoiding the phenomenon of gain expansion of the Doherty power amplifier, improving the gain flatness of the Doherty power amplifier, and achieving the purpose of improving the linearity of the Doherty power amplifier.

[0080] In an embodiment, the first gain adjustment circuit 40 is configured to extract at least part of the first bias signal from the bias circuit 30 when the first gain difference is less than the first threshold value. The first gain difference refers to the difference between the decrease amplitude of the gain of the carrier amplification circuit 10 and the increase amplitude of the gain of the peak amplification circuit 20 in the same time period.

[0081] wherein the first threshold is a value defined by the user according to actual needs. In a specific embodiment, in order to ensure the gain flatness of the Doherty power amplifier, ensure that the first gain adjustment circuit 40 can extract the first bias signal from the bias circuit 30 in a suitable time period, the first threshold should not be set too large.

[0082] In the embodiment, the first gain difference refers to the difference between the decreasing amplitude of the gain of the carrier amplification circuit 10 and the increasing amplitude of the gain of the peak amplification circuit 20 in the same time period. If the first gain difference is less than the first threshold, it means that the decreasing amplitude of the gain of the carrier amplification circuit 10 and the increasing amplitude of the gain of the peak amplification circuit 20 are close in the same time period, and the overall gain of the Doherty power amplifier tends to be flat. In a specific embodiment, when the carrier amplification circuit 10 and the peak amplification circuit 20 work together, the gain of the carrier amplification circuit 10 starts to decrease, and the gain of the peak amplification circuit 20 starts to increase. At the beginning, due to the decreasing trend of the gain of the carrier amplification circuit 10 being greater than the increasing trend of the gain of the peak amplification circuit 20, the overall gain of the Doherty power amplifier still decreases, but as the power of the peak amplification circuit 20 gradually increases, the decreasing trend of the gain of the carrier amplification circuit 10 and the increasing trend of the gain of the peak amplification circuit 20 will reach a balance / same at a certain moment, and then the decreasing trend of the gain of the carrier amplification circuit 10 gradually becomes less than the increasing trend of the gain of the peak amplification circuit 20, so that the overall gain of the Doherty power amplifier starts to increase. In the embodiment, when the first gain difference is less than the first threshold, that is, when the decreasing trend of the gain of the carrier amplification circuit 10 and the increasing trend of the gain of the peak amplification circuit 20 gradually become the same, and the decreasing trend of the gain of the carrier amplification circuit 10 starts to be less than the increasing trend of the gain of the peak amplification circuit 20, that is, when the Doherty power amplifier gain will or starts to increase, the first gain adjustment circuit 40 extracts at least part of the first bias signal from the bias circuit 30 to reduce the first bias signal output to the carrier amplification circuit 10 or the peak amplification circuit 20, thereby avoiding the phenomenon of gain expansion of the Doherty power amplifier, improving the gain flatness of the Doherty power amplifier, and further achieving the purpose of improving the linearity of the Doherty power amplifier.

[0083] In an embodiment, the first gain adjusting circuit 40 comprises a first transistor M41 and a first bias power terminal S41, the second terminal of the first transistor M41 is connected to the first bias power terminal S41, the first terminal of the first transistor M41 is coupled to the input terminal of the bias circuit 30 or the output terminal of the bias circuit 30, and the third terminal of the first transistor M41 is grounded; wherein when the gain of the Doherty power amplifier is in the rising trend, the first bias power terminal S41 outputs a first bias current to the first transistor M41, so that the first transistor M41 extracts at least part of the current signal from the bias circuit 30 to reduce the first bias signal output to the carrier amplification circuit 10 or the peak amplification circuit 20.

[0084] In a specific embodiment, the first gain adjusting circuit 40 comprises a first transistor M41 and a first bias power terminal S41. Optionally, the first transistor M41 can be a field effect transistor or an HBT transistor. Preferably, the first transistor M41 is an HBT transistor.

[0085] In a specific embodiment, the base of the first transistor M41 is connected to the first bias power terminal S41, the collector of the first transistor M41 is coupled to the input terminal of the bias circuit 30 or the output terminal of the bias circuit 30, and the emitter of the first transistor M41 is grounded. In this example, when the gain of the Doherty power amplifier is in the rising trend, the first bias power terminal S41 outputs a first bias current, the base of the first transistor M41 receives the first bias current output by the first bias power terminal S41, and under the action of the first bias current, the first transistor M41 is turned on. The first transistor M41 turned on extracts at least part of the current signal from the bias current, for example, the signal source signal received by the input terminal of the bias circuit 30 or the first bias signal output by the output terminal of the bias circuit 30, thereby reducing the first bias signal output to the carrier amplification circuit 10 or the peak amplification circuit. It can be understood that the size of the first bias current output by the first bias power terminal S41 needs to be sufficient to turn on the first transistor M41.

[0086] In another specific embodiment, when the gain of the Doherty power amplifier is not in the rising trend, the first bias power terminal S41 does not output the first bias current, or controls the first bias power terminal S41 to output a first bias current with a smaller current value, which is insufficient to turn on the first transistor M41. At this time, the first transistor M41 is in the off state and cannot extract the current signal from the bias current.

[0087] In the embodiment, the first gain adjusting circuit 40 comprises a first transistor M41 and a first bias power supply end S41, the first end of the first transistor M41 is connected with the first bias power supply end S41, the second end of the first transistor M41 is coupled to the input end of the bias circuit 30 or the output end of the bias circuit 30, the third end of the first transistor M41 is grounded, when the gain of the Doherty power amplifier shows an upward trend, the first bias power supply end S41 outputs a first bias current to the first transistor M41, so that the first transistor M41 is turned on to extract at least part of the current signal from the bias circuit 30, thereby reducing the first bias signal output to the carrier amplification circuit 10 or the peak value amplification circuit 20, avoiding the phenomenon of gain expansion of the Doherty power amplifier, improving the gain flatness of the Doherty power amplifier, and achieving the purpose of improving the linearity of the Doherty power amplifier.

[0088] The embodiment provides a radio frequency front end module, comprising the Doherty power amplifier.

[0089] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A Doherty power amplifier characterized by, The bias circuit is configured to output a first bias signal to the carrier amplification circuit or the peak amplification circuit. The bias circuit is configured to output a first bias signal to the carrier amplification circuit or the peak amplification circuit. The first gain adjustment circuit is configured to extract at least part of the current signal from the bias circuit to reduce the first bias signal output to the carrier amplification circuit or the peak amplification circuit when the first gain difference is less than a first threshold. The first gain difference refers to the difference between the decrease amplitude of the gain of the carrier amplification circuit and the increase amplitude of the gain of the peak amplification circuit in the same time period.

2. The Doherty power amplifier of claim 1, wherein, The bias circuit includes a bias transistor, a first end of the bias transistor is configured to receive a signal source signal, a second end of the bias transistor is connected to a first power supply end, and a third end of the bias transistor is coupled to an input node of the carrier amplification circuit or the peak amplification circuit.

3. The Doherty power amplifier of claim 2, wherein, The first gain adjustment circuit is configured to extract at least part of the current signal from the first end or the third end of the bias transistor to reduce the first bias signal output to the carrier amplification circuit or the peak amplification circuit when the Doherty power amplifier gain is in an upward trend.

4. The Doherty power amplifier of claim 1, wherein, The bias circuit includes a peak bias circuit configured to provide a peak bias signal to the peak amplification circuit.

5. The Doherty power amplifier of claim 1, wherein, The bias circuit includes a carrier bias circuit configured to provide a carrier bias signal to the carrier amplification circuit.

6. The Doherty power amplifier of claim 1, wherein, The first gain adjustment circuit includes a first transistor and a first bias power supply end, a second end of the first transistor is connected to the first bias power supply end, a first end of the first transistor is coupled to the bias circuit, and a third end of the first transistor is grounded. When the Doherty power amplifier gain is in an upward trend, the first bias power supply end outputs a first bias current to the first transistor, so that the first transistor extracts at least part of the current signal from the bias circuit to reduce the first bias signal output to the carrier amplification circuit or the peak amplification circuit.

7. The Doherty power amplifier of claim 6, wherein, The first gain adjustment circuit further includes a first resistor. A first end of the first resistor is connected to the first bias power supply end and the first end of the first transistor, and a second end of the first resistor is grounded.

8. The Doherty power amplifier of claim 2, wherein, The bias circuit further includes a second resistor, and the third end of the bias transistor is coupled to the input node of the carrier amplification circuit or the peak amplification circuit through the second resistor.

9. The Doherty power amplifier of claim 4, wherein, The Doherty power amplifier further includes a feedback circuit, one end of the feedback circuit is connected to a carrier signal transmission path in the carrier amplification circuit, the other end is coupled to an output end of the peak bias circuit, and the feedback circuit is configured to enable the peak bias circuit under a selected condition; wherein the selected condition is that the power of the carrier signal in the carrier amplification circuit is greater than a preset power, and the preset power indicates that the carrier amplification circuit is in or close to a saturation state.

10. A Doherty power amplifier characterized by, The bias circuit is configured to output a first bias signal to the carrier amplification circuit or the peak amplification circuit. The bias circuit is configured to output a first bias signal to the carrier amplifier circuit or the peak amplifier circuit through a bias output node; The first gain adjustment circuit is coupled to the bias output node and is configured to draw at least part of the current signal from the bias circuit to reduce the first bias signal output to the carrier amplifier circuit or the peak amplifier circuit when a first gain difference value is less than a first threshold value, wherein the first gain difference value refers to a difference between a decrease amplitude of a gain of the carrier amplifier circuit and an increase amplitude of a gain of the peak amplifier circuit in a same time period.

11. The Doherty power amplifier of claim 10, wherein, The first gain adjustment circuit includes a first transistor and a first bias power supply end, a second end of the first transistor is connected to the first bias power supply end, a first end of the first transistor is coupled to the bias circuit, and a third end of the first transistor is grounded. When the gain of the Doherty power amplifier shows an upward trend, the first bias power supply end outputs a first bias current to the first transistor, so that the first transistor draws at least part of the current signal from the bias circuit to reduce the first bias signal output to the carrier amplifier circuit or the peak amplifier circuit.

12. A radio frequency front end module, comprising: The Doherty power amplifier includes the Doherty power amplifier according to any one of claims 1 to 11.

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