An instruction processing method, apparatus, system, and intelligent device

Abstract

This invention discloses an instruction processing method, comprising: executing a target instruction sequence including stub instructions; performing exception handling when the stub instruction is executed; writing the target instruction corresponding to the stub instruction into an instruction cache register; reading the target instruction from the instruction cache register after exception handling is completed; and single-stepping the target instruction. This invention also discloses corresponding apparatus, computing devices, system-on-a-chip, and intelligent devices.

Description

Technical Field

[0001] This invention relates to the field of processors, and more particularly to an instruction processing method, apparatus, system, and intelligent device. Background Technology

[0002] In the processor field, instruction debugging typically employs stub probing methods. Currently widely used stub probing methods, such as Kprobe / Uprobe, replace the instruction at the stub with the stub instruction and copy the replaced instruction to another memory address. Subsequent execution is then performed using either simulated execution or step-by-step execution to read and execute the instruction from the other memory address. Clearly, because this involves executing instructions at different addresses and with different privileges, step-by-step execution cannot effectively simulate some instructions in kernel mode, necessitating software simulation. However, software simulation increases the complexity of software design and the difficulty of maintaining CPU microarchitectures across instruction sets.

[0003] Therefore, it is desirable to provide a more advanced instruction processing scheme to solve the problem that traditional single-step execution mechanisms cannot effectively simulate some instructions. Summary of the Invention

[0004] Therefore, embodiments of the present invention provide an instruction processing method, apparatus, system, and intelligent device in an attempt to solve or at least alleviate the problems mentioned above.

[0005] According to one aspect of the present invention, an instruction processing method is provided, comprising: executing a target instruction sequence including stub instructions; performing exception handling when the stub instruction is executed; writing the target instruction corresponding to the stub instruction into an instruction cache register; reading the target instruction from the instruction cache register after the exception handling is completed; and executing the target instruction step by step.

[0006] Optionally, the method according to an embodiment of the present invention further includes: configuring a stub enable flag in a status control register to be valid in response to an execution to stub instruction.

[0007] Optionally, in the method according to an embodiment of the present invention, writing the target instruction corresponding to the stub instruction into the instruction cache register includes: in response to detecting a valid stub enable flag, obtaining the target instruction corresponding to the stub instruction; and writing the target instruction into the instruction cache register.

[0008] Optionally, the method according to an embodiment of the present invention further includes: replacing the target instruction located at the staking position in the original instruction sequence with a stake instruction before executing the target instruction sequence, thereby obtaining the target instruction sequence.

[0009] Optionally, the method according to an embodiment of the present invention further includes: recording the correspondence between the stake insertion position and the target instruction; and obtaining the target instruction corresponding to the stake insertion instruction, including: determining the target instruction originally located at the stake insertion position where the stake insertion instruction was located based on the correspondence.

[0010] Optionally, the method according to an embodiment of the present invention further includes: after single-step execution of the target instruction, configuring the stub enable flag to be invalid.

[0011] Optionally, in the method according to an embodiment of the present invention, configuring the stub enable flag in the state control register to be valid includes: setting the stub enable flag in the state control register to 1; and configuring the stub enable flag in the state control register to be invalid includes: setting the stub enable flag in the state control register to 0.

[0012] Optionally, in the method according to an embodiment of the present invention, exception handling includes: executing an object associated with the stub instruction.

[0013] Optionally, the method according to an embodiment of the present invention further includes: saving the current running state before performing exception handling; and restoring the saved running state after the exception handling is completed.

[0014] Optionally, in the method according to an embodiment of the present invention, the pile enable flag is a single-step enable flag.

[0015] Optionally, in the method according to an embodiment of the present invention, the stub instruction includes a breakpoint instruction or a jump instruction.

[0016] According to another aspect of the present invention, a program debugging method is provided, comprising: setting instrumentation positions in the original instruction sequence of the program; replacing the target instruction located at the instrumentation position in the original instruction sequence with a stub instruction to obtain a target instruction sequence; starting the program so that an instruction processing device executes the target instruction sequence; and when the stub instruction is executed, performing exception handling, wherein the instruction processing device writes the target instruction corresponding to the stub instruction into an instruction cache register, and after the exception handling is completed, reads the target instruction from the instruction cache register and executes the target instruction step by step.

[0017] According to another aspect of the present invention, an instruction processing apparatus is provided, comprising: an instruction cache register adapted to store instructions; an instruction execution unit adapted to execute a target instruction sequence including stub instructions, wherein when the stub instructions are executed, exception handling is performed; a register configuration unit adapted to write the target instruction corresponding to the stub instructions into the instruction cache register; an instruction fetch unit adapted to read the target instructions from the instruction cache register after exception handling is completed; and a single-step execution unit adapted to execute the target instructions step by step.

[0018] Optionally, in the apparatus according to an embodiment of the present invention, it further includes: a status control register, including a stub enable flag; the register configuration unit is further adapted to configure the stub enable flag to be valid in response to execution of a stub instruction.

[0019] Optionally, in the apparatus according to an embodiment of the present invention, the register configuration unit is further adapted to, in response to detecting a valid stub enable flag, obtain the target instruction corresponding to the stub instruction and write the target instruction into the instruction cache register.

[0020] Optionally, in the apparatus according to an embodiment of the present invention, the instruction execution unit is further adapted to replace the target instruction located at the staking position in the original instruction sequence with a staking point instruction before executing the target instruction sequence, thereby obtaining the target instruction sequence.

[0021] Optionally, in the apparatus according to an embodiment of the present invention, the instruction execution unit is further adapted to record the correspondence between the stubbing position and the target instruction; the register configuration unit is further adapted to determine the target instruction originally located at the stubbing position where the stubbing instruction is located based on the correspondence.

[0022] Optionally, in the apparatus according to an embodiment of the present invention, the register configuration unit is further adapted to configure the stub enable flag to be invalid after single-step execution of the target instruction.

[0023] Optionally, in the apparatus according to an embodiment of the present invention, the register configuration unit is adapted to set the stub enable flag in the status control register to 1, and is also adapted to set the stub enable flag in the status control register to 0.

[0024] Optionally, in the apparatus according to an embodiment of the present invention, the instruction execution unit is further adapted to execute an object associated with the stub instruction.

[0025] Optionally, in the apparatus according to an embodiment of the present invention, the instruction execution unit is further adapted to save the current running state before performing exception handling, and is further adapted to restore the saved running state after the exception handling is completed.

[0026] Optionally, in the apparatus according to an embodiment of the present invention, the pile enable flag is a single-step enable flag.

[0027] Optionally, in the apparatus according to an embodiment of the present invention, the piling command includes a breakpoint command or a jump command.

[0028] According to another aspect of the present invention, a program debugging apparatus is provided, comprising: a stub setting unit, adapted to set instrumentation positions in the original instruction sequence of a program, and further adapted to replace the target instruction located at the instrumentation position in the original instruction sequence with a stub instruction to obtain a target instruction sequence; a program startup unit, adapted to start the program so that an instruction processing device executes the target instruction sequence; and an exception handling unit, adapted to perform exception handling when the stub instruction is executed, wherein the instruction processing device writes the target instruction corresponding to the stub instruction into an instruction cache register, and after the exception handling is completed, reads the target instruction from the instruction cache register and executes the target instruction step by step.

[0029] According to another aspect of the present invention, a computing device is provided, comprising: a memory; one or more processors including instruction processing means according to the present invention; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for performing a program debugging method according to the present invention.

[0030] According to another aspect of the present invention, a system-on-a-chip is provided, including an instruction processing apparatus according to the present invention.

[0031] According to another aspect of the present invention, a smart device is provided, including a system-on-a-chip according to the present invention.

[0032] According to the instruction processing scheme of the present invention, by adding a stub enable flag and an instruction cache register, the target instruction to be replaced by the stub instruction is written into the instruction cache register. This allows the processor (e.g., instruction processing device 200) to read and execute the target instruction from the instruction cache register after the stub exception is handled. At the same time, it jumps normally to the address space of the target instruction sequence, instead of jumping to another address space (e.g., another memory address in Kprobe / Uprobe technology). The target instruction is executed step by step in different address spaces and with different permissions. This achieves single-step execution of the target instruction in the same address space and with the same permissions. It solves the problem that the traditional single-step execution mechanism cannot effectively simulate some instructions in different address spaces and with different permissions. It also avoids the problems that may be caused by software simulation, such as increased software design complexity and difficulty in maintaining CPU microarchitectures across instruction sets.

[0033] The above description is merely an overview of the technical solutions of the embodiments of the present invention. In order to better understand the technical means of the embodiments of the present invention and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of the present invention more apparent and understandable, specific implementation methods of the embodiments of the present invention are described below. Attached Figure Description

[0034] To achieve the foregoing and related objectives, certain illustrative aspects are described herein in conjunction with the following description and accompanying drawings. These aspects indicate various ways in which the principles disclosed herein may be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. The foregoing and other objectives, features, and advantages of this disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings. Throughout this disclosure, the same reference numerals generally refer to the same parts or elements.

[0035] Figure 1 A schematic diagram of a processor 100 according to an embodiment of the present invention is shown;

[0036] Figure 2 A schematic diagram of an instruction processing apparatus 200 according to an embodiment of the present invention is shown;

[0037] Figure 3 A schematic diagram illustrating the variation of an instruction sequence according to an embodiment of the present invention is shown;

[0038] Figure 4 A flowchart of an instruction processing method 400 according to an embodiment of the present invention is shown;

[0039] Figure 5 A schematic diagram of a computing device 500 according to an embodiment of the present invention is shown;

[0040] Figure 6 A flowchart of a program debugging method 600 according to an embodiment of the present invention is shown;

[0041] Figure 7 A schematic diagram of a program debugging apparatus 700 according to an embodiment of the present invention is shown; and

[0042] Figure 8 A schematic diagram of a system-on-a-chip (SoC) 800 according to an embodiment of the present invention is shown. Detailed Implementation

[0043] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0044] Figure 1 A schematic diagram of a processor 100 according to an embodiment of the present invention is shown. In some embodiments, the processor 100 may be a processor, a processor core of a multi-core processor, or a processing element in an electronic system.

[0045] like Figure 1 As shown, processor 100 includes an instruction fetch unit 130. Instruction fetch unit 130 can fetch instructions to be processed from cache 110, memory 120, or other sources (such as instruction cache register 212 described later) and send them to decoding unit 140. Instructions fetched by instruction fetch unit 130 include, but are not limited to, high-level machine instructions or macro instructions. Processor 100 performs specific functions by executing these instructions.

[0046] Decoding unit 140 receives instructions from instruction fetch unit 130 and decodes these instructions to generate low-level micro-operations, microcode entry points, microinstructions, or other low-level instructions or control signals that reflect or are derived from the received instructions. The low-level instructions or control signals can implement the operations of high-level instructions through low-level (e.g., circuit-level or hardware-level) operations. Various different mechanisms can be used to implement decoding unit 140. Examples of suitable mechanisms include, but are not limited to, microcode, lookup tables, hardware implementations, and programmable logic arrays (PLAs). This invention is not limited to any particular mechanism for implementing decoding unit 140; any mechanism that can implement decoding unit 140 is within the scope of this invention.

[0047] Subsequently, these decoded instructions are sent to execution unit 150 and executed by execution unit 150. Execution unit 150 includes circuitry operable for executing instructions. While executing these instructions, execution unit 150 receives data inputs from register set 170, cache 110, and / or memory 120 and generates data outputs to them.

[0048] In one embodiment, register group 170 includes architecture registers, which are also referred to as registers. Unless otherwise specified or clearly apparent herein, the phrases architecture register, register group, and register are used to represent registers that are visible to software and / or the programmer (e.g., software-visible) and / or specified by macro instructions to identify operands. These registers are distinct from other non-architectural registers in a given microarchitecture (e.g., temporary registers, reorder buffers, retirement registers, etc.).

[0049] According to one embodiment, register group 170 may include a set of vector registers 175, each of which may be 512-bit, 256-bit, or 128-bit wide, or may use different vector widths. Optionally, register group 170 may also include a set of general-purpose registers 176. General-purpose registers 176 may be used by execution unit 150 when executing instructions.

[0050] The execution unit 150 may include multiple specific instruction execution units 150a, 150b...150c, etc. These instruction execution units include, for example, vector operation units, arithmetic logic units (ALU), integer units, floating-point units, memory execution units, etc., and can execute different types of instructions respectively.

[0051] To avoid confusion, a relatively simple processor 100 has been shown and described. It should be understood that the processor 100 can take different forms; for example, other embodiments of the processor 100 may have multiple cores, logical processors, or execution engines.

[0052] In an embodiment of the present invention, the processor 100 is implemented as an instruction processing device 200 and configured to execute an instruction processing method 400 according to an embodiment of the present invention.

[0053] Figure 2 A schematic diagram of an instruction processing apparatus 200 according to an embodiment of the present invention is shown. It should be noted that... Figure 2 In this document, the various components of the instruction processing device 200 are logically divided according to the operations to be implemented in the instruction processing device 200. These logical divisions are illustrative and can be re-divided according to actual physical layout and business needs without departing from the scope of protection of this invention. The instruction processing method 400 executed in the instruction processing device 200 can be... Figure 2 The various components shown are used to complete this process. When... Figure 2 When the components shown are recombined and divided, the corresponding method steps can be completed according to the logic carried by the new components, without departing from the protection scope of this invention.

[0054] like Figure 2 As shown, the instruction processing device 200 includes a status control register 211, an instruction cache register 212, an instruction execution unit 220, a register configuration unit 230, an instruction fetch unit 240, and a single-step execution unit 250.

[0055] The status control register 211 is adapted to control and / or store the status of the instruction processing device 200 and includes a stub enable flag for enabling the stub instruction execution mechanism (described in detail below) according to embodiments of the present invention. In some embodiments, the status control register 211 may be a 16-bit or 32-bit register, and the stub enable flag may be a bit in the status control register 211. The instruction cache register 116 may be a 16-bit, 32-bit, or 64-bit register, adapted to register instructions when the stub instruction execution mechanism is enabled.

[0056] The instruction execution unit 220 is adapted to execute a target instruction sequence, which includes stub instructions located at instrumentation positions. The instrumentation position (also called a stub) can be any position in the original instruction sequence that the user is interested in (e.g., for probing or debugging), and is pre-set by the user in the original instruction sequence. The target instruction sequence can be obtained by replacing the instructions located at instrumentation positions in the original instruction sequence with stub instructions; that is, the stub instructions replace the instructions located at instrumentation positions in the original instruction sequence (hereinafter referred to as target instructions). When the instruction processing device 200 executes a stub instruction, it generates an exception and jumps to execute the corresponding exception handling code to complete functions such as program tracing or debugging. Specifically, the stub instruction can be a breakpoint instruction (e.g., the BKPT instruction under the ARM architecture, the int3 instruction under the x86 architecture) or a jump instruction. This embodiment of the invention does not limit the specific type of stub instruction; any instruction that can achieve similar functions is within the scope of protection of this invention.

[0057] In some embodiments, when tracing or debugging a program, the user can specify any position in the program's original instruction sequence (the original instruction sequence is unmodified and does not include stub instructions) as an instrumentation position. After setting the instrumentation position, the target instruction located at the instrumentation position in the original instruction sequence can be replaced with the instrumentation instruction to obtain the aforementioned target instruction sequence.

[0058] For example, in Figure 3 In the diagram, the instruction sequence shown on the left is the original instruction sequence, which has not been modified by the instruction processing unit 200 and does not include stub instructions. Next, the user specifies the position of the instruction "inst3" in the original instruction sequence as the stub position. In this case, the instruction processing unit 200 replaces the target instruction "inst3" located at the stub position with the stub instruction, resulting in the target instruction sequence shown on the right.

[0059] According to one embodiment of the present invention, for example, before executing the target instruction sequence, the instruction execution unit 220 may record the instrumentation position, the target instruction to be replaced at the instrumentation position, and the correspondence between the two for subsequent querying. For example, this can be recorded in a data structure.

[0060] When instruction execution unit 220 executes a stub instruction, an exception is generated (this exception is called a stub exception). It should be understood that an exception is a synchronization event, a response of the processor to certain conditions detected during instruction execution (such as the execution of certain instructions). An exception causes the processor to change the order of instruction execution; for example, the processor may suspend the execution of the current instruction sequence and switch to exception handling, executing the corresponding exception handling code. Exceptions generated by executing stub instructions can be called stub exceptions.

[0061] The instruction execution unit 220 can handle the stub exception. In some embodiments, handling the stub exception includes, but is not limited to, executing the object associated with the stub instruction (the object may be, for example, a function, and may be configurable by the user), viewing the value of a variable, pausing the execution of certain instructions, etc. This invention does not limit this.

[0062] Before handling stub exceptions, the instruction execution unit 220 can also save the current execution state, such as saving the address in the program counter (PC), so that it can be restored after the stub exception is handled. It should be understood that when the processor executes a sequence of instructions, it must sequentially determine the address of the next instruction to be executed to ensure normal execution. The program counter (PC) is precisely the element used for this purpose; it stores the address of the next instruction to be executed. Typically, instructions are executed sequentially. Before execution begins, the address of the first instruction is always written to the program counter (PC). When the first instruction is fetched and executed, the content of the program counter (PC) automatically increments, indicating the address of the next instruction to be executed. Therefore, at this time, the program counter (PC) stores the address of the instruction following the currently executed stub instruction in the target instruction sequence.

[0063] Furthermore, when a stub instruction is executed, the register configuration unit 230, connected to the instruction execution unit 220, is adapted to enable the stub enable flag in the status control register 211 in response to the execution of the stub instruction, thereby enabling the stub instruction execution mechanism. Normally, setting the stub enable flag to 1 indicates that the stub instruction execution mechanism is enabled. Setting the stub enable flag to 0 indicates that the stub instruction execution mechanism is disabled.

[0064] It should be noted that the status control register 211 may also include a single-step enable flag, which is used to enable the traditional single-step execution mechanism. As mentioned in the background section, the instruction at the probe point can currently be replaced with a breakpoint instruction, and the replaced instruction can be copied to another memory address. When the processor executes the breakpoint instruction, an exception (called a breakpoint exception) is generated, the breakpoint exception handling is entered, and the single-step enable flag is simultaneously configured to be valid to enable the traditional single-step execution mechanism.

[0065] In traditional single-step execution, the memory address containing the instruction to be replaced needs to be written to the program counter (PC). This allows the program to jump to that memory address after the breakpoint exception is handled, and execute the instruction step-by-step. Understandably, a single-step exception (an exception that occurs after a single-step execution instruction) will occur after the single-step execution instruction, and the single-step exception handling will be initiated.

[0066] Since the stub instruction execution mechanism according to embodiments of the present invention involves single-step execution of instructions (described in detail below), in some embodiments, the single-step enable flag can be directly used as the stub enable flag. In this case, the stub instruction execution mechanism according to embodiments of the present invention replaces the traditional single-step execution mechanism. In other embodiments, a separate stub enable flag can be added. The stub instruction execution mechanism according to embodiments of the present invention can be enabled by configuring the stub enable flag, and the traditional single-step execution mechanism can be enabled by configuring the single-step enable flag.

[0067] The execution mechanism of the stub command according to an embodiment of the present invention is described in detail below.

[0068] In response to detecting a valid stub enable flag (i.e., when the stub instruction execution mechanism is enabled), the register configuration unit 230 obtains the target instruction corresponding to the currently executed stub instruction and writes the target instruction into the instruction cache register 212.

[0069] Specifically, the register configuration unit 230 can determine the target instruction that was originally located at the stub position of the stub instruction based on the previously recorded correspondence between the stub instruction and the target instruction, and obtain the target instruction.

[0070] After the above-mentioned stub anomaly handling is completed, the instruction execution unit 220 can also restore the running state saved before handling the stub anomaly. For example, the previously saved address can be rewritten to the program counter PC by a return instruction (e.g., a ret instruction). At this time, since the target instruction has not yet been executed, according to the embodiment of the present invention, the instruction execution unit 220 does not temporarily fetch and execute the instruction pointed to by the address, that is, the next instruction in the target instruction sequence of the stub instruction (which is also the next instruction in the original instruction sequence of the target instruction).

[0071] The instruction reading unit 240 is connected to the instruction execution unit 220 and is adapted to read the target instruction from the instruction cache register 212 after the stub anomaly handling is completed and a valid stub enable flag is detected. The single-step execution unit 250 connected to the instruction reading unit 240 then executes the target instruction step by step.

[0072] A single-step exception occurs after single-stepping the target instruction, triggering single-step exception handling. Similarly, before handling a single-step exception, the current execution state can be saved, for example, by saving the address in the program counter (PC). After single-step exception handling is complete, the single-step execution unit 250 can restore the execution state saved before handling the exception, for example, by rewriting the previously saved address into the program counter (PC) using a return instruction. Since the instruction previously pointed to by the program counter (PC) was not fetched and executed, the address in the program counter (PC) remains unchanged, still being the address of the next instruction in the target instruction sequence following the stub instruction. Therefore, the instruction execution unit 220 can resume execution of the target instruction sequence, that is, continue executing the remaining instructions starting from the instruction following the stub instruction in the target instruction sequence.

[0073] Furthermore, in some embodiments, after single-step execution of the target instruction, the register configuration unit 230 is also adapted to configure the stub enable flag to be invalid in order to disable the stub instruction processing mechanism and avoid generating unnecessary stub exceptions again.

[0074] Figure 4 A flowchart of an instruction processing method 400 according to an embodiment of the present invention is shown. Figure 4 As shown, the instruction processing method 400 begins at step S410 and is adapted to be executed in the instruction processing device 200.

[0075] In step S410, the target instruction sequence is executed, for example, execution begins at the user's instruction.

[0076] The target instruction sequence includes a stake point instruction located at the stake position, which replaces the target instruction at the stake position in the original instruction sequence. For example... Figure 3 As shown, if the user specifies the position of the instruction "inst3" in the original instruction sequence as the instrumentation position, then the target instruction sequence is obtained by replacing the target instruction "inst3" with the stub instruction in the original instruction sequence.

[0077] According to one embodiment of the present invention, the above-mentioned stake position, the target command that was replaced at the stake position, and the correspondence between the two can be recorded for subsequent querying.

[0078] When the stub instruction is executed, an exception occurs, and this exception is handled in step S420. Specifically, the current runtime state can be saved first so that it can be restored after the exception is handled. Next, the exception is handled, for example, by executing the object associated with the stub instruction, which can be configured by the user. After the exception is handled, the runtime state before the exception handling is restored based on the saved runtime state. For example, the previously saved address is rewritten to the program counter PC by a return instruction, that is, jumping to the next instruction in the target instruction sequence after the stub instruction, but the instruction is not executed at this time.

[0079] Simultaneously, in step S430, in response to the execution of a stub instruction, the stub enable flag in the status control register 211 is configured to be valid to enable the stub instruction execution mechanism. Next, in step S440, in response to the detection of a valid stub enable flag, the target instruction corresponding to the stub instruction can be obtained and written to the instruction cache register 212.

[0080] Specifically, the target instruction can be determined based on the previously recorded correspondence between the pile point instruction and the target instruction.

[0081] After the above exception handling is completed, if the stub instruction execution mechanism is enabled, the target instruction can be read from the instruction cache register 212 in step S450, and the target instruction can be executed step by step in step S460.

[0082] Understandably, after single-stepping through the target instructions, a single-step exception will occur and need to be handled. According to one embodiment of the present invention, the current running state can be saved before single-step exception handling and restored after single-step exception handling, thereby resuming the execution of the target instruction sequence, that is, continuing to execute the remaining instructions from the instruction following the stub instruction in the target instruction sequence.

[0083] Finally, after stepping through the target instruction, the stub enable flag can be configured to be invalid to disable the stub instruction processing mechanism.

[0084] For detailed processing logic and implementation process of each step in instruction processing method 400, please refer to the preceding text. Figures 1-3 The description of the instruction processing device 200 will not be repeated here.

[0085] In summary, the instruction processing scheme according to embodiments of the present invention adds a stub enable flag and an instruction cache register, and writes the target instruction to be replaced by the stub instruction into the instruction cache register. This allows the processor (e.g., instruction processing device 200) to read and execute the target instruction from the instruction cache register after the stub exception is handled. At the same time, it jumps normally to the address space of the target instruction sequence, instead of jumping to another address space (e.g., another memory address in Kprobe / Uprobe technology). The target instruction is executed step by step in different address spaces and with different permissions, thereby realizing the single-step execution of the target instruction in the same address space and with the same permissions. This solves the problem that the traditional single-step execution mechanism cannot effectively simulate some instructions in different address spaces and with different permissions. It also avoids the problems that may be caused by software simulation, such as increased software design complexity and difficulty in maintaining CPU microarchitectures across instruction sets.

[0086] The following describes a program debugging apparatus that applies an instruction processing scheme according to an embodiment of the present invention. This program debugging apparatus can be implemented as a computing device as described below.

[0087] Figure 5 A schematic diagram of a computing device 500 according to an embodiment of the present invention is shown. Figure 5 As shown, in the basic configuration 502, the computing device 500 typically includes a system memory 506 and one or more processors 504. A memory bus 508 can be used for communication between the processors 504 and the system memory 506.

[0088] Depending on the desired configuration, processor 504 can be any type of processor, including but not limited to: microprocessors (μP), microcontrollers (μC), digital information processors (DSPs), or any combination thereof. Processor 504 may include one or more levels of cache such as L1 cache 510 and L2 cache 512, processor core 514, and registers 516. Example processor core 514 may include an arithmetic logic unit (ALU), a floating-point unit (FPU), a digital signal processing core (DSP core), or any combination thereof. Example memory controller 518 may be used with processor 504, or in some implementations, memory controller 518 may be an internal part of processor 504. Depending on the desired configuration, system memory 506 can be any type of memory, including but not limited to: volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof. System memory 506 may include operating system 520, one or more programs 522, and program data 524. In some embodiments, program 522 may be arranged to execute instructions on the operating system using program data 524.

[0089] The computing device 500 may also include an interface bus 540 that facilitates communication from various interface devices (e.g., output devices 542, peripheral interfaces 544, and communication devices 546) to the basic configuration 502 via a bus / interface controller 530. Example output devices 542 include a graphics processing unit 548 and an audio processing unit 550. They may be configured to facilitate communication with various external devices such as displays or speakers via one or more A / V ports 552. Example peripheral interfaces 544 may include a serial interface controller 554 and a parallel interface controller 556, which may be configured to facilitate communication with external devices such as input devices (e.g., keyboards, mice, pens, voice input devices, touch input devices) or other peripherals (e.g., printers, scanners, etc.) via one or more I / O ports 558. Example communication devices 546 may include a network controller 560, which may be arranged to facilitate communication with one or more other computing devices 562 via a network communication link through one or more communication ports 564.

[0090] A network communication link can be an example of a communication medium. A communication medium can typically be embodied in a modulated data signal, such as a carrier wave or other transmission mechanism, and can include any information delivery medium. A “modulated data signal” can be a signal whose data set, or whose modifications, can be encoded with information within the signal. As a non-limiting example, a communication medium can include wired media such as wired networks or leased lines, and various wireless media such as sound, radio frequency (RF), microwave, infrared (IR), or other wireless media. The term “computer-readable medium” as used herein can include both storage media and communication media.

[0091] The computing device 500 can be implemented as a server, such as a database server, application server, and web server, or as a personal computer with configurations including desktop and laptop computers. Of course, the computing device 500 can also be implemented as part of a small, portable (or mobile) electronic device.

[0092] In an embodiment of the present invention, the computing device 500 is implemented as a program debugging device 700. One or more processors 504 include an instruction processing unit 200 and are configured to execute the instruction processing method 400 according to an embodiment of the present invention. The program 522 of the computing device 500 contains multiple instructions for executing the program debugging method 600 according to an embodiment of the present invention, and the program data 524 may also store configuration data and other content of the program debugging device 700. The program 522 of the computing device 500 may also include other programs to be monitored, tracked, or debugged using the program debugging device 700.

[0093] Figure 6 A flowchart of a program debugging method 600 according to an embodiment of the present invention is shown. Figure 6 As shown, the program debugging method 600 begins at step S610 and is adapted to be executed in the program debugging device 700.

[0094] In step S610, an instrumentation position is set in the original instruction sequence of the program, for example, at the user's instruction. The instrumentation position can be any position in the original instruction sequence that the user is interested in.

[0095] Then, in step S620, the target instruction located at the stub position in the original instruction sequence is replaced with a stub instruction, thereby obtaining the target instruction sequence. Furthermore, the stub position, the target instruction, and the correspondence between them can be recorded.

[0096] After the target instruction is replaced, in step S630, the program is started (e.g., at the user's instruction) so that the instruction processing device 200 executes the target instruction sequence. An exception occurs when the stub instruction is executed. This exception can be handled in step S640. Specifically, the exception can be handled, for example, by the instruction processing device 200 after saving the current operating state. Handling the exception may include executing the object associated with the stub instruction, which may be configured by the user.

[0097] It should be noted that, due to the use of the instruction processing apparatus 200 according to an embodiment of the present invention, the instruction processing apparatus 200 can configure the stub enable flag in the status control register 211 to be valid in response to the execution of a stub instruction. Furthermore, the instruction processing apparatus 200 also acquires the currently executed stub instruction in response to detecting a valid stub enable flag. Place The corresponding target instruction is written into the instruction cache register 212.

[0098] After the exception is handled, the instruction processing unit 200 can read the target instruction from the instruction cache register 212 and execute the target instruction step by step.

[0099] For detailed processing logic and implementation process of each step in program debugging method 600, please refer to the preceding text. Figures 1-4 The descriptions of the instruction processing device 200 and the instruction processing method 400 will not be repeated here.

[0100] Figure 7 A schematic diagram of a program debugging apparatus 700 according to an embodiment of the present invention is shown. It should be noted that... Figure 7 In this document, the various components of the program debugging device 700 are logically divided according to the operations to be implemented in the program debugging device 700. These logical divisions are illustrative and can be re-divided according to actual physical layout and business needs without departing from the scope of protection of this invention. The program debugging device method 600 executed in the program debugging device 700 can be... Figure 7 The various components shown are used to complete this process. When... Figure 7 When the components shown are recombined and divided, the corresponding method steps can be completed according to the logic carried by the new components, without departing from the protection scope of this invention.

[0101] like Figure 7 As shown, the program debugging device 700 includes a pile point setting unit 710, a program startup unit 720, and an exception handling unit 730.

[0102] The stub setting unit 710 is adapted to set the stub position in the original instruction sequence of the program, and replace the target instruction located at the stub position in the original instruction sequence with the stub instruction to obtain the target instruction sequence.

[0103] The program initiation unit 720 is connected to the stub setting unit 710 and is adapted to initiate a program so that the instruction processing device 200 executes the target instruction sequence. An exception occurs when the stub instruction is executed.

[0104] An exception handling unit 730, connected to the program initiation unit 720, is adapted to handle the exception. Specifically, the exception can be handled, for example, via the instruction processing device 200 after saving the current running state. Exception handling may include executing an object associated with the stub instruction, which may be user-configurable.

[0105] It should be noted that, due to the use of the instruction processing apparatus 200 according to an embodiment of the present invention, the instruction processing apparatus 200 can configure the stub enable flag in the status control register 211 to be valid in response to the execution of a stub instruction. Furthermore, the instruction processing apparatus 200 also acquires the currently executed stub instruction in response to detecting a valid stub enable flag. PlaceThe corresponding target instruction is written into the instruction cache register 212 so that after the exception handling is completed, the instruction processing device 200 can read the target instruction from the instruction cache register 212 and execute the target instruction step by step.

[0106] For detailed processing logic and implementation procedures of each unit in the program debugging device 700, please refer to the preceding text. Figures 1-4 The descriptions of the instruction processing device 200 and the instruction processing method 400 will not be repeated here.

[0107] It should be understood that the instruction processing device 200 can take different forms, for example, it can be implemented as a processor core, and the instruction processing method 400 can be executed within the processor core. The processor core can be implemented in different ways in different processors. For example, the processor core can be implemented as a general-purpose ordered core for general-purpose computing, a high-performance general-purpose unordered core for general-purpose computing, and a dedicated core for graphics and / or scientific (throughput) computing. The processor can be implemented as a CPU (Central Processing Unit) and / or a coprocessor, where the CPU may include one or more general-purpose ordered cores and / or one or more general-purpose unordered cores, and the coprocessor may include one or more dedicated cores. Such combinations of different processors can lead to different computer system architectures. In one computer system architecture, the coprocessor is on a separate chip from the CPU. In another computer system architecture, the coprocessor is in the same package as the CPU but on a separate die. In yet another computer system architecture, the coprocessor is on the same die as the CPU (in this case, such a coprocessor is sometimes referred to as dedicated logic such as integrated graphics and / or scientific (throughput) logic, or as a dedicated core). In another type of computer system architecture called a system-on-a-chip, the CPU described above (sometimes referred to as an application core or application processor), the coprocessor described above, and additional functions can be included on the same die.

[0108] Figure 8 A schematic diagram of a system-on-a-chip (SoC) 800 according to an embodiment of the present invention is shown. Figure 8As shown, interconnect unit 802 is coupled to application processor 810, system proxy unit 812, bus controller unit 814, integrated memory controller unit 816, one or more coprocessors 820, static random access memory (SRAM) unit 830, direct memory access (DMA) unit 832, and display unit 840 for coupling to one or more external displays. Application processor 810 includes a collection of one or more cores 811A-N and a shared cache unit 813. Coprocessor 820 includes integrated graphics logic, an image processor, an audio processor, and a video processor. In one embodiment, coprocessor 820 includes a dedicated processor, such as, for example, a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, or an embedded processor, etc.

[0109] In addition, the system-on-a-chip 800 described above can be included in a smart device to implement corresponding functions in the smart device, including but not limited to executing relevant control programs, performing data analysis, calculation and processing, network communication, and controlling peripherals in the smart device.

[0110] Such smart devices include specialized smart devices, such as mobile terminals and personal digital terminals, which include one or more on-chip systems according to embodiments of the present invention for data processing or for controlling peripherals in the device.

[0111] Such smart devices also include specialized devices designed to perform specific functions, such as smart speakers and smart display devices. These devices include a system-on-a-chip (SoC) according to embodiments of the present invention to control the speaker and display device, thereby endowing the speaker and display device with additional communication, sensing, and data processing functions.

[0112] Such smart devices also include various IoT devices and AIoT devices. These devices include on-chip systems according to embodiments of the present invention that perform data processing, such as AI calculations, data communication and transmission, thereby enabling a denser and more intelligent device distribution.

[0113] Such smart devices can also be used in vehicles, for example, as in-vehicle devices or embedded in vehicles, thereby providing data processing capabilities for intelligent driving.

[0114] Such smart devices can also be used in the home and entertainment sectors, for example, as smart speakers, smart air conditioners, smart refrigerators, and smart display devices. These devices utilize the system-on-a-chip according to the present invention for data processing and peripheral control, thereby enabling the intelligentization of home and entertainment devices.

[0115] Furthermore, such intelligent devices can also be used in industrial fields, for example, as industrial control equipment, sensing devices, IoT devices, AIoT devices, and braking devices. These devices include the system-on-a-chip according to the present invention for data processing and peripheral control, thereby realizing the intelligence of industrial equipment.

[0116] The above description of smart devices is merely illustrative. Smart devices based on the present invention are not limited thereto. All smart devices that can perform data processing using the system-on-a-chip according to embodiments of the present invention are within the protection scope of the present invention.

[0117] The various embodiments of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or combinations of these implementations. Embodiments of the invention can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.

[0118] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0119] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various aspects of the invention, in the above description of exemplary embodiments of the invention, various features of the embodiments are sometimes grouped together in a single embodiment, figure, or description thereof. However, this method of disclosure should not be construed as reflecting an intention that the claimed embodiments of the invention require more features than expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the invention.

[0120] Those skilled in the art will understand that modules, units, or components of the devices disclosed in the examples herein can be arranged in the devices described in this embodiment, or alternatively, can be located in one or more devices different from the devices in this example. The modules in the foregoing examples can be combined into a single module or, in addition, can be divided into multiple sub-modules.

[0121] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0122] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features included in other embodiments but not others, combinations of features from different embodiments are meant to be within the scope of the embodiments of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0123] Furthermore, some of the embodiments described herein are methods or combinations of method elements that can be implemented by a processor of a computer system or by other means of performing the above functions. Therefore, a processor having the necessary instructions for implementing the above methods or method elements forms means for implementing the method or method elements. Furthermore, the elements described herein in the apparatus embodiments are examples of means for implementing the functions performed by elements for the purpose of carrying out the invention.

[0124] As used herein, unless otherwise specified, the use of ordinal numbers such as “first,” “second,” “third,” etc., to describe ordinary objects merely indicates different instances of similar objects and is not intended to imply that the objects being described must have a given order in time, space, ordering, or any other manner.

[0125] Although embodiments of the invention have been described with respect to a limited number of examples, those skilled in the art will understand from the foregoing description that other embodiments are conceivable within the scope of the embodiments described herein. Furthermore, it should be noted that the language used in this specification has been chosen primarily for readability and instructional purposes, and not for the purpose of interpreting or limiting the subject matter of the embodiments of the invention. Therefore, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of embodiments of the invention is illustrative rather than restrictive, and the scope of the embodiments is defined by the appended claims.

Claims

1. An instruction processing method, comprising: Execute the target instruction sequence including stub instructions, and perform exception handling when the stub instruction is executed; Write the target instruction corresponding to the stub instruction into the instruction cache register. The target instruction is the instruction in the target instruction sequence that is replaced by the stub instruction at the stub position. After the exception handling is completed, the target instruction is read from the instruction cache register; as well as Execute the target instruction step by step; The method further includes: In response to the execution of the stub instruction, the stub enable flag in the status control register is configured to be valid; Before handling the exception, save the current running state; and after the exception handling is completed, restore the saved running state.

2. The method as described in claim 1, wherein, Writing the target instruction corresponding to the stub instruction into the instruction cache register includes: In response to the detection of a valid pile enable flag, the target instruction corresponding to the pile instruction is obtained; Write the target instruction into the instruction cache register.

3. The method of claim 2, further comprising: Before executing the target instruction sequence, the target instruction located at the staking position in the original instruction sequence is replaced with the staking point instruction to obtain the target instruction sequence.

4. The method of claim 3, further comprising: Record the correspondence between the stake positions and the target commands; as well as Obtaining the target instruction corresponding to the pile point instruction includes: Based on the correspondence, the target instruction that was originally located at the pile insertion position where the pile point instruction was located is determined.

5. The method of claim 1, further comprising: After executing the target instruction step by step, the stub enable flag is configured to be invalid.

6. The method of claim 5, wherein, Configure the stub enable flag in the status control register to be valid, including: Set the stub enable flag in the status control register to 1; and Configure the stub enable flag in the status control register to be invalid, including: Set the stub enable flag in the status control register to 0.

7. The method of claim 1, wherein, Perform exception handling, including: Execute the object associated with the said piling command.

8. The method according to any one of claims 1-7, wherein, The enable flag for the pile point is a single-step enable flag.

9. The method according to any one of claims 1-7, wherein, The piling point commands include breakpoint commands or jump commands.

10. A program debugging method, comprising: Set the instrumentation position in the program's original instruction sequence; Replace the target instruction located at the stake position in the original instruction sequence with the stake point instruction to obtain the target instruction sequence; The program is initiated so that the instruction processing device executes the target instruction sequence; as well as When the stub instruction is executed, exception handling is performed. The instruction processing device writes the target instruction corresponding to the stub instruction into the instruction cache register. After the exception handling is completed, the target instruction is read from the instruction cache register and executed step by step. Before performing exception handling, the instruction processing device saves the current running state. After the exception handling is completed, the saved running state is restored. In response to the execution of the stub instruction, the instruction processing device configures the stub enable flag to be valid.

11. An instruction processing apparatus, comprising: Instruction cache register, suitable for storing instructions; The instruction execution unit is adapted to execute a target instruction sequence including stub instructions, and to perform exception handling when the stub instruction is executed; The register configuration unit is adapted to write the target instruction corresponding to the stub instruction into the instruction cache register, wherein the target instruction is the instruction that is replaced by the stub instruction at the stub position in the target instruction sequence; The instruction fetch unit is adapted to read the target instruction from the instruction cache register after the exception handling is completed; and A single-step execution unit, adapted to execute the target instruction step by step; The instruction execution unit is further adapted to save the current running state before performing exception handling, and is also adapted to restore the saved running state after the exception handling is completed. The device further includes: Status control register, including stub enable flags; The register configuration unit is also adapted to configure the stub enable flag to be valid in response to execution of the stub instruction.

12. The apparatus of claim 11, wherein, The register configuration unit is also adapted to, in response to detecting a valid stub enable flag, obtain the target instruction corresponding to the stub instruction and write the target instruction into the instruction cache register.

13. The apparatus of claim 11, wherein, The instruction execution unit is further adapted to replace the target instruction located at the staking position in the original instruction sequence with a staking point instruction before executing the target instruction sequence, thereby obtaining the target instruction sequence.

14. The apparatus of claim 13, wherein, The instruction execution unit is further adapted to record the correspondence between the instrumentation position and the target instruction; the register configuration unit is further adapted to determine the target instruction originally located at the instrumentation position where the instrumentation instruction was located, based on the correspondence.

15. The apparatus of claim 11, wherein, The register configuration unit is also adapted to configure the stub enable flag to be invalid after single-step execution of the target instruction.

16. The apparatus of claim 15, wherein, The register configuration unit is adapted to set the stub enable flag in the status control register to 1, and is also adapted to set the stub enable flag in the status control register to 0.

17. The apparatus of claim 11, wherein, The instruction execution unit is also adapted to execute objects associated with the stub instruction.

18. The apparatus according to any one of claims 11-17, wherein, The enable flag for the pile point is a single-step enable flag.

19. The apparatus according to any one of claims 11-17, wherein, The piling point commands include breakpoint commands or jump commands.

20. A program debugging device, comprising: The stub setting unit is adapted to set stub positions in the original instruction sequence of the program, and is also adapted to replace the target instruction located at the stub position in the original instruction sequence with a stub instruction to obtain a target instruction sequence. A program initiation unit is adapted to initiate the program so that the instruction processing device executes the target instruction sequence; as well as An exception handling unit is adapted to perform exception handling when the stub instruction is executed. The instruction processing device writes the target instruction corresponding to the stub instruction into the instruction cache register, and after the exception handling is completed, reads the target instruction from the instruction cache register and executes the target instruction step by step. Before performing exception handling, the instruction processing device saves the current running state, and after the exception handling is completed, it restores the saved running state. In response to the execution of the stub instruction, the instruction processing device configures the stub enable flag to be valid.

21. A computing device, comprising: Memory; One or more processors, including the instruction processing means as described in any one of claims 11-19; as well as One or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for performing the program debugging method as described in claim 10.

22. A system-on-a-chip, comprising an instruction processing apparatus as claimed in any one of claims 11-19.

23. A smart device comprising the system-on-a-chip as described in claim 22.

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