Matrix calculation circuit, method, electronic device and computer-readable storage medium

Abstract

The embodiments of the present disclosure disclose a matrix calculation circuit, method, electronic device, and computer-readable storage medium. The matrix calculation circuit includes: a first data reading circuit for reading and caching first data and position information of the first data in a first matrix, wherein the first matrix is ​​a compressed matrix of a data matrix; generating a calculation control signal according to the position information of the first data; a second data reading circuit for reading and caching second data in a second matrix according to the position information of the first data; and a calculation circuit for calculating third data based on the calculation control signal, the first data, and the second data. The above-mentioned matrix calculation circuit controls the calculation process of the calculation circuit by the position information of the read first data, thereby solving the technical problem in the prior art that only single data calculation can be performed when performing matrix calculation and the calculation of the data access address is complicated.

Description

Technical Field

[0001] The present disclosure relates to the field of processors, and in particular to a matrix calculation circuit, method, electronic device, and computer-readable storage medium. Background Art

[0002] With the advancement of science and technology, human society is rapidly entering the intelligent era. A key characteristic of this era is the increasing variety and volume of data available, coupled with the increasing demand for faster data processing. Chips are the cornerstone of task allocation and fundamentally determine our ability to process data. From an application perspective, there are two main approaches to chip development: general-purpose chips, such as CPUs (central processing units), offer significant flexibility but exhibit relatively low effective computing power when processing domain-specific algorithms. Specialized chips, such as TPUs (tensor processing units), offer high effective computing power in specific domains, but their processing capabilities are limited or even incapable of handling the more flexible and diverse general domains. Given the diverse and massive amounts of data in the intelligent era, chips must possess both extreme flexibility to handle diverse and rapidly evolving algorithms and robust processing capabilities to rapidly process vast and rapidly growing volumes of data.

[0003] In neural network calculations, convolution calculations account for the majority of the total computational workload, and convolution calculations can be converted into matrix multiplication calculations. Therefore, to increase the throughput of neural network tasks, reduce latency, and enhance the effective computing power of the chip, the focus is on increasing the speed of matrix multiplication calculations.

[0004] Many neural network data matrices (including neural network parameter data and input data) are sparse matrices, meaning that a large number of elements in the matrix have a value of 0. To reduce the amount of data stored and bandwidth used in neural network calculations, sparse matrices are compressed for storage; to increase the speed of matrix operations, sparse matrix operations are optimized.

[0005] Figure 1a This is a schematic diagram of matrix multiplication calculation in neural networks. Figure 1a As shown, M1 is the data matrix, M2 is the parameter matrix, and M is the output matrix. A row of data in M1 and a column of parameters in M2 are multiplied and added to obtain a data in M. Figure 1a Of the two matrices M1 and M2, one or both may be sparse matrices.

[0006] like Figure 1bThe figure shows a schematic diagram of matrix compression. For storage in sparse matrices, a general compression method can be used: only non-zero elements are stored. When storing the value of this non-zero element, its position information in the matrix is ​​also stored, that is, the relative coordinates X and Y of the element in the matrix. Among them, X represents the matrix row number, and Y represents the matrix column number. This method treats data and coordinates as a data structure and stores them in units of this data structure. Figure 1b As shown, taking an MxN matrix as an example, the MxN matrix on the left is compressed into the compressed matrix on the right, and each data structure in the compressed matrix represents the non-zero data in the left matrix and the coordinates of the non-zero data in the matrix.

[0007] In a sparse matrix, since some elements in the matrix have a value of 0, and these 0 elements do not need to be stored, this compression method can effectively reduce the storage capacity of the matrix. Figure 1c The figure below shows an example of using the above compression method to compress a matrix. For a 16x16 sparse matrix, only a, b, c, and d are non-zero elements. After compression, only the values ​​and coordinates of these elements need to be stored, thus saving storage space.

[0008] When performing M1xM2 matrix operations, the compressed matrix is ​​used as the matrix for actual data retrieval. However, the above technical solution has the following disadvantages: 1. Data utilization is low during matrix operations, and usually only independent operation units can be used to perform calculations on single data; 2. Based on the data coordinates of the compressed matrix, the calculation of the data retrieval address is complex, which affects performance. Summary of the Invention

[0009] This summary is provided to briefly introduce concepts that will be described in detail in the detailed description below. This summary is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0010] In order to solve the above technical problems in the prior art, the present disclosure proposes the following technical solutions:

[0011] In a first aspect, an embodiment of the present disclosure provides a matrix calculation circuit, comprising:

[0012] a first data reading circuit configured to read and cache first data and position information of the first data in a first matrix, wherein the first matrix is ​​a compressed matrix of a data matrix; and generate a calculation control signal according to the position information of the first data;

[0013] a second data reading circuit, configured to read and cache second data in a second matrix according to position information of the first data;

[0014] A calculation circuit is used to calculate and obtain third data according to the calculation control signal, the first data and the second data.

[0015] Furthermore, the first data reading circuit further includes:

[0016] a first data cache circuit, a first data sorting circuit, and a first control circuit;

[0017] Wherein, the first control circuit is used to generate a first data reading address according to the first address of the first matrix;

[0018] The first data cache circuit is used to cache the first data read according to the first data read address and the position information of the first data;

[0019] The first data sorting circuit is used to reorder the first data position information and the first data in a one-to-one position correspondence according to the first data position information in the first data cache circuit, wherein the reordering result is that the data in the same row in the data matrix remains in the same row, and the data in the same column in the data matrix remains in the same column.

[0020] Furthermore, the first data sorting circuit is further configured to send row information in the position information of the first data to the first control circuit; and the first control circuit is further configured to generate the calculation control signal according to the row information.

[0021] Furthermore, the first control circuit is further configured to generate the calculation control signal according to the row information, including:

[0022] The first control circuit is configured to determine whether the row information is a first value;

[0023] If the row information is a first value, generating a first control signal to control a row of computing units corresponding to the row information in the computing circuit not to perform computing;

[0024] If the row information is not the first value, a second control signal is generated to control a row of computing units corresponding to the row information in the computing circuit to perform calculations.

[0025] Furthermore, the second data reading circuit further includes:

[0026] a second data cache circuit and a second control circuit;

[0027] The second control circuit is configured to generate a second data reading address according to the first address of the second matrix and the position information of the first data;

[0028] The second data cache circuit is used to cache the second data read out according to the second data read address.

[0029] Furthermore, the second control circuit is configured to generate a second data reading address according to the first address of the second matrix and the position information of the first data, including:

[0030] The second control circuit is configured to generate the second data reading address according to the first address of the second matrix and the column information in the position information of the first data.

[0031] Furthermore, the calculation circuit includes:

[0032] A computing unit array, wherein the computing unit array includes a plurality of computing units;

[0033] A row computing unit in the computing unit array receives a row of second data in the second data;

[0034] A row computing unit in the computing unit array receives a column of first data in the first data.

[0035] In a second aspect, an embodiment of the present disclosure provides a matrix calculation method, including:

[0036] Reading and buffering first data and position information of the first data in a first matrix, wherein the first matrix is ​​a compressed matrix of a data matrix; and generating a calculation control signal according to the position information of the first data;

[0037] Reading and caching second data in a second matrix according to the position information of the first data;

[0038] Third data is obtained by calculation according to the calculation control signal, the first data and the second data.

[0039] In a third aspect, an embodiment of the present disclosure further provides a processing core, which includes at least one matrix calculation circuit according to any one of the first aspects, a decoding unit, and a storage device.

[0040] In a fourth aspect, an embodiment of the present disclosure further provides a chip, comprising at least one processing core according to the third aspect.

[0041] In a fifth aspect, an embodiment of the present disclosure provides an electronic device, comprising: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, so that the processors implement any matrix calculation method described in the first aspect when executing.

[0042] In a sixth aspect, an embodiment of the present disclosure provides a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions, which are used to enable a computer to execute any matrix calculation method described in the first aspect.

[0043] In a seventh aspect, an embodiment of the present disclosure provides a computer program product, characterized in that it includes computer instructions. When the computer instructions are executed by a computing device, the computing device can execute any matrix calculation method described in the first aspect.

[0044] In an eighth aspect, an embodiment of the present disclosure provides a computing device, characterized in that it includes one or more chips described in the fourth aspect.

[0045] The embodiments of the present disclosure disclose a matrix calculation circuit, method, electronic device, and computer-readable storage medium. The matrix calculation circuit includes: a first data reading circuit for reading and caching first data and position information of the first data in a first matrix, wherein the first matrix is ​​a compressed matrix of a data matrix; generating a calculation control signal according to the position information of the first data; a second data reading circuit for reading and caching second data in a second matrix according to the position information of the first data; and a calculation circuit for calculating third data based on the calculation control signal, the first data, and the second data. The above-mentioned matrix calculation circuit controls the calculation process of the calculation circuit by the position information of the read first data, thereby solving the technical problem in the prior art that only single data calculation can be performed when performing matrix calculation and the calculation of the data access address is complicated.

[0046] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the following specifically cites preferred embodiments and describes them in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the originals and elements are not necessarily drawn to scale.

[0048] Figures 1a-1c It is a schematic diagram of the prior art disclosed herein;

[0049] Figure 2 A schematic diagram of the structure of a matrix calculation circuit provided in an embodiment of the present disclosure;

[0050] Figure 3A schematic structural diagram of a first data reading circuit provided in an embodiment of the present disclosure;

[0051] Figure 4 An example schematic diagram of reordering of a first data reading circuit provided by an embodiment of the present disclosure;

[0052] Figure 5 A schematic structural diagram of a second data reading circuit provided in an embodiment of the present disclosure;

[0053] Figure 6 A schematic diagram of the structure of a calculation control signal generating circuit provided in an embodiment of the present disclosure;

[0054] Figures 7a-7e A schematic diagram of an application example of an embodiment of the present disclosure;

[0055] Figure 8 A flowchart of a matrix calculation method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] The following describes embodiments of the present disclosure in more detail with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0057] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0058] As used herein, the term "including" and its variations are open-ended, i.e., "including but not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment," the term "another embodiment" means "at least one additional embodiment," and the term "some embodiments" means "at least some embodiments." Other terms are defined in the following description.

[0059] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0060] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".

[0061] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0062] Figure 2 Schematic diagram of a matrix calculation circuit provided in an embodiment of the present disclosure. The matrix calculation circuit (EU) 200 provided in this embodiment includes:

[0063] a first data reading circuit (LD_M1) 201 configured to read and cache first data and position information of the first data in a first matrix, wherein the first matrix is ​​a compressed matrix of a data matrix; and generate a calculation control signal according to the position information of the first data;

[0064] a second data reading circuit (LD_M2) 202, configured to read and cache second data in a second matrix according to position information of the first data;

[0065] The calculation circuit 203 is configured to calculate and obtain third data according to the calculation control signal, the first data, and the second data.

[0066] Exemplarily, the first data reading circuit reads and caches multiple first data in the first matrix according to the read address of the first data, and the read address of the first data is generated according to the storage first address of the first matrix; the second data reading circuit generates the read address of the second data according to the position information of the first data, and reads and caches multiple second data in the second matrix according to the read address of the second data, and the read address of the second data is generated according to the storage first address of the second matrix. The storage first address of the first matrix and the storage first address of the second matrix are obtained through the instruction decoding circuit ID (Instruction Decoder), and the instruction decoding circuit is used to decode the matrix calculation instruction to obtain the storage first address of the first matrix, the storage first address of the second matrix, and the size of the first matrix and the second matrix and other parameters.

[0067] Exemplarily, the matrix calculation instruction includes an instruction type, a storage start address of a first matrix, a storage start address of a second matrix, a size parameter of a data matrix, a size parameter of a first matrix, and a size parameter of a second matrix. In one embodiment, the instruction type is a matrix multiplication instruction, the first matrix is ​​a data matrix in a neural network convolution calculation, and the second matrix is ​​a parameter matrix in a neural network convolution calculation; wherein, the first matrix and / or the second matrix is ​​a sparse matrix, and a large number of elements in the sparse matrix have a value of 0. It can be understood that the storage start address of the matrix and the size parameter of the matrix (such as the number of rows and columns of the matrix) in the matrix calculation instruction can be expressed in the form of a register address, and the instruction decoding circuit obtains the corresponding data from the corresponding register address.

[0068] In an embodiment of the present disclosure, the first data reading circuit 201 receives the first address of the first matrix decoded by the instruction decoding circuit, and generates a read address of the first data based on the first address; and reads out multiple first data in the first matrix at one time based on the read address of the first data. Exemplarily, the maximum number of first data to be read at one time is pre-set to be the first data in the K columns of data corresponding to the data matrix, then the first data reading circuit generates the read address of the first data based on the first address of the first matrix and K, reads out and caches multiple first data corresponding to the K columns of data and the position information of the multiple first data from the first matrix at one time. Wherein, the first data is non-zero data in the data matrix, and the first data read by the first data reading circuit is non-zero data in the K columns of data of the data matrix. The first data reading circuit 201 is also used to generate a calculation control signal based on the position information of the multiple first data, and the calculation control signal is used to control the calculation circuit to execute or not execute the calculation instruction.

[0069] In the disclosed embodiment, the second data reading circuit 202 receives the first address of the second matrix decoded by the instruction decoding circuit, and generates a read address for the second data based on the first address and the position information of the plurality of first data; and reads the plurality of second data in the second matrix at one time based on the read address of the second data. Exemplarily, the position information of the first data is the column information of the first data in the data matrix, and the column information corresponds to the row of the second matrix. The row address of the second data to be read is obtained by using the first address of the second matrix and the column information, thereby enabling one or more rows of second data to be read at one time and cached in the second data reading circuit.

[0070] In an embodiment of the present disclosure, the computing circuit receives multiple first data and a computing control signal transmitted from the first data reading circuit, and multiple second data transmitted from the second data reading circuit, controls the computing process according to the computing control signal, and obtains multiple third data by computing the multiple first data and the multiple second data.

[0071] like Figure 3 As shown, in order to realize the function of the first data reading circuit, optionally, the first data reading circuit further includes:

[0072] A first data buffer circuit 301, a first data sorting circuit 302 and a first control circuit 303;

[0073] The first control circuit 303 is configured to generate a first data reading address according to the first address of the first matrix;

[0074] The first data cache circuit 301 is configured to cache the first data read out according to the first data read address and the location information of the first data;

[0075] The first data sorting circuit 302 is used to reorder the first data position information and the first data in a one-to-one position correspondence according to the first data position information in the first data cache circuit, wherein the reordering result is that the data in the same row in the data matrix remains in the same row, and the data in the same column in the data matrix remains in the same column.

[0076] Optionally, the first control circuit 303 receives the starting address of the first matrix obtained by decoding the instruction decoding circuit, a preset parameter K, and the size parameter of the first matrix, e.g., the first matrix includes data in N columns of the data matrix. Optionally, the first control circuit includes a first read control circuit CL1 and a first address generation circuit AG1. The first read control circuit CL1 receives the starting address of the first matrix obtained by decoding the instruction decoding circuit, the preset parameter K, and the size parameter of the data matrix, and controls AG1 to generate a first data read address Addr1, so that the first data read circuit can read the first data in the first matrix corresponding to the K columns of the data matrix at a time according to Addr1.

[0077] Optionally, the first data cache circuit 301 further includes a first memory or a first storage area DB11 for caching first data, and a second memory or a second storage area DB10 for caching location information of the first data. After reading the first data and the location information of the first data from the first matrix, the first data is cached in DB11 and the location information of the first data is cached in DB10.

[0078] Optionally, the first data sorting circuit 302 further includes a reordering position information buffer circuit I RDB and a reordering first data buffer circuit DRDB, wherein the I RDB is used to buffer the position information of the reordered first data, and the DRDB is used to buffer the reordered first data.

[0079] Optionally, the position information of the first data includes the row coordinates and column coordinates of the first data in the data matrix, with X representing the row coordinates and Y representing the column coordinates. Exemplarily, the reordering is performed in the order of columns first and rows later, that is, firstly in ascending order according to the Y coordinate, and then in descending order according to the X coordinate, to ensure that the first data in the same row in the data matrix are still in the same row, and the first data in different rows are still not in the same row, and also to ensure that the first data in the same column in the data matrix are still in the same column, and the first data in different columns are still not in the same column. Since the first matrix is ​​a compressed matrix of the data matrix, some rows in the data matrix lack the first data of this column, while other rows have the data of this column. Then, when reordering, the data in this row maintains its original value unchanged; and the position information after reordering arranges each coordinate in the corresponding position in the same manner as the first data, and the coordinates of the compressed first data, that is, the coordinates of the first data with a value of 0 in the data matrix, are marked with an unconventional coordinate value F, for example, both the coordinate values ​​X and Y are represented as "F". Optionally, F indicates that the coordinate value is not within the actual coordinate range or the F value represents a preset value. The position information after reordering is cached in the IRDB, and the first data after reordering is cached in the DRDB.

[0080] Figure 4 A schematic diagram of a reordering example is shown in FIG. Figure 4 As shown, the data matrix M1_O is a sparse matrix. The first matrix is ​​the compressed matrix M1 of the data matrix. M1 includes the first data Data in the data matrix and the position information (X, Y) of the first data in the data matrix. The first data reading circuit reads the two columns of data in M1, and the position information is first arranged in the order of Y coordinate from small to large, and then rearranged in the order of X coordinate from small to large. The position information with the same X coordinate is located in the same row, the position information with different X coordinates is located in different rows, the position information with the same Y coordinate is located in the same column, and the position information with different Y coordinates is located in different columns. The position without corresponding data is supplemented with the preset position information (F, F); the first data is stored in the position corresponding to the sorting of the position information, and the position information only saves the Y coordinate and is stored in the order of Y coordinate from small to large. As shown Figure 4As shown in the figure, the first data 1 is located in the first row after reordering, and the first data 2 is located in the second row after reordering. The other positions keep their original values ​​unchanged, which are recorded as E here. Here, E indicates that its value can be any value; and the Y-axis coordinates in the position information are saved in ascending order.

[0081] After reordering, the first data reading circuit outputs the position information DO0 and the first data DO1. DO1 represents part or all of the first data in the first data, and the position information DO0 represents the position information of all first data in the DRDB. The position information is transmitted to the second data reading circuit, causing the second data reading circuit to read one or more second data corresponding to the position information.

[0082] Optionally, the first data sorting circuit is further used to send row information in the position information of the first data to the first control circuit; the first control circuit is further used to generate the calculation control signal according to the row information.

[0083] Specifically, the IRDB transmits the row coordinates in the position information to CL1 in the first control circuit; the CL1 generates different calculation control signals CA according to the values ​​of the row coordinates to control the calculation process of the calculation circuit.

[0084] Optionally, in one embodiment, the computing circuit includes a computing unit array, wherein the computing unit array includes a plurality of computing units, and the computing control signal is used to control a row of computing units in the computing units to perform computing.

[0085] Specifically, the first control circuit is used to determine whether the row information is a first value; if the row information is the first value, a first control signal is generated to control a row of calculation units corresponding to the row information in the calculation circuit not to perform calculations; if the row information is not the first value, a second control signal is generated to control a row of calculation units corresponding to the row information in the calculation circuit to perform calculations. Exemplarily, as described in the above embodiment, CL1 in the first control circuit determines whether the row coordinates in the position information are F. If the row coordinates are F, it indicates that the corresponding first data is 0, which is actually not required to be executed during calculation. At this time, the first control signal CA is generated. i =1, where i represents the first data of the i-th row, indicating that the calculation unit corresponding to the i-th row does not perform calculation; if the row coordinate is not F, the first control signal CA is generated i =0, indicating that the calculation is performed on the calculation unit in the corresponding row i.

[0086] Optional, such as Figure 5The schematic diagram of the structure of the circuit CAL for generating the calculation control signal in CL1 is shown. It includes a memory or register F for storing the value of F, and also includes M and a comparison circuit CMP for comparing whether the row coordinate is the same as the value of F. Figure 5 As shown, the row coordinates X0-X M-1 The F value is input into the corresponding comparison circuit CMP, and the comparison circuit CMP outputs the corresponding calculation circuit control signal CA0-CA M-1 .

[0087] like Figure 6 As shown, in order to realize the function of the second data reading circuit, optionally, the second data reading circuit further includes:

[0088] A second data buffer circuit 601 and a second control circuit 602;

[0089] The second control circuit 602 is configured to generate a second data reading address according to the first address of the second matrix and the position information of the first data;

[0090] The second data cache circuit 601 is configured to cache the second data read out according to the second data read address.

[0091] Optionally, the second control circuit 602 receives the first address of the second matrix obtained by decoding the instruction decoding circuit and the column information in the position information of the first data to generate a second data read address. Optionally, the second control circuit includes a second read control circuit CL2 and a second address generation circuit AG2. The second read control circuit CL2 receives the first address of the second matrix obtained by decoding the instruction decoding circuit and the position information of the first data, and controls AG2 to generate a second data read address Addr2, so that the second data reading circuit can read the second data corresponding to the first data in the second matrix at one time according to Addr2. Exemplarily, the position information of the first data is the column coordinates of the first data. Based on the first address and the column coordinates of the second matrix, the second address generation circuit AG2 uses the first address of the second matrix as a base address and the column coordinates as a row offset value of the second data to obtain the row address of the second data, thereby reading one or more rows of second data corresponding to the first data. Optionally, the first data is k columns of first data corresponding to K columns of data in the data matrix, and the second data is K rows of second data in the second matrix corresponding to the K columns of first data in the matrix calculation.

[0092] Optionally, the second data cache circuit 601 includes a second data memory or a second data storage area, the size of which is the size of K rows of second data, and the read second data is cached in the second data cache circuit row by row according to its position in the second matrix.

[0093] like Figure 2 As shown, the calculation circuit 203 includes:

[0094] Computing unit array PUA, the computing unit array includes multiple computing units PU 1,1 ,PU 1,2 ,……PU M,N ;

[0095] The column computing units in the computing unit array simultaneously receive one of the second data;

[0096] The row computing units in the computing unit array receive one of the first data at the same time.

[0097] Optionally, the calculation circuit 203 receives a column of reordered first data output by the first data sorting circuit; receives a row of second data output by the second data cache circuit; and calculates a plurality of third data based on the column of first data, the row of second data, and the calculation circuit control signal. Specifically, one first data in a column of first data output by the first data sorting circuit is output to a row of calculation units in the calculation circuit. If a column of first data includes two first data, the first data in the 0th row of the column of first data is output to the 0th row of calculation units, and the first data in the 1st row of the column of first data is output to the 1st row of calculation units. The above operation is performed on each row of calculation units in the calculation units participating in the calculation, and the first data is used as the first input data of the row calculation unit; the second data in a row output by the second data cache circuit is output to a row of calculation units in the calculation unit array. Specifically, The second data cache circuit outputs a row of second data corresponding to a column of first data output by the first data sorting circuit. If a column of first data includes two first data, the second data output by the second data cache circuit is a row of second data, and the row of second data includes two second data. The two second data in this row are respectively input into the corresponding row of calculation units, the 0th second data is output to the 0th column calculation unit, and the 1st second data is output to the 1st column calculation unit; thus, the calculation units participating in the calculation will obtain two data inputs, one first data and one second data, and then according to the calculation circuit control signal CA iControls whether the computing unit in the i-th row performs calculations. The computing unit performing the calculations performs calculations on the first and second data using the calculation type specified by the calculation instruction type to obtain third data. Multiple computing units obtain and output multiple third data. The above calculation process is repeated, and each computing unit accumulates its calculation results until all the first and second data are read, resulting in an output matrix. The value of each element in the output matrix is ​​the accumulated result of the computing units involved in the calculation.

[0098] Figures 7a-7e is an example of the calculation process of the matrix calculation circuit in the above embodiment. Figure 7a As shown, it is the matrix multiplication calculation that the matrix calculation circuit needs to perform, M1_O is the data matrix, M1 is the compressed matrix of M1_O, M2 is the second matrix, and M is the third matrix M obtained by multiplying the M1_O and M2 matrices.

[0099] Among them, M1_O is stored in the form of a compressed matrix, such as Figure 7b As shown, M1_0 is compressed to generate the first matrix M1 and saved. Assume K=4, that is, during the calculation process, the first data of the four columns in the data matrix M1_O are read each time. For the example described, all the data in M1 are read and cached at once. Figure 7b As shown, the first data reading circuit of the matrix calculation circuit reads the first data in the entire first matrix M1 into the data cache circuit at one time, and reorders it through the first data sorting circuit to obtain the following: Figure 7b The storage content and order in the IRDB and DRDB shown in .

[0100] like Figure 7c The figure shows an overall schematic diagram of matrix calculation using the matrix calculation circuit. The 4 columns of first data of M1 are read in units of K=4 columns, i.e., the columns with column numbers 0-3 in the data matrix. Since the total number of columns of the data matrix M1_O is 4 in this example, the entire M1 is read at once and cached in the first data reading circuit LD_M1; after reading, the data is reordered, the position information is stored in the IRDB of LD_M1, and the first data is stored in the DRDB of LD_M1. IRDB transmits column coordinates 0 and 3 to LD_M2, and LD_M2 reads the second data of row 0 and row 3 from M2 according to the column coordinates 0 and 3 and caches them, as shown in FIG. Figure 7c As shown, the second data in row 0 includes 1 and 2, and the second data in row 3 includes 7 and 8. These two rows of second data are cached in DB2 of LD_M2. The calculation result of the first data and the second data is the output matrix M.

[0101] like Figure 7dThe diagram shows the first calculation. The calculation circuit obtains the first column of first data from the DRDB of LD_M1, wherein the first column of first data includes 1 in row 0 and E in row 1, wherein 1 in row 0 is input to the calculation unit PU in row 0 in the calculation circuit. 0,0 and PU 0,1 The first row of E is input to the first row of computing unit PU in the computing circuit 1,0 and PU 1,1 The second data cache circuit of LD_M2 outputs the second data of row 0 cached in LD_M2, and the second data of row 0 is input to the calculation unit PU of row 0 0,0 and PU 0,1 Neutralize 1 row of computing units PU 1,0 and PU 1,1 In the example, the second data of row 0 includes 1 and 2, wherein the second data 1 is input to the calculation unit PU of column 0. 0,0 and computing unit PU 1,0 The second data 2 is input to the first column computing unit PU 0,1 and PU 1,1 In the first column of the first data, the 0th row is not F, and the row coordinate of the 1st row is F, then the first data reading circuit generates CA0=0, CA1=1, so that the 0th row calculation unit PU 0,0 and PU 0,1 Calculate so that the first row of calculation unit PU 1,0 and PU 1,1 No calculation is performed. After that, the calculation unit in row 0 performs multiplication and accumulation calculations independently, and obtains PU 0,0 The calculation result 1, PU 0,1 The calculation result of the calculation unit in the first row is 2, and the calculation result of the calculation unit in the first row defaults to 0. Since the first data and the second data have not been calculated, the third data obtained is the intermediate data M_temp.

[0102] like Figure 7e The diagram shows the second calculation. The calculation circuit obtains the second column of first data from DRDB of LD_M1, where the second column of first data includes E in row 0 and 2 in row 1, where E in row 0 is input to the calculation unit PU in row 0 in the calculation circuit. 0,0 and PU 0,1 2 in row 1 is input to the first row calculation unit PU in the calculation circuit 1,0 and PU 1,1 LD_M2 second data cache circuit output LD_M2 cached in the first row of the second data, wherein the first row of the second data includes 7 and 8, wherein the second data 7 is input to the computing unit PU 0,0 and PU 1,0 The second data 8 is input to the calculation unit PU0,1 and PU 1,1 wherein the row coordinate of the 0th row in the second column of the first data is F, and the 1st row is not F, then the first data reading circuit generates CA0=1, CA1=0, so that the 0th row calculation unit PU 0,0 and PU 0,1 No calculation is performed, so that the first row of calculation units PU 1,0 and PU 1,1 Then the calculation units in row 1 perform multiplication and accumulation calculations independently to obtain PU 0,0 The calculation result 1, PU 0,1 The calculation result 2, PU 1,0 The calculation results of 14 and PU 1,1 The calculation result is 16; since the first data and the second data are calculated, the third data obtained is the value of the element in the output matrix M.

[0103] It can be seen from the calculation process of the above example that using the matrix calculation circuit in the present disclosure to perform matrix multiplication operations only requires two calculations to complete the multiplication of a 2*4 matrix and a 4*2 matrix, which greatly improves the calculation speed and saves calculation time.

[0104] Through the above-mentioned technical solution disclosed in the present invention, the compressed sparse matrix is ​​directly calculated, which effectively saves storage space and data bandwidth; using the computing unit array, all computing units perform data processing synchronously, which greatly improves data utilization, and multiple computing units can share the same data; directly calculating the compressed sparse matrix, skipping the calculation of some 0 elements, thereby improving the calculation speed and improving the effective computing power of the chip; when calculating non-all-0 columns, the 0 elements in the column can be skipped and the corresponding row computing units can be turned off, saving power consumption; the circuit structure is simple and can effectively reduce circuit costs.

[0105] Figure 8 Flowchart of the matrix calculation method provided by the embodiment of the present disclosure. Figure 8 As shown, the method includes the following steps:

[0106] Step S801: Read and cache first data and location information of the first data in a first matrix, wherein the first matrix is ​​a compressed matrix of a data matrix;

[0107] Step S802: generating a calculation control signal according to the position information of the first data;

[0108] Step S803, reading and caching second data in the second matrix according to the position information of the first data;

[0109] Step S804: Calculate and obtain third data according to the calculation control signal, the first data, and the second data.

[0110] Furthermore, the reading and caching the first data and the position information of the first data in the first matrix includes:

[0111] generating a first data reading address according to the first address of the first matrix;

[0112] caching first data read out according to the first data read address and location information of the first data;

[0113] The first data position information and the first data are reordered in a one-to-one position correspondence according to the first data position information, wherein the reordering result is that the data in the same row in the data matrix remains in the same row, and the data in the same column in the data matrix remains in the same column.

[0114] Furthermore, generating a calculation control signal according to the position information of the first data includes:

[0115] A calculation control signal is generated according to row information in the position information of the first data.

[0116] Furthermore, generating a calculation control signal according to row information in the position information of the first data includes:

[0117] Determining whether the row information is a first value;

[0118] If the row information is a first value, generating a first control signal to control a row of computing units corresponding to the row information in the computing circuit not to perform computing;

[0119] If the row information is not the first value, a second control signal is generated to control a row of computing units corresponding to the row information in the computing circuit to perform calculations.

[0120] Furthermore, the reading and caching the second data in the second matrix according to the position information of the first data includes:

[0121] generating a second data reading address according to the first address of the second matrix and the position information of the first data;

[0122] The second data read out according to the second data read address is cached.

[0123] Furthermore, generating a second data reading address according to the first address of the second matrix and the position information of the first data includes:

[0124] The second data reading address is generated according to the first address of the second matrix and the column information in the position information of the first data.

[0125] First data Second data Further, the calculating of third data according to the calculation control signal, the first data and the second data includes:

[0126] receiving a row of second data in the second data;

[0127] receiving a column of first data in the first data;

[0128] The calculation control signal controls the row of second data and the column of first data to perform calculation to obtain third data.

[0129] In the above, although the various steps in the above method embodiment are described in the above order, those skilled in the art should be aware that the steps in the embodiments of the present disclosure are not necessarily executed in the above order, and they can also be executed in other orders such as reverse order, parallel order, and cross order. Moreover, based on the above steps, those skilled in the art can also add other steps. These obvious variations or equivalent replacement methods should also be included in the scope of protection of the present disclosure and will not be repeated here.

[0130] An embodiment of the present disclosure further provides a processing core, which includes at least one matrix calculation circuit, a decoding unit, and a storage device in any of the above embodiments.

[0131] An embodiment of the present disclosure further provides a chip, which includes at least one processing core of any one of the above embodiments.

[0132] An embodiment of the present disclosure provides an electronic device, comprising: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, so that the processors implement any matrix calculation method described in the embodiments when executing.

[0133] An embodiment of the present disclosure further provides a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions, which are used to enable a computer to execute any matrix calculation method described in the aforementioned embodiments.

[0134] An embodiment of the present disclosure further provides a computer program product, which is characterized in that it includes computer instructions. When the computer instructions are executed by a computing device, the computing device can execute any matrix calculation method described in the aforementioned embodiments.

[0135] An embodiment of the present disclosure further provides a computing device, characterized in that it includes any chip described in the embodiments.

[0136] The flowcharts and block diagrams in the accompanying drawings of the present disclosure illustrate the possible architectures, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, task segment, or part of the code, which contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, as well as the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified functions or operations, or can be implemented using a combination of dedicated hardware and computer instructions.

[0137] The units involved in the embodiments described in this disclosure may be implemented in software or hardware, wherein the name of a unit does not necessarily limit the unit itself.

[0138] The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, and without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chip (SOCs), complex programmable logic devices (CPLDs), and the like.

[0139] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Claims

1. A matrix calculation circuit, characterized in that: include: a first data reading circuit, configured to read and cache first data and position information of the first data in a first matrix, wherein the first matrix is ​​a compressed matrix of a data matrix; generating a calculation control signal according to the position information of the first data; a second data reading circuit, configured to read and cache second data in a second matrix according to position information of the first data; a calculation circuit, configured to calculate and obtain third data according to the calculation control signal, the first data, and the second data; Wherein, the first data reading circuit further includes: a first data cache circuit, a first data sorting circuit, and a first control circuit; Wherein, the first control circuit is used to generate a first data reading address according to the first address of the first matrix; The first data cache circuit is used to cache the first data read according to the first data read address and the position information of the first data; The first data sorting circuit is used to reorder the first data position information and the first data in a one-to-one position correspondence according to the first data position information in the first data cache circuit, wherein the reordering result is that the data in the same row in the data matrix remains in the same row, and the data in the same column in the data matrix remains in the same column.

2. The matrix calculation circuit according to claim 1, wherein: The first data sorting circuit is further configured to send row information in the position information of the first data to the first control circuit; The first control circuit is further configured to generate the calculation control signal according to the row information.

3. The matrix calculation circuit according to claim 2, wherein: The first control circuit is further configured to generate the calculation control signal according to the row information, including: The first control circuit is configured to determine whether the row information is a first value; If the row information is a first value, generating a first control signal to control a row of computing units corresponding to the row information in the computing circuit not to perform computing; If the row information is not the first value, a second control signal is generated to control a row of computing units corresponding to the row information in the computing circuit to perform calculations.

4. The matrix calculation circuit according to any one of claims 1 to 3, wherein: The second data reading circuit further includes: a second data cache circuit and a second control circuit; The second control circuit is configured to generate a second data reading address according to the first address of the second matrix and the position information of the first data; The second data cache circuit is used to cache the second data read out according to the second data read address.

5. The matrix calculation circuit according to claim 4 , wherein the second control circuit is configured to generate a second data reading address according to the first address of the second matrix and the position information of the first data, comprising: The second control circuit is configured to generate the second data reading address according to the first address of the second matrix and the column information in the position information of the first data.

6. The matrix calculation circuit according to any one of claims 1 to 3 and 5, characterized in that: The calculation circuit comprises: A computing unit array, wherein the computing unit array includes a plurality of computing units; a column computing unit in the computing unit array receives one second data in the second data; and a row computing unit in the computing unit array receives one first data in the first data.

7. A matrix calculation method, characterized in that: include: Reading and buffering first data and position information of the first data in a first matrix, wherein the first matrix is ​​a compressed matrix of the data matrix; generating a calculation control signal according to the position information of the first data; Reading and caching second data in a second matrix according to the position information of the first data; Obtain third data by calculation according to the calculation control signal, the first data, and the second data; The reading and caching the first data and the position information of the first data in the first matrix includes: generating a first data reading address according to the first address of the first matrix; caching first data read out according to the first data read address and location information of the first data; The first data position information and the first data are reordered in a one-to-one position correspondence according to the first data position information, wherein the reordering result is that the data in the same row in the data matrix remains in the same row, and the data in the same column in the data matrix remains in the same column.

8. A processing core comprising a decoding unit, a storage device, and at least one matrix calculation circuit according to any one of claims 1 to 6.

9. A chip comprising at least one processing core according to claim 8.

Images