Scan driver and organic light emitting display device including the same

Abstract

A scan driver and an organic light emitting display device including the scan driver are provided for realizing a narrow frame. The scan driver includes a plurality of stages, wherein each of the plurality of stages includes: a Q1 node controller, which controls the voltage of the Q1 node by using a first clock signal and a second clock signal having opposite phases to each other; a QB node controller, which controls the voltage of the QB node by using a first clock signal, a second clock signal, an output clock signal, and a start signal; a first transistor, which outputs a gate low voltage as a scan signal while the QB node is activated; and a second transistor, which outputs a gate high voltage as a scan signal while the Q2 node is activated, and outputs a gate low voltage as a scan signal when the Q2 node is bootstrapped to a voltage lower than the gate low voltage.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2020-0116874, filed on September 11, 2020, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0002] The present invention relates to a scan driver and an organic light emitting display device including the scan driver, and in particular, to a scan driver for realizing a narrow frame and an organic light emitting display device including the scan driver. Background Art

[0003] Representative examples of flat panel display devices that have recently attracted much attention include liquid crystal display (LCD) devices using liquid crystals, organic light emitting diode (OLED) display devices using OLEDs, and electrophoretic display (EPD) devices using electronic inks.

[0004] A flat panel display device includes: a display panel that includes a pixel array and displays an image by using the pixel array, the pixel array including a plurality of pixels independently driven by its thin film transistor (TFT); a scan driver that drives a plurality of scan lines of the display panel; a data driver that drives a plurality of data lines of the display panel; and a timing controller that controls the scan driver and the data driver.

[0005] The scan driver includes a plurality of stages that individually drive scan lines of the display panel, each of which is configured with a plurality of TFTs. Recently, the scan driver mainly uses a gate-in panel (GIP) type, in which the TFT array of the pixel array is implemented and built into the display panel.

[0006] In this case, it is difficult to realize a narrow-frame display device due to the area occupied by the scan driver in the display panel. Summary of the invention

[0007] In order to overcome the aforementioned problems of the related art, the present invention may provide a scan driver for realizing a narrow frame and an organic light emitting display device including the scan driver.

[0008] To achieve these objects and other advantages and in accordance with the intent of the present invention, as embodied and generally described herein, a scan driver includes a plurality of stages, wherein each of the plurality of stages includes: a Q1 node controller, the Q1 node controller controlling the voltage of the Q1 node by using a first clock signal and a second clock signal having opposite phases to each other; a QB node controller, the QB node controller controlling the voltage of the QB node by using the first clock signal, the second clock signal, an output clock signal and a start signal; a first transistor, the first transistor outputting a gate low voltage as a scan signal while the QB node is activated; and a second transistor, the second transistor outputting a gate high voltage as the scan signal while the Q2 node is activated, and the second transistor outputting the gate low voltage as the scan signal when the Q2 node is bootstrapped to a voltage lower than the gate low voltage.

[0009] In addition, each of the multiple stages may further include a first capacitor connected between its clock output terminal and the second transistor, and when the scan signal changes from the gate high voltage to the gate low voltage, the first capacitor can bootstrap the Q2 node by reflecting the voltage change of the output clock terminal to the Q2 node.

[0010] In addition, the QB node controller may include: a third transistor and a fourth transistor, the third transistor and the fourth transistor are connected in series between the QB node and the input terminal corresponding to the start signal; a fifth transistor, the fifth transistor provides the gate high voltage to the second capacitor according to the voltage of the Q1 node; and a sixth transistor, the sixth transistor provides the first clock signal to the second capacitor according to the voltage of the Q1 node, wherein the third transistor can provide the start signal to the fourth transistor in response to the output clock signal, and the fourth transistor can provide the start signal to the QB node in response to the second clock signal.

[0011] In addition, the Q1 node controller may include: a seventh transistor, which provides the second clock signal to the Q1 node according to the voltage of the QB node; an eighth transistor, which provides the gate low voltage to the Q1 node according to the second clock signal; and a ninth transistor, which provides the gate low voltage to the Q1 node according to the first clock signal.

[0012] In addition, each of the multiple stages may further include: a tenth transistor arranged between the Q1 node and the Q2 node; and an eleventh transistor arranged between the Q2 node and the third transistor, wherein when the Q2 node is bootstrapped to a voltage lower than the gate low voltage, the tenth transistor and the eleventh transistor may be turned off.

[0013] In this case, the second capacitor is connected between the QB node and the sixth transistor, and when the scan signal maintains the gate low voltage, the second capacitor can bootstrap the QB node by reflecting the voltage change of the drain of the sixth transistor to the QB node.

[0014] In another aspect of the present invention, an organic light-emitting display device includes: a display panel, the display panel including a display area having a pixel array and a non-display area arranged on at least one side of the display area; and the above-mentioned scan driver, the scan driver provides a scan signal generated by each of the multiple stages to multiple scan lines of the pixel array.

[0015] In this case, the plurality of transistors included in the scan driver may include polysilicon transistors, and the plurality of transistors included in the pixel array may include oxide semiconductor transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention.

[0017] In the attached picture:

[0018] Figure 1 is a block diagram illustrating a display device according to the present invention;

[0019] Figure 2 It is a graphic Figure 1 A circuit diagram of sub-pixels arranged in a pixel array as shown in ;

[0020] Figure 3 It is a graphic Figure 1 A diagram of a configuration of a stage included in a scan driver shown in FIG.

[0021] Figure 4 It is a graphic Figure 3 The circuit diagram of the uppermost stage shown in ;

[0022] FIG. 5A to FIG. 5F is a diagram describing operations performed during first to sixth periods of a first stage as an uppermost stage according to the present invention;

[0023] Figure 6 is a graph showing a voltage applied to a node Q of a first stage which is an uppermost stage according to the present invention. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 is a block diagram illustrating a display device according to the present invention.

[0026] Reference Figure 1 , a display device according to the present invention may include: a display panel 300 including a pixel array 100 and a scan driver 200 , a data driver 400 , and a timing controller 500 .

[0027] The timing controller 500 may receive basic timing control signals and video data provided from a host system, modulate video data by using various data processing methods for compensating image quality or reducing power consumption, and may output the modulated video data to the data driver 400.

[0028] The timing controller 500 may generate a data control signal for controlling the operation timing of the data driver 400 by using the basic timing control signal to provide the data control signal to the data driver 400, and the timing controller 500 may generate a gate control signal for controlling the operation timing of the scan driver 200 by using the basic timing control signal to provide the gate control signal to the scan driver 200. The basic timing control signal may include a dot clock and a data enable signal and may further include a horizontal synchronization signal and a vertical synchronization signal. The data control signal may include a source start pulse and a source shift clock for controlling the latch timing of the image data in the data driver 400, and a source output enable signal for controlling the output period of the image data signal. The gate control signal may include a gate start pulse for controlling the operation time of the scan driver 200, and a gate clock used as an output signal or a shift control signal.

[0029] A level shifter may be additionally provided between the timing controller 500 and the scan driver 200. The level shifter may be built into a power supply unit (not shown). The level shifter may level-shift a gate control signal (i.e., a gate start pulse and a transistor-transistor logic (TTL) of each clock) to make it a gate high voltage (gate-on voltage) and a gate low voltage (low-level voltage or gate-off voltage) of a transistor for driving the pixel array 100 and may provide the gate high voltage and the gate low voltage to the scan driver 200.

[0030] The data driver 400 may be provided with a data control signal and image data from the timing controller 500. The data driver 400 may be driven based on the data control signal and may subdivide a reference gamma voltage set provided from a gamma voltage generator into grayscale voltages respectively corresponding to grayscale values ​​of data, convert digital image data into analog image data signals by using the grayscale voltages, and provide the analog image data signals to the data lines of the display panel 300.

[0031] The data driver 400 may be configured with a plurality of data driver integrated circuits (ICs) for separately driving the data lines of the display panel 300, and each data driver IC may be mounted on a circuit film such as a tape carrier package (TCP), a chip on film (COF), or a flexible printed circuit (FPC), and may be attached to the display panel 300 based on a tape automated bonding (TAB) type, or may be mounted on the display panel 300 by using a chip on glass (COG) type.

[0032] The display panel 300 may display an image by using a pixel array 100 in which a plurality of pixels are arranged in a matrix. Each of the plurality of pixels of the pixel array 100 may realize a desired color based on a combination of a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, and may further include a white sub-pixel for improving brightness.

[0033] like Figure 2 As shown in , each sub-pixel may include a light emitting device OLED, a driving transistor TD, a switching transistor TS, and a storage capacitor Cst.

[0034] The light emitting device OLED may include an anode electrode connected to a driving transistor TD, a cathode electrode connected to an input terminal of a low-level power VSS, and an organic compound layer disposed between the anode electrode and the cathode electrode. The driving transistor TD may control a driving current flowing into the light emitting device OLED based on a voltage difference between its gate and source electrode so that the light emitting device OLED emits light. The switching transistor TS may be turned on based on a scanning signal provided through the scanning line SL and may apply a data voltage charged in the data line DL to a node N. The storage capacitor Cst may include a side electrode connected to the gate of the driving transistor TD through the node N and another side electrode connected to the source of the driving transistor TD. The storage capacitor Cst may maintain the gate-source voltage of the driving transistor TD when the light emitting device OLED emits light.

[0035] The scan driver 200 may be configured as a gate-in-panel (GIP) type (where the scan driver 200 is built into a non-display area of ​​the display panel 300 (i.e., a non-display area adjacent to one side or both sides of the pixel array 100)) and may be referred to as a GIP circuit. The scan driver 200 may include a plurality of stages ST1 to STn-1, STn (n is an integer greater than 1), for example, a plurality of stages ST1 to ST4, ..., wherein the plurality of stages ST1 to ST4, ... respectively drive a plurality of scan lines SL1 to SL4, ... of the pixel array 100 and are connected to each other in a subordinate manner, and each stage ST may include a plurality of transistors formed on a substrate together with transistors of the pixel array 100. The transistors included in the pixel array and each stage may be implemented by at least one of an oxide semiconductor transistor, a polysilicon transistor, and an amorphous silicon transistor. For example, the transistor of each sub-pixel may be implemented by an oxide semiconductor transistor having excellent off current characteristics, and the transistor included in the scan driver 200 may be implemented by a polysilicon transistor having excellent on current characteristics and reliability characteristics. However, this is merely an example, and the structure of the transistor is not limited thereto.

[0036] like Figure 3 As shown in , the operation of the stages ST1 to ST4, ... can be sequentially activated based on the start signal and a scan signal can be output to each of the scan lines SL1 to SL4, ... The operation of the uppermost stage ST1 can be activated based on the external start signal Vst, and the operation of the second stage ST2 to the lowermost stage can be activated based on the scan signal of the preceding stage. The scan signal of the preceding stage can be an internal start signal and can be a carry signal CRY. Here, the preceding stage can refer to a stage that is arranged above the reference stage and generates a scan signal having a leading phase compared to the scan signal output from the reference stage.

[0037] Stages ST1 to ST4, ... can receive a start signal Vst, a first clock signal CLK1, a second clock signal CLK2, a first output clock signal OCLK1, and a second output clock signal OCLK2 from a level shifter, thereby outputting a scan signal SCAN. The start signal Vst, the first clock signal CLK1, the second clock signal CLK2, the first output clock signal OCLK1, and the second output clock signal OCLK2 can all swing between a gate-off voltage and a gate-on voltage.

[0038] The external start signal Vst can be input to the topmost stage ST1, the first clock signal CLK1 and the second clock signal CLK2 can be input to all stages ST1 to ST4, ..., the first output clock signal OCLK1 can be input to the odd stages ST1, ST3, ..., and the second output clock signal OCLK2 can be input to the even stages ST2, ST4, ...

[0039] The first output clock signal OCLK1 and the second output clock signal OCLK2 may have opposite phases and may have a period corresponding to two horizontal periods 2H.

[0040] The first clock signal CLK1 and the second clock signal CLK2 may have opposite phases and may have a period corresponding to two horizontal periods 2H. A pulse width of a high level period of each of the first clock signal CLK1 and the second clock signal CLK2 may be greater than a pulse width of a low level period.

[0041] Each of the stages ST1 to ST4, ... may activate the operation of the node Q based on the start signal Vst applied to the start terminal in each frame. Here, the activation of the node may refer to the gate-on voltage VEL or a voltage lower than the gate-on voltage VEL being applied to the corresponding node. In addition, the deactivation of the node may refer to the gate-off voltage VEH or a voltage higher than the gate-off voltage VEH being applied to the corresponding node.

[0042] Figure 4 It is a graphic Figure 3 1 is a circuit diagram of a first stage as an uppermost stage ST1 included in a gate shift register.

[0043] The other odd-numbered stages ST3, ST5, ... other than the topmost stage ST1 are provided with an internal start signal CRY instead of the start signal Vst and output scan signals with different phases, and other elements may be the same. In addition, the even-numbered stages ST2, ST4, ... are provided with an internal start signal CRY instead of the start signal Vst, are provided with a second output clock signal OCLK2 instead of the first output clock signal OCLK1 and output scan signals with different phases, and other elements may be the same.

[0044] Figure 4 The stage shown in FIG. 1 may include an output buffer unit, a stabilization unit, a QB node controller, a Q1 node controller, a first capacitor CQ, and a second capacitor CQB.

[0045] The output buffer unit may include a sixth transistor T6, a seventh transistor T7 and a first capacitor CQ. The sixth transistor T6 may be controlled by a node Q2 and may provide a current path between an output clock signal terminal OCLK1 and an output terminal OUT. When the voltage of the node Q2 is a gate low voltage VGL, the sixth transistor T6 may be turned on and may provide an output clock signal OCLK1 as a scan signal to the output terminal OUT. The seventh transistor T7 may be controlled by a node QB and may provide a current path between an input terminal corresponding to the gate low voltage VGL and the output terminal OUT. When the voltage of the node QB is a gate low voltage VGL, the seventh transistor T7 may be turned on and may provide a gate low voltage VGL as a scan signal to the output terminal OUT.

[0046] The first capacitor CQ can reflect the voltage change of the output clock signal OCLK1 to the voltage of the node Q2, and can bootstrap the node Q2. When the node Q1 floats due to the cut-off of the tenth transistor T10, the output clock signal OCLK1 corresponding to the gate low voltage VGL can be input, and thus, due to the coupling effect of the first capacitor CQ, the voltage of the node Q2 can be bootstrapped to a first bootstrap voltage Vb1 lower than the gate low voltage VGL. As described above, when the first capacitor CQ bootstraps the voltage of the node Q2, the gate low voltage can be applied to the node Q2, and thus the output delay of the scan signal (which is the gate low voltage of the first output clock signal) can be minimized.

[0047] The stabilization unit may include a tenth transistor T10 and an eleventh transistor T11 connected to the node Q2 .

[0048] While the voltage of the node Q2 is bootstrapped, the tenth transistor T10 may be turned off and the current between the node Q1 and the node Q2 may be cut off. Although the voltage of the node Q2 is bootstrapped, its influence is not applied to the third transistor T3, the fourth transistor T4, and the fifth transistor T5 connected to the node Q1. Therefore, the drain-source voltage of each of the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be prevented from increasing based on the bootstrapped voltage of the node Q2. That is, when the node Q2 is bootstrapped, the drain-source voltage of each of the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be prevented from increasing to the threshold voltage or a higher voltage, thereby preventing the occurrence of a component breakdown phenomenon caused by overload.

[0049] While the voltage of the node Q2 is bootstrapped, the eleventh transistor T11 may be turned off and may cut off the current between the node Q2 and the first transistor T1. Although the voltage of the node Q2 is bootstrapped, its influence is not applied to the first transistor T1.

[0050] The QB node controller may include a first transistor T1 , a second transistor T2 , a fifth transistor T5 , an eighth transistor T8 , and a capacitor CQB for controlling a voltage of a node QB of the output buffer unit.

[0051] The first transistor T1 may be controlled by the first output clock signal OCLK1 and may provide a current path between the start signal terminal and the second transistor T2. In response to the gate low voltage of the first output clock signal OCLK1, the first transistor T1 may transmit the start signal Vst to the second transistor T2. The second transistor T2 may be controlled by the second clock signal CLK2 and may provide a current path between the node QB and the first transistor T1. In response to the gate low voltage of the second clock signal CLK2, the second transistor T2 may transmit the gate low voltage of the start signal Vst transmitted from the first transistor T1 to the node QB. The fifth transistor T5 may be controlled by the voltage of the node Q1 and may provide a current path between the input terminal corresponding to the gate high voltage VGH and the second capacitor CQB. The eighth transistor T8 may be controlled by the voltage of the node QB and may provide a current path between the input terminal corresponding to the first clock signal CLK1 and the second capacitor CQB.

[0052] The second capacitor CQB can reflect the voltage change of the first clock signal CLK1 (or the drain of the eighth transistor T8) to the voltage of the node QB to bootstrap the node QB. When the node QB floats due to the cut-off of the second transistor T2 and the first clock signal CLK1 with the gate low voltage is input, the voltage of the node QB can be bootstrapped to a second bootstrap voltage Vb2 lower than the gate low voltage VGL due to the coupling effect of the second capacitor CQB.

[0053] The Q1 node controller may include a third transistor T3 , a fourth transistor T4 , and a ninth transistor T9 for controlling a voltage of the node Q1 .

[0054] The third transistor T3 may be controlled by the node QB and may provide a current path between an input terminal corresponding to the second clock signal CLK2 and the node Q1. In response to the gate low voltage of the node QB, the third transistor T3 may transmit the gate low voltage or gate high voltage of the second clock signal CLK2 to the node Q1.

[0055] The fourth transistor T4 may be controlled by the second clock signal CLK2 and may provide a current path between an input terminal corresponding to the gate low voltage VGL and the node Q1. In response to the second clock signal CLK2 having the gate low voltage, the fourth transistor T4 may transmit the gate low voltage VGL to the node Q1.

[0056] The ninth transistor T9 may be controlled by the first clock signal CLK1 and may provide a current path between an input terminal corresponding to the gate low voltage VGL and the node Q1. In response to the first clock signal CLK1 having the gate low voltage, the ninth transistor T9 may transmit the gate low voltage VGL to the node Q1.

[0057] FIG. 5A to FIG. 5F is a diagram describing operations performed during first to sixth periods of the first stage as the uppermost stage according to the present invention.

[0058] exist Figure 5A During the first period t1 shown in , the start signal Vst having a gate low voltage, the first clock signal CLK1 having a gate low voltage, the second clock signal CLK2 having a gate high voltage, and the first output clock signal OCLK1 having a gate high voltage may be applied to the first stage ST1. At this time, the first output clock signal OCLK1 having a gate high voltage may also be applied to the output clock terminal of each of the odd-numbered stages ST3, ST5, ... except the first stage ST1, and the second output clock signal OCLK2 having a gate low voltage may be applied to the output clock terminal of each of the even-numbered stages ST2, ST4, ...

[0059] The first transistor T1 may be turned off in response to the first output clock signal OCLK1 having a gate high voltage, the second transistor T2 and the fourth transistor T4 may be turned off in response to the second clock signal CLK2 having a gate high voltage, and the ninth transistor T9 and the tenth transistor T10 may be turned on in response to the first clock signal CLK1 having a gate low voltage.

[0060] The node QB may float based on the cut-off of the first transistor T1 and the second transistor T2. At this time, the voltage of the node QB may be stabilized by the second capacitor CQB coupled to the eighth transistor T8, and thus the voltage of the node QB may be activated to the gate low voltage VGL. In response to the voltage of the node QB, the third transistor T3, the seventh transistor T7, the eighth transistor T8, and the eleventh transistor T11 may be turned on.

[0061] The node Q1 may be provided with the second clock signal CLK2 having a gate high voltage through the turned-on third transistor T3 and may be provided with the gate low voltage VGL through the turned-on ninth transistor T9. At this time, the second clock signal CLK2 having a gate high voltage may have a value much greater than the gate low voltage VGL, and thus the node Q1 may be provided with the second clock signal CLK2 having a gate high voltage and may thus be deactivated to the gate high voltage.

[0062] The node Q2 may be deactivated to a gate high voltage based on the second clock signal CLK2 applied through the tenth transistor T10. In response to the voltage of the node Q2, the sixth transistor T6 may be turned off.

[0063] Therefore, in the first period t1 , the scan signal having the gate low voltage VGL may be output to the output terminal OUT through the turned-on seventh transistor T7 .

[0064] exist Figure 5B During the second period t2 shown in , the start signal Vst having a gate high voltage, the first clock signal CLK1 having a gate high voltage, the second clock signal CLK2 having a gate low voltage, and the first output clock signal OCLK1 having a gate low voltage may be applied to the first stage ST1. At this time, the first output clock signal OCLK1 having a gate low voltage may also be applied to the output clock terminal of each of the odd-numbered stages ST3, ST5, ... except the first stage ST1, and the second output clock signal OCLK2 having a gate high voltage may be applied to the output clock terminal of each of the even-numbered stages ST2, ST4, ...

[0065] The first transistor T1 may be turned on in response to the first output clock signal OCLK1 having a gate low voltage, the second transistor T2 and the fourth transistor T4 may be turned on in response to the second clock signal CLK2 having a gate low voltage, and the ninth transistor T9 and the tenth transistor T10 may be turned off in response to the first clock signal CLK1 having a gate high voltage.

[0066] The node QB may be deactivated to the start signal Vst having a gate high voltage by turning on the first and second transistors T1 and T2. The third transistor T3, the seventh transistor T7, the eighth transistor T8, and the eleventh transistor T11 may be turned off based on the start signal Vst having a gate high voltage applied to the node QB.

[0067] The node Q1 may be activated based on the gate low voltage VGL applied through the turned-on fourth transistor T4 .

[0068] The node Q2 may float due to the turned-off tenth transistor T10. At this time, the node Q2 may be activated to the output clock signal OCLK1 having a gate low voltage by using the first capacitor CQ, and thus the sixth transistor T6 may be turned on.

[0069] Therefore, in the second period t2 , the gate low voltage VGL may be output as a scan signal to the output terminal OUT through the turned-on sixth transistor T6 .

[0070] exist Figure 5CDuring the third period t3 shown in , the start signal Vst having a gate low voltage, the first clock signal CLK1 having a gate low voltage, the second clock signal CLK2 having a gate high voltage, and the first output clock signal OCLK1 having a gate high voltage may be applied to the first stage ST1. At this time, the first output clock signal OCLK1 having a gate high voltage may also be applied to the output clock terminal of each of the odd-numbered stages ST3, ST5, ... except the first stage ST1, and the second output clock signal OCLK2 having a gate low voltage may be applied to the output clock terminal of each of the even-numbered stages ST2, ST4, ...

[0071] The first transistor T1 may be turned off in response to the first output clock signal OCLK1 having a gate high voltage, the second transistor T2 and the fourth transistor T4 may be turned off in response to the second clock signal CLK2 having a gate high voltage, and the ninth transistor T9 and the tenth transistor T10 may be turned on in response to the first clock signal CLK1 having a gate low voltage.

[0072] The node QB may float due to the turned-off second transistor T2 and may maintain the gate high voltage VGH of the second period t2 as the previous period, and thus may be deactivated to the gate high voltage. In response to the gate high voltage VGH of the node QB, the third transistor T3, the seventh transistor T7, the eighth transistor T8, and the eleventh transistor T11 may be turned off.

[0073] The node Q1 may float due to the turned-off third and fourth transistors T3 and T4 and may maintain the gate low voltage VGL of the second period t2 which is the previous period, and thus may be activated to the gate low voltage.

[0074] The node Q2 may be connected to the node Q1 through the tenth transistor T10 and thus may be activated to the gate low voltage VGL. The sixth transistor T6 may be turned on by the gate low voltage VGL of the node Q2.

[0075] Therefore, in the third period t3 , the gate high voltage VGH may be output as a scan signal to the output terminal OUT through the turned-on sixth transistor T6 .

[0076] exist Figure 5DDuring the fourth period t4 shown in , the start signal Vst having a gate low voltage, the first clock signal CLK1 having a gate high voltage, the second clock signal CLK2 having a gate low voltage, and the first output clock signal OCLK1 having a gate low voltage may be applied to the first stage ST1. At this time, the first output clock signal OCLK1 having a gate low voltage may also be applied to the output clock terminal of each of the odd-numbered stages ST3, ST5, ... except the first stage ST1, and the second output clock signal OCLK2 having a gate high voltage may be applied to the output clock terminal of each of the even-numbered stages ST2, ST4, ...

[0077] The first transistor T1 may be turned on in response to the first output clock signal OCLK1 having a gate low voltage, the second transistor T2 and the fourth transistor T4 may be turned on in response to the second clock signal CLK2 having a gate low voltage, and the ninth transistor T9 and the tenth transistor T10 may be turned off in response to the first clock signal CLK1 having a gate high voltage.

[0078] The node QB can be activated to the start signal Vst with a gate low voltage by turning on the first transistor T1 and the second transistor T2. The eighth transistor T8 can be turned on by the start signal Vst with a gate low voltage applied to the node QB. At this time, because the second clock signal CLK2 with a gate high voltage is applied to the source of the third transistor T3 during the previous third period t3, when the second clock signal CLK2 with a gate low voltage is applied in the fourth period t4, the third transistor T3 can maintain a turned-on state until the gate-source voltage Vgs of the third transistor T3 becomes 0V, and when the gate-source voltage Vgs of the third transistor T3 is 0V, the third transistor T3 can be in a turned-off state. Because the first output clock signal OCLK1 having a gate high voltage is applied to the source of the eleventh transistor T11 during the previous third period t3, when the first clock signal CLK1 having a gate high voltage is applied in the fourth period t4, the eleventh transistor T11 may maintain a turned-on state until the gate-source voltage Vgs of the eleventh transistor T11 becomes 0 V, and the eleventh transistor T11 may be in a turned-off state when the gate-source voltage Vgs of the eleventh transistor T11 is 0 V. Because the gate low voltage VGL is applied to the source of the seventh transistor T7 through the input terminal corresponding to the gate low voltage during the previous third period t3, the gate-source voltage Vgs of the seventh transistor T7 may be 0 V (Vgs=0 V) in the fourth period t4, and thus the seventh transistor T7 may be turned off.

[0079] The node Q1 may be activated based on the gate low voltage VGL applied through the turned-on fourth transistor T4 .

[0080] The node Q2 may float due to the turned-off tenth transistor T10. At this time, the node Q2 may be bootstrapped to a first bootstrap voltage Vb1 lower than the gate low voltage of the first output clock signal OCLK1 based on the first capacitor CQ. That is, the first capacitor may reduce the gate low voltage to the first bootstrap voltage Vb1 during the period in which the sixth transistor T6 is turned on, and thus the sixth transistor T6 connected to the node Q2 may be stably turned on.

[0081] Therefore, in the fourth period t4 , the gate low voltage VGL of the first output clock signal OCLK1 may be output as a scan signal to the output terminal OUT through the turned-on sixth transistor T6 .

[0082] As described above, the scan signal Vout1 having a gate low voltage is provided to the first scan line SL1, and when the first output clock signal OCLK1 having a first gate low voltage is input, the voltage of the node Q2 may be bootstrapped in a period in which the scan signal having a gate low voltage is provided. The gate-source voltage of the sixth transistor T6 may be increased by the bootstrap operation, and the gate low voltage VGL, that is, the output voltage of the scan signal may be stably output.

[0083] exist Figure 5E During the fifth period t5 shown in , the start signal Vst having a gate low voltage, the first clock signal CLK1 having a gate low voltage, the second clock signal CLK2 having a gate high voltage, and the first output clock signal OCLK1 having a gate high voltage may be applied to the first stage ST1. At this time, the first output clock signal OCLK1 having a gate high voltage may also be applied to the output clock terminal of each of the odd-numbered stages ST3, ST5, ... except the first stage ST1, and the second output clock signal OCLK2 having a gate low voltage may be applied to the output clock terminal of each of the even-numbered stages ST2, ST4, ...

[0084] The first transistor T1 may be turned off in response to the first output clock signal OCLK1 having a gate high voltage, the second transistor T2 and the fourth transistor T4 may be turned off in response to the second clock signal CLK2 having a gate high voltage, and the ninth transistor T9 and the tenth transistor T10 may be turned on in response to the first clock signal CLK1 having a gate low voltage.

[0085] The node QB may float by the first transistor T1 and the second transistor T2 being turned off. At this time, the node QB may be bootstrapped to a second bootstrap voltage Vb2 lower than the gate low voltage of the first clock signal CLK1 based on the second capacitor CQB. That is, the second capacitor CQB may reduce the gate low voltage VGL to the second bootstrap voltage Vb2 during the period in which the seventh transistor T7 is turned on, and thus the seventh transistor T7 connected to the node QB may be stably turned on.

[0086] The node Q1 may be provided with the second clock signal CLK2 having a high level through the turned-on third transistor T3 and may be provided with the gate low voltage VGL through the turned-on ninth transistor T9. At this time, the second clock signal CLK2 having a high level may have a value much greater than the gate low voltage VGL, and thus the node Q1 may be provided with the second clock signal CLK2 having a high level, and thus may be deactivated to the gate high voltage.

[0087] The node Q2 may be deactivated to a gate high voltage based on the second clock signal CLK2 applied through the tenth transistor T10. In response to the voltage of the node Q2, the sixth transistor T6 may be turned off.

[0088] Therefore, in the fifth period t5 , the scan signal having the gate low voltage VGL may be output to the output terminal OUT through the seventh transistor T7 .

[0089] As described above, during the fifth period t5 , the gate-source voltage of the seventh transistor T7 may be increased through the second bootstrap operation by using the second capacitor CQB, and thus the output voltage of the scan signal may maintain the level of the gate low voltage.

[0090] exist Fig. 5F During the sixth period t6 shown in , the start signal Vst having a gate low voltage, the first clock signal CLK1 having a gate high voltage, the second clock signal CLK2 having a gate low voltage, and the first output clock signal OCLK1 having a gate low voltage may be applied to the first stage ST1. At this time, the first output clock signal OCLK1 having a gate low voltage may also be applied to the output clock terminal of each of the odd-numbered stages ST3, ST5, ... except the first stage ST1, and the second output clock signal OCLK2 having a gate high voltage may be applied to the output clock terminal of each of the even-numbered stages ST2, ST4, ...

[0091] The first transistor T1 may be turned on in response to the first output clock signal OCLK1 having a gate low voltage, the second transistor T2 and the fourth transistor T4 may be turned on in response to the second clock signal CLK2 having a gate low voltage, and the ninth transistor T9 and the tenth transistor T10 may be turned off in response to the first clock signal CLK1 having a gate high voltage.

[0092] The node QB can be activated to the start signal Vst with a gate low voltage by turning on the first transistor T1 and the second transistor T2. The eighth transistor T8 can be turned on by the start signal Vst with a gate low voltage applied to the node QB. At this time, because the second clock signal CLK2 with a gate high voltage is applied to the source of the third transistor T3 during the previous fifth period t5, when the second clock signal CLK2 with a gate low voltage is applied in the sixth period t6, the third transistor T3 can remain in the on state until the gate-source voltage Vgs of the third transistor T3 becomes 0V, and when the gate-source voltage Vgs of the third transistor T3 is 0V, the third transistor T3 can be in the off state. Because the first output clock signal OCLK1 having a gate high voltage is applied to the source of the eleventh transistor T11 during the previous fifth period t5, when the first clock signal CLK1 having a gate high voltage is applied in the sixth period t6, the eleventh transistor T11 may maintain a turned-on state until the gate-source voltage Vgs of the eleventh transistor T11 becomes 0 V, and the eleventh transistor T11 may be in a turned-off state when the gate-source voltage Vgs of the eleventh transistor T11 is 0 V. Because the gate low voltage VGL is applied to the source of the seventh transistor T7 through the input terminal corresponding to the gate low voltage during the previous fifth period t5, the gate-source voltage Vgs of the seventh transistor T7 may be 0 V (Vgs=0 V) in the sixth period t6, and thus the seventh transistor T7 may be turned off.

[0093] The node Q1 may be activated based on the gate low voltage VGL applied through the turned-on fourth transistor T4 .

[0094] The node Q2 may float due to the turned-off tenth transistor T10. At this time, the node Q2 may be activated to the first output clock signal OCLK1 having a gate low voltage by using the first capacitor CQ.

[0095] Therefore, in the sixth period t6 , the gate low voltage VGL of the first output clock signal OCLK1 may be output as a scan signal to the output terminal OUT through the turned-on sixth transistor T6 .

[0096] Figure 6 is a graph showing a voltage applied to a node Q2 of the first stage ST1 which is the uppermost stage according to the present invention.

[0097] like Figure 6As shown in FIG. 1 , it can be seen that the scan signal Vout1 having the gate high voltage VGH is provided to the first scan line SL1, and then, based on the bootstrap phenomenon using the output clock signal OCLK, the voltage of the node Q2 is the first bootstrap voltage Vb1 lower than the gate low voltage VGL. Therefore, the problem that the sixth transistor T6 is not turned on or its turn-on delay can be solved, and thus the falling time of the scan signal can be improved, thereby preventing the output delay of the gate low voltage VGL.

[0098] As described above, in the embodiment of the present invention, the falling time of the scan signal shifted or converted from the gate high voltage to the gate low voltage can be improved to 1 μs or less through the first bootstrap operation using the first capacitor CQ.

[0099] In addition, according to an embodiment of the present invention, each stage ST of the scan driver 200 can be configured with eleven transistors T1 to T11 and two capacitors CQ and CQB, thereby simplifying the circuit configuration. Therefore, the area occupied by each stage ST in the display panel 300 can be reduced, and thus the line width of the frame area can be reduced by at least 100 μm.

[0100] In addition, compared with a comparative example including a larger number of transistors than those included in each stage according to an embodiment of the present invention, the transistors included in each stage according to an embodiment of the present invention can ensure a threshold voltage margin similar to that of each transistor included in the stage of the comparative example.

[0101] Furthermore, according to an embodiment of the present invention, scan signals supplied to scan lines may be shifted and output at a frequency of about 1 Hz without overlapping, and thus driving may be performed at a lower frequency for each scan line.

[0102] Furthermore, according to the embodiment of the present invention, the node QB may be periodically activated through a bootstrap operation based on the second capacitor CQB, and thus a gate low voltage may be stably maintained in driving performed at a lower frequency.

[0103] In the present invention, an organic light emitting display apparatus is described as an example, but is not limited thereto, and the present invention may be applied to an electronic device including a scan line.

[0104] As described above, according to an embodiment of the present invention, each of the plurality of stages of the scan driver can be configured with eleven transistors and two capacitors, thereby simplifying the circuit configuration. Therefore, the area occupied by each stage in the display panel can be reduced, and thus the line width of the frame area can be reduced by at least 100 μm.

[0105] Furthermore, according to an embodiment of the present invention, scan signals supplied to scan lines may be shifted and output at a frequency of about 1 Hz without overlapping, and thus driving may be performed at a lower frequency for each scan line.

[0106] Furthermore, according to the embodiment of the present invention, a falling time of a scan signal shifted from a gate high voltage to a gate low voltage may be improved through the first bootstrap operation based on the first capacitor.

[0107] Furthermore, according to the embodiment of the present invention, the node can be periodically activated through the second bootstrap operation based on the second capacitor, and thus the gate low voltage can be stably maintained in driving performed at a lower frequency.

[0108] The effects according to the present invention are not limited to the above examples, and other various effects may be included in the present application.

[0109] While the invention has been particularly shown and described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as defined by the following claims.

Claims

1. A scanning driver, comprising: Multiple levels, Each of the plurality of stages comprises: a Q1 node controller that controls a voltage of the Q1 node by using a first clock signal and a second clock signal that are opposite in phase to each other; a QB node controller that controls a voltage of a QB node by using the first clock signal, the second clock signal, an output clock signal, and a start signal; a first transistor (T7) which is controlled by the QB node and outputs a gate low voltage as a scan signal while the QB node is activated; and a second transistor (T6) which outputs a gate high voltage as the scan signal while the Q2 node is activated and which outputs the gate low voltage as the scan signal when the Q2 node is bootstrapped to a voltage lower than the gate low voltage, The Q1 node controller includes: a seventh transistor (T3), the seventh transistor providing the second clock signal to the Q1 node according to the voltage of the QB node; an eighth transistor (T4) that provides the gate low voltage to the Q1 node according to the second clock signal; and A ninth transistor (T9), wherein the ninth transistor provides the gate low voltage to the Q1 node according to the first clock signal.

2. The scan driver according to claim 1, wherein Each of the plurality of stages further includes a first capacitor connected between a clock output terminal thereof and the second transistor, and The first capacitor bootstraps the Q2 node by reflecting a voltage change of the output clock terminal to the Q2 node when the scan signal transitions from the gate high voltage to the gate low voltage.

3. The scan driver according to claim 1, wherein The QB node controller comprises: a third transistor (T1) and a fourth transistor (T2), the third transistor and the fourth transistor being connected in series between the QB node and an input terminal corresponding to the start signal; a fifth transistor (T5), the fifth transistor providing the gate high voltage to the second capacitor according to the voltage of the Q1 node; and a sixth transistor (T8), the sixth transistor providing the first clock signal to the second capacitor according to the voltage of the QB node, wherein the third transistor provides the start signal to the fourth transistor in response to the output clock signal, and The fourth transistor provides the start signal to the QB node in response to the second clock signal.

4. The scan driver according to claim 3, wherein Each of the plurality of stages further comprises: a tenth transistor (T10) disposed between the Q1 node and the Q2 node; and an eleventh transistor (T11) disposed between the Q2 node and the third transistor, When the Q2 node is bootstrapped to a voltage lower than the gate low voltage, the tenth transistor and the eleventh transistor are turned off.

5. The scan driver according to claim 3, wherein The second capacitor is connected between the QB node and the sixth transistor, and The second capacitor bootstraps the QB node by reflecting a voltage change of the drain of the sixth transistor to the QB node when the scan signal maintains the gate low voltage.

6. An organic light emitting display device, comprising: A display panel, the display panel comprising a display area provided with a pixel array and a non-display area provided on at least one side of the display area; and According to any one of claims 1 to 5, the scan driver provides the scan signal generated by each of the plurality of stages to the plurality of scan lines of the pixel array.

7. The organic light emitting display device according to claim 6, wherein The plurality of transistors included in the scan driver include polysilicon transistors, and The pixel array includes a plurality of transistors, and the plurality of transistors included in the pixel array include oxide semiconductor transistors.

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