A GIP circuit for improving display screen stability and driving method thereof

Abstract

The present invention discloses a GIP circuit and a driving method thereof for improving the stability of a display screen. Each level of GIP has 16 TFTs from T1 to T16 and 1 capacitor C1. The device sizes of T15 and T16 are designed to be larger than T14, the device size of T2 is designed to be larger than T8, and the device size of T12 is designed to be larger than T9. When the Q point needs to maintain a high level, the present invention uses T14, T15, and T16 to effectively prevent T3 and T13 from leaking electricity, causing the Q point to be insufficient in high potential level, thereby affecting the GIP level transmission and ultimately causing the screen to be abnormal.

Description

Technical Field

[0001] The present invention relates to the technical field of display screen driving, and in particular to a GIP circuit for improving the stability of a display screen and a driving method thereof. Background Art

[0002] There is a leakage problem of TFT devices in the voltage stabilization circuit in the GIP circuit of the LCD display. If the leakage is large, it will cause problems such as mischarging, GIP level transmission failure, insufficient charging, etc., resulting in abnormal display of the display. Summary of the invention

[0003] The object of the present invention is to provide a GIP circuit and a driving method thereof for improving the stability of a display screen.

[0004] The technical solution adopted by the present invention is:

[0005] A GIP circuit for improving the stability of a display screen, comprising transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16 and a capacitor C1;

[0006] The gate of T1 is connected to Gn-4, the drain of T1 is connected to VGH, and the source of T1 is connected to Q point;

[0007] The gate of T2 is connected to point Q, the drain of T2 is connected to point P1, and the source of T2 is connected to VGL;

[0008] The gate of T3 is connected to point P1, the drain of T3 is connected to point Q, and the source of T3 is connected to point S;

[0009] The gate of T4 is connected to the Q point, the drain of T4 is connected to CK(n), and the source of T4 is connected to Gn;

[0010] The gate of T5 is connected to point P2, the drain of T5 is connected to Gn, and the source of T5 is connected to VGL;

[0011] The gate of T6 is connected to point P1, the drain of T6 is connected to Gn, and the source of T6 is connected to VGL;

[0012] The gate of T7 is connected to Gn+4, the drain of T7 is connected to VGL, and the source of T7 is connected to Q point;

[0013] The gate and drain of T8 are connected to V2, and the source of T8 is connected to point P1;

[0014] The gate and drain of T9 are connected to V1, and the source of T9 is connected to point P2;

[0015] The gate of T10 is connected to V1, the drain of T10 is connected to point P1, and the source of T10 is VGL;

[0016] The gate of T11 is connected to V2, the drain of T11 is connected to point P2, and the source of T11 is connected to VGL;

[0017] The gate of T12 is connected to the Q point, the drain of T12 is connected to the P2 point, and the source of T12 is connected to VGL;

[0018] The gate of T13 is connected to point P2, the drain of T13 is connected to point S, and the source of T13 is connected to point Q;

[0019] The gate of T14 is connected to the Q point, the drain of T14 is connected to the S point, and the source of T14 is connected to VGH;

[0020] The gate of T15 is connected to point P1, the drain of T15 is connected to point S, and the source of T15 is connected to VGL;

[0021] The gate of T16 is connected to point P2, the drain of T16 is connected to point S, and the source of T16 is connected to VGL;

[0022] One plate of C1 is connected to point Q, and the other plate of C1 is connected to Gn.

[0023] Furthermore, the device sizes of T15 and T16 are larger than that of T14, the device size of T2 is larger than that of T8, and the device size of T12 is larger than that of T9.

[0024] Furthermore, the GIP circuit is disposed on the display panel and is located on one side of the display panel.

[0025] Furthermore, the display panel is an OLED display panel or an LCD display panel.

[0026] Furthermore, a driving IC is included, and Gn, Gn-4, and Gn+4 are connected to the driving IC.

[0027] Furthermore, transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, and T16 are all thin film transistors.

[0028] A driving method of a GIP circuit for improving the stability of a display screen is applied to the GIP circuit for improving the stability of a display screen. The method includes a positive frame part and a negative frame part, and specifically includes the following steps:

[0029] For the positive frame: set V1 to VGL and V2 to VGH;

[0030] At t1: Gn-4 outputs a high potential, making Q point a high potential; making P1 point a low potential, T11 and T12 are turned on, P2 point changes from a high potential to a low potential, and S point is a high potential; CKn, CKn+4, Gn, Gn+4 and VGL are maintained at a low potential;

[0031] At t2: Gn-4 outputs a low potential, CKn is a high potential, which makes Gn a high potential. The potential of Q point is pulled up again due to the coupling of C1 capacitor; CKn+4, Gn+4 and VGL are maintained at a low potential;

[0032] At t3: CKn outputs a low potential, the potential of Q point decreases due to the coupling of C1 capacitor, and Gn outputs a low potential; Gn-4, CKn+4, Gn+4 and VGL remain at a low potential;

[0033] At t4: CKn+4 outputs high potential, Gn+4 outputs high potential, making Q point low potential, P1 point high potential, P2 point low potential, S point low potential, Q point discharges through T3 and T15; CKn, Gn-4, Gn and VGL are maintained at low potential;

[0034] For negative frames: set V1 to VGH and V2 to VGL;

[0035] At t1: Gn-4 outputs a high potential, making Q point a high potential and P2 point a low potential; T2 and T10 are turned on, and P1 point is pulled from a high potential to a low potential; S point is a high potential; CKn, CKn+4, Gn, Gn+4 and VGL are maintained at a low potential;

[0036] At t2: Gn-4 outputs a low potential, CKn changes from a low potential to a high potential, making Gn a high potential. The potential of the Q point is pulled up again due to the coupling effect of the C1 capacitor; CKn+4, Gn+4 and VGL remain at a low potential;

[0037] At t3: CKn outputs a low potential, the potential of Q point decreases due to the coupling of C1 capacitor, and Gn outputs a low potential; Gn-4, CKn+4, Gn+4 and VGL remain at a low potential;

[0038] At time t4: CKn+4 outputs high potential, Gn+4 outputs high potential, causing point Q to change from high potential to low potential, point P2 is pulled to high potential, point S changes from high potential to low potential, and point Q discharges through T13 and T16; CKn, Gn-4, Gn and VGL are maintained at low potential.

[0039] The present invention adopts the above technical solution to raise the level of the key node of TFT at a specific moment, thereby preventing the problem of abnormal display caused by leakage of TFT device of the voltage stabilizing circuit, and improving the stability of the display screen. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments;

[0041] Figure 1It is a structural schematic diagram of a GIP circuit for improving the stability of a display screen according to the present invention;

[0042] Figure 2 This is a positive frame timing diagram of a GIP circuit for improving display screen stability according to the present invention;

[0043] Figure 3 The negative frame timing diagram of a GIP circuit for improving the stability of a display screen according to the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0045] like Figures 1 to 3 As shown in one, the present invention discloses a GIP circuit for improving the stability of a display screen, which includes transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16 and a capacitor C1;

[0046] The gate of T1 is connected to Gn-4, the drain of T1 is connected to VGH, and the source of T1 is connected to Q point;

[0047] The gate of T2 is connected to point Q, the drain of T2 is connected to point P1, and the source of T2 is connected to VGL;

[0048] The gate of T3 is connected to point P1, the drain of T3 is connected to point Q, and the source of T3 is connected to point S;

[0049] The gate of T4 is connected to the Q point, the drain of T4 is connected to CK(n), and the source of T4 is connected to Gn;

[0050] The gate of T5 is connected to point P2, the drain of T5 is connected to Gn, and the source of T5 is connected to VGL;

[0051] The gate of T6 is connected to point P1, the drain of T6 is connected to Gn, and the source of T6 is connected to VGL;

[0052] The gate of T7 is connected to Gn+4, the drain of T7 is connected to VGL, and the source of T7 is connected to Q point;

[0053] The gate and drain of T8 are connected to V2, and the source of T8 is connected to point P1;

[0054] The gate and drain of T9 are connected to V1, and the source of T9 is connected to point P2;

[0055] The gate of T10 is connected to V1, the drain of T10 is connected to point P1, and the source of T10 is VGL;

[0056] The gate of T11 is connected to V2, the drain of T11 is connected to point P2, and the source of T11 is connected to VGL;

[0057] The gate of T12 is connected to the Q point, the drain of T12 is connected to the P2 point, and the source of T12 is connected to VGL;

[0058] The gate of T13 is connected to point P2, the drain of T13 is connected to point S, and the source of T13 is connected to point Q;

[0059] The gate of T14 is connected to the Q point, the drain of T14 is connected to the S point, and the source of T14 is connected to VGH;

[0060] The gate of T15 is connected to point P1, the drain of T15 is connected to point S, and the source of T15 is connected to VGL;

[0061] The gate of T16 is connected to point P2, the drain of T16 is connected to point S, and the source of T16 is connected to VGL;

[0062] One plate of C1 is connected to point Q, and the other plate of C1 is connected to Gn.

[0063] Specifically, Figure 1 As shown, each level of the GIP circuit of the invention has 16 TFTs T1 to T16, 1 capacitor C1, Figure 2 and Figure 3 The circuit diagram and timing diagram are shown below. VGH is the DC high voltage, VGL is the DC low voltage, the device sizes of T15 and T16 are designed to be larger than T14, the device size of T2 is designed to be larger than T8, and the device size of T12 is designed to be larger than T9. Large devices can determine the direction of current flow. When two devices are turned on at the same time, the current is affected by the large device.

[0064] When the Q point needs to maintain a high level, the present invention uses T14, T15, and T16 to effectively prevent T3 and T13 from leaking electricity and causing the Q point to be insufficiently high, thereby affecting the GIP level transmission and ultimately causing the screen to be abnormal.

[0065] The GIP driving process is as follows:

[0066] 1. Normal frame: V1=VGL, V2=VGH.

[0067] At t1: Gn-4 is at high potential, T1 is turned on, Q point is pulled to high potential, T2, T4, T12, and T14 are turned on; V2 is at high potential, T8 is turned on, and since the device size of T2 is larger than that of T8, P1 point is at low potential; T11 and T12 are turned on, P2 point is pulled to low potential. Since T3, T13, T15, and T16 are turned off, T14 is turned on, and S point is at high potential.

[0068] At time t2: Gn-4 becomes low potential, T1 is closed, CKn changes from low potential to high potential, T4 gives the high potential of CKn to Gn, and the potential of Q point is pulled up again due to the coupling effect of C1 capacitor.

[0069] At t3: the CKn potential changes from high potential to low potential, and the potential of the Q point decreases due to the capacitive coupling of C1.

[0070] At time t4: Gn+4 becomes a high potential, T7 opens to give the low potential of VGL to point Q, and point Q changes from a high potential to a low potential. T2, T4, T12, and T14 are closed, and the potential of P1 is pulled to a high potential by T8. T3, T6, and T15 are turned on. Since the device size of T15 is larger than that of T14, point S is a low potential, and point Q discharges through T3 and T15.

[0071] 2. Negative frame: V1=VGH, V2=VGL.

[0072] At time t1: Gn-4 is at high potential, T1 is turned on, point Q is pulled to high potential, T2, T4, T12, and T14 are turned on; V1 is at high potential, T9 and T10 are turned on, and since the device size of T12 is larger than that of T9, point P2 is at low potential; T2 and T10 are turned on, and P1 is pulled to low potential; since T3, T13, T15, and T16 are closed, T14 is turned on, and point S is at high potential.

[0073] At time t2: Gn-4 becomes low potential, T1 is closed, CKn changes from low potential to high potential, T4 gives the high potential of CKn to Gn, and the potential of Q point is pulled up again due to the coupling effect of C1 capacitor.

[0074] At t3: the CKn potential changes from high potential to low potential, and the potential of the Q point decreases due to the capacitive coupling of C1.

[0075] At time t4: Gn+4 becomes a high potential, T7 opens and gives the low potential of VGL to point Q, point Q changes from a high potential to a low potential, T2, T4, T12, and T14 are closed, the potential of point P2 is pulled to a high potential by T9, T5, T13, and T16 are turned on, and since the device size of T16 is larger than that of T14, point S becomes a low potential, and point Q discharges through T13 and T16.

[0076] The present invention adopts the above technical solution. During the driving process, there is T14. Even if the Vth of T3 and T13 drifts from positive voltage to negative voltage, the voltage leaked in is still HIGH level, which effectively prevents display abnormality caused by leakage of T3 and T13 and improves the stability of the display screen.

[0077] Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians of the art without making creative work are within the scope of protection of the present application.

Claims

1. A method for driving a GIP circuit for improving the stability of a display screen, wherein the GIP circuit for improving the stability of a display screen comprises transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16 and a capacitor C1; The gate of T1 is connected to Gn-4, the drain of T1 is connected to VGH, and the source of T1 is connected to Q point; The gate of T2 is connected to point Q, the drain of T2 is connected to point P1, and the source of T2 is connected to VGL; The gate of T3 is connected to point P1, the drain of T3 is connected to point Q, and the source of T3 is connected to point S; The gate of T4 is connected to the Q point, the drain of T4 is connected to CK(n), and the source of T4 is connected to Gn; The gate of T5 is connected to point P2, the drain of T5 is connected to Gn, and the source of T5 is connected to VGL; The gate of T6 is connected to point P1, the drain of T6 is connected to Gn, and the source of T6 is connected to VGL; The gate of T7 is connected to Gn+4, the drain of T7 is connected to VGL, and the source of T7 is connected to Q point; The gate and drain of T8 are connected to V2, and the source of T8 is connected to point P1; The gate and drain of T9 are connected to V1, and the source of T9 is connected to point P2; The gate of T10 is connected to V1, the drain of T10 is connected to point P1, and the source of T10 is VGL; The gate of T11 is connected to V2, the drain of T11 is connected to point P2, and the source of T11 is connected to VGL; The gate of T12 is connected to the Q point, the drain of T12 is connected to the P2 point, and the source of T12 is connected to VGL; The gate of T13 is connected to point P2, the drain of T13 is connected to point S, and the source of T13 is connected to point Q; The gate of T14 is connected to the Q point, the drain of T14 is connected to the S point, and the source of T14 is connected to VGH; The gate of T15 is connected to point P1, the drain of T15 is connected to point S, and the source of T15 is connected to VGL; The gate of T16 is connected to point P2, the drain of T16 is connected to point S, and the source of T16 is connected to VGL; One electrode of C1 is connected to Q point, and the other electrode of C1 is connected to Gn; the method includes a positive frame part and a negative frame part, and the specific steps are as follows: For the positive frame: set V1 to VGL and V2 to VGH; At t1: Gn-4 outputs a high potential, making Q point a high potential; making P1 point a low potential, T11 and T12 are turned on, P2 point changes from a high potential to a low potential, and S point is a high potential; CKn, CKn+4, Gn, Gn+4 and VGL are maintained at a low potential; At t2: Gn-4 outputs a low potential, CKn is a high potential, which makes Gn a high potential. The potential of Q point is pulled up again due to the coupling of C1 capacitor; CKn+4, Gn+4 and VGL are maintained at a low potential; At t3: CKn outputs a low potential, the potential of Q point decreases due to the coupling of C1 capacitor, and Gn outputs a low potential; Gn-4, CKn+4, Gn+4 and VGL remain at a low potential; At t4: CKn+4 outputs high potential, Gn+4 outputs high potential, making Q point low potential, P1 point high potential, P2 point low potential, S point low potential, Q point discharges through T3 and T15; CKn, Gn-4, Gn and VGL are maintained at low potential; For negative frames: set V1 to VGH and V2 to VGL; At t1: Gn-4 outputs a high potential, making Q point a high potential and P2 point a low potential; T2 and T10 are turned on, and P1 point is pulled from a high potential to a low potential; S point is a high potential; CKn, CKn+4, Gn, Gn+4 and VGL are maintained at a low potential; At t2: Gn-4 outputs a low potential, CKn changes from a low potential to a high potential, making Gn a high potential. The potential of the Q point is pulled up again due to the coupling effect of the C1 capacitor; CKn+4, Gn+4 and VGL remain at a low potential; At t3: CKn outputs a low potential, the potential of Q point decreases due to the coupling of C1 capacitor, and Gn outputs a low potential; Gn-4, CKn+4, Gn+4 and VGL remain at a low potential; At time t4: CKn+4 outputs high potential, Gn+4 outputs high potential, causing point Q to change from high potential to low potential, point P2 is pulled to high potential, point S changes from high potential to low potential, and point Q discharges through T13 and T16; CKn, Gn-4, Gn and VGL are maintained at low potential.

2. The driving method of the GIP circuit for improving the stability of a display screen according to claim 1, characterized in that: The device size of T15 and T16 is larger than that of T14, the device size of T2 is larger than that of T8, and the device size of T12 is larger than that of T9.

3. The driving method of the GIP circuit for improving the stability of a display screen according to claim 1, characterized in that: The GIP circuit is disposed on the display panel and is located on one side of the display panel.

4. The driving method of the GIP circuit for improving the stability of a display screen according to claim 3, characterized in that: The display panel is an OLED display panel or an LCD display panel.

5. The driving method of a GIP circuit for improving display screen stability according to claim 1, characterized in that: It also includes a driving IC, and Gn, Gn-4, and Gn+4 are connected to the driving IC.

6. The driving method of a GIP circuit for improving display screen stability according to claim 1, characterized in that: Transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, and T16 are all thin film transistors.

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