Memory Devices

Abstract

The present disclosure relates to a memory device. A device is disclosed. The device includes a first tracking control line, a first tracking circuit, a first sensing circuit, and a precharge circuit. The first tracking control line is configured to transmit a first tracking control signal. The first tracking circuit is configured to generate a first tracking signal associated with a first tracking unit in a memory array in response to the first tracking control signal. The first sensing circuit is configured to receive the first tracking signal and is configured to generate a first sensing tracking signal in response to the first tracking signal. The precharge circuit is configured to generate a precharge signal for precharging a data line associated with a memory cell in a memory array in response to a rising edge of the first sensing tracking signal and a falling edge of a read enable delay signal. A method is also disclosed herein.

Description

Technical Field

[0001] The present disclosure relates to memory devices. Background Art

[0002] Memory devices have been used in various applications. Typically, memory devices include, for example, static random access memory (SRAM) and dynamic random access memory (DRAM). SRAM devices are commonly used in high-speed communications, image processing, and system-on-chip (SOC) applications. In some methods, SRAM devices include sense amplifiers. The sense amplifiers typically dominate the SRAM speed, and are also associated with circuits of the SRAM device that generate precharge signals for activating SRAM cells. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor device is provided, including: a first tracking control line, configured to transmit a first tracking control signal associated with a clock pulse signal; a first tracking circuit, configured to generate a first tracking signal associated with a plurality of first tracking units in a memory array in response to the first tracking control signal; a first sensing circuit, configured to receive the first tracking signal, and configured to generate a first sensing tracking signal in response to the first tracking signal; and a precharge circuit, coupled between the first sensing circuit and the memory array, and configured to generate a precharge signal in response to a rising edge of the first sensing tracking signal and a falling edge of a read enable delay signal, the precharge signal being used to precharge a data line associated with at least one memory unit in the memory array.

[0004] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a plurality of first tracking units in a memory array, coupled to an output of a first tracking circuit; a first sensing circuit, including an input coupled to the output of the first tracking circuit, and configured to generate a first sensing tracking signal; a plurality of second tracking units in the memory array, coupled to the output of the second tracking circuit; a second sensing circuit, including an input coupled to the output of the second tracking circuit, and configured to generate a second sensing tracking signal; a latch circuit, configured to latch a read enable signal, and configured to generate a read enable delay signal associated with the read enable signal; and a control circuit, configured to generate a sensing enable signal for enabling a sensing amplifier circuit in response to the second sensing tracking signal and the read enable delay signal.

[0005] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, including: generating a precharge signal in response to a rising edge of a first sensing tracking signal generated by a first sensing circuit and in response to a falling edge of a read enable delay signal, the first sensing circuit being configured to sense a first tracking signal associated with a plurality of first tracking units in a memory array, the precharge signal being used to precharge a data line associated with at least one memory cell in the memory array; and generating a sensing enable signal for enabling a sensing amplifier circuit in response to a second sensing tracking signal generated by a second sensing circuit and in response to the read enable delay signal, the second sensing circuit being configured to sense a second tracking signal associated with a plurality of second tracking units in the memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram illustrating a memory device according to some embodiments of the present disclosure.

[0008] Figure 2 is a diagram showing some embodiments of the present disclosure Figure 1 The memory device shown corresponds to an example diagram of the structure of the memory device.

[0009] Figure 3 is a diagram showing some embodiments of the present disclosure Figure 2 The memory device shown corresponds to a layout diagram of the memory device.

[0010] Figure 4 is a diagram showing some embodiments of the present disclosure Figure 3 The memory device shown corresponds to an example diagram of the structure of the memory device.

[0011] Figure 5 is a diagram showing some embodiments of the present disclosure Figure 4 An example diagram of the structure of a sensing-enabled global control unit corresponding to the sensing-enabled global control unit shown.

[0012] Figure 6 is a diagram showing some embodiments of the present disclosure Figure 4 The latch circuit shown corresponds to an example diagram of the structure of the latch circuit.

[0013] Figure 7 is a diagram showing some embodiments of the present disclosure Figures 4 to 6 A signal waveform diagram showing the relationship between relative signals over time in a memory device.

[0014] Figure 8 According to some embodiments of the present disclosure, Figure 4 The memory device shown corresponds to a flowchart of a method of the memory device.

[0015] Fig. 9 is a block diagram of a system for designing an IC layout design according to some embodiments of the present disclosure.

[0016] Fig.10 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] The terms used in this specification generally have their ordinary meanings in the art and in the specific context in which each term is used. The use of examples in this specification (including examples of any term discussed herein) is illustrative only and in no way limits the scope and meaning of the present disclosure or any exemplary term. Likewise, the present disclosure is not limited to the various embodiments given in this specification.

[0019] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. For example, without departing from the scope of the embodiment, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0020] As used herein, the terms "including", "comprising", "having", "containing", "involving", etc. should be understood as open-ended, ie, meaning including but not limited to.

[0021] References throughout the specification to "one embodiment," "an embodiment," or "some embodiments" indicate that a particular feature, structure, implementation, or characteristic described in conjunction with the embodiment(s) is included in at least one embodiment of the present disclosure. Thus, use of the phrases "in one embodiment" or "in an embodiment" or "in some embodiments" in various places throughout the specification does not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, implementations, or characteristics may be combined in any suitable manner.

[0022] Herein, the term “coupled” may also be referred to as “electrically coupled”, and the term “connected” may be referred to as “electrically connected.” “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

[0023] In addition, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used throughout the description to facilitate understanding and description of the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The structures may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0024] As used herein, "approximately," "about," "approximately," or "substantially" shall generally refer to any approximation of a given value or range, wherein the approximation varies according to the field to which it belongs, and its range shall be consistent with the broadest interpretation understood by those skilled in the art to cover all such modifications and similar structures. In some embodiments, it generally means within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. The values ​​given herein are approximate, meaning that if not explicitly stated, the term "approximately," "about," "approximately," or "substantially" can be inferred, or other approximate values ​​are meant.

[0025] Figure 1 is a schematic diagram showing a memory device 100 according to some embodiments of the present disclosure. In some embodiments, the memory device 100 is implemented by a static random access memory (SRAM). Figure 11 , the memory device 100 includes a control circuit 110, read assist circuits 121 and 122, sense amplifier circuits 131 and 132, and memory arrays CA1 and CA2. The control circuit 110 is coupled to the read assist circuits 121 and 122, and the sense amplifier circuits 131 and 132. The memory array CA1 is coupled between the assist circuit 121 and the sense amplifier circuit 131, and the memory array CA2 is coupled between the assist circuit 122 and the sense amplifier circuit 132.

[0026] The memory device 100 is used to read or write digital data from the bit cells BC11-BCmn in the memory array CA1 and the bit cells BC11-BCmn in the memory array CA2. These digital data can be stored in the bit cells BC11-BCmn and can be read or accessed by the memory device 100 from the bit cells BC11-BCmn in the memory array CA1 or CA2.

[0027] In some embodiments, the memory array CA1 or CA2 may include M*N bit cells BC11~BCmn arranged along M columns and N rows. The bit cells on the same column are connected to the same bit line and the same complementary bit line. For example, the bit cells BC11, BC12... and BC1n on the same column are connected to the bit line BL1 and the complementary bit line BLB1; the bit cells BCm1, BCm2... and BCmn on the same column are connected to the bit line BLm and the complementary bit line BLBm. The bit cells on the same row are connected to the same word line. For example, the bit cells BC11 and BCm1 on the same row are connected to the word line WL1; the bit cells BC12 and BCm2 on the same row are connected to the word line WL2; and the bit cells BC1n and BCmn on the same row are connected to the word line WLn. For simplicity, for the purpose of explanation, each bit cell BC11, BC12 ... and BC1n, BCm1, BCm2 ... and BCmn is referred to as BC below, because in some embodiments, the bit cells BC11, BC12 ... and BC1n, BCm1, BCm2 ... and BCmn operate in a similar manner. Similarly, for the purpose of explanation, each bit line BL1 and BLm is referred to as BL below, each complementary bit line BLB1 and BLBm is referred to as BLB, and each word line WL1, WL2 and WLn is referred to as WL.

[0028] The read assist circuit 121 or 122 is configured to select at least one bit line BL and at least one complementary bit line BLB, and is configured to adjust the voltage level on the corresponding bit line BL and the complementary bit line BLB in the read operation. In some embodiments, in the read operation, in response to the precharge signal, the read assist circuit 121 or 122 precharges both the selected bit line BL and the complementary bit line BLB to a logic high, so that the voltage of the selected bit line BL and the complementary bit line BLB is floating. Subsequently, the selected bit line BL and the complementary bit line BLB begin to discharge. The voltage of the selected bit line BL and the complementary bit line BLB drops rapidly and has a sufficiently large voltage difference to distinguish when the sense amplifier circuit 131 or 132 is activated.

[0029] The sense amplifier circuit 131 or 132 is configured to sense the voltage difference between the selected bit line BLm and the complement bit line BLBm in a read operation. In some embodiments discussed above with respect to the read assist circuit 121 or 122, the sense amplifier circuit 131 or 132 is activated to distinguish the voltage difference in response to the sense enable signal. In this way, the activated sense enable signal is later than the activated precharge signal, and the sense enable signal has a delay compared to the precharge signal. Therefore, the voltage difference between the selected bit line BL and the complement bit line BLB is detected by the sense amplifier circuit 131 or 132, and the data stored in the corresponding bit cell BC can be read.

[0030] For illustrative purposes, the configuration of the memory device 100 as described above is also given. Various configurations of the memory device 100 are within the intended scope of the present disclosure. For example, in various embodiments, the memory device 100 also includes a word line driver configured to select a word line in a read operation. The word line driver is coupled between the memory arrays CA1 and CA2 and is also coupled to the control circuit 110.

[0031] Reference now Figure 2 . Figure 2 is a diagram showing some embodiments of the present disclosure Figure 1 FIG. 1 is an example diagram of a structure of a memory device 200 corresponding to the memory device 100 shown in FIG. Figure 2As shown, the memory device 200 includes a control circuit 210, a read assist circuit 220, a sense amplifier circuit 230 and a bit cell BC. The control circuit 210 includes a global control unit 211, a precharge local control unit 212 and a sense enable local control unit 213. The global control unit 211 is coupled to the precharge local control unit 212 and the sense enable local control unit 213. The precharge local control unit 212 is coupled between the global control unit 211 and the read assist circuit 220. The sense enable local control unit 213 is also coupled between the global control unit 211 and the read assist circuit 220. The read assist circuit 220 is further coupled to the bit cell BC and the sense amplifier circuit 230. The bit cell BC and the sense amplifier circuit 230 are coupled together. Figure 1 Compared to the embodiment shown, in some embodiments, the control circuit 210 corresponds to the control circuit 110; the read assist circuit 220 corresponds to the read assist circuit 121 or 122; the sense amplifier circuit 230 corresponds to the sense amplifier circuit 131 or 132; and the bit cell BC corresponds to one of the bit cells BC in the memory array CA1 or CA2. Figure 1 An embodiment of Figure 2 The same elements in the drawings are marked with the same reference numerals for easy understanding.

[0032] like Figure 2 As shown, the precharge local control unit 212 includes a NAND logic operator 212a and NOT logic operators 212b and 212c. The NAND logic operator 212a and the NOT logic operators 212b and 212c are coupled in series. One of the inputs of the NAND logic operator 212a is coupled to the output of the global control unit 211 for receiving the global precharge signal RE to generate the precharge signal PREB. The other input of the NAND logic operator 212a is configured to receive a bank select signal BSD for selecting a corresponding memory bank (not shown) of the memory device 200 to be accessed. The output of the NAND logic operator 212a is coupled to the input of the NOT logic operator 212b. The output of the NOT logic operator 212b is coupled to the input of the NOT logic operator 212c. The output of the NOT logic operator 212c is coupled to the input of the read assist circuit 220 for outputting the local precharge signal GPREB.

[0033] The sense enable local control unit 213 includes a NAND logic operator 213a and a NOT logic operator 213b. The NAND logic operator 213a and the NOT logic operator 213b are coupled in series. One of the inputs of the NAND logic operator 213a is coupled to another output of the global control unit 211 for receiving the global sense enable signal WLP_SAE to generate the sense enable signal SAE. The output of the NAND logic operator 213a is coupled to the input of the NOT logic operator 213b. The output of the NOT logic operator 213b is coupled to another input of the read assist circuit 220 for outputting the local sense enable signal GSAE.

[0034] In some embodiments, the global precharge signal RE and the global sense enable signal WLP_SAE are referred to as global control signals. The global control signals are used in a read operation to control the memory bank of the memory device 200 to be accessed. The memory bank may include, for example, Figure 1 At least one of the memory arrays such as the memory array CA1 or CA2 shown. In some other embodiments, the local precharge signal GPREB and the local sense enable signal GSAE are referred to as local control signals. The local control signals are also utilized in the read operation to control the bit cells in the corresponding memory bank of the memory device 200 to be accessed. When the corresponding memory bank is selected in response to the bank select signal BSD, the local control signals are similar to or identical to the global control signals.

[0035] As described above, in response to the global precharge signal RE and the global sense enable signal WLP_SAE, and the bank select signal BSD, the precharge local control unit 212 and the sense enable local control unit 213 are used to generate the local precharge signal GPREB and the local sense enable signal GSAE. Through this configuration, in some embodiments, when the global precharge signal RE and the bank select signal BSD are at logic high, the output signal of the NAND logic operator 212a is at logic low, so that the local precharge signal GPREB is at logic low. When the global sense enable signal WLP_SAE and the bank select signal BSD are at logic high, the local sense enable signal GSAE is also at logic high.

[0036] like Figure 2As shown, the read assist circuit 220 includes NAND logic operators 220a and 220b, and NOT logic operators 220c, 220d, and 220e. NOT logic operators 220c, 220d, and 220e are coupled in series. One of the inputs of the NAND logic operator 220a is coupled to the output of the NOT logic operator 212c, and the other input of the NAND logic operator 220a is coupled to the output of the NOT logic operator 220c. The output of the NAND logic operator 220a is coupled to one of the inputs of the NAND logic operator 220b, and is also coupled to the input of the bit cell BC to output the precharge signal PREB to the bit cell BC. The input of the NOT logic operator 220c is coupled to the output of the NOT logic operator 213b to receive the local sense enable signal GSAE from the sense enable local unit 213. The output of the NOT logic operator 220c is coupled to the input of the NOT logic operator 220d and is also coupled to one of the inputs of the NAND logic operator 220a for outputting the first delayed sense enable signal SAEB. The output of the NOT logic operator 220d is coupled to the input of the NOT logic operator 220e and is also coupled to the input of the sense amplifier circuit 230 to output the sense enable signal SAE to the sense amplifier circuit 230. The output of the NOT logic operator 220e is coupled to one of the inputs of the NOT logic operator 220b for outputting the second delayed sense enable signal SAEC.

[0037] In addition, the input of the NAND logic operator 220b is coupled to the output of the NAND logic operator 220a and the output of the NOT logic operator 220e, and is configured to receive the precharge signal PREB from the NAND logic operator 220a and the second delayed sensing enable signal SAEC from the NOT logic operator 220e. Another input of the NAND logic operator 220b is further configured to receive the bit line enable signal BLEQB for selecting the corresponding word line to activate the corresponding bit line BL and the complement bit line BLB. The output of the NAND logic operator 220b is coupled to the selected word line of the bit cell BC, and is used to output the word line enable signal PGB to activate the corresponding word line WL.

[0038] In some embodiments, the precharge signal PREB and the sense enable signal SAE are referred to as control signals to read the bit data stored in the bit cell BC in the corresponding memory array arranged in the selected memory bank. When the corresponding bit cell BC is selected in response to the bit line enable signal BLEQB, the control signal is similar to or the same as the local control signal. In various embodiments, the word line enable signal PGB is a combination signal from the precharge signal PREB and the sense enable signal SAE, and the activation bit line enable signal BLEQB.

[0039] As described above, in response to the local precharge signal GPREB, the local sense enable signal GSAE, and the bit line enable signal BLEQB, the read assist circuit 220 is used to generate the precharge signal PREB and the sense enable signal SAE. In some embodiments, the read assist circuit 220 is used in a read operation to control the bit cell BC to be accessed in the selected memory bank of the memory device 200. Specifically, in the read operation, the precharge signal PREB output from the read assist circuit 220 is configured to precharge the corresponding bit line BL and the complement bit line BLB of the selected bit cell BC. The sense enable signal SAE output from the read assist circuit 220 is configured to activate the sense amplifier circuit 230 to start distinguishing the bit data stored in the bit cell BC. In some embodiments, as Figure 2 As shown, bit data is associated with the voltages on nodes DL_IN and DLB_IN.

[0040] In some embodiments, using Figure 2 In the configuration shown, when the corresponding memory bank is selected in the above-mentioned read operation using the control circuit 210, the local sense enable signal GSAE is at a logic high and the local precharge signal GPREB is at a logic low, so that the first delayed sense enable signal SAEB is at a logic low. The sense enable signal SAE is at a logic high, and the second delayed sense enable signal SAEC is at a logic low. In addition, the precharge signal PREB is operated to a logic high by the NAND logic operator 220a. When the bit line enable signal BLEQB is also at a logic high to select the bit cell BC, the word line enable signal PGB is operated to a logic high by the NAND logic operator 220b. In other words, when the memory bank of the memory device 200 is selected for reading, the global precharge signal RE, the global sense enable signal WLP_SAE and the bank select signal BSD are activated and at a logic high, so that the local precharge signal GPREB is a logic low and the local sense enable signal GSAE is at a logic high. The local precharge signal GPREB and the local sense enable signal GSAE are transmitted to the read assist circuit 220 for selecting the bit cell BC to be accessed. When the bit cell BC arranged in the selected memory bank is selected for reading, the bit line enable signal BLEQB is activated and is at a logic high, so that the precharge signal PREB and the sense enable signal SAE are at a logic high. The precharge signal PREB is transmitted to the selected bit cell BC for precharging the corresponding bit line BL and the complement bit line BLB coupled to the selected bit cell BC. The sense enable signal SAE is transmitted to the sense amplifier circuit 230 coupled to the selected bit cell BC for triggering the sense amplifier circuit 230. In addition, in response to the word line enable signal PGB, the corresponding word line coupled to the selected bit cell BC is activated.

[0041] The sense amplifier circuit 230 includes a transistor T1, which is an n-type metal oxide semiconductor transistor (NMOS transistor) in some embodiments, and a transistor 231, which is a p-type metal oxide semiconductor transistor (PMOS transistor) in some embodiments. The gate terminal of the transistor T1 is coupled to the output of the NOT logic operator 220d and is configured to receive the sense enable signal SAE. The source terminal of the transistor T1 is coupled to the bit cell BC, and the drain terminal of the transistor T1 is coupled to the reference node (which is ground in some embodiments). The gates of the transistor 231 are coupled together and are configured to receive a signal YB for selecting the corresponding bit line BL and the complementary bit line BLB. The source of the transistor 231 is coupled to the bit cell BC to receive the data lines DL and DLB. In some embodiments, when the transistor 231 is activated by the signal YB, the data line DL has the same signal transmitted to the bit line BL, and the data line DLB has the same signal transmitted to the complementary bit line BLB. In some embodiments, transistor 231 is configured to sense voltages on bit line BL and complement bit line BLB and generate a signal (not shown) representing bit data stored in bit cell BC.

[0042] The number and arrangement of sense amplifier circuits 230 are given for illustrative purposes. Various numbers and arrangements of sense amplifier circuits 230 are within the intended scope of the present disclosure. For example, in various embodiments, in addition to sense amplifier 231, Figure 2 The sense amplifier circuit 230 shown in FIG. 2 also includes more than one sense amplifier.

[0043] like Figure 2 As shown, in some embodiments, the bit cell BC is an SRAM cell formed by six transistors (6T-SRAM). Note that Figure 2 The bit cell BC shown is an illustrative example. The bit cell BC is not limited to 6T-SRAM, and the bit cell BC can be formed by other equivalent SRAM bit cells. For the sake of simplicity, Figure 2 The read assist circuit 220 and the sense amplifier circuit 230 shown in FIG. 1 show structures related to adjusting and sensing the voltages on the bit line BL and the complementary bit line BLB, respectively. For those skilled in the art, it is known that the read assist circuit 220 and the sense amplifier circuit 230 also include similar structures corresponding to other bit lines and complementary bit lines on different columns, and these similar structures are not shown in FIG. Figure 2 Shown in.

[0044] In addition, transistors T2, T3 and T4 (which are PMOS transistors in some embodiments) are arranged in the bit cell BC and coupled to the bit cell BC. The gate terminals of transistors T2, T3 and T4 are coupled together and further coupled to the output of the NAND logic operator 220a for receiving the precharge signal PREB. The source terminals of transistors T2, T3 and T4 are coupled to the 6T-SRAM, and the drain terminals of transistors T2, T3 and T4 are also coupled to the 6T-SRAM. In some embodiments, transistors T2, T3 and T4 are indicated as precharge auxiliary circuits and are configured to control the bit cell BC to be precharged in a read operation in response to the precharge signal PREB.

[0045] In some embodiments, using Figure 2 In this configuration shown in , when the bit cell BC is ready to be accessed in a read operation, the voltages of the nodes DL_IN and DLB_IN are pulled up to a relatively logic high in response to the precharge signal PREB, and accordingly, the voltages of the nodes DL_IN and DLB_IN are floating. In response to the sense enable signal SAE, when the transistor T1 in the sense amplifier circuit 230 is turned on, the voltages of the nodes DL_IN and DLB_IN begin to drop and are sharply pulled to ground. Since the initial voltages on the nodes DL_IN and DLB_IN may be slightly different, the voltage difference between the nodes DL_IN and DLB_IN becomes larger and will be large enough to be distinguished by the sense amplifier circuit 230.

[0046] The above configuration of the memory device 200 is provided for illustration purposes. Various implementations of the memory device 200 are within the intended scope of the present disclosure. For example, in various embodiments, the precharge local control unit 212, the sense enable local control unit 213, and the read assist circuit 220 are integrated together.

[0047] Reference now Figure 3 . Figure 3 is a diagram showing some embodiments of the present disclosure Figure 2 The memory device 200 shown in FIG. 3 is a layout diagram of a memory device layout 300 corresponding to the memory device 200. Figure 2 An embodiment of Figure 3 The same elements in the diagram are labeled with the same reference numerals for ease of understanding. Layout 300 includes several areas for configurations with various circuits. Figure 3As shown, the layout 300 includes a main control region MCNT, a vertical word line driver region WLDV, a local control region LCTRL, main input / output regions MIO1 and MIO2, cell array regions CA1 and CA2, and local input / output regions LIO1 and LIO2. These regions in the layout 300 are arranged in a matrix. The main input / output region MIO1, the cell array region CA1, and the local input / output region LIO1 are arranged in a first column C1; the main control region MCNT, the vertical word line driver region WLDV, and the local control region LCTRL are arranged in a second column C2 that is adapted to the first column C1; and the main input / output region MIO2, the cell array region CA2, and the local input / output region LIO2 are arranged in a third column C3 that is adapted to the second column C2.

[0048] refer to Figure 2 and Figure 3 , the bit cell BC is arranged in the memory arrays CA1 and CA2. The read assist circuit 220 is arranged in the local input / output regions LIO1 and LIO2, respectively. The global control unit 211 is arranged in the main control region MCNT. The precharge local control unit 212 and the sense enable local control unit 213 are arranged in the local control region LCTRL. The sense amplifier circuit 230 is arranged in the memory arrays CA1 and CA2, and for the sake of simplicity, is shown in FIG. Figure 3 The sense amplifier circuit 230 is not shown in FIG. The precharge local control unit 212, the sense enable local control unit 213 and the read assist circuit 220 have the same structure as that of the reference circuit 210. Figure 2 The discussed precharge local control unit 212, sense enable local control unit 213 and read assist circuit 220 are similarly configured. Therefore, similar configurations are not described in detail here.

[0049] and Figure 2 In comparison, Figure 3In the illustrated layout 300, the memory device further includes clock units 311 and 312, tracking word lines tWL1 and tWL2, tracking circuits 321 and 322, tracking units 331 and 332, a capacitor circuit 333, tracking bit lines tBL1 and tBL2, sensing circuits 341 and 342, and a latch circuit 350. The clock units 311 and 312, the sensing circuits 341 and 342, and the latch circuit 350 are disposed in the main control region MCNT. The tracking circuit 321 and the tracking unit 331 are disposed in the memory array CA1. The tracking circuit 322, the tracking unit 332, and the capacitor circuit 333 are disposed in the memory array CA2. The tracking word line tWL1 is disposed across the main control region MCNT, the main input / output region MIO1, and the vertical word line driver region WLDV. The tracking word line tWL2 is disposed across the main control region MCNT, the main input / output region MIO2, and the vertical word line driver region WLDV. Tracking bit lines tBL1 and tBL2 are disposed in the vertical word line driver region WLDV.

[0050] like Figure 3 As shown, the clock unit 311 is coupled to the tracking circuit 321 through the tracking word line tWL1, and the tracking word line tWL1 transmits the clock signal ( Figure 4 The tracking circuit 321 is also coupled to the sensing circuit 341 through the tracking bit line tBL1, and the tracking bit line tBL1 transmits the bit line tracking signal RE_TRKBL associated with the tracking cell 331 set in the memory array CA1. The tracking cell 331 is coupled to the tracking bit line tBL1. The sensing circuit 341 is also coupled to the global control unit 211. Similarly, the clock unit 312 is coupled to the tracking circuit 322 through the tracking word line tWL2, and the tracking word line tWL2 transmits the word line tracking signal TRKWL associated with the clock signal. The tracking circuit 322 is also coupled to the sensing circuit 342 through the tracking bit line tBL2, and the tracking bit line tBL2 transmits the bit line tracking signal TRKBL associated with the tracking cell 332 and the capacitance circuit 333 set in the memory array CA2. The tracking cell 332 and the capacitance circuit 333 are coupled to the tracking bit line tBL2. The sensing circuit 342 is also coupled to the global control unit 211.

[0051] In addition, the global control unit 211 is coupled to the sensing circuits 341 and 342 and the latch circuit 350. The global control unit 211 is also coupled to the precharge local control unit 212 and is configured to transmit the global precharge signal RE to the precharge local control unit 212. The global control unit 211 is also coupled to the sense enable local control unit 213 and is configured to transmit the global sense enable signal WLP_SAE to the sense enable local control unit 213.

[0052] The above configuration of layout 300 is provided for illustration purposes. Various implementations of a memory device corresponding to layout 300 are within the contemplated scope of the present disclosure.

[0053] Reference now Figure 4 . Figure 4 is a diagram showing some embodiments of the present disclosure Figure 3 FIG. 3 is an exemplary diagram of the structure of a memory device 400 corresponding to the memory device represented by the layout 300 shown in FIG. Figure 3 An embodiment of Figure 4 The same elements in the drawings are marked with the same reference numerals for easy understanding.

[0054] and Figure 3 In contrast, the global control unit 211 of the memory device 400 further includes a precharge global control unit 411 and a sense enable global control unit 412. The precharge global control unit 411 is coupled to the sense enable global control unit 412 at a node N1, which is further coupled to the output of the latch circuit 350. The precharge global control unit 411 is also coupled between the sense circuit 341 and the precharge local control unit 212. The sense enable global control unit 412 is also coupled between the sense circuit 342 and the sense enable local control unit 213.

[0055] like Figure 4 As shown, the clock unit 311 includes NOT logic operators 311a and 311b. The NOT logic operators 311a and 311b are coupled in series. The input of the NOT logic operator 311a is configured to receive a clock signal CKP generated by a clock generator (not shown). The output of the NOT logic operator 311b is coupled to the tracking word line tWL1.

[0056] The tracking word line tWL1 is coupled between the NOT logic operator 311b of the clock unit 311 and the input of the tracking circuit 321. The tracking word line tWL1 is configured to provide a word line tracking signal RE_TRKWL and transmit it to the tracking circuit 321. Since the resistor-capacitor (RC) load on the tracking word line tWL1 is similar to Figure 2 The bit cell BC shown is coupled to the word line, so the word line tracking signal RE_TRKWL will be similar to the signal on the word line. The length of the tracking word line tWL1 is related to the RC load and further affects the duration on the tracking word line tWL1. In other words, the tracking word line tWL1 is configured to track the Figure 1 Explained in another way, the tracking word line tWL1 is configured to simulate Figure 1 The corresponding word line WL in .

[0057] The tracking circuit 321 includes a transistor T5 (which is a PMOS transistor in some embodiments), and the tracking unit 331 includes transistors T6, T7, and T8 (which are NMOS transistors in some embodiments). Transistors T6-T8 are coupled in series. The drain terminal of transistor T5 is coupled to the source terminal of transistor T6 at node N2, which is further coupled to the tracking bit line tBL1. All gate terminals of transistors T5-T8 are coupled together to the tracking word line tWL1, so that transistors T5-T8 are controlled by the word line tracking signal RE_TRKWL.

[0058] In some embodiments, Figure 4 The number of transistors T6, T7 and T8 in the tracking unit 331 shown is substantially equal to that located at Figure 2 In other words, transistors T6, T7, and T8 in tracking cell 331 can replicate (or simulate) Figure 1 The charging or discharging path of one of the bit cells BC shown is from the read assist circuit 121 through the corresponding bit line BL and the complement bit line BLB to the sense amplifier circuit 131. Explained in another way, Figure 4 The transistors T6 , T7 , and T8 in the tracking unit 331 are shown to be able to adjust the duration of the node N2 from logic high to logic low. Figure 4 The number of transistors T6, T7, and T8 in the tracking unit 331 shown is for illustration purposes only and is not limited to three herein.

[0059] Tracking bit line tBL1 is coupled to tracking circuit 321 and tracking unit 331, and further coupled to an input of sensing circuit 341. Tracking bit line tBL1 is configured to provide a bit line tracking signal RE_TRKBL and transmit it to sensing circuit 341. Bit line tracking signal RE_TRKBL is associated with tracking unit 331.

[0060] In some embodiments, the number of tracking cells 331 coupled to the tracking bit line tBL1 is substantially equal to Figure 1 For example, referring to Figure 1 , the memory array CA1 includes N rows of bit cells BC, 256 rows in some embodiments, and the tracking bit line tBL1 is coupled to a total of 256 tracking cells 331. In some embodiments, the tracking cell 331 may include a similar Figure 2 The internal structure of the bit cell BC shown in FIG. 1 is the same as or similar to that of the bit cell BC, so that the tracking bit line tBL1 coupled to the tracking cell 331 will have a similar internal structure to that of the bit cell BC shown in FIG. Figure 2 The resistor-capacitor (RC) load of the bit line BL is shown in FIG. Figure 4As shown, the charging or discharging speed of the bit line tracking signal RE_TRKBL on the node N2 can be similar to Figure 1 The bit lines BL1 to BLm in the memory array CA1 shown in FIG. Figure 2 In various embodiments, the number of tracking cells 331 having tracking bit lines tBL1 is greater than Figure 1 The number of cell rows in the memory array CA1 is shown, thereby tracking the bit line tBL1 with a smaller RC load to speed up the transmission of the bit line tracking signal RE_TRKBL.

[0061] The sensing circuit 341 includes transistors T9, T10 and T11 (which are PMOS transistors in some embodiments) and transistor T12 (which are NMOS transistors in some embodiments). The transistors T9, T10 and T12 are coupled in parallel. All gate terminals of the transistors T9, T10 and T12 are coupled together to the tracking bit line tBL1. The drain terminal of the transistor T9 is coupled to the source terminal of the transistor T10 at the node N3, which is further coupled to the source terminal of the transistor T11. The drain terminal of the transistor T10 is coupled to the source terminal of the transistor T12 at the node N4, which is further coupled to the gate terminal of the transistor T11. The node N4 is also indicated as the output of the sensing circuit 341, and is further coupled to one of the inputs of the precharge global control unit 411. The sensing circuit 341 is configured to generate a sensing tracking signal RE_TRKBL1B at the node N4 in response to the bit line tracking signal RE_TRKBL.

[0062] In some embodiments, Figure 4 As shown, the sensing circuit 341 includes a Schmitt trigger. In some embodiments, the Schmitt trigger includes three P-type transistors T9, T10 and T11 and one N-type transistor T12. Figure 4 The Schmitt trigger shown is an exemplary structure of a Schmitt trigger. The sensing circuit 341 is not limited to Figure 4 The structure of the Schmitt trigger in FIG. The Schmitt trigger includes two threshold voltages (a high threshold voltage and a low threshold voltage).

[0063] like Figure 4As shown, the precharge global control unit 411 includes a NAND logic operator 411a and a NOT logic operator 411b. The NAND logic operator 411a and the NOT logic operator 411b are coupled in series. One input of the NAND logic operator 411a is coupled to the node N4 and is configured to receive the sense tracking signal RE_TRKBL1B output from the sense circuit 341. The other input of the NAND logic operator 411a is coupled to the node N1 and is configured to receive the read enable delay signal REND output from the latch circuit 350. The output of the NAND logic operator 411a is coupled to the input of the NOT logic operator 411b. The output of the NOT logic operator 411b is coupled to one of the inputs of the NAND logic operator 212a in the precharge local control unit 212. The precharge global control unit 411 is configured to generate a global precharge signal RE in response to the sense tracking signal RE_TRKBL1B and the read enable delay signal REND.

[0064] In some embodiments, using Figure 4 In the configuration shown, when the word line tracking signal RE_TRKWL reaches a relatively logic high, the voltage of the bit line tracking signal RE_TRKBL on the node N2 begins to be pulled to ground. In other words, the voltage on the node N2 is discharged through transistors T6, T7 and T8. In addition, when the voltage on the node N2 is pulled down to a logic low, in the sensing circuit 341, transistors T9 and T10 are turned on, and transistor T12 is turned off, so that the voltage on the node N4 is pulled up to the reference voltage VDD. In other words, the voltage on the node N4 is charged by transistors T9 and T10 in the sensing circuit 341. Therefore, the sensing tracking signal RE_TRKBL1B input to the precharge global control unit 411 is at a logic high. In addition, in the read operation, when the read enable delay signal REND is also at a logic high, the global precharge signal RE is at a logic high, and the NAND operation and the inversion operation are performed by the NAND logic operator 411a and the NOT logic operator 411b, respectively. Therefore, the global precharge signal RE is activated, as described above with reference to FIG. Figure 2 discussed.

[0065] As described above, the global precharge signal RE is generated using the clock unit 311, the tracking word line tWL1, the tracking circuit 321, the tracking bit line tBL1, the sensing circuit 341, and the precharge global control unit 411. The global precharge signal RE is used to generate the precharge signal PREB, and the precharge signal PREB is used to precharge the bit line BL and the complementary bit line BLB of the selected bit cell BC in the read operation, as shown in FIG. Figure 2 shown.

[0066] Continue to refer Figure 4, similar to the clock unit 311, the clock unit 312 includes NOT logic operators 312a and 312b coupled in series. The input of the NOT logic operator 312a is configured to receive the clock signal CKP, and the output of the NOT logic operator 312b is coupled to the tracking word line tWL2.

[0067] The tracking word line tWL2 is coupled between the NOT logic operator 312b of the clock unit 312 and the input of the tracking circuit 322. The tracking word line tWL2 is configured to provide a word line tracking signal TRKWL and transmit it to the tracking circuit 322. The RC load on the tracking word line tWL2 is similar to or greater than Figure 2 The load on the word line in the bit cell BC shown, therefore, the word line tracking signal TRKWL will be similar to or have a delay with the signal on the word line. In some embodiments, the delay is related to the length of the tracking word line tWL2, which is greater than the length of the word line. In various embodiments, the length of the tracking word line tWL2 is greater than the length of the tracking word line tWL1, and the length of the tracking word line tWL1 is substantially equal to the length of the word line.

[0068] The tracking circuit 322 has a similar configuration as the above-mentioned tracking circuit 321 and includes a P-type transistor T12. The tracking unit 332 has a similar configuration as the above-mentioned tracking unit 331 and includes N-type transistors T13, T14 and T15. As such, similar configurations are not described in detail herein. The input of the tracking circuit 322 is indicated as the gate terminal of the transistor T12 and is configured to receive the word line tracking signal TRKWL. The output of the tracking circuit 322 is indicated as a node N5 and is further coupled to the tracking unit 332 for transmitting the bit line tracking signal TRKBL on the tracking bit line tBL2.

[0069] Tracking bit line tBL2 has a similar configuration as tracking bit line tBL1 and is coupled to tracking circuit 322 and tracking unit 332, which is further coupled to the input of sensing circuit 342 and capacitance circuit 333. Figure 4 As shown, in some embodiments, the tracking unit 332 and the capacitive circuit 333 are coupled in parallel with the tracking bit line tBL2 . The tracking bit line tBL2 is configured to provide a bit line tracking signal TRKBL and transmit it to the sensing circuit 342 .

[0070] In some embodiments, an RC load is coupled to the tracking bit line tBL2 due to the tracking cell 332, and another RC load is coupled to the tracking bit line tBL2 due to the capacitive circuit 333. In various embodiments, the number of tracking cells 332 with tracking bit line tBL2 is substantially equal to Figure 1The number of cell rows in the memory array CA2 shown. In some other embodiments, the number of tracking cells 332 coupled to the tracking bit line tBL2 is less than the number of tracking cells 331 coupled to the tracking bit line tBL1, so that the tracking bit line tBL2 has a delay with respect to the tracking bit line tBL1. The delay is at least related to the difference in number between the tracking cells 331 and 332, or the RC associated with the capacitor circuit 333. In other words, the RC load coupled to the tracking bit line tBL1 is greater than the RC load coupled to the tracking bit line tBL2. Therefore, according to the same clock signal CKP, the bit line tracking signal TRKBL is slower than the bit line tracking signal RE_TRKBL.

[0071] The sensing circuit 342 has a configuration similar to the above-mentioned sensing circuit 341, and includes transistors T16, T17 and T18 of the P type and a transistor T19 of the N type. As such, similar configurations are not described in detail herein. The input of the sensing circuit 342 is indicated as a node N6 coupled to the gate terminals of the transistors T16, T17 and T19, and is configured to receive a bit line tracking signal TRKBL. The output of the sensing circuit 342 is indicated as a node N7, and is further coupled to the input of the sensing enable global control unit 412. The sensing circuit 342 is configured to generate a sensing tracking signal TRKBL1B at a node N7 in response to the bit line tracking signal TRKBL.

[0072] like Figure 4 As shown, the sense enable global control unit 412 includes a NAND logic operator 412a, a NOT logic operator 412b, and a delay chain circuit 412c. The NAND logic operator 412a, the NOT logic operator 412b, and the delay chain circuit 412c are coupled in series. The input of the delay chain circuit 412c is coupled to the node N7, and is configured to receive the sense tracking signal TRKBL1B output from the node N7 in the sense circuit 342. The output of the delay chain circuit 412c is coupled to one of the inputs of the NAND logic operator 412a, and is configured to generate a sense tracking signal TRKBL3B in response to the sense tracking signal TRKBL1B. The other input of the NAND logic operator 412a is configured to receive the read enable delay signal REND output from the latch circuit 350 at the node N1. The output of the NAND logic operator 412a is coupled to the input of the NOT logic operator 412b. The output of the NOT logic operator 412b is coupled to one of the inputs of the NAND logic operator 213a in the sense enable local control unit 213. The sense enable global control unit 412 is configured to generate a global sense enable signal WLP_SAE in response to a sense tracking signal TRKBL3B associated with the sense tracking signal TRKBL1B.

[0073] In some embodiments, using Figure 4 In the configuration shown, when the word line tracking signal TRKWL is at a logic high, the voltage of the bit line tracking signal TRKBL on the node N5 begins to be pulled to ground, which is controlled by transistors T13-T15. In addition, when the voltage on the node N5 is pulled down to a logic low, in the sensing circuit 342, transistors T16 and T17 are turned on, and transistor T19 is turned off, so that the voltage on the node N7 is pulled up to the reference voltage VDD. Therefore, the sensing tracking signal TRKBL1B input to the sensing enable global control unit 412 is at a logic high. In addition, as described above, the read enable delay signal REND is at a logic high, and therefore, through the delay chain circuit 412c, the NAND operation is performed by the NAND logic operator 412a and the inversion operation is performed by the NOT logic operator 412b, and the global sensing enable signal WLP_SAE is at a logic high. Therefore, the global sensing enable signal WLP_SAE is activated, as described above with reference to FIG. Figure 2 discussed.

[0074] As described above, the global sense enable signal WLP_SAE is generated using the clock unit 312, the tracking word line tWL2, the tracking circuit 322, the capacitor circuit 333, the tracking bit line tBL2, the sensing circuit 342, and the sense enable global control unit 412. The global sense enable signal WLP_SAE is used to generate the sense enable signal SAE, and the sense enable signal SAE is used to activate the sense amplifier circuit 230 coupled to the selected bit cell BC in the read operation, as shown in FIG. Figure 2 shown.

[0075] Reference now Figure 5 . Figure 5 is a diagram showing some embodiments of the present disclosure Figure 4 The structure of the sensing enabled global control unit 412 corresponding to the sensing enabled global control unit 412 is shown in FIG. Figure 4 An embodiment of Figure 5 The same elements in the drawings are marked with the same reference numerals for easy understanding.

[0076] and Figure 4 In comparison, Figure 5 As shown, the delay chain circuit 412c includes a plurality of NOT logic operators 511, 512, 513 and 514. The NOT logic operators 511-514 are coupled in series and further coupled to the NAND logic operator 412a. The input of the NOT logic operator 511 is coupled to the node N7 (as shown in FIG. Figure 4), and is configured to receive the sensing tracking signal TRKBL1B output from the sensing circuit 342. The output of the NOT logic operator 511 is coupled to the input of the NOT logic operator 512. The output of the NOT logic operator 513 is coupled to the input of the NOT logic operator 514, and is configured to generate and transmit the sensing tracking delay signal TRKBL2. The output of the NOT logic operator 514 is coupled to one of the inputs of the NAND logic operator 412a, and is configured to generate and transmit the sensing tracking signal TRKBL3B.

[0077] In some embodiments, using Figure 5 In this configuration, when the sensing tracking signal TRKBL1B is at logic high, as shown in the above reference Figure 4 As discussed, the tracking delay signal TRKBL2 is at logic low, so that the sensing tracking signal TRKBL3B is at logic high. In some embodiments, when the read enable delay signal REND is also at logic high, the global sensing enable signal WLP_SAE is at logic high, so that other signals are at corresponding logic levels, such as reference Figure 2 and Figure 4 discussed.

[0078] In some embodiments, the NOT logic operators 511-514 are used as inverters and are configured to generate delays for corresponding output signals. For example, in response to the sensing tracking signal TRKBL1B, the sensing tracking delay signal TRKBL2 is inverted by the NOT logic operators 511-513. The sensing tracking delay signal TRKBL2 has a delay for the sensing tracking signal TRKBL1B, and the delay is associated with the number of NOT logic operators 511-513 (three in this embodiment). In addition, in response to the sensing tracking delay signal TRKBL2, the sensing tracking signal TRKBL3B is inverted by the NOT logic operator 514. The sensing tracking signal TRKBL3B has a delay for the sensing tracking delay signal TRKBL2, and has another delay for the sensing tracking signal TRKBL1B. In other words, the sensing tracking signal TRKBL3B is slower than the sensing tracking delay signal TRKBL2, and the sensing tracking delay signal TRKBL2 is slower than the sensing tracking signal TRKBL1B.

[0079] Reference now Figure 6 . Figure 6 is a diagram showing some embodiments of the present disclosure Figure 4 The latch circuit 350 shown in FIG. 3 corresponds to an exemplary diagram of the structure of the latch circuit 350. Figure 4 An embodiment of Figure 6 The same elements in the drawings are marked with the same reference numerals for easy understanding.

[0080] like Figure 6 As shown, the latch circuit 350 includes a NOT logic operator 610, P-type transistors T61, T62, T63 and T64, and N-type transistors T65, T66, T67 and T68. The transistors T61, T62, T65 and T66 are coupled in parallel, and the transistors T63, T64, T67 and T68 are coupled in parallel. The NOT logic operator 610 is coupled to the transistors T62, T63, T64, T65, T67 and T68. The latch circuit 350 is configured to generate a read enable delay signal REND in response to a read enable signal REN.

[0081] The gate terminal of transistor T61 is configured to receive the sensing tracking signal TRKBL3B. The source terminals of transistors T61 and T63 are coupled together and further coupled to a reference voltage VDD. The drain terminal of transistor T61 is coupled to the source terminal of transistor T62. The gate terminals of transistors T62 and T65 are coupled together at node N61 and are configured to receive a read enable signal REN. In some embodiments, node N61 is also indicated as an input of latch circuit 350. The drain terminal of transistor T62 is coupled to the source terminal of transistor T65 at node N62. The gate terminal of transistor T66 is configured to receive the sensing tracking delay signal TRKBL2. The source terminal of transistor T66 is coupled to the drain terminal of transistor T65. The drain terminals of transistors T66 and T68 are coupled together and further coupled to a reference voltage (which is ground in some embodiments).

[0082] In addition, the gate terminals of transistors T63 and T68 are coupled together and further coupled to the output of NOT logic operator 610 at node N63. The drain terminal of transistor T63 is coupled to the source terminal of transistor T64. The gate terminal of transistor T64 is configured to receive the sensing tracking delay signal TRKBL2. The drain terminal of transistor T64 is coupled to the source terminal of transistor T67 at node N62. The gate terminal of transistor T67 is configured to receive the sensing tracking signal TRKBL3B. The drain terminal of transistor T67 is coupled to the source terminal of transistor T68. In addition, the input of NOT logic operator 610 is coupled to the source / drain terminals of transistors T62 and T65 at node N62. The output of NOT logic operator 610 is coupled to the gate terminals of transistors T63 and T68 at node N63, and is configured to output the read enable delay signal REND. In some embodiments, node N63 is also indicated as the output of latch circuit 350. In some other embodiments, the NOT logic operator 610 functions as an inverter and is configured to generate a delay for the signal output at the node N63 .

[0083] In some embodiments, using the above Figure 6 The latch circuit 350 and Figure 5 In the configuration of the sensing enable global control unit 412 shown, in a read operation, the sensing tracking signal TRKBL1B is at a logic high, the tracking delay signal TRKBL2 is at a logic low, and the sensing tracking signal TRKBL3B is at a logic high. When the read enable signal REN is at a logic high, transistors T61, T62, and T66 are turned off, and transistors T64, T65, and T67 are turned on, so that the voltage on the node N62 is at a logic low. In this way, the voltage on the node N63 is at a logic high due to the NOT logic operator 610, so that the transistor T63 is turned off and the transistor T68 is turned on. Since the transistors T67 and T68 are turned on, the voltage on the node N62 remains at a logic low, so that the voltage on the node N63 remains at a logic high. Therefore, the read enable delay signal REND is at a logic high, as shown in reference. Figure 4 discussed.

[0084] In some embodiments, transistors T62 and T65 are used as latches and are configured to latch the read enable signal REN at node N62. Node N62 is also indicated as the output of such latch. In some other embodiments, inverter 610 is also used as a latch with a self-timing loop to postpone the previous bit data at node N62. Therefore, the read enable delay signal REND is a double latch signal generated by transistors T62 and T65 and inverter 610. In various embodiments, using Figure 6 In the configuration shown, the read enable delay signal REND has a delay with respect to the read enable signal REN, and the delay is associated with transistors T62 and T65, and the NOT logic operator 610. In addition, the delay is also related to the signals input to the gate terminals of transistors T61-T68. These signals include the sensing tracking delay signal TRKBL2 and the sensing tracking signal TRKBL3B. In other words, the read enable delay signal REND is later than the read enable signal REN, and is controlled by the sensing tracking delay signal TRKBL2 and the sensing tracking signal TRKBL3B, wherein the sensing tracking signal TRKBL3B is related to the sensing tracking delay signal TRKBL2, as shown in FIG. Figure 5 Explained in another way, the sensing tracking delay signal TRKBL2 is used to latch the read enable signal REN. The delay between the read enable delay signal REND and the read enable signal REN is generated by a latching operation rather than a logic delay including, for example, a gate delay.

[0085] In some embodiments, the read enable signal REN is a latch signal generated by another latch circuit (not shown) in response to a word line enable signal (not shown) and / or a clock signal CKP. The word line enable signal is configured to activate or select a corresponding word line WL ( Figure 2 shown).

[0086] Reference now Figure 7 . Figure 7 4 is a diagram showing that when the bit cell BC in the memory device 400 is in a read operation according to some embodiments of the present disclosure, Figures 4 to 6 The signal waveform diagram shows the relationship between the relative signal and the time. Figures 4 to 6 An embodiment of Figure 7 The same elements in the drawings are marked with the same reference numerals for ease of understanding. Figure 7 , shows that during a read operation Figure 4 Various signals utilized in the memory device 400 shown. Period T1 is associated with the bit line enable signal BLEQB, the word line WL, and the bit line BL and the complement bit line BLB. Period T2 is associated with the local precharge signal GPREB, the precharge signal PREB, the sense enable signal SAE, the word line enable signal PGB, and the signals on the nodes DL_IN and DLB_IN. In some embodiments, the period of the bit line enable signal BLEQB dominates the duration of period T1, and the period of the precharge signal PREB dominates the duration of period T2. In other words, the frequency of the bit line enable signal BLEQB and the length of period T1 are related and have a negative correlation. The frequency of the precharge signal PREB and the length of period T2 are related and have a negative correlation.

[0087] refer to Figures 4 to 7 The clock signal CKP is used in the memory device 400 as an initial signal model for generating other signals for a read operation. The sensing tracking signal RE_TRKBL1B is generated by the sensing circuit 341 and is associated with the bit line tracking signal RE_TRKBL, which is further associated with the clock signal CKP. In some embodiments, using Figure 4 In the configuration discussed, the sensing tracking signal RE_TRKBL1B has a delay with respect to the clock signal CKP and also has characteristics with respect to the tracking cell 331 and the tracking word line tWL1 .

[0088] The global precharge signal RE is generated by the precharge global control unit 411 in response to the sensing tracking signal RE_TRKBL1B and the read enable delay signal REND. Figure 7As shown, the global precharge signal RE is generated in response to the rising edge of the sensing tracking signal RE_TRKBL1B, and also in response to the falling edge of the sensing tracking signal RE_TRKBL1B. The falling edge of the global precharge signal RE is also associated with the falling edge of the read enable delay signal REND, so that the global precharge signal RE lasts for a period of time before being pulled low by the falling edge of the sensing tracking signal RE_TRKBL1B.

[0089] In addition, the sensing tracking signal RE_TRKBL1B and the read enable delay signal REND are also related to the precharge signal PREB. The precharge signal PREB is generated by the read assist circuit 220 in response to the rising edge of the sensing tracking signal RE_TRKBL1B, and also in response to the falling edge of the read enable delay signal REND. In other words, in response to the leading edge of the sensing tracking signal RE_TRKBL1B, the leading edge of the precharge signal PREB is pulled to a logic high. It is known that the sensing tracking signal RE_TRKBL1B is a signal that tracks / copies (simulates) the word line WL and the bit line BL / complement bit line BLB coupled to the selected bit cell BC, as shown in reference Figure 4 discussed. Therefore, the precharge signal PREB is adapted to the bit cell BC in the memory device 400. In addition, by adjusting the length of the tracking word line tWL1, and / or the number of tracking cells 331, the leading edge of the precharge signal PREB can be pulled back to reduce the duration of the period T2. Therefore, the frequency of the precharge signal PREB can be increased, thereby correspondingly improving the read operation of the memory device 400. On the other hand, in response to the back-edge of the read enable delay signal REND, the trailing edge of the precharge signal PREB is pulled down to a logic low. The precharge signal PREB is pulled high at the beginning of the period T2 and remains high for a period of time before being pulled low. Therefore, the pulse width of the precharge signal PREB is long enough to ensure that the read operation is available. Therefore, since the bit cell BC is activated in response to the precharge signal PREB, Figure 2 The voltages of nodes DL_IN and DLB_IN in bit cell BC are shown to be accessible during period T2.

[0090] The sensing tracking signal TRKBL3B is generated by the delay chain circuit 412c. The read enable delay signal REND is generated by the latch circuit 350 according to the sensing tracking signal TRKBL3B and the read enable signal REN. Figure 6 and Figure 7 , when the sensing tracking signal TRKBL3B changes from logic high to logic low, the read enable signal REN is already at logic low, and the tracking delay signal TRKBL2 is changed from logic high to logic low. Figure 5The sensing enable global control unit 412 shown operates as a logic high. Thus, transistors T61, T62 and T66 are turned on, and transistors T64, T65 and T67 are turned off. In this way, the voltage on node N62 is still at a logic low due to the conduction of transistors T61 and T62, so the voltage on node N63 is still at a logic high due to the NOT operator 610, and the transistor T63 is turned off and the transistor T68 is turned on. Therefore, even if the read enable signal REN is pulled to a logic low, the read enable delay signal REND remains at a logic high for a period of time until the voltage on node N62 is pulled to a logic high by transistors T61 and T62. Therefore, compared with the read enable signal REN, the read enable delay signal REND has a delay time and is therefore later than the read enable signal REN. In addition, the trailing edge of the read enable delay signal REND is related to the sensing tracking signal TRKBL3B. In other words, the read enable delay signal REND is generated in response to the falling edge of the sensing tracking signal TRKBL3B.

[0091] In some embodiments, Figure 7 As shown, the read enable signal REN is generated in response to the falling edge of the clock signal CKP.

[0092] The sensing enable signal SAE is generated by the read assist circuit 220 in response to the rising edge of the clock signal CKP and also in response to the falling edge of the read enable delay signal REND. Figure 7 As shown, the leading edge of the sense enable signal SAE is later than the leading edge of the precharge signal PREB. This is due to the operation including tracking the word line tWL2 and the bit line tBL2, and the transmission of the delay chain circuit 412c. Therefore, since the sense amplifier circuit 230 is activated in response to the sense enable signal SAE, Figure 2 The voltage difference between nodes DL_IN and DLB_IN in bit cell BC shown can be used for reading and distinguishing.

[0093] The word line enable signal PGB is generated by the read assist circuit 220 and is a combination signal from the precharge signal PREB and the sense enable signal SAE. During the period T2, the rising edge of the word line enable signal PGB reflects the start of the sense amplifier circuit 230 being activated. In some embodiments, as Figure 7 As shown, in the period T2, the pulse width of the word line enable signal PGB is substantially equal to twenty percent of the pulse width of the precharge signal PREB.

[0094] Reference now Figure 8 . Figure 8 According to some embodiments of the present disclosure, Figure 4The memory device 400 shown corresponds to a flowchart of a method 800 of a memory device. Figure 4 The memory device 400 shown in FIG. Figure 8 The following description of method 800 in includes exemplary operations. However, Figure 8 The operations are not necessarily performed in the order shown. In other words, according to the spirit and scope of various embodiments of the present disclosure, operations may be appropriately added, replaced, changed in order, and / or eliminated.

[0095] In operation S810, a word line tracking signal is transmitted to a corresponding tracking circuit via a tracking word line. Figure 4 As shown, in order to generate the precharge signal PREB, the word line tracking signal RE_TRKWL is transmitted to the tracking circuit 321 through the tracking word line tWL1. In addition, in order to generate the sensing enable signal SAE, the word line tracking signal TRKWL is transmitted to the tracking circuit 322 through the tracking word line tWL2.

[0096] In operation S820, the tracking circuit generates a corresponding bit line tracking signal in response to the corresponding word line tracking signal. The bit line tracking signal is associated with a corresponding tracking unit arranged in a memory array of the memory device. For illustration, Figure 4 As shown, in order to generate the precharge signal PREB, the tracking circuit 321 generates a bit line tracking signal RE_TRKBL in response to the word line tracking signal RE_TRKWL. The bit line tracking signal RE_TRKBL is connected to the memory array CA1 ( Figure 3 In addition, in order to generate the sensing enable signal SAE, the tracking circuit 322 generates a bit line tracking signal TRKBL in response to the word line tracking signal TRKWL. The bit line tracking signal TRKBL is associated with the memory array CA2 ( Figure 3 The tracking unit 332 and the capacitor circuit 333 are associated with each other. With this configuration, the bit line tracking signal TRKBL is later than the bit line tracking signal RE_TRKBL, which is also referred to as Figure 4 discuss.

[0097] In operation S830, the sensing circuits generate respective sensing tracking signals in response to the corresponding bit line tracking signals. Figure 4 As shown, in order to generate the precharge signal PREB, the sensing circuit 341 generates the sensing tracking signal RE_TRKBL1B in response to the bit line tracking signal RE_TRKBL. In addition, in order to generate the sensing enable signal SAE, the sensing circuit 342 generates the sensing tracking signal TRKBL1B in response to the bit line tracking signal TRKBL.

[0098] In operation S840, the global control unit of the control circuit generates a global precharge signal and a global sense enable signal in response to the corresponding sense tracking signal and the read enable delay signal. Figure 4 and Figure 7 As shown, in order to generate the precharge signal PREB, the global control unit 211 of the control circuit 210 generates the global precharge signal RE in response to the sense tracking signal RE_TRKBL1B and the read enable delay signal REND. In addition, in order to generate the sense enable signal SAE, the global control unit 211 of the control circuit 210 generates the global sense enable signal WLP_SAE in response to the sense tracking signal TRKBL1B and the read enable delay signal REND. Specifically, the global precharge signal RE is generated by the precharge global control unit 411 in the global control unit 211 in response to the rising edge of the sense tracking signal RE_TRKBL1B and the falling edge of the read enable delay signal REND. The global sense enable signal WLP_SAE is generated by the sense enable global control unit 412 in the global control unit 211 in response to the rising edge of the sense tracking signal TRKBL1B and the falling edge of the read enable delay signal REND.

[0099] In operation S850, the local control unit of the control circuit generates a local precharge signal and a local sense enable signal in response to the global precharge signal, the global sense enable signal, and the bank select signal. Figure 2 and Figure 4 As shown, in order to generate the precharge signal PREB, the precharge local control unit 212 of the control circuit 210 generates the local precharge signal GPREB in response to the global precharge signal RE and the bank selection signal BSD. In addition, in order to generate the sense enable signal SAE, the sense enable local control unit 213 of the control circuit 210 generates the local sense enable signal GSAE in response to the global sense enable signal WLP_SAE and the bank selection signal BSD.

[0100] In operation S860, the read assist circuit generates a precharge signal and a sense enable signal in response to the local precharge signal, the local sense enable signal, and the bit line enable signal and transmits them to the selected bit cell and the sense amplifier circuit. Figure 2 and Figure 4 As shown, the read assist circuit 220 generates a precharge signal PREB in response to the local precharge signal GPREB and the bit line enable signal BLEQB and transmits it to the bit cell BC. In addition, the read assist circuit 220 generates a sense enable signal SAE in response to the local sense enable signal GSAE and the bit line enable signal BLEQB and transmits it to the sense amplifier circuit 230. Therefore, the selected bit cell BC can be read.

[0101] Reference now Fig. 9 . Fig. 9 is a block diagram of an electronic design automation (EDA) system 900 for designing integrated circuit layout designs according to some embodiments of the present disclosure. The EDA system 900 is configured to implement Figure 8 In combination with Figures 2 to 6 One or more operations of method 800 are further explained. In some embodiments, EDA system 900 includes an APR system.

[0102] In some embodiments, EDA system 900 is a general purpose computing device that includes a hardware processor 920 and a non-transitory computer readable storage medium 960. Storage medium 960 is encoded with (i.e., stores) computer program code (instructions) 961, i.e., a set of executable instructions, among other items. Execution of instructions 961 by hardware processor 920 (at least in part) represents an EDA tool that implements, for example, part or all of method 800.

[0103] The processor 920 is electrically coupled to a computer-readable storage medium 960 via a bus 950. The processor 920 is also electrically coupled to an I / O interface 910 and a manufacturing tool 970 via the bus 950. The network interface 930 is also electrically connected to the processor 920 via the bus 950. The network interface 930 is connected to a network 940 so that the processor 920 and the computer-readable storage medium 960 can be connected to external elements via the network 940. The processor 920 is configured to execute a computer program code 961 encoded in the computer-readable storage medium 960 so that the EDA system 900 can be used to perform part or all of the process and / or method. In one or more embodiments, the processor 920 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0104] In one or more embodiments, the computer-readable storage medium 960 is an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or device). For example, the computer-readable storage medium 960 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, a random access memory (RAM), a read-only memory (ROM), a rigid disk, and / or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 960 includes a compact disk read-only memory (CD-ROM), a compact disk that reads / writes (CD-R / W), and / or a digital video disk (DVD).

[0105] In one or more embodiments, the storage medium 960 stores computer program code 961 configured to enable the EDA system 900 (where such execution (at least in part) represents an EDA tool) to perform part or all of the processes and / or methods. In one or more embodiments, the storage medium 960 also stores information that facilitates the execution of part or all of the processes and / or methods. In one or more embodiments, the storage medium 960 stores a library 962 of standard cells, including such standard cells disclosed herein, such as those described above with respect to Figure 2 , Figure 4 and Figure 6 The cells of transistors T1-T19 and T61-T68 are discussed.

[0106] The EDA system 900 includes an I / O interface 910. The I / O interface 910 is coupled to external circuits. In one or more embodiments, the I / O interface 910 includes a keyboard, a keypad, a mouse, a trackball, a touchpad, a touch screen, and / or cursor direction keys for transmitting information and commands to the processor 920.

[0107] The EDA system 900 also includes a network interface 930 coupled to the processor 920. The network interface 930 allows the EDA system 900 to communicate with a network 940 to which one or more other computer systems are connected. The network interface 930 includes: a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more systems 900.

[0108] The EDA system 900 also includes a fabrication tool 970 coupled to the processor 920. The fabrication tool 970 is configured to fabricate an integrated circuit based on the design file processed by the processor 920 and / or the IC layout design as described above, including, for example Figure 1 A memory device 100 is shown.

[0109] The EDA system 900 is configured to receive information through the I / O interface 910. The information received through the I / O interface 910 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 920. The information is transmitted to the processor 920 via the bus 950. The EDA system 900 is configured to receive information related to the UI through the I / O interface 910. The information is stored in the computer readable medium 960 as a user interface (UI) 963.

[0110] In some embodiments, part or all of the processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in for a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the EDA system 900. In some embodiments, the system 900 is implemented using a software application such as that available from Cadence Design Systems, Inc. A tool such as , or another suitable layout generation tool, is used to generate a layout diagram including standard cells.

[0111] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, such as one or more of an optical disk (e.g., DVD), a magnetic disk (e.g., a hard disk), a semiconductor memory (e.g., ROM, RAM), a memory card, etc.

[0112] Fig.10 1 is a block diagram of an IC manufacturing system 1000 and an IC manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, the IC manufacturing system 1000 is used to manufacture at least one of the following items: (A) one or more semiconductor masks, or (B) at least one component in a layer of a semiconductor integrated circuit.

[0113] exist Fig.10In the present invention, the IC manufacturing system 1000 includes entities that interact with each other in the design, development, and manufacturing cycles and / or services related to manufacturing IC devices 1040, such as a design room 1010, a mask room 1020, and an IC manufacturer / fabricator ("fab") 1030. The entities in the IC manufacturing system 1000 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 1010, the mask room 1020, and the IC manufacturer / fabricator 1030 are owned by a single larger company. In some embodiments, two or more of the design room 1010, the mask room 1020, and the IC manufacturer / fabricator 1030 coexist in a public facility and use public resources.

[0114] The design office (or design team) 1010 generates an IC design layout 1011. The IC design layout 1011 includes a schematic diagram for an IC device 1040 (e.g., Figure 2 , Figure 4 , Figure 5 , and / or Figure 6 Various geometric patterns of memory device designs discussed, such as Figure 3 The IC layout design depicted in . The geometric pattern corresponds to the pattern of the metal, oxide, or semiconductor layer of the various components that make up the IC device 1040 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout diagram 1011 includes various IC features (such as active areas, gate electrodes, source and drain, conductive segments or through holes for interlayer interconnection) to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers arranged on the semiconductor substrate. The design room 1010 implements an appropriate design process to form the IC design layout diagram 1011. The design process includes one or more of logic design, physical design, or layout and routing. The IC design layout diagram 1011 is presented in one or more data files with geometric pattern information. For example, the IC design layout diagram 1011 can be expressed in a GDSII file format or a DFII file format.

[0115] The mask chamber 1020 includes data preparation 1021 and mask manufacturing 1022. The mask chamber 1020 uses the IC design layout drawing 1011 to manufacture one or more masks 1023, which are used to manufacture various layers of the IC device 1040 based on the IC design layout drawing 1011. The mask chamber 1020 performs mask data preparation 1021, wherein the IC design layout drawing 1011 is converted into a representative data file ("RDF"). The mask data preparation 1021 provides the RDF to the mask manufacturing 1022. The mask manufacturing 1022 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 1023 or a semiconductor wafer 1033. The mask data preparation 1021 processes the IC design layout drawing 1011 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturer / fabricator 1030. In Fig.10 , data preparation 1021 and mask manufacturing 1022 are shown as separate elements. In some embodiments, data preparation 1021 and mask manufacturing 1022 may be collectively referred to as mask data preparation.

[0116] In some embodiments, data preparation 1021 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 1011. In some embodiments, data preparation 1021 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, etc. or combinations thereof. In some embodiments, an inverse lithography technique (ILT) is also used, which treats OPC as an inverse imaging problem.

[0117] In some embodiments, data preparation 1021 includes a mask rule checker (MRC) that checks an IC design layout 1011 that has been processed in OPC using a set of mask creation rules that contain certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1011 to compensate for the constraints during mask fabrication 1022, which can undo some of the modifications performed by the OPC to satisfy the mask creation rules.

[0118] In some embodiments, data preparation 1021 includes a lithography process check (LPC), which simulates the process to be implemented by the IC manufacturer / fabricator 1030 to manufacture the IC device 1040. The LPC simulates the process based on the IC design layout 1011 to create a simulated manufacturing device, such as the IC device 1040. The process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or a combination thereof. In some embodiments, after the simulated manufacturing device is created by LPC, if the simulated device is not close enough in shape to meet the design rules, the OPC and / or MRC are repeated to further refine the IC design layout 1011.

[0119] It should be understood that the above description of data preparation 1021 has been simplified for clarity. In some embodiments, data preparation 1021 includes additional features such as logic operations (LOPs) to modify IC design layout 1011 according to manufacturing rules. In addition, the processes applied to IC design layout 1011 during data preparation 1021 can be performed in a variety of different orders.

[0120] After data preparation 1021 and during mask manufacturing 1022, a mask 1023 or a set of masks 1023 are manufactured based on the modified IC design layout 1011. In some embodiments, mask manufacturing 1022 includes performing one or more photolithography exposures based on the IC design layout 1011. In some embodiments, based on the modified IC design layout 1011, a pattern is formed on a mask (photomask or intermediate mask) 1023 using an electron beam (e-beam) or a plurality of electron beams. The mask 1023 can be formed with various techniques. In some embodiments, the mask 1023 is formed using a binary technique. In some embodiments, the mask pattern includes an opaque region and a transparent region. A radiation beam (e.g., an ultraviolet (UV) beam) for exposing an image sensitive material layer (e.g., a photoresist) that has been coated on a wafer is blocked by the opaque region and transmitted through the transparent region. In one example, a binary mask version of mask 1023 includes a transparent substrate (e.g., fused quartz), and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 1023 is formed using a phase shift technique. In a phase shift mask (PSM) version of mask 1023, each feature in a pattern formed on the phase shift mask is configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The (one or more) masks generated by mask manufacturing 1022 are used in various processes. For example, such (one or more) masks are used in ion implantation processes to form various doped regions in semiconductor wafer 1033, in etching processes to form various etching regions in semiconductor wafer 1033, and / or in other suitable processes.

[0121] IC manufacturer / fabricator 1030 includes wafer fabrication 1032. IC manufacturer / fabricator 1030 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC manufacturer / fabricator 1030 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end-of-line, FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end-of-line, BEOL) manufacturing) for interconnecting and packaging IC products, and a third manufacturing facility may provide other services for the foundry enterprise.

[0122] IC manufacturer / fabricator 1030 uses (one or more) masks 1023 manufactured by mask chamber 1020 to manufacture IC device 1040. Therefore, IC manufacturer / fabricator 1030 at least indirectly uses IC design layout 1011 to manufacture IC device 1040. In some embodiments, semiconductor wafer 1033 is manufactured by IC manufacturer / fabricator 1030 using (one or more) masks 1023 to form IC device 1040. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based at least indirectly on IC design layout 1011. Semiconductor wafer 1033 includes a silicon substrate or other suitable substrate with a material layer formed thereon. Semiconductor wafer 1033 also includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0123] In some embodiments, a device is disclosed. The device includes a first tracking control line, a first tracking circuit, a first sensing circuit, and a precharge circuit. The first tracking control line is configured to transmit a first tracking control signal associated with a clock pulse signal. The first tracking circuit is configured to generate a first tracking signal associated with a plurality of first tracking cells in a memory array in response to the first tracking control signal. The first sensing circuit is configured to receive the first tracking signal and is configured to generate a first sensing tracking signal in response to the first tracking signal. The precharge circuit is coupled between the first sensing circuit and the memory array and is configured to generate a precharge signal in response to a rising edge of the first sensing tracking signal and a falling edge of a read enable delay signal, the precharge signal being used to precharge a data line associated with at least one memory cell in the memory array.

[0124] In some embodiments, the precharge circuit includes a first NAND gate, a first inverter, a second NAND gate, a second inverter, and a third inverter. The first NAND gate includes an input configured to receive a first sensing tracking signal and a read enable delay signal. The first inverter includes an input coupled to an output of the first NAND gate. The second NAND gate includes an input coupled to an output of the first inverter. The second inverter includes an input coupled to an output of the second NAND gate. The third inverter includes an input coupled to an output of the second inverter, and an output configured to output a precharge signal.

[0125] In some embodiments, the first sensing circuit includes a first transistor of a first conductivity type, a second transistor of a second conductivity type, a third transistor of the second conductivity type, and a fourth transistor of the second conductivity type. The gate terminals of the first transistor, the second transistor, and the third transistor are coupled together to receive a first tracking signal, and the first terminal of the first transistor is coupled to a first reference node. The second terminal of the first transistor, the first terminal of the second transistor, and the gate terminal of the fourth transistor are coupled together to one of the inputs of the first NAND gate. The second terminal of the second transistor is coupled to the first terminal of the third transistor and the first terminal of the fourth transistor, the second terminal of the third transistor is coupled to the second reference node, and the second terminal of the fourth transistor is coupled to the first reference node.

[0126] In some embodiments, the device further includes a sense enable circuit and a second sense circuit. The sense enable circuit is configured relative to the precharge circuit and is configured to generate a sense enable signal for enabling the sense amplifier circuit in response to the second sense tracking signal and the read enable delay signal. The second sense circuit is configured to generate a second sense tracking signal associated with a plurality of second tracking cells in the memory array.

[0127] In some embodiments, the sense enable circuit includes a delay chain circuit, a NAND gate, and an inverter. The delay chain circuit is configured to delay the second sense tracking signal to generate a third sense tracking signal. The NAND gate includes an input configured to receive a read enable delay signal. The inverter includes an input coupled to an output of the NAND gate, and an output configured to output a sense enable signal.

[0128] In some embodiments, the device further includes a latch circuit configured to latch the read enable signal in response to the delay and inversion of the second sensing tracking signal and to generate a read enable delay signal.

[0129] In some embodiments, the device further includes a second tracking control line, a second tracking circuit, a tracking data line, a second sensing circuit, and a capacitive circuit. The second tracking control line is configured to transmit a second tracking control signal associated with the clock pulse signal. The second tracking circuit is configured to generate a second tracking signal associated with a plurality of second tracking cells in the memory array in response to the second tracking control signal. The tracking data line is configured to transmit a second tracking signal. The second sensing circuit is configured to receive the second tracking signal and is configured to generate a second sensing tracking signal in response to the second tracking signal. The capacitive circuit is coupled to the tracking data line and the second tracking circuit.

[0130] In some embodiments, a length of the first tracking control line is less than a length of the second tracking control line.

[0131] In some embodiments, a device is also disclosed. The device includes a plurality of first tracking units in a memory array, a first sensing circuit, a plurality of second tracking units in the memory array, a second sensing circuit, a latch circuit, and a control circuit. The plurality of first tracking units in the memory array are coupled to the output of the first tracking circuit. The first sensing circuit includes an input coupled to the output of the first tracking circuit and is configured to generate a first sensing tracking signal. The plurality of second tracking units in the memory array are coupled to the output of the second tracking circuit. The second sensing circuit includes an input coupled to the output of the second tracking circuit and is configured to generate a second sensing tracking signal. The latch circuit is configured to latch a read enable signal and is configured to generate a read enable delay signal associated with the read enable signal. The control circuit is configured to generate a sensing enable signal for enabling a sense amplifier circuit in response to the second sensing tracking signal and the read enable delay signal.

[0132] In some embodiments, the control circuit includes a first NAND gate, a first inverter, a second NAND gate, a second inverter, and a third inverter. The first NAND gate includes an input coupled to the output of the first sensing circuit and the output of the latch circuit, and is configured to receive a first sensing tracking signal and a read enable delay signal. The first inverter includes an input coupled to the output of the first NAND gate. The second NAND gate includes an input coupled to the output of the first inverter. The second inverter includes an input coupled to the output of the second NAND gate. The third inverter includes an input coupled to the output of the second inverter, and an output configured to output a precharge signal for precharging a data line associated with at least one memory cell in the memory array.

[0133] In some embodiments, the control circuit further includes a delay chain circuit, a third NAND gate, a fourth inverter, a fourth NAND gate, and a fifth inverter. The delay chain circuit includes an input coupled to the output of the second sensing circuit, and is configured to delay the second sensing tracking signal to generate a third sensing tracking signal. The third NAND gate includes an input coupled to the output of the delay chain circuit and the output of the latch circuit, and is configured to receive the third sensing tracking signal and the read enable delay signal. The fourth inverter includes an input coupled to the output of the third NAND gate. The fourth NAND gate includes an input coupled to the output of the fourth inverter. The fifth inverter includes an input coupled to the output of the fourth NAND gate, and an output configured to output a sensing enable signal.

[0134] In some embodiments, the latch circuit includes an inverter, a first transistor of a first conductivity type and a second transistor of a second conductivity type, a third transistor of the first conductivity type, a fourth transistor of the second conductivity type, a fifth transistor of the first conductivity type, a sixth transistor of the first conductivity type, a seventh transistor of the second conductivity type, and an eighth transistor of the second conductivity type. The inverter is configured to output a read enable delay signal. The control terminals of the first transistor and the second transistor are configured to receive the read enable signal, and the first terminals of the first transistor and the second transistor are coupled together to the input of the inverter. The third transistor of the first conductivity type is coupled in series with the first transistor. The control terminal of the third transistor is configured to receive a third tracking signal derived from the second sensing tracking signal. The fourth transistor of the second conductivity type is coupled in series with the second transistor. The control terminal of the fourth transistor is configured to receive a fourth tracking signal derived from the third tracking signal. The control terminal of the fifth transistor is configured to receive the fourth tracking signal. The sixth transistor of the first conductivity type is coupled in series with the fifth transistor and in parallel with the third transistor. The control terminal of the sixth transistor is coupled to the output of the inverter. The control terminal of the seventh transistor is configured to receive the third tracking signal, and the first terminals of the fifth transistor and the seventh transistor are coupled together to the input of the inverter. An eighth transistor of the second conductivity type is coupled in series with the seventh transistor and in parallel with the fourth transistor. A control terminal of the eighth transistor is coupled to the output of the inverter.

[0135] In some embodiments, the device further includes a first tracking control line and a second tracking control line. The first tracking control line is coupled to the first sensing circuit through the first tracking circuit and is configured to transmit a first tracking control signal associated with the clock pulse signal to the first tracking circuit. The second tracking control line is coupled to the second sensing circuit through the second tracking circuit and is configured to transmit a second tracking control signal associated with the clock pulse signal to the second sensing circuit. The length of the first tracking control line is less than the length of the second tracking control line.

[0136] In some embodiments, the number of the plurality of first tracking units is greater than the number of the plurality of second tracking units.

[0137] In some embodiments, the device further comprises a plurality of capacitive elements, wherein the plurality of capacitive elements are coupled to the tracking data lines and the plurality of second tracking units.

[0138] In some embodiments, the control circuit is configured to generate the precharge signal in response to a rising edge of the first sense tracking signal and a falling edge of the read enable delay signal. The control circuit is configured to generate the sense enable signal in response to a falling edge of the read enable delay signal.

[0139] In some embodiments, a method is also disclosed. The method includes the following operations. A precharge signal is generated in response to a rising edge of a first sensing tracking signal generated by a first sensing circuit and in response to a falling edge of a read enable delay signal, the first sensing circuit being configured to sense a first tracking signal associated with a plurality of first tracking cells in a memory array, the precharge signal being used to precharge a data line associated with at least one memory cell in the memory array. A sensing enable signal for enabling a sensing amplifier circuit is generated in response to a second sensing tracking signal generated by a second sensing circuit and in response to the read enable delay signal, the second sensing circuit being configured to sense a second tracking signal associated with a plurality of second tracking cells in the memory array.

[0140] In some embodiments, the operation of generating the precharge signal includes the following operations: performing a NAND operation of the first sensing tracking signal and the read enable delay signal to generate a NAND output signal; performing an inversion operation of the NAND output signal to generate the precharge signal.

[0141] In some embodiments, the method further comprises the following operation: generating a read enable delay signal according to the latched read enable signal and the delayed second sensing tracking signal.

[0142] In some embodiments, the method further includes the following operations. A first tracking control signal associated with the clock pulse signal is transmitted through a first tracking control line to generate a first tracking signal associated with a plurality of first tracking units. A second tracking control signal associated with the clock pulse signal is transmitted through a second tracking control line to generate a second tracking signal associated with a plurality of second tracking units. The length of the first tracking control line is less than the length of the second tracking control line. The number of the plurality of first tracking units is greater than the number of the plurality of second tracking units.

[0143] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0144] Example 1 is a semiconductor device comprising: a first tracking control line configured to transmit a first tracking control signal associated with a clock pulse signal; a first tracking circuit configured to generate a first tracking signal associated with a plurality of first tracking units in a memory array in response to the first tracking control signal; a first sensing circuit configured to receive the first tracking signal and to generate a first sensing tracking signal in response to the first tracking signal; and a precharge circuit coupled between the first sensing circuit and the memory array and configured to generate a precharge signal in response to a rising edge of the first sensing tracking signal and a falling edge of a read enable delay signal, the precharge signal being used to precharge a data line associated with at least one memory cell in the memory array.

[0145] Example 2 is the device described in Example 1, wherein the precharge circuit includes: a first NAND gate including an input configured to receive the first sensing tracking signal and the read enable delay signal; a first inverter including an input coupled to the output of the first NAND gate; a second NAND gate including an input coupled to the output of the first inverter; a second inverter including an input coupled to the output of the second NAND gate; and a third inverter including an input coupled to the output of the second inverter and an output configured to output the precharge signal.

[0146] Example 3 is the device described in Example 2, wherein the first sensing circuit includes: a first transistor of a first conductivity type; a second transistor of a second conductivity type; a third transistor of the second conductivity type; and a fourth transistor of the second conductivity type, wherein the gate terminals of the first transistor, the second transistor, and the third transistor are coupled together to receive the first tracking signal, the first terminal of the first transistor is coupled to a first reference node, the second terminal of the first transistor, the first terminal of the second transistor, and the gate terminal of the fourth transistor are coupled together to one of the inputs of the first NAND gate, and the second terminal of the second transistor is coupled to the first terminal of the third transistor and the first terminal of the fourth transistor, the second terminal of the third transistor is coupled to a second reference node, and the second terminal of the fourth transistor is coupled to the first reference node.

[0147] Example 4 is the device described in Example 1, further comprising: a sensing enable circuit, configured relative to the precharge circuit, and configured to generate a sensing enable signal for enabling a sensing amplifier circuit in response to a second sensing tracking signal and the read enable delay signal; and a second sensing circuit, configured to generate the second sensing tracking signal associated with a plurality of second tracking cells in the memory array.

[0148] Example 5 is the device described in Example 4, wherein the sense enable circuit includes: a delay chain circuit configured to delay the second sense tracking signal to generate a third sense tracking signal; a NAND gate including an input configured to receive the read enable delay signal; and an inverter including an input coupled to the output of the NAND gate, and an output configured to output the sense enable signal.

[0149] Example 6 is the device described in Example 4, further comprising: a latch circuit configured to latch a read enable signal in response to a delay and an inversion of the second sensing tracking signal, and configured to generate the read enable delay signal.

[0150] Example 7 is the device described in Example 1, further including: a second tracking control line, configured to transmit a second tracking control signal associated with the clock pulse signal; a second tracking circuit, configured to generate a second tracking signal associated with multiple second tracking units in the memory array in response to the second tracking control signal; a tracking data line, configured to transmit the second tracking signal; a second sensing circuit, configured to receive the second tracking signal and configured to generate a second sensing tracking signal in response to the second tracking signal; and a capacitive circuit, coupled to the tracking data line and the second tracking circuit.

[0151] Example 8 is the device of Example 7, wherein a length of the first tracking control line is less than a length of the second tracking control line.

[0152] Example 9 is a semiconductor device comprising: a plurality of first tracking cells in a memory array, coupled to an output of a first tracking circuit; a first sensing circuit, comprising an input coupled to the output of the first tracking circuit, and configured to generate a first sensing tracking signal; a plurality of second tracking cells in the memory array, coupled to the output of the second tracking circuit; a second sensing circuit, comprising an input coupled to the output of the second tracking circuit, and configured to generate a second sensing tracking signal; a latch circuit, configured to latch a read enable signal, and configured to generate a read enable delay signal associated with the read enable signal; and a control circuit, configured to generate a sensing enable signal for enabling a sensing amplifier circuit in response to the second sensing tracking signal and the read enable delay signal.

[0153] Example 10 is the device described in Example 9, wherein the control circuit includes: a first NAND gate, including an input coupled to the output of the first sensing circuit and the output of the latch circuit, and configured to receive the first sensing tracking signal and the read enable delay signal; a first inverter, including an input coupled to the output of the first NAND gate; a second NAND gate, including an input coupled to the output of the first inverter; a second inverter, including an input coupled to the output of the second NAND gate; a third inverter, including an input coupled to the output of the second inverter, and an output configured to output a precharge signal, the precharge signal being used to precharge a data line associated with at least one memory cell in the memory array.

[0154] Example 11 is the device described in Example 10, wherein the control circuit further includes: a delay chain circuit, including an input coupled to the output of the second sensing circuit, and configured to delay the second sensing tracking signal to generate a third sensing tracking signal; a third NAND gate, including an input coupled to the output of the delay chain circuit and the output of the latch circuit, and configured to receive the third sensing tracking signal and the read enable delay signal; a fourth inverter, including an input coupled to the output of the third NAND gate; a fourth NAND gate, including an input coupled to the output of the fourth inverter; and a fifth inverter, including an input coupled to the output of the fourth NAND gate, and an output configured to output the sensing enable signal.

[0155] Example 12 is the device described in Example 9, wherein the latch circuit includes: an inverter configured to output the read enable delay signal; a first transistor of a first conductivity type and a second transistor of a second conductivity type, wherein the control terminals of the first transistor and the second transistor are configured to receive the read enable signal, and the first terminals of the first transistor and the second transistor are coupled together to the input of the inverter; a third transistor of the first conductivity type coupled in series with the first transistor, wherein the control terminal of the third transistor is configured to receive a third tracking signal derived from the second sensing tracking signal; and a fourth transistor of the second conductivity type coupled in series with the second transistor, wherein the control terminal of the fourth transistor is configured to receive a third tracking signal derived from the third sensing tracking signal. a fourth tracking signal derived; a fifth transistor of the first conductivity type, wherein a control terminal of the fifth transistor is configured to receive the fourth tracking signal; a sixth transistor of the first conductivity type, coupled in series with the fifth transistor and in parallel with the third transistor, wherein a control terminal of the sixth transistor is coupled to the output of the inverter; a seventh transistor of the second conductivity type, wherein a control terminal of the seventh transistor is configured to receive the third tracking signal, and first terminals of the fifth transistor and the seventh transistor are coupled together to the input of the inverter; and an eighth transistor of the second conductivity type, coupled in series with the seventh transistor and in parallel with the fourth transistor, wherein a control terminal of the eighth transistor is coupled to the output of the inverter.

[0156] Example 13 is the device described in Example 9, further including: a first tracking control line, coupled to the first sensing circuit through the first tracking circuit, and configured to transmit a first tracking control signal associated with a clock pulse signal to the first tracking circuit; and a second tracking control line, coupled to the second sensing circuit through the second tracking circuit, and configured to transmit a second tracking control signal associated with the clock pulse signal to the second sensing circuit, wherein the length of the first tracking control line is less than the length of the second tracking control line.

[0157] Example 14 is the device of Example 9, wherein the number of the plurality of first tracking units is greater than the number of the plurality of second tracking units.

[0158] Example 15 is the device of Example 9, further comprising: a plurality of capacitive elements coupled to the tracking data lines and the plurality of second tracking units.

[0159] Example 16 is a device described in Example 9, wherein the control circuit is configured to generate a precharge signal in response to a rising edge of the first sensing tracking signal and a falling edge of the read enable delay signal, and the control circuit is configured to generate the sensing enable signal in response to a falling edge of the read enable delay signal.

[0160] Example 17 is a method for forming a semiconductor device, comprising: generating a precharge signal in response to a rising edge of a first sensing tracking signal generated by a first sensing circuit and in response to a falling edge of a read enable delay signal, the first sensing circuit being configured to sense a first tracking signal associated with a plurality of first tracking units in a memory array, the precharge signal being used to precharge a data line associated with at least one memory cell in the memory array; and generating a sensing enable signal for enabling a sensing amplifier circuit in response to a second sensing tracking signal generated by a second sensing circuit and in response to the read enable delay signal, the second sensing circuit being configured to sense a second tracking signal associated with a plurality of second tracking units in the memory array.

[0161] Example 18 is the method described in Example 17, wherein generating the pre-charge signal includes: performing a NAND operation of the first sensing tracking signal and the read enable delay signal to generate a NAND output signal; and performing an inversion operation of the NAND output signal to generate the pre-charge signal.

[0162] Example 19 is the method of Example 17, further comprising generating the read enable delay signal based on the latched read enable signal and the delayed second sensing tracking signal.

[0163] Example 20 is the method described in Example 17, further comprising: transmitting a first tracking control signal associated with a clock pulse signal through a first tracking control line to generate the first tracking signal associated with the multiple first tracking units; and transmitting a second tracking control signal associated with the clock pulse signal through a second tracking control line to generate the second tracking signal associated with the multiple second tracking units, wherein the length of the first tracking control line is less than the length of the second tracking control line, and the number of the multiple first tracking units is greater than the number of the multiple second tracking units.

Claims

1. A semiconductor device, comprising: A first tracking control line configured to transmit a first tracking control signal associated with the clock pulse signal; a first tracking circuit configured to generate a first tracking signal associated with a plurality of first tracking cells in a memory array in response to the first tracking control signal; a first sensing circuit configured to receive the first tracking signal and configured to generate a first sensing tracking signal in response to the first tracking signal; as well as A precharge circuit is coupled between the first sensing circuit and the memory array and is configured to generate a precharge signal in response to a rising edge of the first sensing tracking signal and a falling edge of a read enable delay signal, wherein the precharge signal is used to precharge a data line associated with at least one memory cell in the memory array.

2. The device according to claim 1, wherein The pre-charging circuit comprises: a first NAND gate including an input configured to receive the first sense tracking signal and the read enable delay signal; a first inverter including an input coupled to an output of the first NAND gate; a second NAND gate including an input coupled to the output of the first inverter; a second inverter including an input coupled to the output of the second NAND gate; and A third inverter includes an input coupled to the output of the second inverter, and an output configured to output the precharge signal.

3. The device according to claim 2, wherein The first sensing circuit comprises: a first transistor of a first conductivity type; a second transistor of a second conductivity type; a third transistor of the second conductivity type; and the fourth transistor of the second conductivity type, wherein gate terminals of the first transistor, the second transistor, and the third transistor are coupled together to receive the first tracking signal, a first terminal of the first transistor is coupled to a first reference node, The second terminal of the first transistor, the first terminal of the second transistor, and the gate terminal of the fourth transistor are coupled together to one of the inputs of the first NAND gate, and A second terminal of the second transistor is coupled to a first terminal of the third transistor and a first terminal of the fourth transistor, a second terminal of the third transistor is coupled to a second reference node, and a second terminal of the fourth transistor is coupled to the first reference node.

4. The device according to claim 1, further comprising: a sense enable circuit configured relative to the precharge circuit and configured to generate a sense enable signal for enabling a sense amplifier circuit in response to a second sense tracking signal and the read enable delay signal; as well as The second sensing circuit is configured to generate the second sensing tracking signal associated with a plurality of second tracking cells in the memory array.

5. The device according to claim 4, wherein The sensing enabling circuit comprises: a delay chain circuit configured to delay the second sensing tracking signal to generate a third sensing tracking signal; a NAND gate including an input configured to receive the read enable delay signal; and An inverter includes an input coupled to the output of the NAND gate, and an output configured to output the sense enable signal.

6. The device according to claim 4, further comprising: A latch circuit is configured to latch a read enable signal in response to the delay and inversion of the second sensing tracking signal and is configured to generate the read enable delayed signal.

7. The device according to claim 1, further comprising: A second tracking control line configured to transmit a second tracking control signal associated with the clock pulse signal; a second tracking circuit configured to generate a second tracking signal associated with a plurality of second tracking cells in the memory array in response to the second tracking control signal; a tracking data line configured to transmit the second tracking signal; a second sensing circuit configured to receive the second tracking signal and configured to generate a second sensing tracking signal in response to the second tracking signal; as well as A capacitive circuit is coupled to the tracking data line and the second tracking circuit.

8. The device according to claim 7, wherein The length of the first tracking control line is shorter than the length of the second tracking control line.

9. A semiconductor device comprising: a plurality of first tracking cells in the memory array coupled to the output of the first tracking circuit; a first sensing circuit comprising an input coupled to the output of the first tracking circuit and configured to generate a first sensing tracking signal; a plurality of second tracking cells in the memory array coupled to an output of a second tracking circuit; a second sensing circuit including an input coupled to the output of the second tracking circuit and configured to generate a second sensing tracking signal; a latch circuit configured to latch a read enable signal and configured to generate a read enable delay signal associated with the read enable signal; as well as a control circuit configured to generate a sense enable signal for enabling a sense amplifier circuit in response to the second sense tracking signal and the read enable delay signal, the control circuit comprising: A precharge circuit is coupled between the first sensing circuit and the memory array and is configured to generate a precharge signal in response to a rising edge of the first sensing tracking signal and a falling edge of the read enable delay signal, wherein the precharge signal is used to precharge a data line associated with at least one memory cell in the memory array.

10. The device according to claim 9, wherein The control circuit comprises: a first NAND gate including an input coupled to an output of the first sensing circuit and an output of the latch circuit and configured to receive the first sensing tracking signal and the read enable delay signal; a first inverter including an input coupled to an output of the first NAND gate; a second NAND gate including an input coupled to the output of the first inverter; a second inverter including an input coupled to the output of the second NAND gate; A third inverter includes an input coupled to the output of the second inverter, and an output configured to output the precharge signal.

11. The device according to claim 10, wherein The control circuit further comprises: a delay chain circuit including an input coupled to an output of the second sensing circuit and configured to delay the second sensing tracking signal to generate a third sensing tracking signal; a third NAND gate including an input coupled to the output of the delay chain circuit and the output of the latch circuit and configured to receive the third sense tracking signal and the read enable delay signal; a fourth inverter comprising an input coupled to the output of the third NAND gate; a fourth NAND gate comprising an input coupled to the output of the fourth inverter; and A fifth inverter includes an input coupled to the output of the fourth NAND gate, and an output configured to output the sense enable signal.

12. The device according to claim 9, wherein The latch circuit comprises: an inverter configured to output the read enable delay signal; a first transistor of a first conductivity type and a second transistor of a second conductivity type, wherein control terminals of the first transistor and the second transistor are configured to receive the read enable signal and first terminals of the first transistor and the second transistor are coupled together to an input of the inverter; a third transistor of the first conductivity type coupled in series with the first transistor, wherein a control terminal of the third transistor is configured to receive a third tracking signal derived from the second sensing tracking signal; a fourth transistor of the second conductivity type coupled in series with the second transistor, wherein a control terminal of the fourth transistor is configured to receive a fourth tracking signal derived from the third tracking signal; a fifth transistor of the first conductivity type, wherein a control terminal of the fifth transistor is configured to receive the fourth tracking signal; a sixth transistor of the first conductivity type coupled in series with the fifth transistor and in parallel with the third transistor, wherein a control terminal of the sixth transistor is coupled to an output of the inverter; a seventh transistor of the second conductivity type, wherein a control terminal of the seventh transistor is configured to receive the third tracking signal, and first terminals of the fifth transistor and the seventh transistor are coupled together to an input of the inverter; and An eighth transistor of the second conductivity type is coupled in series with the seventh transistor and in parallel with the fourth transistor, wherein a control terminal of the eighth transistor is coupled to the output of the inverter.

13. The device according to claim 9, further comprising: a first tracking control line coupled to the first sensing circuit through the first tracking circuit and configured to transmit a first tracking control signal associated with a clock pulse signal to the first tracking circuit; as well as a second tracking control line coupled to the second sensing circuit through the second tracking circuit and configured to transmit a second tracking control signal associated with the clock pulse signal to the second sensing circuit, Wherein, the length of the first tracking control line is smaller than the length of the second tracking control line.

14. The device according to claim 9, wherein The number of the plurality of first tracking units is greater than the number of the plurality of second tracking units.

15. The device according to claim 9, further comprising: A plurality of capacitive elements are coupled to the tracking data lines and the plurality of second tracking units.

16. The device according to claim 9, wherein The control circuit is configured to generate the sense enable signal in response to a falling edge of the read enable delay signal.

17. A method for operating a semiconductor device, comprising: generating a precharge signal in response to a rising edge of a first sense tracking signal generated by a first sense circuit configured to sense first tracking signals associated with a plurality of first tracking cells in a memory array and in response to a falling edge of a read enable delay signal, the precharge signal being used to precharge a data line associated with at least one memory cell in the memory array; as well as A sense enable signal for enabling a sense amplifier circuit is generated in response to a second sense tracking signal generated by a second sense circuit configured to sense second tracking signals associated with a plurality of second tracking cells in the memory array and in response to the read enable delay signal.

18. The method according to claim 17, wherein: Generating the precharge signal comprises: performing a NAND operation of the first sense tracking signal and the read enable delay signal to generate a NAND output signal; and An inversion operation of the NAND output signal is performed to generate the precharge signal.

19. The method according to claim 17, further comprising: The read enable delay signal is generated according to the latched read enable signal and the delayed second sensing tracking signal.

20. The method of claim 17, further comprising: transmitting a first tracking control signal associated with a clock pulse signal through a first tracking control line to generate the first tracking signals associated with the plurality of first tracking units; as well as transmitting a second tracking control signal associated with the clock pulse signal through a second tracking control line to generate the second tracking signals associated with the plurality of second tracking units, Wherein, the length of the first tracking control line is less than the length of the second tracking control line, and The number of the plurality of first tracking units is greater than the number of the plurality of second tracking units.

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