An antifuse memory reading circuit with controllable reading time

Abstract

The present invention discloses an anti-fuse memory reading circuit with controllable reading time, which relates to the field of anti-fuse memories. In the anti-fuse memory reading circuit, a reading time control circuit generates a control signal corresponding to the reading time, and a programmable read pulse generating circuit generates a reading pulse with a pulse width corresponding to the control signal based on a clock signal; a read amplifier circuit selects a pull-up current source corresponding to the reading time and a voltage on a bit line of an anti-fuse memory cell according to the reading pulse and the control signal, and reads data stored in the anti-fuse memory cell starting from the rising edge of the reading pulse and latching the data at the falling edge of the reading pulse; the anti-fuse memory reading circuit can generate a reading pulse with a corresponding pulse width and a pull-up current source of a corresponding size according to the required reading time, thereby realizing customized programming control of the reading time, having high flexibility and meeting the user's choice between actual reading speed and power consumption requirements.

Description

Technical Field

[0001] The present invention relates to the field of anti-fuse memory, in particular to an anti-fuse memory reading circuit with controllable reading time. Background Art

[0002] MTM (Metal-To-Metal) antifuse memory mainly includes an antifuse storage array composed of antifuses and programming tubes. MTM antifuse memory uses a breakdown medium between two layers of metal plates for programming to store data. It has natural radiation resistance, high reliability, and high integration, so it is widely used.

[0003] When the antifuse memory is in use, a reading circuit is required to read the data stored in the antifuse memory. However, existing antifuse memory reading circuits read data according to a fixed reading time, which is difficult to meet actual application requirements. Summary of the Invention

[0004] In response to the above problems and technical requirements, the inventors have proposed an anti-fuse memory reading circuit with controllable reading time. The technical solution of the present invention is as follows:

[0005] An anti-fuse memory reading circuit with controllable reading time includes an anti-fuse memory unit, the anti-fuse memory reading circuit includes a reading time control circuit, a programmable read pulse generating circuit, a read amplifier circuit and a read register;

[0006] The read time control circuit generates a control signal having K control bits corresponding to the read time and provides the control signal to the programmable read pulse generating circuit and the read amplifier circuit;

[0007] The programmable read pulse generating circuit generates a read pulse with a pulse width corresponding to the control signal based on the clock signal and outputs it to the read amplifier circuit;

[0008] The read amplifier circuit includes several pull-up current sources of different sizes. The read amplifier circuit selects the pull-up current source corresponding to the read time and pulls up the voltage on the bit line of the anti-fuse memory cell based on the read pulse and the control signal. The read amplifier circuit reads the data stored in the anti-fuse memory cell starting from the rising edge of the read pulse and latches the read data into the read register at the falling edge of the read pulse.

[0009] A further technical solution is that the shorter the reading time is, the shorter the pulse width of the corresponding reading pulse is and the larger the current value of the pull-up current source is.

[0010] Its further technical solution is that the reading time control circuit includes K parallel programming branches, each programming branch includes a pull-up device and a pull-down device in series, each programming branch is connected to the power supply VDD through the pull-up device and to the ground GND through the pull-down device, the common end of the pull-up device and the pull-down device in each programming branch is connected to a programming switch, and the other ends of the K programming switches are connected and connected to the programming voltage HV_PGM. The reading time control circuit obtains a programming signal and controls the on and off of the K programming switches according to the programming signal to program the corresponding programming branch. The common end of the pull-up device and the pull-down device in each programming branch is used to output a control bit of the control signal, and at most one control bit in the control signal is 1.

[0011] A further technical solution is that the pull-up device and the pull-down device of the read time control circuit are both implemented by antifuses. The voltage difference between the upper and lower metal plates of the pull-up antifuse is the voltage difference between the programming voltage HV_PGM and the power supply VDD, and the voltage difference between the upper and lower metal plates of the pull-down antifuse is the voltage difference between the programming voltage HV_PGM and the ground GND. K programming switches are controlled on and off according to programming signals to program the antifuses in the corresponding programming branches. The programming voltage HV_PGM is applied to both ends of the pull-up antifuse and the pull-down antifuse, respectively, to complete the programming of the pull-up antifuse or the pull-down antifuse.

[0012] When programming the pull-up antifuse, the voltage values ​​of the power supply VDD and the ground GND are adjusted so that the voltage difference between the upper and lower metal plates of the pull-up antifuse exceeds the breakdown voltage of the antifuse and the voltage difference between the upper and lower metal plates of the pull-down antifuse is less than the breakdown voltage of the antifuse, thereby completing the programming of the pull-up antifuse. When programming the pull-down antifuse, the voltage values ​​of the power supply VDD and the ground GND are adjusted so that the voltage difference between the upper and lower metal plates of the pull-down antifuse exceeds the breakdown voltage of the antifuse and the voltage difference between the upper and lower metal plates of the pull-up antifuse is less than the breakdown voltage of the antifuse, thereby completing the programming of the pull-down antifuse. The resistance value of the antifuse when not programmed is in the hundreds of megohms level.

[0013] A further technical solution is that the programmable read pulse generating circuit includes a delay circuit, K delay selection switches, and a logic AND gate. The clock signal CLK is input into the delay circuit. The delay circuit performs multi-stage delay on the clock signal CLK and respectively generates clock delay signals with different delay values ​​relative to the clock signal CLK at K different delay stages. Each clock delay signal is respectively connected to a delay selection switch. The other ends of the K delay selection switches are connected and connected to an input end of the logic AND gate. The other input end of the logic AND gate is connected to the clock signal CLK. The output end of the logic AND gate is connected to the read amplifier circuit to output the read pulse.

[0014] Among them, the K delay selection switches are respectively controlled by the K control bits of the control signal, and the delay selection switch is closed when the corresponding control bit is at a high level to output the corresponding clock delay signal to the logic AND gate. The greater the delay value of the clock delay signal relative to the clock signal CLK, the greater the pulse width of the read pulse.

[0015] A further technical solution is that the read amplifier circuit includes an NMOS type discharge tube MN0, a plurality of pull-up current sources of different sizes and a current source selection circuit;

[0016] The source of discharge tube MN0 is grounded, and its drain is connected to a read register via a buffer. The output of the programmable read pulse generating circuit is connected to the gate of discharge tube MN0 via an inverter. Several pull-up current sources of different sizes are connected to the drain of discharge tube MN0 via a gating network. The drain of discharge tube MN0 is also connected to the bit line of the anti-fuse storage unit.

[0017] The current source selection circuit controls the gating network according to the read pulse and the control signal to connect the pull-up current source corresponding to the read time to the drain of the discharge tube MN0.

[0018] A further technical solution is that the read amplifier circuit includes a reference current source and K additional current sources. The reference current source is connected to the source of the corresponding PMOS transistor. The drain of the PMOS transistor to which the reference current source is connected is connected to the drain of the discharge transistor MN0. The gate is connected to the gate of the discharge transistor MN0 and is connected to the output end of the inverter. The K additional current sources are connected to the drain of the discharge transistor MN0 through a gating network.

[0019] The current source selection circuit controls the gating network according to the read pulse and the control signal so that when the K additional current sources are not conductive to the drain of the discharge tube MN0, the reference current source forms a pull-up current source conductive to the drain of the discharge tube MN0;

[0020] The current source selection circuit controls the gating network according to the read pulse and the control signal so that when one of the additional current sources is connected to the drain of the discharge tube MN0, the reference current source and the one connected additional current source are superimposed to form a pull-up current source connected to the drain of the discharge tube MN0; the one reference current source and K additional current sources form a total of K+1 different pull-up current sources.

[0021] A further technical solution is that the gating network includes K gating PMOS transistors, and the current source selection circuit includes K logic NAND gates;

[0022] Each additional current source is connected to the source of a corresponding gated PMOS transistor, and the drain of each gated PMOS transistor is connected to the drain of the discharge tube MN0;

[0023] One input end of each logic NAND gate in the current source selection circuit is connected to the read time control circuit to obtain a control bit of the control signal, the other input end is connected to the programmable read pulse generation circuit to obtain a read pulse, and the output end is connected to the gate of a corresponding gate PMOS tube;

[0024] The K logic NAND gates in the current source selection circuit respectively correspond to the K control bits of the control signal, and thereby control the on and off of a corresponding gate PMOS tube.

[0025] Its further technical solution is that the read amplifier circuit reads the data stored in the anti-fuse memory cell starting from the rising edge of the read pulse. When the anti-fuse memory cell is read to be in an unprogrammed high-impedance state, the drain of the discharge tube MN0 is pulled up to a high level; when the anti-fuse memory cell is read to be in a programmed low-impedance state, the drain of the discharge tube MN0 remains at a low level, and the read data is sent to the read register.

[0026] A further technical solution is to design the reading register using triple-module redundancy technology.

[0027] The beneficial technical effects of the present invention are:

[0028] The present application discloses an anti-fuse memory reading circuit with controllable reading time. The anti-fuse memory reading circuit can generate a reading pulse of corresponding pulse width and a pull-up current source of corresponding size according to a programming signal corresponding to the required reading time, thereby realizing customized programming control of the reading time. It has high flexibility and meets the user's choice between actual reading speed and power consumption requirements.

[0029] The read time control circuit in this antifuse memory read circuit can be further constructed based on antifuses, resulting in low bias current and static power consumption. This also reduces circuit footprint, increases integration, and ensures data integrity during power outages. The read register utilizes a triple-module redundant design, ensuring high reliability and radiation resistance across the entire read circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 2 is a circuit structure diagram of the anti-fuse memory reading circuit disclosed in this application.

[0031] Figure 2 1 is a schematic diagram of waveforms of a read pulse and a voltage on a bit line BL of an anti-fuse memory cell in different embodiments of the anti-fuse memory read circuit disclosed in this application.

[0032] Figure 3 FIG. 1 is a schematic diagram showing the correspondence between different read times and current magnitudes of the pull-up current source in an embodiment. DETAILED DESCRIPTION

[0033] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0034] The present application discloses an anti-fuse memory reading circuit with controllable reading time, which is used to read data in an anti-fuse memory cell 100. The anti-fuse memory cell 100 includes an anti-fuse AF and a programming transistor. The potential of the upper plate of each anti-fuse is controlled by the bit line BL of the anti-fuse memory cell 100, and the lower plate is grounded through the corresponding programming transistor. Multiple such anti-fuses and programming transistors are connected in series in parallel to form an array structure. The gate of each programming transistor is controlled by the word line WL. Figure 1 As shown, the gates of n programming transistors are connected by word lines WL <0> 、WL <1> ...WL <n>When data needs to be read from the anti-fuse memory cell 100, a high level is given to the corresponding word line to open the programming tube, and the anti-fuse memory reading circuit reads the stored data.

[0035] The anti-fuse memory read circuit of the present application includes a read time control circuit 200, a programmable read pulse generation circuit 300, a read amplifier circuit 400, and a read register 500, which are described as follows:

[0036] 1. Reading time control circuit 200 .

[0037] The read time control circuit 200 generates a control signal with K control bits corresponding to the desired read time and provides it to the programmable read pulse generation circuit and the read amplifier circuit. At most, only one control bit in the control signal is 1.

[0038] The read time control circuit 200 can generate a control signal based on a corresponding instruction or shift register, with different control signals corresponding to different read times. In actual applications, the read time control circuit 200 can be used to generate different control signals, and then the data in the antifuse memory cell 100 can be read at different read times. This process is equivalent to a debugging process. Through continuous debugging, the reading effect of the read times corresponding to different control signals can be determined, and the control signal corresponding to the read time with the best reading effect can be determined as the optimal control signal. In subsequent operation, the optimal control signal is generated by the read time control circuit 200.

[0039] To avoid having to generate the optimal control signal each time through external instructions, in one embodiment, the internal circuitry of the read time control circuit 200 is programmed so that it subsequently outputs the optimal control signal in a fixed manner. Specifically, the read time control circuit 200 includes K parallel programming branches, each of which includes a pull-up device 210 and a pull-down device 220 connected in series. Each programming branch is connected to the power supply VDD via the pull-up device 210 and to the ground GND via the pull-down device 220. The common end of the pull-up device 210 and the pull-down device 220 in each programming branch is connected to a programming switch 230. The other ends of the K programming switches 230 are connected and connected to a programming voltage HV_PGM, which is higher than the voltages of VDD and GND. The read time control circuit 200 obtains a programming signal, which is a control signal corresponding to the read time to be finally achieved, generally corresponding to the above-mentioned optimal control signal, and then controls the on and off of K programming switches 230 according to the programming signal to program the corresponding programming branches. The programming branch corresponding to each programming switch 230 is the programming branch connected to the programming switch 230. The common end of the pull-up device 210 and the pull-down device 220 in each programming branch is used to output a control bit of the control signal. Therefore, a total of K+1 control signals can be formed by combining K control bits, such as Figure 1 In the example of K=4, five control signals, 0000, 0001, 0010, 0100, and 1000, can be formed in combination. After programming is completed, the read time control circuit 200 can output one of the control signals by default.

[0040] In the above circuit structure, the pull-up device 210 and the pull-down device 220 can be implemented by ordinary devices such as resistors. However, in one embodiment of the present application, the pull-up device 210 and the pull-down device 220 of the read time control circuit 200 are both implemented by antifuses. Therefore, the pull-up device 210 implemented by the antifuse is referred to as a pull-up antifuse, and the pull-down device 220 implemented by the antifuse is referred to as a pull-down antifuse. The voltage difference between the upper and lower metal plates of the pull-up antifuse is the voltage difference between the programming voltage HV_PGM and the power supply VDD, and the voltage difference between the upper and lower metal plates of the pull-down antifuse is the voltage difference between the programming voltage HV_PGM and ground GND. According to the programming signal, the K programming switches are controlled to be on and off to program the antifuses in the corresponding programming branches. The programming voltage HV_PGM is applied to both ends of the pull-up antifuse and the pull-down antifuse, respectively, to complete the programming of the pull-up antifuse or the pull-down antifuse:

[0041] When programming the pull-up antifuse, the voltage values ​​of the power supply VDD and ground GND are adjusted so that the voltage difference between the upper and lower metal plates of the pull-up antifuse exceeds the breakdown voltage of the antifuse and the voltage difference between the upper and lower metal plates of the pull-down antifuse is less than the breakdown voltage of the antifuse, thereby completing the programming of the pull-up antifuse. When programming the pull-down antifuse, the voltage values ​​of the power supply VDD and ground GND are adjusted so that the voltage difference between the upper and lower metal plates of the pull-down antifuse exceeds the breakdown voltage of the antifuse and the voltage difference between the upper and lower metal plates of the pull-up antifuse is less than the breakdown voltage of the antifuse, thereby completing the programming of the pull-down antifuse.

[0042] In this embodiment, the breakdown voltage of the antifuse used is within the range of 7 to 8V, and the programming voltage HV_PGM used in this embodiment is 10V. When programming the pull-up antifuse, the power supply VDD is adjusted to 0V and the ground GND is adjusted to 5V. At this time, the voltage difference between the upper and lower metal plates of the pull-up antifuse is 10V, exceeding the breakdown voltage of the antifuse, while the voltage difference between the upper and lower metal plates of the pull-down antifuse is 5V, less than the breakdown voltage of the antifuse, thereby protecting the pull-down antifuse from breakdown. When programming the pull-down antifuse, the power supply VDD is adjusted to 5V and the ground GND is adjusted to 0V, so that the voltage difference between the upper and lower metal plates of the pull-down antifuse is 10V, exceeding the breakdown voltage of the antifuse, and the voltage difference between the upper and lower metal plates of the pull-up antifuse is 5V, less than the breakdown voltage of the antifuse, thereby protecting the pull-up antifuse from breakdown.

[0043] After programming, the pull-up and pull-down antifuses are in a low-impedance state, with resistance values ​​in the hundreds of ohms, typically 50 to 150 Ω. However, when unprogrammed, they are in a high-impedance state, with resistance values ​​reaching hundreds of megohms, specifically greater than 200 MΩ. Therefore, the bias current of the read time control circuit 200 is very low, below 0.02 uA. Compared to using conventional resistors to implement pull-up and pull-down devices, this significantly reduces the circuit's static power consumption. Furthermore, using antifuses also occupies a smaller circuit area, resulting in a higher level of circuit integration and the advantage of maintaining power loss during power outages.

[0044] 2. Programmable read pulse generating circuit 300.

[0045] Programmable read pulse generator circuit 300 generates read pulses based on clock signal CLK, each with a pulse width corresponding to a control signal, and outputs them to the read amplifier circuit. The shorter the required read time, the smaller the pulse width W of the corresponding read pulse (Pluse) generated by the control signal. This control signal can expand the operating frequency range and support higher external CLK clock frequencies.

[0046] Specifically, the programmable read pulse generating circuit 300 includes a delay circuit 310, K delay selection switches 320, and a logic AND gate 330. The clock signal CLK is input to the delay circuit 310. The delay circuit performs multi-stage delay on the clock signal CLK and respectively generates clock delay signals with different delay values ​​relative to the clock signal CLK at K different delay stages. The higher the number of delay stages, the greater the delay value of the corresponding clock delay signal relative to the clock signal CLK. Each clock delay signal is connected to a delay selection switch 320. The other ends of the K delay selection switches 320 are connected and connected to one input end of the logic AND gate 330. The other input end of the logic AND gate 330 is connected to the clock signal CLK. In one embodiment, Figure 1 As shown, taking K=4 as an example, the delay circuit 310 is a multi-stage cascaded RC delay circuit, X0 and C0 constitute the first delay stage, X1 and C1 constitute the second delay stage, X2 and C2 constitute the third delay stage, X3 and C3 constitute the fourth delay stage, and X4 and C4 constitute the fifth delay stage. Clock delay signals are respectively derived from the output ends of the second delay stage, the third delay stage, the fourth delay stage, and the fifth delay stage.

[0047] The K delay select switches 320 are each controlled by the K control bits of the control signal. When a corresponding control bit is high, a delay select switch 320 closes and outputs the corresponding clock delay signal to a logic AND gate 330. Logic AND gate 330 performs a logical AND operation on the clock signal CLK and the corresponding clock delay signal to generate a read pulse. The pulse width of the generated read pulse is the delay value of the clock delay signal relative to the clock signal CLK at that time. Therefore, the higher the delay level corresponding to the delay select switch 320 closed by the control signal, the greater the delay value of the generated clock delay signal relative to the clock signal CLK, and the wider the pulse width of the read pulse generated and output to the sense amplifier circuit. The output of the logic AND gate 330 is connected to the sense amplifier circuit and outputs the generated read pulse.

[0048] 3. Sense amplifier circuit 400.

[0049] The read amplifier circuit 400 includes several pull-up current sources of different sizes. The read amplifier circuit selects the pull-up current source corresponding to the read time according to the read pulse and control signal, and pulls up the voltage on the bit line BL of the anti-fuse memory cell. The shorter the required read time, the larger the current value of the pull-up current source selected by the read pulse and control signal. As a result, the charging and discharging time of the voltage on the bit line BL of the anti-fuse memory cell is shortened, achieving faster reading. Please refer to Figure 2 , case1, case2, and case3 represent three different instances of reading time from large to small, such as Figure 2 As shown in the comparison diagram, the pulse width W of the read pulse Pluse in case 1, case 2, and case 3 decreases successively. At the same time, since the current value of the selected pull-up current source increases successively, Figure 2 It shows that the rising speed of the corresponding BL voltage in the three examples is accelerated successively.

[0050] The read amplifier circuit 400 begins reading the data stored in the antifuse memory cell at the rising edge of the read pulse and latches the read data into the read register 500 at the falling edge of the read pulse. The read amplifier circuit 400 begins reading the data stored in the antifuse memory cell 100 at the rising edge of the read pulse. When the antifuse memory cell 100 is in the unprogrammed high-impedance state, the drain of the discharge transistor MN0 is pulled high. When the antifuse memory cell 100 is in the programmed low-impedance state, the drain of the discharge transistor MN0 remains low, and the read data is sent to the read register 500.

[0051] The read amplifier circuit 400 includes an NMOS discharge transistor MN0, several pull-up current sources of varying magnitudes, and a current source selection circuit 410. The source of discharge transistor MN0 is grounded, and its drain is connected to the read register 500 via a buffer 420. The output of the programmable read pulse generator 300 is connected to the gate of discharge transistor MN0 via an inverter 450. Several pull-up current sources of varying magnitudes are connected to the drain of discharge transistor MN0 via a gating network 430. The drain of discharge transistor MN0 is also connected to the bit line BL of the anti-fuse memory cell 100. The current source selection circuit controls the gating network 430 based on the read pulse and control signal, connecting the pull-up current source corresponding to the read time to the drain of discharge transistor MN0.

[0052] The read amplifier circuit includes a reference current source I0 and K additional current sources 440. Figure 1 In the example shown, where K = 4, four additional current sources 440 are included, designated I1, I2, I3, and I4. Reference current source I0 is connected to the source of the corresponding PMOS transistor MP0. The drain of the PMOS transistor MP0 to which reference current source I0 is connected is connected to the drain of discharge transistor MN0, and the gate is connected to the gate of discharge transistor MN0 and to the output of inverter 450. K additional current sources 440 are connected to the drain of discharge transistor MN0 via gating network 430. The current source selection circuit controls gating network 430 based on read pulses and control signals, so that when none of the K additional current sources 440 are conductive to the drain of discharge transistor MN0, reference current source I0 forms a pull-up current source conductive to the drain of discharge transistor MN0.

[0053] Based on the read pulse and control signal, current source selection circuit 410 controls gating network 430 to connect one of additional current sources 440 to the drain of discharge tube MN0. The reference current source I0 and the enabled additional current source then combine to form a pull-up current source connected to the drain of discharge tube MN0. Thus, a total of K+1 different pull-up current sources are formed by one reference current source and K additional current sources.

[0054] For example, Figure 1 In the example, assuming I0 = 10uA, I1 = 8uA, I2 = 6uA, I3 = 4uA, I4 = 2uA, the following five pull-up current sources of different sizes can be formed: I0 alone realizes a pull-up current source of 10uA, I0 and I4 are superimposed to realize a pull-up current source of 12uA, I0 and I3 are superimposed to realize a pull-up current source of 14uA, I0 and I2 are superimposed to realize a pull-up current source of 16uA, and I0 and I1 are superimposed to realize a pull-up current source of 18uA. In this way, five different pull-up current sources of 10uA, 12uA, 14uA, 16uA, and 18uA can be realized. The relationship between the read times corresponding to these five different pull-up current sources is as follows: Figure 3 As shown, it can be seen that the shorter the required reading time T is, the larger the corresponding pull-up current source is, and then a pull-up current source of one size is selected according to the required reading time.

[0055] In one embodiment, the gating network 430 includes K gating PMOS transistors, and the current source selection circuit 410 includes K logic NAND gates. Each additional current source 440 is connected to the source of a corresponding gating PMOS transistor, such as Figure 1 The additional current sources I1, I2, I3 and I4 are connected to the gate PMOS transistors MP1, MP2, MP3 and MP4 respectively, and the drain of each gate PMOS transistor is connected to the drain of the discharge tube MN0.

[0056] One input end of each logic NAND gate in the current source selection circuit 410 is connected to the read time control circuit 200 to obtain a control bit of the control signal, the other input end is connected to the programmable read pulse generation circuit to obtain the read pulse, and the output end is connected to the gate of a corresponding enable PMOS tube.

[0057] The K logic NAND gates in the current source selection circuit 410 respectively correspond to the K control bits of the control signal, and thereby control the on / off of a corresponding gated PMOS transistor, thereby realizing on / off control of the connected additional current source 440 and the drain of the discharge tube MN0.

[0058] 4. Read register 500.

[0059] The D terminal of read register 500 is connected to the output of read amplifier circuit 400 to obtain the read data, and the Q terminal can output the stored data DATA. The output of programmable read pulse generator circuit 300 is connected to the clk terminal of read register 500 via an inverter. Furthermore, in one embodiment, read register 500 is designed using triple-module redundancy technology to improve overall radiation hardening performance.

[0060] The above description is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is understood that other improvements and variations directly derived or imagined by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the scope of protection of the present invention.< / n>

Claims

1. An anti-fuse memory reading circuit with controllable reading time, comprising an anti-fuse memory unit, characterized in that: The anti-fuse memory reading circuit includes a reading time control circuit, a programmable reading pulse generating circuit, a reading amplifier circuit and a reading register; The read time control circuit generates a control signal having K control bits corresponding to the read time and provides the control signal to the programmable read pulse generating circuit and the read amplifier circuit; The programmable read pulse generating circuit generates a read pulse with a pulse width corresponding to the control signal based on the clock signal and outputs the pulse to the read amplifier circuit; The read amplifier circuit includes a plurality of pull-up current sources of different sizes. The read amplifier circuit selects the pull-up current source corresponding to the read time according to the read pulse and the control signal, and pulls up the voltage on the bit line of the anti-fuse memory cell. The read amplifier circuit reads the data stored in the anti-fuse memory cell from the rising edge of the read pulse, and latches the read data into the read register at the falling edge of the read pulse. The read time control circuit includes K parallel programming branches, each programming branch includes a pull-up device and a pull-down device in series, each programming branch is connected to the power supply VDD through the pull-up device and to the ground GND through the pull-down device, the common end of the pull-up device and the pull-down device in each programming branch is connected to a programming switch, and the other ends of the K programming switches are connected and connected to the programming voltage HV_PGM. The read time control circuit obtains a programming signal and controls the on and off of the K programming switches according to the programming signal to program the corresponding programming branch. The common end of the pull-up device and the pull-down device in each programming branch is used to output a control bit of the control signal, and at most one control bit in the control signal is 1.

2. The anti-fuse memory reading circuit according to claim 1, wherein: The shorter the read time is, the shorter the pulse width of the corresponding read pulse is and the larger the current value of the pull-up current source is.

3. The anti-fuse memory reading circuit according to claim 1, wherein: The pull-up device and the pull-down device of the read time control circuit are both implemented by antifuses. The voltage difference between the upper and lower metal plates of the pull-up antifuse is the voltage difference between the programming voltage HV_PGM and the power supply VDD, and the voltage difference between the upper and lower metal plates of the pull-down antifuse is the voltage difference between the programming voltage HV_PGM and the ground GND. According to the programming signal, the K programming switches are controlled to be on and off to perform programming operations on the antifuses in the corresponding programming branches. The programming voltage HV_PGM is applied to both ends of the pull-up antifuse and the pull-down antifuse, respectively, to complete the programming of the pull-up antifuse or the pull-down antifuse: When programming the pull-up antifuse, the voltage values ​​of the power supply VDD and the ground GND are adjusted so that the voltage difference between the upper and lower metal plates of the pull-up antifuse exceeds the breakdown voltage of the antifuse and the voltage difference between the upper and lower metal plates of the pull-down antifuse is less than the breakdown voltage of the antifuse, thereby completing the programming of the pull-up antifuse. When programming the pull-down antifuse, the voltage values ​​of the power supply VDD and the ground GND are adjusted so that the voltage difference between the upper and lower metal plates of the pull-down antifuse exceeds the breakdown voltage of the antifuse and the voltage difference between the upper and lower metal plates of the pull-up antifuse is less than the breakdown voltage of the antifuse, thereby completing the programming of the pull-down antifuse. The resistance value of the antifuse when not programmed is in the hundreds of megohms level.

4. The anti-fuse memory reading circuit according to claim 1, wherein: The programmable read pulse generating circuit includes a delay circuit, K delay selection switches, and a logic AND gate. A clock signal CLK is input into the delay circuit. The delay circuit performs multi-stage delay on the clock signal CLK and respectively generates clock delay signals with different delay values ​​relative to the clock signal CLK at K different delay stages. Each clock delay signal is respectively connected to a delay selection switch. The other ends of the K delay selection switches are connected to an input end of the logic AND gate. The other input end of the logic AND gate is connected to the clock signal CLK. The output end of the logic AND gate is connected to the read amplifier circuit to output the read pulse. Among them, the K delay selection switches are respectively controlled by the K control bits of the control signal, and the delay selection switch is closed when a corresponding control bit is at a high level to output a corresponding clock delay signal to the logic AND gate. The greater the delay value of the clock delay signal relative to the clock signal CLK, the greater the pulse width of the read pulse.

5. The anti-fuse memory reading circuit according to claim 1, wherein: The read amplifier circuit includes an NMOS type discharge tube MN0, a plurality of pull-up current sources of different sizes, and a current source selection circuit; The source of the discharge tube MN0 is grounded, and the drain is connected to the read register via a buffer. The output of the programmable read pulse generating circuit is connected to the gate of the discharge tube MN0 via an inverter. Several pull-up current sources of different sizes are connected to the drain of the discharge tube MN0 via a gating network. The drain of the discharge tube MN0 is also connected to the bit line of the anti-fuse memory cell. The current source selection circuit controls the gating network to connect the pull-up current source corresponding to the reading time to the drain of the discharge tube MN0 according to the read pulse and the control signal.

6. The anti-fuse memory reading circuit according to claim 5, wherein: The read amplifier circuit includes a reference current source and K additional current sources. The reference current source is connected to the source of the corresponding PMOS transistor. The drain of the PMOS transistor to which the reference current source is connected is connected to the drain of the discharge transistor MN0, and the gate is connected to the gate of the discharge transistor MN0 and connected to the output end of the inverter. The K additional current sources are connected to the drain of the discharge transistor MN0 through the gating network. The current source selection circuit controls the gating network according to the read pulse and the control signal so that when the K additional current sources are not conductive to the drain of the discharge tube MN0, the reference current source forms a pull-up current source conductive to the drain of the discharge tube MN0; The current source selection circuit controls the gating network according to the read pulse and the control signal so that one of the additional current sources is connected to the drain of the discharge tube MN0. The reference current source and the connected additional current source are superimposed to form a pull-up current source connected to the drain of the discharge tube MN0. One reference current source and K additional current sources form a total of K+1 different pull-up current sources.

7. The anti-fuse memory reading circuit according to claim 6, wherein: The gating network includes K gating PMOS transistors, and the current source selection circuit includes K logic NAND gates; Each additional current source is connected to the source of a corresponding gated PMOS transistor, and the drain of each gated PMOS transistor is connected to the drain of the discharge tube MN0; One input end of each logic NAND gate in the current source selection circuit is connected to the read time control circuit to obtain a control bit of the control signal, the other input end is connected to the programmable read pulse generation circuit to obtain the read pulse, and the output end is connected to the gate of a corresponding gate PMOS transistor; The K logic NAND gates in the current source selection circuit respectively obtain the K control bits of the control signal, and thereby control the on and off of a corresponding gated PMOS tube.

8. The anti-fuse memory reading circuit according to claim 5, wherein: The read amplifier circuit reads the data stored in the anti-fuse memory cell starting from the rising edge of the read pulse. When the anti-fuse memory cell is read to be in an unprogrammed high-impedance state, the drain of the discharge tube MN0 is pulled to a high level; when the anti-fuse memory cell is read to be in a programmed low-impedance state, the drain of the discharge tube MN0 remains at a low level, and the read data is sent to the read register.

9. The anti-fuse memory reading circuit according to claim 1, wherein: The read register is designed using triple-module redundancy technology.

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