A method of patterning a semiconductor

Abstract

The method for manufacturing a semiconductor pattern of the present application forms a first strip pattern and a second strip pattern on a layer to be etched, and after depositing a preset material on the layer to be etched and then performing a planarization treatment, the first hole type pattern is formed in the region where the two types of strip patterns overlap, and then the second hole type pattern is formed on the layer to be etched where the two types of strip patterns do not exist, thereby obtaining a small-pitch pattern which will not be short-circuited.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device processing, and in particular to a semiconductor pattern manufacturing method. BACKGROUND

[0002] In order to form a structure of a semiconductor device on a wafer, a photoetch process is needed to form a pattern of each layer. A typical photoetch process is to set a photoresist and form a pattern on the photoresist and then etch. However, as the size of the semiconductor device is reduced, it is more and more difficult to prepare a small-pitch pattern by using the photoetch process when a small-pitch pattern is generated by using the photoetch process, because the pattern is easily short-circuited due to optical effects. SUMMARY

[0003] In view of the above problems, the present application is proposed to provide a semiconductor pattern manufacturing method which overcomes the above problems or at least partially solves the above problems.

[0004] The present application provides the following technical solutions through an embodiment of the present application:

[0005] A semiconductor pattern manufacturing method comprises the following steps.

[0006] A semiconductor substrate is provided, and a layer to be etched is formed on the semiconductor substrate.

[0007] A first strip pattern and a second strip pattern are formed on the layer to be etched, wherein the first strip pattern and the second strip pattern intersect and form an intersection region.

[0008] After a preset material is deposited on the layer to be etched, a planarization process is performed until the second strip pattern is exposed.

[0009] The second strip pattern is etched until the first strip pattern in the intersection region is exposed.

[0010] The first strip pattern in the intersection region is etched until the layer to be etched is exposed.

[0011] The exposed layer to be etched is continuously etched to form a first hole pattern.

[0012] The preset material layer is removed until the layer to be etched is exposed.

[0013] The exposed layer to be etched is etched to form a second hole pattern.

[0014] Optionally, the step of forming the first strip pattern and the second strip pattern on the layer to be etched specifically comprises the following steps.

[0015] The first material layer and the second material layer are sequentially deposited on the layer to be etched.

[0016] etching the second material layer and the first material layer to obtain the first strip pattern.

[0017] Optionally, the forming the first strip pattern and the second strip pattern on the layer to be etched specifically comprises:

[0018] sequentially depositing the third material layer and the fourth material layer on the layer to be etched;

[0019] etching the fourth material layer and the third material layer in a direction different from the first strip pattern to obtain the second strip pattern, wherein the height of the second strip pattern relative to the layer to be etched is higher than the height of the first strip pattern relative to the layer to be etched.

[0020] Optionally, the height of the preset material relative to the layer to be etched is higher than the height of the second strip pattern relative to the layer to be etched.

[0021] Optionally, the etching the second strip pattern to expose the first strip pattern in the intersection region specifically comprises:

[0022] selectively etching the fourth material layer in the second strip pattern by taking the preset material as a mask;

[0023] selectively etching part of the third material layer in the second strip pattern by taking the preset material as the mask, to expose the first strip pattern in the intersection region.

[0024] Optionally, the etching the first strip pattern in the intersection region to expose the layer to be etched specifically comprises:

[0025] selectively etching the second material layer exposed on the intersection region by taking the preset material and the remaining third material layer in the second strip pattern as the mask;

[0026] selectively etching the first material layer exposed on the intersection region by taking the preset material and the remaining third material layer as the mask, to expose the layer to be etched.

[0027] Optionally, after the etching the exposed layer to be etched to form a second hole pattern, the method further comprises:

[0028] etching the remaining first strip pattern and the remaining third material layer on the layer to be etched.

[0029] Optionally, the etching the remaining first strip pattern on the layer to be etched specifically comprises:

[0030] Taking the remaining third material layer as the mask, the second material layer remaining on the to-be-etched layer is selectively etched;

[0031] Taking the remaining third material layer as the mask, the first material layer remaining on the to-be-etched layer is selectively etched.

[0032] Optionally, the angle formed by the intersection of the first strip pattern and the second strip pattern is 0-90 degrees.

[0033] The application further discloses a method for manufacturing a capacitor hole, comprising the method in any of the above technical solutions, and

[0034] A lower electrode is formed in the first hole pattern and the second hole pattern;

[0035] The remaining to-be-etched layer is etched;

[0036] A capacitor dielectric layer and an upper electrode are formed in and outside the lower electrode.

[0037] The one or more technical solutions provided in the embodiments of the application have at least the following technical effects or advantages:

[0038] The semiconductor pattern manufacturing method can form a first hole pattern in the area where the two types of strip patterns overlap, and then form a second hole pattern on the to-be-etched layer where the two types of strip patterns do not exist, so that a small-pitch pattern which will not be short-circuited and connected can be obtained. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0040] Figure 1 A schematic diagram of a hole pattern in a semiconductor in an embodiment of the application is shown.

[0041] Figure 2 A schematic diagram of a cross-sectional direction in an embodiment of the application is shown.

[0042] Figures 3-14 A top view schematic diagram of a hole pattern in an embodiment of the application is shown.

[0043] Figures 3A-14A A cross-sectional view in the 11 direction of a top view of a hole pattern in an embodiment of the application is shown.

[0044] Figures 3B-14B A cross-sectional view along the direction 22 in the top view of the hole pattern is shown in the embodiment of the present application. DETAILED DESCRIPTION

[0045] Exemplary embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0046] Various structural diagrams according to the embodiments of the present disclosure are shown in the accompanying drawings. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity, and certain details can be omitted. The shapes of various regions, layers, and the relative sizes and positional relationships between them shown in the diagrams are merely exemplary, and in actuality can be deviated due to manufacturing tolerances or technical limitations, and regions / layers with different shapes, sizes, and relative positions can be additionally designed by those skilled in the art according to actual needs.

[0047] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it can be "under" the other layer / element when the orientation is reversed.

[0048] The first embodiment of the present application provides a method for manufacturing a small-pitch pattern of a semiconductor, which aims to make a small-pitch pattern that will not be short-circuited. Referring to Figure 1 is a schematic diagram of the small-pitch pattern made. In the actual manufacturing process, after each material layer is deposited, selective etching is performed, for example, with a selectivity of 8:1, to first form a first hole pattern in the region where the two types of bar patterns overlap, and then form a second hole pattern on the layer to be etched where neither of the two types of bar patterns exists.

[0049] It is worth noting that the materials used for each material layer in this embodiment can be flowable carbon, SiON, SiO2, polysilicon, SiN, etc. For example, the first material layer and the third material layer in the following embodiments can be selected from flowable carbon, and the second material layer and the fourth material layer can be selected from SiON. The preset material can be polysilicon. Of course, other options are also possible, which are not limited herein.

[0050] It is worth noting that, in order to illustrate and explain the present application, example diagrams of the semiconductor after each step is performed are shown for reference. Specifically,Figures 3-14 This is a top view of a semiconductor. Figures 3A-14A It is a cross-sectional view along direction 11 of the top view of the hole pattern. Figures 3B-14B It is a cross-sectional view along direction 22 on the top view of the hole pattern. All etching methods in this embodiment can be physical or chemical etching, such as dry etching, wet etching, etc., and there is no limitation on the etching method.

[0051] The semiconductor patterning method of this embodiment will now be described in detail.

[0052] A semiconductor substrate is provided, and an etchable layer is formed on the semiconductor substrate, wherein a first stripe pattern and a second stripe pattern are formed on the etchable layer.

[0053] Specifically, the number of first bar patterns is not limited in this embodiment, and all first bar patterns are parallel to each other and are formed along the first direction. See [reference needed] Figure 3 and Figure 3A Of course, the first direction can also be other directions; the attached diagram is only an example. Further, a first material layer and a second material layer are sequentially deposited on the layer to be etched. Then, the second material layer and the first material layer are selectively etched to obtain a first stripe pattern. The first stripe pattern, from bottom to top, includes: the first material layer and the second material layer.

[0054] Regarding the second bar pattern, the number of second bar patterns is not limited in this embodiment, and all second bar patterns are parallel to each other. The first and second bar patterns intersect to form an intersection area. Furthermore, the angle formed by the intersection of the first and second bar patterns is 0°-90°, for example, a vertical angle of 90° can be selected.

[0055] Specifically, a third material layer and a fourth material layer are sequentially deposited on the layer to be etched. Since the second material layer is deposited on top of the first stripe pattern already present on the first layer, its height relative to the first layer is greater than the first stripe pattern's height relative to the first layer. Then, the fourth and third material layers are etched in a direction different from the first stripe pattern to obtain the second stripe pattern. For example, etching can be performed perpendicular to the first stripe pattern. The resulting second stripe pattern will partially cover the first stripe pattern; this covered area is the intersection region. The second stripe pattern, from bottom to top, includes the third and fourth material layers.

[0056] If the first material layer and the third material layer are both selected as flowable carbon, but the percentage of components can be different. Similarly, if the second material layer and the fourth material layer are both selected as SiON, the percentage of components can be different. Then, in the process of etching each material layer, the corresponding etching selectivity can be selected to etch to obtain two different strip patterns in different directions.

[0057] At this time, the area on the layer to be etched is divided into three parts: the intersection area obtained by the intersection of the two types of strip patterns, the coverage area covered by the two types of strip patterns respectively (excluding the intersection area), and the area on the layer to be etched which is not covered by the two types of strip patterns (uncovered area).

[0058] On this basis, after depositing a preset material on the layer to be etched and then performing planarization treatment, the second strip pattern is exposed.

[0059] Specifically, when depositing the preset material on the layer to be etched, the preset material will cover the layer to be etched, the first strip pattern and the second strip pattern, and the height of the preset material relative to the layer to be etched is higher than the height of the second strip pattern relative to the layer to be etched.

[0060] Among them, since the preset material is deposited on the layer to be etched after the second strip pattern, the preset material on the second strip pattern is also covered, so in the process of planarization treatment, the preset material will be etched until its height relative to the layer to be etched and the height of the second strip pattern relative to the layer to be etched are the same, and the second strip pattern is exposed.

[0061] Etching the second strip pattern, until the first strip pattern in the intersection area is exposed.

[0062] Specifically, since the second strip pattern includes the fourth material layer and the third material layer from top to bottom. Therefore, in the process of etching, the fourth material layer in the second strip pattern is selectively etched with the preset material as a mask, and then part of the third material layer in the second strip pattern is selectively etched with the preset material as a mask, until the first strip pattern in the intersection area is exposed.

[0063] Etching the first strip pattern in the intersection area until the layer to be etched is exposed.

[0064] Specifically, after etching the second strip pattern, the second material layer in the intersection area is exposed. And the intersection area from top to bottom is the second material layer, the first material layer and the layer to be etched in the intersection area. Therefore, in the process of etching, the exposed second material layer in the intersection area is selectively etched with the preset material and the remaining third material layer in the second strip pattern as a mask, and then the exposed first material layer in the intersection area is selectively etched with the preset material and the remaining third material layer as a mask, until the layer to be etched is exposed.

[0065] If the first material layer and the third material layer are made of the same material (for example, flowing carbon), when the first material layer exposed on the intersection area is etched selectively, the third material layer will also be etched, and the height of the third material layer relative to the layer to be etched will be lowered. However, since the thickness of the first material layer itself is smaller than the thickness of the third material layer around it, when the first material layer exposed on the intersection area is etched, a part of the third material layer on the layer to be etched will remain. If the first material layer and the third material layer are made of different materials, the third material layer around the first material layer will not be affected when the first material layer exposed on the intersection area is etched.

[0066] The exposed layer to be etched is continuously etched to form the first hole pattern. At this time, the layer to be etched exposed in the intersection area will also be etched, but the etching depth of the layer to be etched in the intersection area is smaller than the thickness of the layer to be etched formed on the semiconductor substrate, so as to avoid etching through the layer to be etched. The specific etching thickness of the layer to be etched is determined according to the actual situation, which is not limited here. The hole pattern of the present embodiment can be circular, square, etc.

[0067] It can be seen that the present embodiment actually only etches the first hole pattern from top to bottom in the intersection area of the first bar pattern and the second bar pattern, and the connection of each intersection area is still covered at this time, so the first hole patterns will not be short-circuited with each other, and a small-pitch pattern without short-circuit connection is obtained.

[0068] After the first hole pattern is etched, from the cross section, the height of the preset material relative to the layer to be etched in the uncovered area and the height of the remaining third material layer relative to the layer to be etched are the same, and the entire layer to be etched is covered by the preset material.

[0069] At this time, the preset material layer is removed to expose the layer to be etched, and the exposed layer to be etched is etched to form the second hole pattern. At this time, the layer to be etched in the uncovered area will also be etched, but the etching depth of the layer to be etched in the uncovered area is smaller than the thickness of the layer to be etched formed on the semiconductor substrate, so as to avoid etching through the layer to be etched. The specific etching thickness of the layer to be etched is determined according to the actual situation, which is not limited here. The hole pattern of the present embodiment can be circular, square, etc.

[0070] It is worth noting that although two types of holes are formed in the layer to be etched, in order to distinguish the first hole pattern, the second hole pattern and the layer to be etched, the two types of hole patterns in the present embodiment are distinguished by different colors, as shown in the drawings.

[0071] It can be seen that, on the basis of the first hole pattern, the embodiment can further etch the second hole pattern from top to bottom in the uncovered area, so as to further reduce the spacing between the patterns, so as to form patterns with a size smaller than the resolution limit of photolithography. And due to the blocking effect of the remaining first strip pattern on the to-be-etched layer and the remaining third material layer, short-circuit connection can be avoided when etching the first hole pattern, and further, small-pitch patterns without short-circuit connection can be obtained.

[0072] After obtaining the two types of hole patterns, the embodiment further etches the remaining first strip pattern and the remaining third material layer on the to-be-etched layer, so that the etching on the entire to-be-etched layer is completed, and small-pitch patterns without short-circuit connection are obtained. Specifically, with respect to the remaining first strip pattern on the to-be-etched layer, the remaining second material layer on the to-be-etched layer is selectively etched with the remaining third material layer as a mask, and then the remaining first material layer on the to-be-etched layer is selectively etched with the remaining third material layer as a mask.

[0073] The process flow of the semiconductor pattern manufacturing method described in the above embodiment is used as a basis, and the application embodiment further discloses a method for manufacturing a capacitor hole, which includes the content described in any of the above embodiments, and the following processes: forming a lower electrode in the first hole pattern and the second hole pattern, etching the remaining to-be-etched layer, and forming a capacitor dielectric layer and an upper electrode inside and outside the lower electrode.

[0074] The technical solutions in the above embodiments of the application have at least the following technical effects or advantages:

[0075] The semiconductor pattern manufacturing method of the application forms a first strip pattern and a second strip pattern on a to-be-etched layer, and after depositing a preset material on the to-be-etched layer and then performing a planarization process, after the second strip pattern is exposed, a first hole pattern can be formed in the region where the two types of strip patterns overlap, and then a second hole pattern can be formed on the to-be-etched layer where neither type of strip pattern exists, and further, small-pitch patterns without short-circuit connection can be obtained.

[0076] The above process can be used to prepare capacitor hole patterns in DRAM manufacturing processes and channel hole patterns in Vertical NAND, and other processes that need to prepare small-pitch hole patterns in semiconductor devices.

[0077] In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, those skilled in the art will understand that the layers, regions, etc. of desired shapes can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the above-described methods in order to form the same structure. In addition, although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0078] Although preferred embodiments of the application have been described herein, those skilled in the art will readily devise many additional variations of these preferred embodiments that fall within the scope of the present application. Accordingly, the scope of the application is intended to be interpreted only as is indicated in the appended claims and equivalents thereof.

[0079] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A method for patterning a semiconductor, characterized in that, include: Provide a semiconductor substrate and form a layer to be etched on the semiconductor substrate; A first stripe pattern and a second stripe pattern are formed on the layer to be etched, wherein the first stripe pattern and the second stripe pattern intersect and form an intersection area; After depositing a preset material on the layer to be etched, a planarization process is performed until the second strip pattern is exposed. The second strip pattern is etched until the first strip pattern in the intersection area is exposed; The first strip pattern in the intersection area is etched until the layer to be etched is exposed; Continue etching the exposed layer to be etched to form a first aperture pattern; Remove the preset material layer until the layer to be etched is exposed; The exposed layer to be etched is etched to form a second aperture pattern; The formation of the first stripe pattern and the second stripe pattern on the layer to be etched specifically includes: A first material layer and a second material layer are sequentially deposited on the layer to be etched. The second material layer and the first material layer are etched to obtain the first strip pattern; A third material layer and a fourth material layer are sequentially deposited on the etchable layer on which the first stripe pattern and the second stripe pattern are formed; The fourth material layer and the third material layer are etched in a direction different from that of the first strip pattern to obtain the second strip pattern; wherein the height of the second strip pattern relative to the layer to be etched is higher than the height of the first strip pattern relative to the layer to be etched.

2. The method as described in claim 1, characterized in that, The height of the preset material relative to the layer to be etched is higher than the height of the second strip pattern relative to the layer to be etched.

3. The method as described in claim 1, characterized in that, The etching of the second stripe pattern until the first stripe pattern in the intersection area is exposed specifically includes: Using the preset material as a mask, the fourth material layer in the second strip pattern is selectively etched; Using the preset material as a mask, a portion of the third material layer in the second strip pattern is selectively etched until the first strip pattern in the intersection area is exposed.

4. The method as described in claim 3, characterized in that, The etching of the first stripe pattern in the intersection region until the layer to be etched is exposed specifically includes: Using the preset material and the remaining third material layer in the second strip pattern as the mask, the exposed second material layer on the intersection area is selectively etched; Using the preset material and the remaining third material layer as the mask, the exposed first material layer on the intersection area is selectively etched until the layer to be etched is exposed.

5. The method as described in claim 4, characterized in that, After etching the exposed layer to be etched to form a second aperture pattern, the method further includes: The remaining first strip pattern and the remaining third material layer on the layer to be etched are etched.

6. The method as described in claim 5, characterized in that, The etching of the remaining first strip pattern on the layer to be etched specifically includes: Using the remaining third material layer as the mask, the remaining second material layer on the layer to be etched is selectively etched; Using the remaining third material layer as the mask, the remaining first material layer on the layer to be etched is selectively etched.

7. The method as described in claim 1, characterized in that, The angle formed by the intersection of the first and second bar patterns is 90°.

8. A method for manufacturing a capacitor aperture, characterized in that, Includes the method as described in any one of claims 1-7 above, and, The lower electrode is formed within the first and second aperture patterns; Etch the remaining layer to be etched; A capacitor dielectric layer and an upper electrode are formed outside the lower electrode.

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