Fan-out packaging method and packaging structure

Abstract

The present invention provides a fan-out packaging method and a packaging structure. The method includes: providing a wafer carrier, a panel carrier, and multiple groups of first chips, wherein a plurality of conductive bumps are disposed on the front surface of the first chips; fixing the back surfaces of the multiple groups of first chips on the surface of the wafer carrier in the form of a first array, and forming a first encapsulation layer on the front surfaces of the multiple groups of first chips; separating the multiple groups of first chips from the wafer carrier, and forming a high-density interconnect wiring layer on the front surfaces of the multiple groups of first chips; cutting the multiple groups of first chips, and fixing the side with the high-density interconnect wiring layer on the surface of the panel carrier in the form of a second array; forming a second encapsulation layer on the side of the multiple groups of first chips facing away from the high-density interconnect wiring layer; separating the multiple groups of first chips from the panel carrier, and forming a low-density interconnect wiring layer on the high-density interconnect wiring layer. The packaging method of the present invention can not only well meet the requirements of high-density interconnection, but also has low cost and high yield.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and particularly relates to a fan-out packaging method and a packaging structure. Background Art

[0002] With the development of semiconductor technology, packaging technology has been developing towards high density / high integration. Currently, the fan-out technology has become an important development direction for high-density interconnection. By using the redistribution layer to connect single-chip and multi-chip, the flexibility of packaging integration has been greatly improved. The fan-out technology has been applied to fields such as high-performance computing (HPC) and mobile phone processors.

[0003] Currently, there are two main development directions for the fan-out technology. One is the fan-out wafer-level packaging (FOWLP) based on wafer technology, and the other is the fan-out panel-level packaging (FOPLP) based on panel technology. The wiring density of the fan-out wafer-level packaging can be higher. Currently, mass production with a line width of 2um has been achieved, but the yield is low and the cost is high. The fan-out panel-level packaging has a high yield and low cost. However, due to the large panel size, it is difficult to achieve a fine line width. Currently, the line widths that can be mass-produced are all above 5um.

[0004] In view of the above problems, it is necessary to propose a fan-out packaging method and a packaging structure with reasonable design that can effectively solve the above problems. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a fan-out packaging method and a packaging structure.

[0006] In one aspect of the present invention, a fan-out packaging method is provided, and the method includes:

[0007] Providing a wafer carrier, a panel carrier, and multiple groups of first chips, wherein a plurality of conductive bumps are disposed on the front surface of the first chips;

[0008] Fixing the back surfaces of the multiple groups of first chips on the surface of the wafer carrier in a first array, and forming a first encapsulation layer on the front surfaces of the multiple groups of first chips;

[0009] Separating the multiple groups of first chips from the wafer carrier, and forming a high-density interconnect wiring layer on the front surfaces of the multiple groups of first chips;

[0010] Cutting the multiple groups of first chips, and fixing the side with the high-density interconnect wiring layer on the surface of the panel carrier in a second array;

[0011] Forming a second encapsulation layer on the side of the multiple groups of first chips facing away from the high-density interconnect wiring layer;

[0012] Separate the multiple groups of first chips from the panel carrier, and form a low-density interconnect wiring layer on the high-density interconnect wiring layer.

[0013] Optionally, before forming the high-density interconnect wiring layer on the front surface of the first chip, the method further includes:

[0014] Separate the multiple groups of first chips from the wafer carrier, and grind the front surface of the first chips to expose the conductive bumps.

[0015] Optionally, forming the high-density interconnect wiring layer on the front surface of the multiple groups of first chips includes:

[0016] Form a first dielectric layer on the first encapsulation layer and the conductive bumps, pattern the first dielectric layer to form a plurality of first openings;

[0017] Form a first metal interconnect layer on the surface of the patterned first dielectric layer, pattern the first metal interconnect layer to form the high-density interconnect wiring layer, wherein the first metal interconnect layer is electrically connected to the conductive bumps.

[0018] Optionally, forming the low-density interconnect wiring layer on the surface of the high-density interconnect wiring layer includes:

[0019] Form a second dielectric layer on the surface of the high-density interconnect wiring layer, pattern the second dielectric layer to form a plurality of second openings;

[0020] Form a second metal interconnect layer on the surface of the patterned second dielectric layer, pattern the second metal interconnect layer to form the low-density interconnect wiring layer.

[0021] Optionally, the dielectric materials of the first dielectric layer and the second dielectric layer are different.

[0022] Optionally, after forming the low-density interconnect wiring layer, the method further includes:

[0023] Form a third dielectric layer on the surface of the patterned second metal interconnect layer, pattern the third dielectric layer to form a plurality of third openings;

[0024] Perform ball planting at the multiple third openings to form a plurality of solder balls;

[0025] Cut the multiple groups of first chips to form a single-group chip package structure.

[0026] Optionally, after forming the plurality of solder balls, the method further includes: grinding the side of the second encapsulation layer facing away from the multiple groups of first chips; or

[0027] After forming a second encapsulation layer on a side of the multiple groups of first chips facing away from the high-density interconnect wiring layer, the method further includes:

[0028] Grinding a side of the second encapsulation layer facing away from the multiple groups of first chips.

[0029] Optionally, each group of first chips includes one or more first chips.

[0030] Another aspect of the present invention provides a fan-out package structure, the package structure includes: a first chip, an encapsulation layer, a high-density interconnect wiring layer, and a low-density interconnect wiring layer, wherein, a plurality of conductive bumps are disposed on a front surface of the first chip;

[0031] The encapsulation layer wraps the first chip, and the high-density interconnect wiring layer is sandwiched between the encapsulation layer and the low-density interconnect wiring layer.

[0032] Optionally, the high-density interconnect wiring layer includes a first dielectric layer disposed on the conductive bumps, and a first metal interconnect layer disposed on the first dielectric layer,

[0033] wherein, the first metal interconnect layer is electrically connected to the conductive bumps;

[0034] The low-density interconnect wiring layer includes a second dielectric layer disposed on the first metal interconnect layer, and a second metal interconnect layer disposed on the second dielectric layer.

[0035] For the fan-out package method and package structure of the present invention, after the high-density interconnect layer is completed by using the fan-out wafer-level packaging technology in the package method, the low-density interconnect layer is completed by using the fan-out panel-level packaging technology. Compared with the current traditional fan-out wafer-level packaging, the fan-out package method of the present invention can provide lower cost and higher yield under the condition of the same interconnect density. Compared with the current traditional fan-out panel-level packaging, the fan-out package method of the present invention can provide higher interconnect density to meet the requirements of high-performance devices. Description of the Drawings

[0036] Figure 1 It is a schematic flow chart of a fan-out package method according to an embodiment of the present invention;

[0037] Figure 2 It is a schematic diagram of the chip arrangement area in a wafer carrier according to another embodiment of the present invention;

[0038] Figure 3 It is a schematic diagram of the second array B on a panel carrier according to another embodiment of the present invention;

[0039] Figure 4 It is a schematic diagram of the first array A on a wafer carrier according to another embodiment of the present invention;

[0040] Figures 5 to 21 Schematic diagram of the packaging process of a fan-out packaging structure according to another embodiment of the present invention. Specific embodiments

[0041] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0042] As Figure 1 shown, one aspect of the present invention provides a packaging method S100 for a fan-out packaging structure. The packaging method S100 includes:

[0043] S110. Provide a wafer carrier, a panel carrier, and multiple groups of first chips. Among them, a plurality of conductive bumps are provided on the front surface of the first chips.

[0044] Specifically, as Figure 2 , Figure 3 and Figure 4 shown, provide a wafer carrier 110, a panel carrier 120, and multiple groups of first chips 130. Among them, a plurality of conductive bumps 131 are provided on the front surface of the first chips 130. In this embodiment, the conductive bumps 131 are provided at both ends of the first chips 130. The conductive bumps 131 are metal copper conductive bumps, and other metal materials can also be used. This embodiment does not make specific limitations.

[0045] It should be noted that the main material of the wafer carrier 110 is glass, silicon wafer, or metal. The main material of the panel carrier 120 is glass, metal, or glass fiber resin sheet. This embodiment does not make specific limitations on the materials of the wafer carrier 110 and the panel carrier 120, and can be selected according to needs.

[0046] S120. Fix the back surfaces of the multiple groups of first chips on the surface of the wafer carrier in the form of a first array, and form a first encapsulation layer on the front surfaces of the multiple groups of first chips.

[0047] Specifically, as Figure 5 shown, fix the back surfaces of the multiple groups of first chips 130 on the surface of the wafer carrier 110 through a first adhesive 111. That is to say, the first chips 130 are fixed on the surface of the wafer carrier 110 with the front sides facing up. Using wafer-level packaging technology, the high-density interconnection requirements can be well realized. As Figure 3 shown, after pasting, the multiple groups of first chips 130 form a first array A, and the first array A is a square array. As Figure 6 shown, use encapsulation material to encapsulate the front surfaces of the multiple groups of first chips 130 to form a first encapsulation layer 140. The first encapsulation layer 140 plays a protective role for the first chips 130. The encapsulation method can be film layer vacuum lamination or traditional encapsulation process. This embodiment does not make specific limitations.

[0048] It should be noted that each group of first chips 130 includes one or more first chips 130. In this embodiment, each group of first chips only includes one first chip 130.

[0049] S130. Separate the multiple groups of first chips from the wafer carrier, and form a high-density interconnect wiring layer on the front surface of the multiple groups of first chips.

[0050] Specifically, as Figure 7 shown, separate the back surfaces of the multiple groups of first chips 130 from the wafer carrier 110. The separation method can adopt thermal separation, laser separation, ultraviolet light separation, mechanical separation, etc. These methods are all currently commonly used temporary bonding separation methods. The separation method is not specifically limited in this embodiment and can be selected according to actual needs.

[0051] As Figure 8 shown, after separating the back surfaces of the multiple groups of first chips 130 from the wafer carrier 110, grind the front surfaces of the multiple groups of first chips 130 to expose the conductive bumps 131 on the front surfaces of the first chips 130. Other processes can also be used to expose the conductive bumps 131, which is not specifically limited in this embodiment.

[0052] Exemplarily, forming a high-density interconnect wiring layer on the front surfaces of the multiple groups of first chips includes:

[0053] First, form a first dielectric layer on the first encapsulation layer and the conductive bumps, and pattern the first dielectric layer to form a plurality of first openings.

[0054] Specifically, as Figure 9 shown, coat the first dielectric layer 150 on the first encapsulation layer 140 and the conductive bumps 131. The material of the first dielectric layer 150 is polyimide (PI), polybenzoxazole (PBO), etc. The coating method is usually wafer spin coating, which is not specifically limited in this embodiment. The first dielectric layer 150 plays a protective role for the multiple groups of first chips 130. The material and coating process of the first dielectric layer 150 are not specifically limited in this embodiment and can be selected according to actual needs.

[0055] As Figure 9 shown, pattern the first dielectric layer 150 through a photolithography process to form a plurality of first openings 151 on the first dielectric layer 150.

[0056] Secondly, form a first metal interconnect layer on the surface of the patterned first dielectric layer, and pattern the first metal interconnect layer to form the high-density interconnect wiring layer, wherein the first metal interconnect layer is electrically connected to the conductive bumps.

[0057] Specifically, asFigure 10 As shown, a first metal interconnect layer 160 is deposited on the surface of the patterned first dielectric layer 150, wherein the first metal interconnect layer 160 is electrically connected to the conductive bump 131. The deposition method can adopt processes such as electroplating, sputtering, thermal evaporation, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition. The metal material of the first metal interconnect layer 160 is usually metal titanium and metal copper, and the deposition method and metal material are not specifically limited in this embodiment. The first metal interconnect layer 160 is electrically connected to the conductive bump 131.

[0058] As Figure 10 shown, the first metal interconnect layer 160 is patterned through photolithography and etching processes to form a high-density interconnect wiring layer. The etching process can be wet etching or dry etching, and this embodiment does not make specific limitations.

[0059] Adopting the fan-out wafer-level packaging to form the above-mentioned high-density interconnect wiring layer can provide a higher interconnect density and meet the requirements of high-performance devices.

[0060] S140. Cut the multiple groups of first chips and fix the side with the formed high-density interconnect wiring layer on the surface of the panel carrier in the form of a second array.

[0061] Specifically, as Figure 11 shown, cut the multiple groups of first chips 130 according to the area size of the panel carrier 120 and fix them on the surface of the panel carrier 120 in the form of the second array B as Figure 4 shown. Using the panel-level packaging technology can improve the yield and reduce the manufacturing cost. In this embodiment, as Figure 12 shown, fix the side with the formed high-density interconnect wiring layer on the panel carrier 120 through the second adhesive 121, that is, the first metal interconnect layer 160 is adhered to the second adhesive 121.

[0062] S150. Form a second encapsulation layer on the side of the multiple groups of first chips facing away from the high-density interconnect wiring layer.

[0063] Specifically, as Figure 13 shown, fix the multiple groups of first chips 130 on the panel carrier 120 in the form of the second array B, and then form a second encapsulation layer 170 on the side of the multiple groups of first chips 130 facing away from the high-density interconnect wiring layer. The encapsulation method can be film layer vacuum lamination or traditional encapsulation process, and this embodiment does not make specific limitations.

[0064] S160. Separate the multiple groups of first chips from the panel carrier and form a low-density interconnect wiring layer on the high-density interconnect wiring layer.

[0065] Specifically, as Figure 14 shown, separate multiple groups of first chips 130 from the panel carrier 120. The separation method can be thermal separation, laser separation, ultraviolet light separation, mechanical separation, etc. These methods are all currently commonly used temporary bonding separation methods. The separation method is not specifically limited in this embodiment and can be selected according to actual needs.

[0066] Exemplarily, forming a low - density interconnect wiring layer on the high - density interconnect wiring layer includes:

[0067] First, form a second dielectric layer on the surface of the high - density interconnect wiring layer, and pattern the second dielectric layer to form a plurality of second openings.

[0068] Specifically, as Figure 15 shown, on the surface of the high - density interconnect wiring layer, that is, on the surface of the first metal interconnect layer 160, cover the second dielectric layer 180. The second dielectric layer 180 plays a protective role for the first metal interconnect layer 160. The material of the second dielectric layer 180 is a photosensitive dielectric layer (PID) or an Ajinomoto build - up film (ABF), etc. This embodiment does not make specific limitations. The process of covering the second dielectric layer 180 on the surface of the first metal interconnect layer 160 can be vacuum laminating or printing process. This embodiment does not make specific limitations. As Figure 15 shown, pattern the second dielectric layer 180 through a photolithography process to form a plurality of second openings 181.

[0069] Secondly, form a second metal interconnect layer on the surface of the patterned second dielectric layer, and pattern the second metal interconnect layer to form the low - density interconnect wiring layer.

[0070] Specifically, as Figure 16 shown, deposit the second metal interconnect layer 190 on the surface of the patterned second dielectric layer 180. The deposition method can adopt processes such as electroplating, sputtering, thermal evaporation, plasma - enhanced chemical vapor deposition, low - pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition. The metal material of the second metal interconnect layer 190 is usually titanium and copper. This embodiment does not make specific limitations on the deposition method and the metal material of the second metal interconnect layer 190.

[0071] As Figure 16 shown, pattern the second metal interconnect layer 190 through a photolithography and etching process to form a low - density interconnect wiring layer. The etching process can be wet etching or dry etching. This embodiment does not make specific limitations.

[0072] Exemplarily, as Figure 16As shown, the dielectric materials of the first dielectric layer 150 and the second dielectric layer 180 are different. The material of the first dielectric layer 150 is polyimide (PI), polybenzoxazole (PBO), etc., and the material of the second dielectric layer 180 is photosensitive dielectric layer (PID) or Ajinomoto build-up film (ABF), etc. This is because the first dielectric layer 150 is fabricated using a wafer-level process, and the second dielectric layer 180 is fabricated using a panel-level process. Selecting preferred dielectric layers for different processes and having similar materials for the two dielectric layers will not cause problems such as contact difference or process infeasibility.

[0073] Forming the above-mentioned low-density interconnect wiring layer using fan-out panel-level packaging can provide lower costs under the condition of the same interconnect density.

[0074] Exemplarily, after forming the low-density interconnect wiring layer, the method further includes:

[0075] First, a third dielectric layer is formed on the surface of the patterned second metal interconnect layer, and the third dielectric layer is patterned to form a plurality of third openings.

[0076] Specifically, as Figure 17 shown, a third dielectric layer 200 is covered on the surface of the patterned second metal interconnect layer 190. The material of the third dielectric layer 200 can be photosensitive solder resist (PSR), etc., and no specific limitation is made in this embodiment. The process of covering the third dielectric layer 200 on the second metal interconnect layer 190 can be vacuum lamination or printing process, and no specific limitation is made in this embodiment. As Figure 17 shown, the third dielectric layer 200 is patterned using a lithography process to form a plurality of third openings 201.

[0077] Second, ball implantation is performed at the plurality of third openings to form a plurality of solder balls.

[0078] Specifically, as Figure 18 shown, ball implantation is performed at the plurality of third openings 201 to form a plurality of solder balls 210.

[0079] Finally, the multi-group first chips are diced to form a single-group chip package structure.

[0080] Exemplarily, as Figure 19 shown, after forming the plurality of solder balls 210, the multi-group first chips 130 are diced to form a single-group chip package structure.

[0081] Exemplarily, as Figure 20 shown, after forming the plurality of solder balls 210, the side of the second encapsulation layer 170 facing away from the multi-group first chips 130 is polished to reduce the encapsulation thickness, and finally the package structure as Figure 21 shown is formed.

[0082] Exemplarily, as Figure 13 shown, after forming the second encapsulation layer 170 on the side of the multiple groups of first chips 130 facing away from the high-density interconnect wiring layer, the side of the second encapsulation layer 170 facing away from the multiple groups of first chips 130 is polished to reduce the encapsulation thickness.

[0083] It should be noted that in the given embodiments, the dielectric layer structure is 3-layer or 4-layer. Actually, the present invention can be applied to multiple layers and can be adjusted according to actual design requirements. The number of interconnect layers used in wafer-level and panel-level processes can also be adjusted according to actual design requirements. For example, when the second interconnect layer also requires high-density interconnect (which cannot be achieved in panel-level processes), two interconnect layers can be fabricated using wafer-level processes and then transferred to panel-level processes for subsequent processing.

[0084] It should be further noted that in the present invention, as Figure 2 shown, the middle area of the wafer carrier 110 is the chip arrangement area 112. The chip arrangement area 112 is distributed in the first array A as shown. The chip arrangement area 112 is a square structure, and the length of its diagonal is equivalent to the diameter of the wafer carrier 110. Through temporary bonding and wafer-level re-wiring, a high-density interconnect wiring layer is formed in the middle area. The chip arrangement area 112 that has completed high-density interconnect is cut and then integrally built onto the panel carrier 120 in the form of the second array B as shown. Figure 3 Figure 4 Figure 4 shown, the currently commonly used panel carrier 120 has a size of 510×515 mm. In this case, 4 chip arrangement areas 112 can be placed simultaneously, and the subsequent processes can be completed using panel-level packaging interconnect technology. The production efficiency can reach 4 times that of wafer-level packaging technology. In the future, if LCD panel technology is used, the production efficiency can be increased to 6 - 8 times, and the cost will be greatly reduced.

[0085] As Figure 4 shown, since the area of the chip arrangement area 112 is smaller than the area of the wafer carrier 110, there will be a certain area loss. Considering that the chips are all rectangular or square in size, the main loss area is the blank area 113 in the figure, and the short side dimension of it is 28 mm. For samples with a packaging size close to or larger than 28 mm, this area is an invalid area. However, for samples with a packaging size close to or smaller than 28 mm, the blank area 113 can still be used. Therefore, the design of the chip arrangement area 112 will not increase the cost of wafer-level packaging. Since high-density interconnect is mainly applied to fields such as high-performance computing, and the packaging in this field is developing towards larger sizes, the present invention has a significant effect of reducing costs.

[0086] As Figure 2 shown, since the area of the chip arrangement area 112 is smaller than the area of the wafer carrier 110, there will be a certain area loss. Considering that the chips are all rectangular or square in size, the main loss area is the blank area 113 in the figure, and the short side dimension of it is 28 mm. For samples with a packaging size close to or larger than 28 mm, this area is an invalid area. However, for samples with a packaging size close to or smaller than 28 mm, the blank area 113 can still be used. Therefore, the design of the chip arrangement area 112 will not increase the cost of wafer-level packaging. Since high-density interconnect is mainly applied to fields such as high-performance computing, and the packaging in this field is developing towards larger sizes, the present invention has a significant effect of reducing costs.

[0087] In the package design, generally, the interconnect layer density near the chip is high, while the interconnect layer density far from the chip is low, and the line width of the connection lines shows a trend of gradually increasing. Taking advantage of this feature, in the package method of the fan-out package structure provided by the present invention, the fan-out wafer-level packaging technology and the fan-out panel-level packaging technology are integrally used to complete the fan-out package manufacturing. For the interconnect layer near the chip, the wafer-level packaging technology can well meet the high-density interconnect requirements, while for the interconnect layer far from the chip, the panel-level packaging technology can improve the yield and reduce the manufacturing cost.

[0088] As Figure 21 shown, on the other hand, the present invention provides a fan-out package structure 100, and the package structure 100 includes: a first chip 130, a molding compound layer 140, a high-density interconnect wiring layer (not marked in the figure) and a low-density interconnect wiring layer (not marked in the figure). Among them, a plurality of conductive bumps 131 are provided on the front surface of the first chip 130. In this embodiment, the conductive bumps 131 are metal copper conductive bumps, and other metal materials can also be used, which are not specifically limited in this embodiment.

[0089] The molding compound layer 140 wraps the first chip 130, and the high-density interconnect wiring layer is sandwiched between the molding compound layer 140 and the low-density interconnect wiring layer. Among them, the conductive bumps 131 are electrically connected to the high-density interconnect wiring layer.

[0090] Exemplarily, as Figure 21 shown, the high-density interconnect wiring layer includes a first dielectric layer 150 provided on the conductive bumps 131, and a first metal interconnect layer 160 provided on the first dielectric layer 150. Among them, the first metal interconnect layer 160 is electrically connected to the conductive bumps 131.

[0091] It should be noted that the material of the first dielectric layer 150 is polyimide (PI), polybenzoxazole (PBO), etc., and the coating method is usually wafer spin coating, which is not specifically limited in this embodiment. The first dielectric layer 150 plays a protective role for multiple groups of the first chips 130. The material and coating process of the first dielectric layer 150 are not specifically limited in this embodiment and can be selected according to actual needs.

[0092] It should be further noted that the first metal interconnect layer 160 can be deposited on the first dielectric layer 150 by processes such as electroplating, sputtering, thermal evaporation, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition. The metal material of the first metal interconnect layer 160 is usually titanium and copper, and the deposition method and metal material of the first metal interconnect layer 160 are not specifically limited in this embodiment.

[0093] As Figure 21As shown, the low-density interconnect wiring layer includes a second dielectric layer 180 disposed on the first metal interconnect layer 160, and a second metal interconnect layer 190 disposed on the second dielectric layer 180.

[0094] It should be noted that the material of the second dielectric layer 180 is a photosensitive dielectric layer (PID) or an Ajinomoto build-up film (ABF), etc., and no specific limitation is made in this embodiment. The process of covering the second dielectric layer 180 on the surface of the first metal interconnect layer 160 can be a vacuum laminating process or a printing process, and no specific limitation is made in this embodiment.

[0095] It should be further noted that processes such as electroplating, sputtering, thermal evaporation, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition can be used to deposit the second metal interconnect layer 190 on the second dielectric layer 180. The metal material of the second metal interconnect layer 190 is usually titanium and copper, and no specific limitation is made on the deposition method of the second metal interconnect layer 190 and the metal material of the second metal interconnect layer 190 in this embodiment.

[0096] The dielectric materials of the first dielectric layer 150 and the second dielectric layer 180 are different. The material of the first dielectric layer 150 is polyimide (PI), polybenzoxazole (PBO), etc., and the material of the second dielectric layer 180 is a photosensitive dielectric layer (PID) or an Ajinomoto build-up film (ABF), etc. This is because the first dielectric layer 150 is made in a wafer-level process, and the second dielectric layer 180 is made in a panel-level process. Preferred dielectric layers are selected according to different processes, and there will be no problems such as contact difference or process unfeasibility if the materials of the two dielectric layers are close.

[0097] Exemplarily, as Figure 21 shown, the package structure 100 further includes a third dielectric layer 200 disposed on the second metal interconnect layer 190, and a plurality of solder balls 210 disposed on the third dielectric layer 200.

[0098] It should be noted that the material of the third dielectric layer 200 can be a photosensitive solder resist (PSR), etc., and no specific limitation is made in this embodiment. The process of covering the third dielectric layer 200 on the second metal interconnect layer 190 can be a vacuum laminating process or a printing process, and no specific limitation is made in this embodiment.

[0099] The fan-out package structure of the present invention not only has low cost and high yield, but also can well meet the requirements of high-density interconnect.

[0100] It is understandable that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present invention. However, the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A fan-out packaging method, characterized in that, The method includes: Providing a wafer carrier, a panel carrier, and multiple groups of first chips, wherein a plurality of conductive bumps are provided on the front surface of the first chips; Fixing the back surfaces of the multiple groups of first chips on the surface of the wafer carrier in the form of a first array, and forming a first encapsulation layer on the front surfaces of the multiple groups of first chips; Separating the multiple groups of first chips from the wafer carrier, and forming a high-density interconnect wiring layer on the front surfaces of the multiple groups of first chips; Cutting the multiple groups of first chips, and fixing the side with the high-density interconnect wiring layer formed thereon on the surface of the panel carrier in the form of a second array; Forming a second encapsulation layer on the side of the multiple groups of first chips facing away from the high-density interconnect wiring layer; Separating the multiple groups of first chips from the panel carrier, and forming a low-density interconnect wiring layer on the high-density interconnect wiring layer.

2. The method according to claim 1, characterized in that Before forming the high-density interconnect wiring layer on the front surfaces of the multiple groups of first chips, the method further includes: Separating the multiple groups of first chips from the wafer carrier, and grinding the front surfaces of the first chips to expose the conductive bumps.

3. The method according to claim 2, characterized in that, Forming the high-density interconnect wiring layer on the front surfaces of the multiple groups of first chips includes: Forming a first dielectric layer on the first encapsulation layer and the conductive bumps, patterning the first dielectric layer to form a plurality of first openings; Forming a first metal interconnect layer on the surface of the patterned first dielectric layer, patterning the first metal interconnect layer to form the high-density interconnect wiring layer, wherein the first metal interconnect layer is electrically connected to the conductive bumps.

4. The method according to claim 3, characterized in that, Forming the low-density interconnect wiring layer on the high-density interconnect wiring layer includes: Forming a second dielectric layer on the surface of the high-density interconnect wiring layer, patterning the second dielectric layer to form a plurality of second openings; Forming a second metal interconnect layer on the surface of the patterned second dielectric layer, patterning the second metal interconnect layer to form the low-density interconnect wiring layer.

5. The method according to claim 4, characterized in that The dielectric materials of the first dielectric layer and the second dielectric layer are different.

6. The method according to claim 3, characterized in that, After forming the low-density interconnect wiring layer, the method further includes: Forming a third dielectric layer on the surface of the patterned second metal interconnect layer, patterning the third dielectric layer to form a plurality of third openings; Performing ball planting at the plurality of third openings to form a plurality of solder balls; Cutting the multiple groups of first chips to form a single-group chip package structure.

7. The method according to any one of claims 1 to 6, characterized in that After forming the plurality of solder balls, the method further includes: Polishing the side of the second encapsulation layer facing away from the multiple groups of first chips; or After forming the second encapsulation layer on the side of the multiple groups of first chips facing away from the high-density interconnect wiring layer, the method further includes: Polishing the side of the second encapsulation layer facing away from the multiple groups of first chips.

8. The method according to any one of claims 1 to 6, characterized in that Each group of first chips includes one or more first chips.

9. A fan-out package structure, characterized in that, Performing encapsulation using the fan-out encapsulation method according to any one of claims 1 to 8; wherein The package structure includes: a first chip, a first encapsulation layer, a second encapsulation layer, a high-density interconnect wiring layer, and a low-density interconnect wiring layer, wherein a plurality of conductive bumps are provided on the front surface of the first chip; The first encapsulation layer encapsulates the first chip, and the second encapsulation layer encapsulates the first encapsulation layer; The high-density interconnect wiring layer is sandwiched between the encapsulation layer and the low-density interconnect wiring layer.

10. The encapsulation structure according to claim 9, wherein the high-density interconnect wiring layer includes a first dielectric layer disposed on the conductive bump and a first metal interconnect layer disposed on the first dielectric layer, wherein the first metal interconnect layer is electrically connected to the conductive bump; the low-density interconnect wiring layer includes a second dielectric layer disposed on the first metal interconnect layer and a second metal interconnect layer disposed on the second dielectric layer.

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