Multi-layer Stacked Memory Encapsulation Method and Encapsulation Structure

Abstract

The present invention provides a method and a packaging structure for a multi-layer stacked memory package. The method includes: fixing each first memory chip in a first slot of a corresponding first dummy chip to form a first memory micro-module, wherein the first dummy chip is provided with a first cooling through-hole; anodically bonding a second dummy chip and a third dummy chip to form a second slot at a position corresponding to the first slot on the second dummy chip and the third dummy chip, and forming a second cooling through-hole at a position corresponding to the first cooling through-hole on the third dummy chip, and the second cooling through-hole communicates with the first cooling through-hole; fixing the first memory chip in the second slot to form a second memory micro-module; sequentially hybrid-bonding and stacking the second memory micro-module and a plurality of first memory micro-modules on a buffer chip, and the orthographic projections of the second memory micro-module and the first memory micro-modules on the buffer chip coincide with the buffer chip. By forming cooling through-holes on the dummy chip, forced cooling is achieved, and the chips are connected through hybrid bonding, greatly improving the interconnection density.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and particularly relates to a multi-layer stacked memory packaging method and a packaging structure. Background Art

[0002] For enterprise applications such as data centers, high-capacity high-speed storage has become a necessity. To meet this demand, high bandwidth memory (HBM) has emerged. As Figure 1 shown, HBM uses through-silicon vias (TSVs) 12 to vertically interconnect several memory chips 11, and conducts data interaction with the outside world through a buffer chip 10 at the bottom layer. Due to the advantages of high density and short vertical interconnection distance of TSVs, the data transmission speed is greatly improved.

[0003] However, memory chips are sensitive to heat. After multiple memory chips are stacked, heat accumulation will seriously affect the performance of the memory chips. The industry needs a high heat dissipation solution for high bandwidth memory chips.

[0004] In view of the above problems, it is necessary to propose a multi-layer stacked memory packaging method and a packaging structure that are reasonably designed and can effectively solve the above problems. Summary of the Invention

[0005] The present invention aims to at least solve one of the technical problems existing in the prior art, and provides a multi-layer stacked memory packaging method and a packaging structure.

[0006] One aspect of the present invention provides a multi-layer stacked memory packaging method, and the method includes:

[0007] Providing a buffer chip, a plurality of first dummy chips, a second dummy chip, a third dummy chip, and a plurality of first memory chips, wherein the first dummy chip is provided with a first groove and a plurality of first cooling through holes, the buffer chip is provided with a plurality of first conductive through holes, and the first memory chip is provided with a plurality of second conductive through holes corresponding to the plurality of first conductive through holes;

[0008] Fixing each of the first memory chips in the first groove of the corresponding first dummy chip to form a plurality of first memory micromodules;

[0009] Anodic bonding the second dummy chip and the third dummy chip, forming a second groove at the position corresponding to the first groove on the bonded second dummy chip and third dummy chip, and forming a second cooling through hole at the position corresponding to the first cooling through hole on the third dummy chip, wherein the second cooling through hole is communicated with the first cooling through hole;

[0010] Fix the first memory chip in the second slot body to form a second memory micro-module;

[0011] Stack the second memory micro-module and the multiple first memory micro-modules on the buffer chip by hybrid bonding in sequence, wherein the orthographic projections of the second memory micro-module and the first memory micro-modules on the buffer chip both coincide with the buffer chip.

[0012] Optionally, before anodic bonding the second dummy chip and the third dummy chip, the method further includes:

[0013] Form a cooling through groove on the second dummy chip, and the cooling through groove communicates with the second cooling through hole.

[0014] Optionally, a first passivation layer and a first metal pad are provided on a first surface of the first memory chip facing the buffer chip, and a second passivation layer and a second metal pad are provided on a second surface of the first memory chip facing away from the buffer chip;

[0015] The step of respectively fixing each first memory chip in the slot body of the corresponding first dummy chip to form multiple first memory micro-modules includes:

[0016] Form a first adhesive between the bottom wall of the first slot body and the first surface of the first memory chip to fix the first memory chip in the first slot body;

[0017] Form a second adhesive between the first dummy chip and the second surface of the first memory chip, and make part of the second adhesive fill into the first cooling through hole and the gap between the side wall of the first slot body and the first memory chip;

[0018] Completely remove the second adhesive on the second surface of the first memory chip to expose the second passivation layer and the second metal pad, and at the same time retain part of the second adhesive on the surface of the first dummy chip;

[0019] Remove the first adhesive on the first surface of the first memory chip to expose the first passivation layer, the first metal pad and the first cooling through hole, and form the first memory micro-module.

[0020] Optionally, the step of fixing the first memory chip in the second slot body to form a second memory micro-module includes:

[0021] Form the first adhesive between the bottom wall of the second slot body and the first surface of the first memory chip to fix the first memory chip in the second slot body;

[0022] Form the second adhesive on the second surface of the third dummy chip and the first memory chip, and make part of the second adhesive fill into the second cooling through-hole and the gap between the side wall of the second groove and the first memory chip;

[0023] Completely remove the second adhesive on the second surface of the first memory chip to expose the second passivation layer and the second metal pad, while retaining part of the second adhesive on the surface of the third dummy chip;

[0024] Remove the first adhesive on the first surface of the first memory chip to expose the first passivation layer and the first metal pad, and form the second memory micro-module.

[0025] Optionally, a third passivation layer and a third metal pad are provided on one side of the buffer chip facing the second memory micro-module;

[0026] The step of sequentially hybrid bonding and stacking the second memory micro-module and the multiple first memory micro-modules on the buffer chip includes:

[0027] Bond the first passivation layer of the second memory micro-module to the third passivation layer on the buffer chip, and bond the first metal pad of the second memory micro-module to the third metal pad on the buffer chip;

[0028] Bond the first passivation layer of the bottom first memory micro-module to the second passivation layer of the second memory micro-module, and bond the first metal pad of the bottom first memory micro-module to the second metal pad of the second memory micro-module;

[0029] Sequentially hybrid bond and stack the remaining first memory micro-modules on the second memory micro-module, wherein the first passivation layer and the second passivation layer in each adjacent two layers of first memory micro-modules are bonded; and the first metal pad and the second metal pad in each adjacent two layers of first memory micro-modules are bonded.

[0030] Optionally, after sequentially hybrid bonding and stacking the second memory micro-module and the multiple first memory micro-modules on the buffer chip, the method further includes:

[0031] Remove the second adhesive in the first cooling through-hole and the second cooling through-hole.

[0032] Optionally, the surfaces of the first groove and the second groove both protrude from the surface of the first memory chip.

[0033] Another aspect of the present invention provides a multi-layer stacked memory package structure, including a buffer chip and a plurality of first memory micromodules and second memory micromodules;

[0034] The buffer chip is provided with a plurality of first conductive through holes;

[0035] The second memory micromodule is hybrid-bonded and stacked on the buffer chip, the plurality of first memory micromodules are sequentially hybrid-bonded and stacked on the second memory micromodule, and the orthographic projections of the first memory micromodule and the second memory micromodule on the buffer chip overlap with the buffer chip; wherein,

[0036] Each of the first memory micromodules includes a first memory chip and a first dummy sheet provided with a first slot and a plurality of first cooling through holes, wherein the first slot is provided with the first memory chip, and the first memory chip is provided with a plurality of second conductive through holes corresponding to and electrically connected to the plurality of first conductive through holes;

[0037] The second memory micromodule includes a first memory chip, a second dummy sheet, and a third dummy sheet sandwiched between the first dummy sheet and the second dummy sheet, the second dummy sheet and the third dummy sheet are provided with a second slot body corresponding to the first slot body, the first memory chip is provided in the second slot body, and the third dummy sheet is provided with a second cooling through hole corresponding to and connected to the first cooling through hole.

[0038] Optionally, a cooling groove is provided on the second dummy plate, and the cooling groove is connected to the second cooling hole.

[0039] Optionally, a first passivation layer and a first metal pad are disposed on a first surface of the first memory chip facing the buffer chip, and a second passivation layer and a second metal pad are disposed on a second surface of the first memory chip facing away from the buffer chip;

[0040] The first passivation layer and the second passivation layer in each two adjacent first memory micro-modules are hybrid-bonded; and

[0041] The first metal pads and the second metal pads in every two adjacent layers of the first memory micro-modules are connected by hybrid bonding.

[0042] Optionally, the second passivation layer in the second memory micromodule is hybrid-bonded to the first passivation layer in the underlying first memory micromodule; and

[0043] The second metal layer in the second memory micromodule is hybrid-bonded to the first metal layer in the underlying first memory micromodule.

[0044] Optionally, a third passivation layer and a third metal pad are provided on the surface of the buffer chip facing the memory micro-module;

[0045] The third passivation layer is hybrid-bonded to the first passivation layer in the second memory micro-module, and the third metal pad is bonded to the first metal pad in the second memory micro-module.

[0046] The multi-layer stacked memory packaging method and packaging structure of the present invention adjust the first memory chips to the same size as the buffer chip through the first dummy chip, the second dummy chip and the third dummy chip. The first memory chips and between the first memory chips and the buffer chip are all hybrid-bonded, greatly improving the interconnection density; forming interconnected first cooling through-holes, second cooling through-holes and cooling grooves on the first dummy chip, the second dummy chip and the third dummy chip can become the inlet and outlet channels for external coolant, and forcibly cool the first memory chips, greatly improving the heat dissipation performance of the memory chips. Through the coordinated improvement of the electro-thermal performance, the product characteristics of the memory chips are improved. Description of the Drawings

[0047] Figure 1 is a schematic structural diagram of a typical traditional multi-layer memory packaging structure in the prior art;

[0048] Figure 2 A schematic flow chart of a multi-layer stacked memory packaging method according to an embodiment of the present invention;

[0049] Figures 3 to 17 is a schematic packaging process diagram of a multi-layer stacked memory packaging method according to another embodiment of the present invention. Detailed Embodiments

[0050] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0051] As Figure 2 shown, one aspect of the present invention provides a multi-layer stacked memory packaging method S100, and the packaging method S100 includes:

[0052] S110. Provide a buffer chip, a plurality of first dummy chips, a second dummy chip, a third dummy chip and a plurality of first memory chips. The first dummy chip is provided with a first groove body and a plurality of first cooling through-holes. The buffer chip is provided with a plurality of first conductive through-holes. The first memory chips are provided with a plurality of second conductive through-holes corresponding to the plurality of first conductive through-holes.

[0053] Specifically, as Figure 17As shown, a buffer chip 110, a plurality of first dummy chips 120, a second dummy chip 130, a third dummy chip 140, and a plurality of first memory chips 150 are provided. A groove (not marked in the figure) is provided on the first dummy chip 120, a first groove (not marked in the figure) is provided in the central region of the first dummy chip 120, and a plurality of first cooling through holes 121 are provided in the edge region of the first dummy chip 120. The buffer chip 110 is provided with a plurality of first conductive vias 111, and the first memory chip 150 is provided with a plurality of second conductive vias 151 corresponding to the plurality of first conductive vias 111. Among them, both the first conductive via 111 and the second conductive via 151 can be through-silicon vias. The vertical electrical interconnection of the through-silicon vias is realized by using the through-silicon via technology, reducing the package height. The first memory chip 150 can be a dynamic random access memory chip or other memory chips, and no specific limitation is made in this embodiment.

[0054] S120. Fix each of the first memory chips in the first grooves of the corresponding first dummy chips respectively to form a plurality of first memory micro-modules.

[0055] Specifically, as Figure 3 shown, a first passivation layer 152 and a first metal pad 153 are provided on the first surface of the first memory chip 150 facing the buffer chip 110, and a second passivation layer 154 and a second metal pad 155 are provided on the second surface of the first memory chip 150 facing away from the buffer chip 110.

[0056] It should be noted that in this embodiment, the materials of the first passivation layer 152 and the second passivation layer 154 can be silicon dioxide or silicon nitride materials, or other materials with a passivation effect, and no specific limitation is made in this embodiment. In this embodiment, the materials of the first metal pad 153 and the second metal pad 155 can be copper, or other metal materials, and no specific limitation is made in this embodiment.

[0057] The step of fixing each of the first memory chips in the grooves of the corresponding first dummy chips respectively to form a plurality of first memory micro-modules includes:

[0058] First, form a first adhesive between the bottom wall of the first groove and the first surface of the first memory chip to fix the first memory chip in the first groove.

[0059] Specifically, as Figure 3As described above, a first adhesive 122 is formed on the bottom wall of the first cell body and the first surface of the first memory chip 150. In this embodiment, that is, the back surface of the first memory chip 150 is fixed in the first cell body through the first adhesive 122. It should be noted that the size of the first cell body is slightly larger than that of the first memory chip 150, and the depth of the cell body is lower than the height of the first memory chip 150. That is to say, the surface of the first memory chip 150 protrudes from the surface of the first dummy chip 120. Since the surface of the first memory chip 150 protrudes from the surface of the first dummy chip 120, a plurality of first dummy chips 120 can be pasted and fixed.

[0060] Secondly, a second adhesive is formed on the second surfaces of the first dummy chip and the first memory chip, and part of the second adhesive is filled into the first cooling through holes and the gaps between the side wall of the first cell body and the first memory chip.

[0061] Specifically, as Figure 4 shown, a second adhesive 123 is formed on the second surfaces of the first dummy chip 120 and the first memory chip 150. In this embodiment, that is, the second adhesive 123 is formed on the front surfaces of the first dummy chip 120 and the first memory chip 150, and part of the second adhesive 123 is filled into the first cooling through holes 121 and the gaps between the side wall of the first cell body and the first memory chip 150. Filling part of the second adhesive 123 into the gaps between the side wall of the first cell body and the first memory chip 150 can further fix the first memory chip 150 in the first cell body.

[0062] Thirdly, the second adhesive on the second surface of the first memory chip is completely removed to expose the second passivation layer and the second metal pads, while part of the second adhesive on the surface of the first dummy chip is retained.

[0063] Specifically, as Figure 5 shown, the second surface of the first memory chip 150 is polished and chemically cleaned to completely remove the second adhesive 123 on the second surface of the first memory chip 150 to expose the second passivation layer 154 and the second metal pads 155, while part of the second adhesive 123 on the surface of the first dummy chip 120 is retained. The remaining second adhesive 123 on the surface of the first dummy chip 120 is flush with the second passivation layer 154.

[0064] Finally, the first adhesive on the first surface of the first memory chip is removed to expose the first passivation layer, the first metal pads, and the first cooling through holes, thereby forming the first memory micromodule.

[0065] Specifically, as Figure 6As shown, the back surface of the first dummy chip 120 is ground and polished to remove the silicon on the back surface of the first dummy chip 120 and the first adhesive 122 on the first surface of the first memory chip 150, exposing the first passivation layer 152, the first metal pads 153, and a plurality of first cooling through holes 121, thus forming the first memory micro-module A formed by the combination of the first dummy chip 120 and the first memory chip 150.

[0066] S130. Anodic bond the second dummy chip and the third dummy chip, form a second groove at the position corresponding to the first groove in the bonded second dummy chip and third dummy chip, and form a second cooling through hole at the position corresponding to the first cooling through hole in the third dummy chip, wherein the second cooling through hole communicates with the first cooling through hole.

[0067] Specifically, as Figure 8 shown, anodic bond the second dummy chip 130 and the third dummy chip 140, and then as Figure 9 shown, thin the side of the third dummy chip 140 facing away from the second dummy chip 130 according to the packaging requirements. As Figure 10 shown, form a second groove 142 at the position corresponding to the first groove in the thinned second dummy chip 130 and third dummy chip 140 by etching, and form a plurality of second cooling through holes 141 at the position corresponding to the first cooling through hole 121 in the thinned third dummy chip 140 by etching, wherein the second cooling through holes 141 communicate with the first cooling through hole 121.

[0068] Exemplarily, before anodic bonding the second dummy chip and the third dummy chip, the method further includes:

[0069] Form a cooling through groove on the second dummy chip, and the cooling through groove communicates with the second cooling through hole.

[0070] Specifically, as Figure 7 shown, form a cooling through groove 131 on the side of the second dummy chip 130 facing the first memory chip 150 by etching, and the cooling through groove 131 communicates with the second cooling through hole 141. In this way, the first cooling through hole 121, the second cooling through hole 141, and the cooling through groove 131 together form the cooling channels of a plurality of first memory chips, which can be the channels for external coolant to enter and exit, and perform forced refrigeration on the plurality of first memory chips 150 to improve the heat dissipation performance of the first memory chips 150.

[0071] S140. Fix the first memory chip in the second groove to form a second memory micro-module.

[0072] First, form the first adhesive between the bottom wall of the second slot and the first surface of the first memory chip to fix the first memory chip in the second slot.

[0073] Specifically, as Figure 11 shown, form the first adhesive 122 between the bottom wall of the second slot 142 and the first surface of the first memory chip 150. In this embodiment, that is, fix the back surface of the first memory chip 150 in the second slot 142 through the first adhesive 122. It should be noted that the size of the second slot 142 is slightly larger than the size of the first memory chip 150, and the depth of the slot is lower than the height of the first memory chip 150. That is to say, the surface of the first memory chip 150 protrudes from the surface of the third dummy chip 140. Since the surface of the first memory chip 150 protrudes from the surface of the third dummy chip 140, multiple first dummy chips 120 can be pasted and fixed to the third dummy chip 140.

[0074] Second, form the second adhesive between the third dummy chip and the second surface of the first memory chip, and make part of the second adhesive fill into the second cooling through holes and the gap between the side wall of the second slot and the first memory chip.

[0075] Specifically, as Figure 12 shown, form the second adhesive 123 between the third dummy chip 140 and the second surface of the first memory chip 150, and make part of the second adhesive 123 fill into the second cooling through holes 141 and the gap between the side wall of the second slot 142 and the first memory chip 150. By filling part of the second adhesive 123 into the gap between the side wall of the second slot 142 and the first memory chip 150, the first memory chip 150 can be further fixed in the second slot 142.

[0076] Third, completely remove the second adhesive on the second surface of the first memory chip to expose the second passivation layer and the second metal pad, while retaining part of the second adhesive on the surface of the third dummy chip.

[0077] Specifically, as Figure 13 shown, polish and chemically clean the second surface of the first memory chip 150 to completely remove the second adhesive 123 on the second surface of the first memory chip 150 to expose the second passivation layer 154 and the second metal pad 155, while retaining part of the second adhesive 123 on the surface of the third dummy chip 140. The second adhesive 123 remaining on the surface of the third dummy chip 140 is flush with the second passivation layer 154.

[0078] Finally, remove the first adhesive on the first surface of the first memory chip to expose the first passivation layer and the first metal pad, thereby forming the second memory micro-module.

[0079] Specifically, as Figure 14 shown, grind and polish the back surface of the third dummy chip 140 to remove the silicon on the back surface of the third dummy chip 140 and the first adhesive 122 on the first surface of the first memory chip 150, exposing the first passivation layer 152, the first metal pad 153, and a plurality of second cooling through-holes 141, thus forming the second memory micro-module B formed by combining the second dummy chip 130, the third dummy chip 140, and the first memory chip 150.

[0080] S150. Sequentially hybrid-bond and stack the second memory micro-module and the plurality of first memory micro-modules on the buffer chip, wherein the orthographic projections of the second memory micro-module and the first memory micro-module on the buffer chip both coincide with the buffer chip.

[0081] Specifically, as Figure 15 shown, a third passivation layer 112 and a third metal pad 113 are provided on one side of the buffer chip 110 facing the second memory micro-module B. Among them, in this embodiment, the material of the third passivation layer 112 can be a silicon dioxide material or a silicon nitride material, and the material of the third metal pad 113 can be copper. The materials of the third passivation layer 112 and the third metal pad 113 are not specifically limited in this embodiment.

[0082] The step of sequentially hybrid-bonding and stacking the second memory micro-module and the plurality of first memory micro-modules on the buffer chip includes:

[0083] First, bond the first passivation layer of the second memory micro-module to the third passivation layer on the buffer chip, and bond the first metal pad of the second memory micro-module to the third metal pad on the buffer chip.

[0084] Specifically, as Figure 15 and Figure 16 shown, heat and apply pressure to hybrid-bond the first passivation layer 152 of the second-layer memory micro-module B to the third passivation layer 112 on the buffer chip 110, align the first metal pad 153 of the second memory micro-module B with the third metal pad 113 on the buffer chip 110, and through the action of high-temperature pressing, utilize the thermal expansion of copper to achieve bonding connection. Among them, the second adhesive 123 remaining on the surface of the third dummy chip 140 in the second memory micro-module B can further fix and paste the second memory micro-module B on the buffer chip 110.

[0085] Next, bond the first passivation layer of the bottom first memory micro-module to the second passivation layer of the second memory micro-module, and bond the first metal pad of the bottom first memory micro-module to the second metal pad of the second memory micro-module.

[0086] Specifically, as Figure 16 and Figure 17 shown, bond the first passivation layer 152 of the bottom first memory micro-module A and the second passivation layer 154 of the second memory micro-module B by hybrid bonding under heating and pressure conditions, and bond the first metal pad 153 of the bottom first memory micro-module A and the second metal pad 155 of the second memory micro-module B by hybrid bonding under heating and pressure conditions.

[0087] Finally, stack the remaining first memory micro-modules by hybrid bonding on the second memory micro-module in sequence, where the first passivation layer and the second passivation layer in each adjacent two layers of the first memory micro-modules are bonded; and the first metal pad and the second metal pad in each adjacent two layers of the first memory micro-modules are bonded.

[0088] Specifically, as Figure 16 and Figure 17 shown, stack the remaining first memory micro-modules A by hybrid bonding on the second memory micro-module B in sequence, where the first passivation layer 152 of one of each adjacent two layers of the first memory micro-modules A and the second passivation layer 154 of the other are bonded by hybrid bonding under heating and pressure conditions, and the first metal pad 153 of one of each adjacent two layers of the first memory micro-modules A and the second metal pad 155 of the other are bonded by hybrid bonding under heating and pressure conditions.

[0089] That is to say, as Figure 16 shown, the second memory micro-module B is hybrid-bonded with the buffer chip 110, the bottom first memory micro-module A is hybrid-bonded with the second memory micro-module B, the second-layer first memory micro-module A is disposed above the first-layer first memory micro-module A and hybrid-bonded with the first-layer memory micro-module A, and so on, stacking the first memory micro-modules A of each layer by hybrid bonding on the second memory micro-module B in sequence.

[0090] As Figure 17 shown, only one side of the topmost first memory micro-module A facing the buffer chip 110 is provided with the first passivation layer 152 and the first metal pad 153. Since the topmost first memory micro-module A plays a role in protecting the package structure, the thickness of the topmost first memory micro-module A is thicker than that of the other first memory micro-modules A, and no second conductive via 151 is provided on the first memory chip 150.

[0091] Between the first memory chips 150 and between the first memory chips 150 and the buffer chip 110, hybrid bonding is used for connection, which can achieve a smaller pitch. At the same density, the number of vertical interconnections can be increased, and the increase in the number of data channels can improve data throughput.

[0092] As Figure 15 、 Figure 16 and Figure 17 shown, the orthographic projection of the first memory micro-module A on the buffer chip 110 coincides with the buffer chip 110, and the orthographic projection of the second memory micro-module B on the buffer chip 110 coincides with the buffer chip 110. That is to say, the sizes of the first memory micro-module A and the second memory micro-module B are the same as the size of the buffer chip 110. The size of the first memory chip 150 is adjusted to be the same as the size of the buffer chip 110 through the first dummy chip 120, the second dummy chip 130, and the third dummy chip 140. In this way, wafer-level hybrid bonding can be achieved, and while achieving high-density interconnection, the efficiency of hybrid bonding is much higher than that of single-chip bonding, realizing mass producibility.

[0093] Exemplarily, after successively hybrid-bonding and stacking the second memory micro-module and the plurality of first memory micro-modules on the buffer chip, the method further includes:

[0094] Removing the second adhesive in the first cooling through-hole and the second cooling through-hole.

[0095] Specifically, as Figure 17 shown, a laser and a cleaning agent are used to remove the second adhesive 123 in the first cooling through-hole 121 and the second cooling through-hole 141, forming a hollow cooling channel, which becomes the inlet and outlet channel for external coolant for forced refrigeration. Then, cutting is performed to form independent particles, and after forming a plurality of bumps 170, cutting is performed to form a plurality of independent memory package structures.

[0096] In this embodiment, a plurality of protrusions 160 are provided on the side of the buffer chip 110 facing away from the second memory micro-module B, and the plurality of protrusions 160 correspond to and are electrically connected to the plurality of conductive vias 111.

[0097] In the multi-layer stacked memory packaging method of the present invention, the size of the first memory chip is adjusted to be the same as that of the buffer chip through the first dummy chip, the second dummy chip, and the third dummy chip. Between the first memory chips and between the first memory chips and the buffer chip, hybrid bonding is used for connection, greatly improving the interconnection density; mutually connected first cooling through-holes, second cooling through-holes, and cooling grooves are formed on the first dummy chip, the second dummy chip, and the third dummy chip, which can achieve forced cooling of the first memory chip, greatly improving the heat dissipation performance of the memory chip. Through the coordinated improvement of electro-thermal performance, the characteristics of HBM products are improved.

[0098] As Figure 17 shown, another aspect of the present invention provides a multi-layer stacked memory package structure 100, including a buffer chip 110, and a plurality of first memory micro-modules A and second memory micro-modules B; the buffer chip 110 is provided with a plurality of first conductive vias 111; the second memory micro-module B is hybrid-bonded and stacked on the buffer chip 110, and the plurality of first memory micro-modules A are sequentially hybrid-bonded and stacked on the second memory micro-module B, and the orthographic projections of the first memory micro-modules A and the second memory micro-modules B on the buffer chip 110 coincide with the buffer chip 110. That is to say, the sizes of the first memory micro-modules A and the second memory micro-modules B are the same as the size of the buffer chip 110.

[0099] Each first memory micro-module A includes a first memory chip 150 and a first dummy chip 120 provided with a first groove and a plurality of first cooling vias 121. The first groove is provided with the first memory chip 150, and the first memory chip 150 is provided with a plurality of second conductive vias 151 corresponding to and electrically connected to the plurality of first conductive vias 111.

[0100] Among them, both the first conductive via 111 and the second conductive via 151 can be through-silicon vias. The through-silicon via technology is used to realize the vertical electrical interconnection of the through-silicon vias, reducing the package height. The first memory chip 150 can be a dynamic random access memory chip or other memory chips, which is not specifically limited in this embodiment.

[0101] The second memory micro-module B includes a first memory chip 150, a second dummy chip 130, and a third dummy chip 140 sandwiched between the first dummy chip 120 and the second dummy chip 130. The second dummy chip 130 and the third dummy chip 140 are provided with second grooves corresponding to the first groove, and the second grooves are provided with the first memory chip 150. The third dummy chip 140 is provided with second cooling vias 141 corresponding to and communicating with the first cooling vias 121.

[0102] Exemplarily, as Figure 17 shown, the second dummy chip 130 is provided with a cooling through-groove 131, and the cooling through-groove 131 communicates with the second cooling via 141. In this way, the first cooling via 121, the second cooling via 141, and the cooling through-groove 131 together form the cooling channels of the plurality of first memory chips, which can be the channels for the external coolant to enter and exit, and perform forced refrigeration on the plurality of first memory chips 150 to improve the heat dissipation performance of the first memory chips 150.

[0103] Exemplarily, as Figure 17As shown, a first passivation layer 152 and a first metal pad 153 are provided on a first surface of the first memory chip 150 facing the buffer chip 110, and a second passivation layer 154 and a second metal pad 155 are provided on a second surface of the first memory chip 150 facing away from the buffer chip 110.

[0104] The first passivation layer 152 and the second passivation layer 154 in each adjacent two layers of the first memory micro-module A are connected by hybrid bonding, and the first metal pad 153 and the second metal pad 155 in each adjacent two layers of the first memory micro-module A are connected by hybrid bonding.

[0105] Exemplarily, the second passivation layer 154 in the second memory micro-module B is connected by hybrid bonding to the first passivation layer 152 in the underlying first memory micro-module A, and the second metal pad 155 in the second memory micro-module B is connected by hybrid bonding to the first metal pad 153 in the underlying first memory micro-module A.

[0106] Exemplarily, as Figure 17 shown, a third passivation layer 112 and a third metal pad 113 are provided on a surface of the buffer chip 110 facing the second memory micro-module B. The third passivation layer 112 is connected by hybrid bonding to the first passivation layer 152 in the second memory micro-module B, and the third metal pad 113 is connected to the first metal pad 153 in the second memory micro-module B.

[0107] It should be noted that in this embodiment, the materials of the first passivation layer 152, the second passivation layer 154, and the third passivation layer 112 can be silicon dioxide or silicon nitride, or other materials, which are not specifically limited in this embodiment. The materials of the first metal pad 153, the second metal pad 155, and the third metal pad 113 are copper, or other metal materials, which are not specifically limited in this embodiment.

[0108] In this embodiment, as Figure 17 shown, a plurality of protrusions 160 are provided on a side of the buffer chip 110 facing away from the second memory micro-module B. The plurality of protrusions 160 correspond to and are electrically connected to a plurality of conductive vias 111.

[0109] The encapsulation structure of the present invention adjusts the first memory chip to the same size as the buffer chip through the first dummy chip, the second dummy chip and the third dummy chip. The first memory chips and between the first memory chip and the buffer chip are all connected by hybrid bonding, greatly improving the interconnection density. The first cooling through holes, the second cooling through holes and the cooling through grooves which are communicated with each other are arranged on the first dummy chip, the second dummy chip and the third dummy chip, and can be used as channels for the external coolant to enter and exit, realizing forced cooling of the first memory chip, greatly improving the heat dissipation performance of the memory chip, and improving the product characteristics of the memory chip through the coordinated improvement of the electro-thermal performance.

[0110] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A method for packaging a multi-layer stacked memory, characterized in that, The method comprises: A buffer chip, a plurality of first dummy chips, a second dummy chip, a third dummy chip and a plurality of first memory chips are provided, wherein the first dummy chip is provided with a first slot and a plurality of first cooling through holes, the buffer chip is provided with a plurality of first conductive through holes, and the first memory chip is provided with a plurality of second conductive through holes corresponding to the plurality of first conductive through holes; Respectively fixing each of the first memory chips in the first slot of the corresponding first dummy chip to form a plurality of first memory micro-modules; Anodic bonding is performed on the second dummy sheet and the third dummy sheet, so that a second slot is formed at the bonded second dummy sheet and the third dummy sheet corresponding to the first slot, and a second cooling through hole is formed at the third dummy sheet corresponding to the first cooling through hole, wherein the second cooling through hole is connected to the first cooling through hole; Fixing the first memory chip in the second slot to form a second memory micromodule; The second memory micromodule and the plurality of first memory micromodules are sequentially hybrid-bonded and stacked on the buffer chip, wherein the orthographic projections of the second memory micromodule and the first memory micromodule on the buffer chip both overlap with the buffer chip.

2. The method according to claim 1, characterized in that, Before performing anodic bonding on the second dummy sheet and the third dummy sheet, the method further comprises: A cooling through groove is formed on the second dummy plate, and the cooling through groove is communicated with the second cooling through hole.

3. The method according to claim 1, wherein A first passivation layer and a first metal pad are disposed on a first surface of the first memory chip facing the buffer chip, and a second passivation layer and a second metal pad are disposed on a second surface of the first memory chip facing away from the buffer chip; The method of fixing each of the first memory chips in the slot of the corresponding first dummy chip to form a plurality of first memory micro-modules includes: forming a first adhesive between the bottom wall of the first slot and the first surface of the first memory chip to fix the first memory chip in the first slot; forming a second adhesive on the second surface of the first dummy sheet and the first memory chip, and allowing a portion of the second adhesive to fill the first cooling through hole and the gap between the first slot sidewall and the first memory chip; Completely removing the second adhesive glue on the second surface of the first memory chip to expose the second passivation layer and the second metal pad, while retaining a portion of the second adhesive glue on the surface of the first dummy chip; The first adhesive on the first surface of the first memory chip is removed to expose the first passivation layer, the first metal pad and the first cooling through hole to form the first memory micromodule.

4. The method according to claim 3, wherein The method of fixing the first memory chip in the second slot to form a second memory micromodule includes: forming the first adhesive between the bottom wall of the second slot and the first surface of the first memory chip to fix the first memory chip in the second slot; Form the second adhesive on the second surface of the third dummy chip and the first memory chip, and make part of the second adhesive fill into the second cooling through-holes and the gaps between the side walls of the second grooves and the first memory chip; Completely remove the second adhesive on the second surface of the first memory chip to expose the second passivation layer and the second metal pads, while retaining part of the second adhesive on the surface of the third dummy chip; Remove the first adhesive on the first surface of the first memory chip to expose the first passivation layer and the first metal pads, and form the second memory micro-module.

5. The method according to claim 4, wherein A third passivation layer and third metal pads are provided on the side of the buffer chip facing the second memory micro-module; The step of sequentially hybrid bonding and stacking the second memory micro-module and the multiple first memory micro-modules on the buffer chip includes: Bond the first passivation layer of the second memory micro-module to the third passivation layer on the buffer chip, and bond the first metal pads of the second memory micro-module to the third metal pads on the buffer chip; Bond the first passivation layer of the bottom first memory micro-module to the second passivation layer of the second memory micro-module, and bond the first metal pads of the bottom first memory micro-module to the second metal pads of the second memory micro-module; Sequentially hybrid bond and stack the remaining layers of the first memory micro-modules on the second memory micro-module, wherein the first passivation layer and the second passivation layer in each adjacent two layers of the first memory micro-modules are bonded; and the first metal pads and the second metal pads in each adjacent two layers of the first memory micro-modules are bonded.

6. The method according to claim 5, characterized in that, After sequentially hybrid bonding and stacking the second memory micro-module and the multiple first memory micro-modules on the buffer chip, the method further includes: Remove the second adhesive in the first cooling through-holes and the second cooling through-holes.

7. The method according to any one of claims 1 to 6, characterized in that, The surfaces of the first groove and the second groove both protrude from the surface of the first memory chip.

8. A multi-layer stacked memory packaging structure, characterized in that, It includes a buffer chip, multiple first memory micro-modules and a second memory micro-module; The buffer chip is provided with a plurality of first conductive through-holes; The second memory micro-module is hybrid bonded and stacked on the buffer chip, the multiple first memory micro-modules are sequentially hybrid bonded and stacked on the second memory micro-module, and the orthographic projections of the first memory micro-module and the second memory micro-module on the buffer chip both coincide with the buffer chip; wherein, Each of the first memory micro-modules includes a first memory chip and a first dummy chip provided with a first groove and a plurality of first cooling through-holes, the first groove is provided with the first memory chip, and the first memory chip is provided with a plurality of second conductive through-holes corresponding to and electrically connected to the plurality of first conductive through-holes; The second memory micro-module includes a first memory chip, a second dummy chip, and a third dummy chip sandwiched between the first dummy chip and the second dummy chip. Second grooves corresponding to the first grooves are provided on the second dummy chip and the third dummy chip. The first memory chip is disposed in the second grooves. Second cooling through-holes corresponding to and communicating with the first cooling through-holes are provided on the third dummy chip.

9. The encapsulation structure according to claim 8, characterized in that, A cooling through-groove is provided on the second dummy chip, and the cooling through-groove communicates with the second cooling through-holes.

10. The encapsulation structure according to claim 9, wherein A first passivation layer and a first metal pad are provided on a first surface of the first memory chip facing the buffer chip, and a second passivation layer and a second metal pad are provided on a second surface of the first memory chip facing away from the buffer chip. The first passivation layer and the second passivation layer in every two adjacent layers of the first memory micro-modules are connected by hybrid bonding. And, The first metal pad and the second metal pad in every two adjacent layers of the first memory micro-modules are connected by hybrid bonding.

11. The encapsulation structure according to claim 10, wherein, The second passivation layer in the second memory micro-module is connected by hybrid bonding with the first passivation layer in the bottom-layer first memory micro-module; and, The second metal pad in the second memory micro-module is connected by hybrid bonding with the first metal pad in the bottom-layer first memory micro-module.

12. The encapsulation structure according to claim 11, wherein A third passivation layer and a third metal pad are provided on a surface of the buffer chip facing the memory micro-module. The third passivation layer is connected by hybrid bonding with the first passivation layer in the second memory micro-module, and the third metal pad is bonded to the first metal pad in the second memory micro-module.

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