Integrated circuit manufacturing method and integrated circuit

Abstract

Disclosed is a manufacturing method of an integrated circuit and an integrated circuit, comprising: forming an N-type buried layer on a substrate by ion implantation; forming an epitaxial layer on the N-type buried layer; forming an active region and a passive region in the epitaxial layer; forming multiple field oxide layers in the passive region; forming multiple low-voltage N-type wells and multiple low-voltage P-type wells in the epitaxial layer; forming multiple gate structures on the low-voltage N-type well, the low-voltage P-type well and the field oxide layer; forming multiple deep trench isolation structures, the deep trench isolation structures penetrating the epitaxial layer, the N-type buried layer and extending into the substrate. The manufacturing method of the integrated circuit and the integrated circuit of the present application reduce the latch-up effect of the integrated circuit by adopting the process of the back-end deep trench isolation structure, thereby improving the reliability of the integrated circuit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a manufacturing method of an integrated circuit and the integrated circuit. Background Art

[0002] BiCMOS (Bipolar-CMOS) technology is a process technology for monolithically integrating bipolar junction transistors (BJT) and CMOS (complementary metal oxide semiconductor). This process is generally based on the process of embedding bipolar transistors with epitaxy into CMOS devices, thereby realizing a variety of devices and making full use of the various advantages of bipolar devices and unipolar devices. In power integrated circuits (chips), bipolar transistors are widely used due to their rich device types, excellent device parameters, and flexible process flow.

[0003] Conventional BiCMOS technology is still based on common lateral PN junction isolation, which will cause many reliability problems in practical applications. Figure 1 As shown, PN junction isolation will have a greater latch-up (gate lock) problem, and the latch-up path 108 in the figure shows the latch-up problem in the existing integrated circuit. Summary of the invention

[0004] In view of the above problems, an object of the present invention is to provide a method for manufacturing an integrated circuit and an integrated circuit, which can reduce the latch-up effect of the integrated circuit by adopting a back-end deep trench isolation structure process, thereby improving the reliability of the process.

[0005] According to one aspect of the present invention, a method for manufacturing an integrated circuit is provided, comprising: forming an N-type buried layer in a substrate by ion implantation; forming an epitaxial layer on the N-type buried layer; forming an active region and a passive region in the epitaxial layer; forming a plurality of field oxide layers in the passive region; forming a plurality of low-voltage N-type wells and a plurality of low-voltage P-type wells in the epitaxial layer; forming a plurality of gate structures on the low-voltage N-type well, the low-voltage P-type well and the field oxide layer; and forming a plurality of deep trench isolation structures, wherein the deep trench isolation structures penetrate the epitaxial layer, the N-type buried layer and extend into the substrate.

[0006] Optionally, the step of forming multiple deep trench isolation structures includes: forming multiple deep trenches penetrating the epitaxial layer and the N-type buried layer, the bottom of the deep trenches extending into the substrate; filling the deep trenches with a dielectric layer, the dielectric layer covering the sidewalls and bottom of the deep trenches.

[0007] Optionally, after the step of filling the dielectric layer in the deep trench, the method further includes: removing the dielectric layer at the bottom of the deep trench; forming a P-type buried layer in the substrate at the bottom of the deep trench through the deep trench by ion implantation, wherein the P-type buried layer surrounds the bottom of the deep trench.

[0008] Optionally, after the step of forming the P-type buried layer, the method further includes: filling a second polysilicon layer in the deep trench; and performing P-type doping on the second polysilicon layer to form the deep trench isolation structure.

[0009] Optionally, the dielectric layer is filled in the deep trench by low pressure chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition.

[0010] Optionally, the dielectric layer has a thickness of 0.2 μm to 0.5 μm.

[0011] Optionally, the depth of the deep groove ranges from 10 μm to 20 μm, and the width of the deep groove ranges from 0.5 μm to 1.5 μm.

[0012] Optionally, the aspect ratio of the deep groove is 5:1-20:1.

[0013] Optionally, the substrate is a P-type substrate, and the epitaxial layer is an N-type epitaxial layer.

[0014] Optionally, in the step of forming the N-type buried layer in the substrate by ion implantation, no photolithography process is required.

[0015] Optionally, the epitaxial layer has a thickness of 4.0 μm to 6.0 μm.

[0016] Optionally, the gate structure includes a gate oxide layer and a first polysilicon layer.

[0017] Optionally, the doping dose of the first polysilicon layer includes 1.0E13-1.0E14 / cm 2 .

[0018] Optionally, a resistance value of the first polysilicon layer is 1.0 kilohm / square to 4.0 kilohm / square.

[0019] Optionally, between the steps of forming a plurality of gate structures and forming a deep trench isolation structure, the method further includes: forming a plurality of ohmic contact regions in the low voltage N-type well and the low voltage P-type well.

[0020] Optionally, after the step of forming the deep trench isolation structure, it also includes: forming an insulating layer on the multiple gate structures, the multiple ohmic contact regions, the epitaxial layer, the multiple low-voltage N-type wells and the multiple low-voltage P-type wells; forming multiple metal electrodes on the insulating layer, the metal electrodes passing through the insulating layer and respectively contacting the ohmic contact regions or the gate structures; and forming a passivation layer on the metal electrodes.

[0021] Optionally, the deep trench isolation structure further includes the metal electrode in contact with the second polysilicon layer.

[0022] Optionally, the metal electrode in the deep trench isolation structure serves as a grounded lead-out terminal.

[0023] Optionally, the integrated circuit comprises a high-voltage CMOS device, a CMOS device and a bipolar device, and the high-voltage CMOS device, the CMOS device and the bipolar device are separated by the deep trench isolation structure.

[0024] Optionally, the integrated circuit further includes an ED-NMOS device, and the ED-NMOS device, the high-voltage CMOS device, the CMOS device and the bipolar device are separated by the deep trench isolation structure.

[0025] According to another aspect of the present invention, there is provided an integrated circuit, which is formed by the manufacturing method as described above, and includes: a substrate; an N-type buried layer located in the substrate; an epitaxial layer located on the N-type buried layer; a plurality of low-voltage N-type wells, a plurality of low-voltage P-type wells and a plurality of ohmic contact regions located in the epitaxial layer; a plurality of field oxide layers and a plurality of gate structures located on the epitaxial layer; a plurality of deep trench isolation structures located in the epitaxial layer and the substrate; and an insulating layer located on the epitaxial layer and a plurality of metal electrodes penetrating the insulating layer and electrically connected to the ohmic contact regions, the gate structures and the deep trench isolation structures, respectively.

[0026] Optionally, the epitaxial layer has a thickness of 4.0 μm to 6.0 μm.

[0027] The integrated circuit manufacturing method and the integrated circuit provided by the present invention use a deep trench isolation process of afterDTI for lateral isolation in the process flow, have high reliability, can reduce latch-up effect, and thus improve process reliability.

[0028] Furthermore, the integrated circuit and integrated circuit provided by the present invention fill P-type polysilicon in the deep trench isolation structure and directly serve as the lead-out terminal of the ground (GND), which can greatly reduce the isolation rules (isolation size) in the circuit, especially reduce the lateral rules (PN junction isolation size) in the high-voltage device.

[0029] The integrated circuit manufacturing method and integrated circuit provided by the present invention redesign the integrated circuit manufacturing process flow in order to cooperate with the back-end deep trench isolation process. In the new process flow, no photolithography is required to manufacture the N-type buried layer, and only 12 layers of photolithography are required to complete the manufacturing process of the entire integrated circuit, thereby reducing process complexity, improving efficiency, and also reducing process costs.

[0030] Furthermore, the integrated circuit manufacturing method and integrated circuit provided by the present invention have relatively few furnace tube processes in the entire process flow, so that the diffusion of the N-type buried layer into the epitaxial layer is less, and the thickness of the epitaxial layer can be very thin, only 4.0μm~6.0μm, and the production throughput and production efficiency are improved, saving energy.

[0031] The integrated circuit manufacturing method and the integrated circuit provided by the present invention have the advantages of a complete range of devices, good device performance, high process reliability, high process cost performance, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0033] Figure 1 The latch-up problem in the high voltage gate drive according to the prior art is shown;

[0034] Figure 2 A schematic diagram of the principle of truncating the latch effect in an embodiment of the present invention is shown;

[0035] Figure 3 A structural diagram of an integrated circuit according to an embodiment of the present invention is shown;

[0036] Figure 4 A flow chart showing a method for manufacturing an integrated circuit according to an embodiment of the present invention;

[0037] Figure 5a to Figure 5g The diagram shows cross-sectional views of various stages of an integrated circuit manufacturing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0039] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0040] If it is intended to describe a situation where it is directly on another layer or another area, this article will use the expression “directly on…” or “on… and adjacent to…”.

[0041] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.

[0042] Figure 2 A schematic diagram of the principle of cutting off the latch effect in an embodiment of the present invention is shown.

[0043] refer to Figure 2 A deep trench isolation structure is formed between the PN junctions where the latch effect 108 occurs. The deep trench isolation structure includes a deep trench extending into the substrate 301, a dielectric layer 303 on the sidewall of the deep trench, a second polysilicon layer 304 surrounded by the dielectric layer 303, a P-type buried layer 302 surrounding the bottom of the deep trench, and a metal electrode 314 penetrating the insulating layer 316 and connected to the second polysilicon layer 304, wherein the metal electrode 314 serves as a ground (GND) lead. Figure 2 As shown, the latch-up effect is cut off by the deep trench isolation structure, which can enlarge the current path, thereby alleviating the latch-up effect. In addition, due to the isolation effect of the deep trench isolation, the negative voltage problem and dV / dT problem in the actual application of the inductive load can be well alleviated; the second polysilicon layer 304 in the deep trench isolation structure as the grounding lead can greatly reduce the isolation rule, thereby further alleviating the latch-up effect.

[0044] Figure 3 The structure diagram of the integrated circuit according to the embodiment of the present invention is shown.

[0045] refer to Figure 3 The integrated circuit 300 includes: a substrate 301, an N-type buried layer 305 located on the substrate 301, an epitaxial layer 306 located on the N-type buried layer 305, and a CMOS device 320, a high-voltage HVCMOS device 330, and a bipolar device 340 located in the epitaxial layer 306. The CMOS device 320, the high-voltage HVCMOS device 330, and the bipolar device 340 are separated by a deep trench isolation structure.

[0046] In other embodiments, the integrated circuit 300 may also include an ED-NMOS device (extended drain NMOS) 310, wherein the ED-NMOS device 310 is also separated from other devices by a deep trench isolation structure. The several devices listed in this application are all examples, and their positions may also be adjusted accordingly, and are not intended to limit this application. Those skilled in the art should understand that the devices in the integrated circuit 300 are not limited to the several devices in the embodiments, and may also be other devices that can be applied to the integrated circuit and are not mentioned in this embodiment, and the positional relationship between the various devices may also be adjusted according to the specific structure.

[0047] The ED-NMOS device 310 includes a low voltage P-type well 307 and a low voltage N-type well 308 located in the epitaxial layer 306, the low voltage P-type well 307 and the low voltage N-type well 308 are not in contact, and the ohmic contact regions (including the N-type ohmic contact region 312 and the P-type ohmic contact region 311) located in the low voltage P-type well 307 and the low voltage N-type well 308 respectively serve as the source region and / or drain region of the ED-NMOS device. The ED-NMOS device 310 also includes an insulating layer 316 located on the epitaxial layer 306, the low voltage P-type well 307 and the low voltage N-type well 308, and a gate structure 313 located in the insulating layer 316. The gate structure 313 is located on the epitaxial layer 306 and the low voltage P-type well 307. A metal electrode 314 connected to the ohmic contact region and the gate structure 313 is also formed on the insulating layer 316.

[0048] The CMOS device 320 includes a low voltage P-type well 307, a low voltage N-type well 308, a field oxide layer 309, and an N-type ohmic contact region 312 and a P-type ohmic contact region 311 respectively located in the low voltage P-type well 307 and the low voltage N-type well 308 in the epitaxial layer 306. The CMOS device 320 also includes an insulating layer 316 located on the epitaxial layer 306 and the field oxide layer 309, and a gate structure 313 located in the insulating layer 316, wherein the gate structure 313 is located on the low voltage P-type well 307 and the low voltage N-type well 308.

[0049] The high-voltage HVCMOS device 330 includes a plurality of low-voltage P-type wells 307 and a low-voltage N-type well 308 in the epitaxial layer 306, a plurality of field oxide layers 309, and an N-type ohmic contact region 312 and a P-type ohmic contact region 311 respectively located in the low-voltage P-type well 307 and the low-voltage N-type well 308. The high-voltage HVCMOS device 330 also includes a gate structure 313 located on the surface of the epitaxial layer 306, the low-voltage P-type well 307, the low-voltage N-type well 308, and the field oxide layer 309, an insulating layer 316 located on the epitaxial layer 306 and the gate structure 313, and a metal electrode 314 located on the insulating layer 316, wherein the metal electrode 314 is connected to the ohmic contact region and the gate structure 313 respectively via a contact hole 315.

[0050] The bipolar device 340 includes a low voltage P-type well 307 and a low voltage N-type well 308 in the epitaxial layer 306, a plurality of field oxide layers 309, and an N-type ohmic contact region 312 and a P-type ohmic contact region 311 in the low voltage P-type well 307. The bipolar NPN device 340 also includes an insulating layer 316 on the epitaxial layer 306 and the field oxide layer 309. The bipolar device 340 can be an NPN device or a PNP device.

[0051] In this embodiment, the deep trench isolation structure penetrates the epitaxial layer 306 and the N-type buried layer 305, and the bottom reaches the substrate 301. The deep trench isolation structure includes a deep trench, a dielectric layer 303 located on the sidewall of the deep trench, and a second polysilicon layer 304 located in the central area of ​​the deep trench structure, wherein the second polysilicon layer 304 is a P-type polysilicon layer, which directly serves as a lead-out terminal for grounding (GND), which can greatly reduce the isolation rule (isolation size) in the circuit, especially reduce the lateral rule (PN junction isolation size) in the high-voltage device, so as to effectively isolate multiple devices in the integrated circuit 100, reduce the latch effect, and improve the reliability of the integrated circuit.

[0052] Preferably, a P-type buried layer 302 is formed at the bottom of the deep trench isolation structure 303 to further improve the isolation effect between devices.

[0053] The above device structures are merely exemplary and are not intended to limit the present application. Those skilled in the art should understand that the specific structures of the above devices may be adjusted according to actual applications.

[0054] Figure 4 The flowchart of the method for manufacturing an integrated circuit according to the embodiment of the present invention is shown. Figure 5a to Figure 5g The invention shows cross-sectional views of various stages of a method for manufacturing an integrated circuit according to an embodiment of the present invention.

[0055] Step S01: forming an N-type buried layer in a substrate.

[0056] refer to Figure 5a , ion implantation is performed on the surface of the substrate 301, thereby forming an N-type buried layer (Buried-Layer) 305. Wherein, when forming the N-type buried layer 305, no photolithography process is required, and the surface of the entire substrate 301 is formed by an implantation process, and the N-type buried layer 305 is activated by push-junction after ion implantation, and the push-junction activation adopts a high-temperature annealing process, for example. In this embodiment, the main function of the N-type buried layer 305 is to reduce the collector series resistance and provide a floating substrate for high-voltage devices.

[0057] In this embodiment, the substrate 301 is, for example, a P-type substrate.

[0058] Step S02: forming an epitaxial layer on the N-type buried layer.

[0059] refer to Figure 5a , an epitaxial layer 306 is formed on the N-type buried layer 305 .

[0060] In this embodiment, an epitaxial layer 306 is formed on the N-type buried layer 305 by an epitaxial process.

[0061] In this embodiment, the epitaxial layer 306 is, for example, an N-type epitaxial layer, the material of which is, for example, single crystal silicon, and the thickness of which is, for example, 4.0 μm to 6.0 μm.

[0062] Step S03: photolithography to form an active area and a field oxide layer.

[0063] refer to Figure 5b An active region and an inactive region are formed on the surface of the epitaxial layer 306 by photolithography, and a field oxide layer 309 is formed by a thermal oxidation process, wherein the field oxide layer 309 is a local oxidation isolation of silicon (LOCOS).

[0064] Step S04: forming a low-voltage N-type well and a low-voltage P-type well in the epitaxial layer.

[0065] refer to Figure 5c , a plurality of low-voltage N-type wells 308 and a low-voltage P-type well 307 are formed in the epitaxial layer 306 .

[0066] In this embodiment, ion implantation windows are defined on the surface of the semiconductor structure by photolithography, and then N-type dopants, such as phosphorus, and P-type dopants, such as boron, are implanted by high-energy ions to form a plurality of low-voltage N-type wells 308 and low-voltage P-type wells 307.

[0067] In this embodiment, the low voltage N-type well 308 and the low voltage P-type well 307 are located in the epitaxial layer 306 and are used as wells for various devices.

[0068] Step S05: forming a plurality of gate structures.

[0069] refer to Figure 5d , a plurality of gate structures 313 are formed on the surface of the semiconductor structure.

[0070] In this embodiment, the gate structure 313 includes a gate oxide layer and a first polysilicon layer. In this step, a thin gate oxide layer is first formed on the surface of the semiconductor structure by a thermal oxidation process, and then a first polysilicon layer is formed on the surface of the gate oxide layer, and the first polysilicon layer is doped. Furthermore, the gate oxide layer and the doped first polysilicon layer are etched and patterned.

[0071] In this embodiment, the doping dose of the first polysilicon layer is 1.0E13-1.0E14 / cm2 , thus forming a high value resistor (1.0 kiloohm / square ~ 4.0 kiloohm / square).

[0072] Step S06: forming a plurality of ohmic contact regions.

[0073] refer to Figure 5e , an ion implantation window is formed by photolithography, and at least one ohmic contact region is formed in each of the plurality of low-voltage N-type wells 308 and the low-voltage P-type well 307 by ion implantation, wherein the ohmic contact region includes an N-type ohmic contact region 312 and a P-type ohmic contact region 311 .

[0074] In this embodiment, the N-type ohmic contact region 312 is, for example, an N+-doped N-type ohmic contact region, and the P-type ohmic contact region 311 is, for example, a P+-doped P-type ohmic contact region.

[0075] Step S07: forming a deep trench isolation structure.

[0076] refer to Figure 5f , a plurality of deep trench isolation structures are formed in the epitaxial layer 306 and the substrate 301 .

[0077] In this embodiment, the deep trench isolation structure penetrates the epitaxial layer 306 and the N-type buried layer 305 and extends into the substrate 301 , separating the epitaxial layer 306 , the N-type buried layer 305 and the substrate 301 into multiple regions to separate devices in different regions.

[0078] In this embodiment, for example, a mask layer is formed on the surface of the semiconductor structure, and then anisotropic etching is performed to form a deep groove in the semiconductor structure, and the deep groove penetrates the epitaxial layer 306 and the N-type buried layer 305 and extends into the substrate 301. Anisotropic etching can be performed by dry etching, such as ion milling etching, plasma etching, reactive ion etching, and laser ablation. For example, by controlling the etching time, the etching stops in the substrate 301. In this embodiment, the depth of the formed deep groove is 10 μm to 20 μm, the width is 0.5 μm to 1.5 μm, and the aspect ratio is, for example, 5:1 to 20:1.

[0079] Furthermore, after forming the deep trench, a sacrificial oxidation step is also included to reduce the impact on the thermal process of the front-end process. In this step, the RTO (rapid thermal oxidation) process is generally used.

[0080] Furthermore, the process further includes filling the dielectric layer 303 in the deep groove. In this embodiment, the dielectric layer 303 is filled by using the LPTEOS (low pressure chemical vapor deposition tetraethyl orthosilicate) process or the SA-CVD (sub-atmospheric pressure chemical vapor deposition) process, and the dielectric layer 303 formed in this way has the characteristics of good film quality and uniformity, high yield and low cost. In this step, the thickness of the dielectric layer 303 is 0.2 μm to 0.5 μm.

[0081] Furthermore, the step of removing the dielectric layer 303 at the bottom of the deep trench is included. In the step of filling the dielectric layer 303 in the deep trench, the dielectric layer 303 covers the sidewall and bottom of the deep trench, so the dielectric layer 303 at the bottom of the deep trench can be removed by anisotropic etching process to expose the substrate 301 at the bottom of the deep trench.

[0082] Furthermore, it also includes forming a P-type buried layer 302 in the substrate 301 at the bottom of the deep trench through the deep trench. In this step, the deep trench serves as a channel for ion implantation, and P-type ions are implanted at the bottom of the deep trench through the self-masking effect of the oxide layer (dielectric layer 303), thereby forming a P-type buried layer 302, and the P-type buried layer 302 surrounds the bottom of the deep trench. The P-type buried layer 302 is used to improve the isolation effect of the process.

[0083] Furthermore, the method further includes filling the deep trench with a second polysilicon layer 304, such as Figure 5f shown.

[0084] In this step, a second polysilicon layer 304 is deposited in the cavity of the dielectric layer 303 in the deep trench, and the second polysilicon layer 304 is doped with P type, so that the second polysilicon layer 304 is a P type polysilicon layer. The upper surface of the second polysilicon layer 304 is lower than the surface of the epitaxial layer 306, and then a dielectric layer is deposited again on the upper surface of the second polysilicon layer 304, so that the dielectric layer 303 on the side wall of the deep trench and the dielectric layer on the upper surface of the second polysilicon layer 304 surround the second polysilicon layer 304. Figure 5f In and after, the dielectric layer on the sidewall of the deep trench and the dielectric layer on the upper surface of the second polysilicon layer 304 are collectively shown as a dielectric layer 303 .

[0085] Step S08: forming an insulating layer and a metal electrode.

[0086] refer to Figure 5g , an insulating layer 316 is formed on the surface of the semiconductor structure, a contact hole 315 is formed in the insulating layer 316 , and a metal electrode 314 is formed on the insulating layer 316 .

[0087] In this embodiment, for example, an insulating layer 316 is formed on the surface of the semiconductor structure by a chemical vapor deposition process, a plurality of contact holes 315 are formed in the insulating layer 316 by a photolithography process, a metal material is deposited on the insulating layer 316 and in the contact holes 315, and the metal material on the surface of the insulating layer 316 is patterned to form a metal electrode 314.

[0088] In this embodiment, the metal electrode 314 penetrates the insulating layer 316 through the conductive channel 315, and is respectively connected to the N-type ohmic contact region 312, the P-type ohmic contact region 311 and the gate structure 313. Further, the metal electrode 314 also penetrates the insulating layer 316 and the dielectric layer 303 on the upper surface of the second polysilicon layer 304 through the conductive channel 315 and is connected to the second polysilicon layer 304 in the deep trench isolation structure. That is, the deep trench isolation structure also includes a metal electrode 314 connected to the second polysilicon layer 304 in the deep trench isolation structure, wherein the metal electrode 314 connected to the second polysilicon layer 304 is directly used as the lead-out terminal of the ground (GND), which can greatly reduce the isolation rule.

[0089] Furthermore, a passivation layer and a second metal layer are formed on the metal electrode 314 and the insulating layer 316. The method of forming the passivation layer and the second metal layer is a conventional technical means in the art and will not be described in detail here.

[0090] The integrated circuit and the integrated circuit provided by the present invention adopt a deep trench isolation process after DTI for lateral isolation, have high reliability, can reduce the latch effect, and thus improve the reliability of the integrated circuit.

[0091] Furthermore, the integrated circuit and integrated circuit provided by the present invention fill P-type polysilicon in the deep trench isolation structure and directly serve as the lead-out terminal of the ground (GND), which can greatly reduce the isolation rules (isolation size) in the circuit, especially reduce the lateral rules (PN junction isolation size) in the high-voltage device.

[0092] The integrated circuit manufacturing method and integrated circuit provided by the present invention redesign the integrated circuit manufacturing process flow in order to cooperate with the back-end deep trench isolation process. In the new process flow, no photolithography is required to manufacture the N-type buried layer, and only 12 layers of photolithography are required to complete the manufacturing process of the entire integrated circuit, thereby reducing process complexity, improving efficiency, and also reducing process costs.

[0093] Furthermore, the integrated circuit manufacturing method and integrated circuit provided by the present invention have relatively few furnace tube processes in the entire process flow, so that the diffusion of the N-type buried layer into the epitaxial layer is less, so that the thickness of the epitaxial layer can be very thin, only 4.0μm~6.0μm, and the production throughput and production efficiency are improved, saving energy.

[0094] The integrated circuit manufacturing method and the integrated circuit provided by the present invention have the advantages of a complete range of devices, good device performance, high process reliability, high process cost performance, etc.

[0095] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing an integrated circuit, characterized in that: include: forming an N-type buried layer in the substrate by ion implantation; forming an epitaxial layer on the N-type buried layer; forming an active region and an inactive region in the epitaxial layer; forming a plurality of field oxide layers in the inactive region; forming a plurality of low-voltage N-type wells and a plurality of low-voltage P-type wells in the epitaxial layer; forming a plurality of gate structures on the low voltage N-type well, the low voltage P-type well and the field oxide layer; forming a plurality of deep trench isolation structures, wherein the deep trench isolation structures penetrate the epitaxial layer, the N-type buried layer and extend into the substrate, The deep trench isolation structure includes a deep trench, a dielectric layer located in the deep trench, and a second polysilicon layer located in a central area of ​​the deep trench.

2. The method for manufacturing an integrated circuit according to claim 1, wherein: The steps of forming a plurality of deep trench isolation structures include: forming a plurality of deep trenches penetrating the epitaxial layer and the N-type buried layer, wherein the bottoms of the deep trenches extend into the substrate; A dielectric layer is filled in the deep trench, and the dielectric layer covers the sidewall and the bottom of the deep trench.

3. The method for manufacturing an integrated circuit according to claim 2, wherein: After the step of filling the dielectric layer in the deep trench, the method further comprises: removing the dielectric layer at the bottom of the deep trench; A P-type buried layer is formed in the substrate at the bottom of the deep trench by ion implantation through the deep trench, and the P-type buried layer surrounds the bottom of the deep trench.

4. The method for manufacturing an integrated circuit according to claim 3, wherein: After the step of forming the P-type buried layer, the method further comprises: Filling a second polysilicon layer in the deep trench; The second polysilicon layer is doped with P type to form the deep trench isolation structure.

5. The method for manufacturing an integrated circuit according to claim 2, wherein: A dielectric layer is filled in the deep trench by low pressure chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition.

6. The method for manufacturing an integrated circuit according to claim 2, wherein: The thickness of the dielectric layer is 0.2 μm to 0.5 μm.

7. The method for manufacturing an integrated circuit according to claim 2, wherein: The depth of the deep grooves ranges from 10 μm to 20 μm, and the width of the deep grooves ranges from 0.5 μm to 1.5 μm.

8. The manufacturing method according to claim 2, wherein: The aspect ratio of the deep groove is 5:1-20:

1.

9. The method for manufacturing an integrated circuit according to claim 1, wherein: The substrate is a P-type substrate, and the epitaxial layer is an N-type epitaxial layer.

10. The method for manufacturing an integrated circuit according to claim 1, wherein: In the step of forming the N-type buried layer in the substrate by ion implantation, no photolithography process is required.

11. The method for manufacturing an integrated circuit according to claim 1, wherein: The thickness of the epitaxial layer is 4.0 μm to 6.0 μm.

12. The method for manufacturing an integrated circuit according to claim 1, wherein: The gate structure includes a gate oxide layer and a first polysilicon layer.

13. The method for manufacturing an integrated circuit according to claim 12, wherein: The doping dose of the first polysilicon layer includes 1.0E13-1.0E14 / cm 2 .

14. The method for manufacturing an integrated circuit according to claim 12, wherein: The resistance value of the first polysilicon layer is 1.0 kilohm / square to 4.0 kilohm / square.

15. The method for manufacturing an integrated circuit according to claim 4, wherein: Between the steps of forming a plurality of gate structures and forming a deep trench isolation structure, the method further includes: A plurality of ohmic contact regions are formed in the low voltage N-type well and the low voltage P-type well.

16. The method for manufacturing an integrated circuit according to claim 15, wherein: After the step of forming the deep trench isolation structure, the method further comprises: forming an insulating layer on the plurality of gate structures, the plurality of ohmic contact regions, the epitaxial layer, the plurality of low-voltage N-type wells, and the plurality of low-voltage P-type wells; forming a plurality of metal electrodes on the insulating layer, wherein the metal electrodes penetrate the insulating layer and are in contact with the ohmic contact region or the gate structure respectively; A passivation layer is formed on the metal electrode.

17. The method for manufacturing an integrated circuit according to claim 16, wherein: The deep trench isolation structure further includes the metal electrode contacting the second polysilicon layer.

18. The method for manufacturing an integrated circuit according to claim 17, wherein: The metal electrode in the deep trench isolation structure serves as a grounded lead-out terminal.

19. The method for manufacturing an integrated circuit according to claim 1, wherein: The integrated circuit comprises a high-voltage CMOS device, a CMOS device and a bipolar device, and the high-voltage CMOS device, the CMOS device and the bipolar device are separated by the deep trench isolation structure.

20. The method for manufacturing an integrated circuit according to claim 19, wherein: The integrated circuit also includes an ED-NMOS device, and the ED-NMOS device, the high-voltage CMOS device, the CMOS device and the bipolar device are separated by the deep trench isolation structure.

21. An integrated circuit formed by the method for manufacturing an integrated circuit according to any one of claims 1 to 20, comprising: substrate; an N-type buried layer located in the substrate; an epitaxial layer located on the N-type buried layer; A plurality of low-voltage N-type wells, a plurality of low-voltage P-type wells and a plurality of ohmic contact regions located in the epitaxial layer; A plurality of field oxide layers and a plurality of gate structures located on the epitaxial layer; A plurality of deep trench isolation structures located in the epitaxial layer and the substrate, the deep trench isolation structures comprising a dielectric layer located in the deep trench and a second polysilicon layer located in a central region of the deep trench; as well as An insulating layer is located on the epitaxial layer, and a plurality of metal electrodes penetrate the insulating layer and are electrically connected to the ohmic contact region, the gate structure and the deep trench isolation structure respectively.

22. The integrated circuit of claim 21, wherein: The thickness of the epitaxial layer is 4.0 μm to 6.0 μm.

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