Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. The semiconductor device according to the embodiment includes a semiconductor substrate having a first surface on which semiconductor elements are provided and a second surface located on the side opposite to the first surface. A metal electrode is provided in a through hole that penetrates the semiconductor substrate between the first surface and the second surface. A first insulating film is provided on the first surface side of the semiconductor substrate and, when viewed from above the first surface, protrudes radially from the opening end portion on the second surface side of the through hole toward the center of the through hole. A second insulating film protrudes radially from the first insulating film when viewed from above the first surface, is thinner than the film thickness of the first insulating film, and is in contact with the metal electrode. A third insulating film is provided between the inner wall of the through hole and the metal electrode and includes a first portion that contacts the first insulating film and a second portion that is in contact with the inner wall of the through hole and is closer to the second surface side than the first portion.

Description

[0001] [Related Application Cases]

[0002] This application claims priority based on Japanese Patent Application No. 2020-153229 (filing date: September 11, 2020). This application incorporates the entire content of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0004] The industry has developed a semiconductor device in which a plurality of semiconductor chips are stacked and packaged. In such a semiconductor device, in order to electrically connect the stacked plurality of semiconductor chips, through electrodes called TSVs (Through-Silicon Vias) are sometimes provided on the semiconductor chips.

[0005] On the other hand, in order to reduce the thickness of the semiconductor device, it is conceivable to reduce the thickness of the substrate of each semiconductor chip. However, if the thickness of the substrate of the semiconductor chip is reduced, the aspect ratio of the TSV decreases. As a result, the thickness of the insulating film used as a mask when the TSV is opened is the same on the upper surface of the semiconductor chip and the bottom surface of the TSV. In this case, it is difficult to selectively remove the insulating film located at the bottom surface of the TSV, and the opening at the bottom of the TSV becomes smaller. A smaller opening of the TSV results in a higher connection resistance between the semiconductor chips due to the TSV. Summary of the Invention

[0006] Embodiments provide a semiconductor device and a method for manufacturing the same that can both reduce the package thickness and connect between semiconductor chips with a sufficiently low resistance.

[0007] The semiconductor device of the present embodiment includes a semiconductor substrate having a first surface on which semiconductor elements are provided and a second surface on the opposite side of the first surface. A metal electrode is provided in a through hole that penetrates the semiconductor substrate between the first surface and the second surface. A first insulating film is provided on the first surface side of the semiconductor substrate and protrudes radially from the opening end on the second surface side of the through hole toward the center of the through hole when viewed from above the first surface. A second insulating film protrudes radially from the first insulating film when viewed from above the first surface, is thinner than the film thickness of the first insulating film, and is in contact with the metal electrode. A third insulating film is provided between the inner wall of the through hole and the metal electrode and includes a first portion that contacts the first insulating film and a second portion that is in contact with the inner wall of the through hole and is closer to the second surface side than the first portion. Description of the Drawings

[0008] Figure 1It is a cross-sectional view showing a configuration example of the semiconductor device of the present embodiment.

[0009] Figure 2 It is a cross-sectional view showing a configuration example of a through electrode.

[0010] Figure 3 It is a top view showing a configuration example of a through electrode.

[0011] Figure 4 It is a cross-sectional view showing a configuration example of a through electrode.

[0012] Figures 5 to 13 It is a cross-sectional view showing an example of a manufacturing method of a semiconductor device.

[0013] Figure 14 It is a cross-sectional view in the middle of the manufacturing steps of a semiconductor device showing a variation example of the present embodiment. Detailed Embodiment

[0014] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The present embodiments do not limit the present invention. In the following embodiments, the up-down direction of the semiconductor substrate represents the relative direction when the surface on which the semiconductor elements are provided is regarded as the upper or lower surface, and may be different from the up-down direction according to the gravitational acceleration. The accompanying drawings are schematic or conceptual diagrams, and the ratios of the respective parts are not necessarily the same as the actual ones. In the specification and the accompanying drawings, the same reference numerals are assigned to the elements that are the same as those described above with respect to the previously presented drawings, and the detailed description is appropriately omitted.

[0015] Figure 1 It is a cross-sectional view showing an example of the configuration of the semiconductor device 1 of the present embodiment. The semiconductor device 1 is not particularly limited. For example, it may be a logic circuit (CMOS (Complementary Metal Oxide Semiconductor) circuit) for controlling a NAND (Not AND) type flash memory or the like. In addition, the semiconductor device 1 can be electrically connected to the memory cell array by bonding to a semiconductor wafer on which a memory cell array (not shown) is mounted. Alternatively, the semiconductor device 1 can also be electrically connected to the memory cell array via Figure 1 the through electrode TSV (Through-Silicon Via) shown. The semiconductor device 1 can be provided below a memory cell array (not shown). That is, the semiconductor device 1 can be a semiconductor wafer or a semiconductor chip formed separately from the memory wafer or the memory chip, or can be a semiconductor wafer or a semiconductor chip formed integrally with the memory wafer or the memory chip.

[0016] This semiconductor device 1 includes a very low voltage transistor VLV (Very low Voltage Transistor), a low voltage transistor LV (Low Voltage Transistor), a high voltage transistor HV (High Voltage Transistor), etc. as logic circuits. Figure 1 Among them, the very low voltage transistor VLV, the low voltage transistor LV, the high voltage transistor HV, and the through electrode TSV are sequentially shown from the left. In addition, the semiconductor device 1 may further include various semiconductor elements such as transistors.

[0017] Hereinafter, the configuration of the semiconductor device 1 will be described in more detail.

[0018] The semiconductor device 1 includes a semiconductor substrate 10, a well diffusion layer 15, an STI (Shallow Trench Isolation) 20, gate insulating films 30-32, a spacer layer 40, a gate electrode 60, a metal film 65, an upper coating film 70, an interlayer insulating film 80, a via hole 90, a termination film 77, a barrier metal 99, a metal electrode 100, and a bump 110.

[0019] The semiconductor substrate 10 is, for example, a thinned silicon substrate. The semiconductor substrate 10 has a first surface F1 and a second surface F2 located on the opposite side of the first surface F1. The very low voltage transistor VLV, the low voltage transistor LV, and the high voltage transistor HV are provided on the first surface F1 of the semiconductor substrate 10. In addition, a through hole that penetrates between the first surface F1 and the second surface F2 is provided in the semiconductor substrate 10, and a metal electrode 100 is provided inside the through hole.

[0020] In addition, in the present embodiment, the direction perpendicular to the first or second surface F1, F2 of the semiconductor substrate 10 is defined as the Z direction. One direction in the plane perpendicular to the Z direction is defined as the X direction, and the direction perpendicular to the X direction in the perpendicular plane is defined as the Y direction. Figure 1 The semiconductor device 1 is shown with the direction from the second surface F2 toward the first surface F1 in the Z direction as the upper direction. However, in the description of the through electrode TSV, the direction from the first surface F1 toward the second surface F2 may be defined as the upper direction for explanation.

[0021] A STI (Shallow Trench Isolation) 20, serving as the first insulating film, is provided on a first surface F1 of a semiconductor substrate 10. The STI 20 defines a working area for forming elements on the first surface F1 and electrically isolates adjacent working areas. Semiconductor elements such as a memory cell array, transistors, resistance elements, and capacitor elements are formed in the working areas. The STI 20 uses, for example, a silicon oxide film formed by a CVD (Chemical Vapor Deposition) method or the like.

[0022] A well diffusion layer 15 is provided in the working area. Gate insulating films 30 - 32 are provided on the well diffusion layer 15 and function as gate insulating films for an ultra-low voltage transistor VLV, a constant voltage transistor LV, and a high voltage transistor HV, respectively. The gate insulating films 30 - 32 use, for example, a thermal oxide film formed by oxidizing the semiconductor substrate 10.

[0023] The thickness of the gate insulating film 30 is the thinnest, followed by the gate insulating film 31 with a relatively thin thickness, and the gate insulating film 32 is the thickest. Thus, the threshold voltage and breakdown voltage of the ultra-low voltage transistor VLV are the lowest. Next, the threshold voltage and breakdown voltage of the low voltage transistor LV are relatively low. The threshold voltage and breakdown voltage of the high voltage transistor HV are the highest. The structures of the ultra-low voltage transistor VLV, the low voltage transistor LV, and the high voltage transistor HV other than the gate insulating films 30 - 32 can be the same. Thus, the ultra-low voltage transistor VLV, the low voltage transistor LV, and the high voltage transistor HV can be formed simultaneously using common manufacturing steps for the structures other than the gate insulating films 30 - 32.

[0024] Gate electrodes 60 are respectively provided on the gate insulating films 30 - 32 and are electrically insulated from the well diffusion layer 15 of the semiconductor substrate 10 through the gate insulating films 30 - 32. The gate electrodes 60 use, for example, a conductive material such as doped polysilicon. A metal film 65 is provided on the gate electrodes 60. The metal film 65 uses, for example, a low-resistance metal compound such as tungsten silicide (WSi). A capping film 70 is provided on the metal film 65. The capping film 70 uses an insulating material such as a silicon nitride film.

[0025] Sidewall films 75 are provided on the sides of the gate electrodes 60, the metal film 65, and the capping film 70. The sidewall films 75 use, for example, an insulating material such as a silicon oxide film. Furthermore, a liner layer 76 is provided so as to cover the outside of the sidewall films 75. The liner layer 76 uses, for example, an insulating material such as a silicon nitride film.

[0026] The interlayer insulating film 80 is provided on the first surface F1 of the semiconductor substrate 10 so as to cover the ultra-low voltage transistor VLV, the low voltage transistor LV, and the high voltage transistor HV. The interlayer insulating film 80 is, for example, a silicon oxide film formed using TEOS (TetraEthOxySilane). The termination film 77 is provided on top of the upper covering film 70 within the interlayer insulating film 80. The upper covering film 70 is, for example, an insulating film such as a silicon nitride film.

[0027] The via hole 90 penetrates through the interlayer insulating film 80 and the termination film 77 and is electrically connected to the ultra-low voltage transistor VLV, the low voltage transistor LV, and the high voltage transistor HV. The via hole 90 is, for example, made of a low-resistance metal such as tungsten.

[0028] In this way, the ultra-low voltage transistor VLV, the low voltage transistor LV, and the high voltage transistor HV are formed. The ultra-low voltage transistor VLV, the low voltage transistor LV, and the high voltage transistor HV differ in the thickness of the gate insulating films 30 - 32, while other configurations can be the same. Of course, in actual use, the ultra-low voltage transistor VLV, the low voltage transistor LV, and the high voltage transistor HV can also have different dimensions (gate width W / gate length L), impurity concentrations in the channel regions of the well diffusion layers 15, materials of the gate electrodes, etc.

[0029] In the case where the memory cell array includes a plurality of memory cells capable of writing or erasing data, the high voltage transistor HV can be a transistor for applying a write voltage or an erase voltage to the memory cells.

[0030] Next, the structure of the through electrode TSV will be described in more detail.

[0031] Figure 2 It is a cross-sectional view showing a configuration example of the through electrode TSV. Figure 2 Indicates making Figure 1 The state where the through electrode TSV is inverted in the vertical direction.

[0032] The through electrode TSV includes the semiconductor substrate 10, STI 20, gate insulating film 32, spacer layer 40, barrier metal 99, metal electrode 100, bump 110, gate electrode (electrode pad) 60, metal film 65, upper covering film 70, termination film 77, interlayer insulating film 80, and via hole 90.

[0033] A via BV is provided in a semiconductor substrate 10, and the via is provided between a first surface F1 and a second surface F2. The via BV is formed from the second surface F2 toward the first surface F1, and a gate electrode 60 is provided at the bottom. When viewed from the second surface F2 side in a plan view, the via BV is provided within the range of the gate electrode 60, and the gate electrode 60 or the metal film 65 is exposed over the entire bottom of the via BV. In addition, the gate electrode 60 of the via electrode TSV functions as an electrode pad for electrically connecting between the plug hole 90 and the metal electrode 100, rather than functioning as a gate electrode.

[0034] A spacer layer 40 is provided on the inner wall of the via BV and a part of the second surface F2 of the semiconductor substrate 10. The spacer layer 40 is interposed between the semiconductor substrate 10 and the barrier metal 99 to electrically insulate between the semiconductor substrate 10 and the barrier metal 99. The spacer layer 40 is formed of, for example, a silicon oxide film formed using TEOS (TetraEthOxySilane), a silicon oxide film with hydrogen, silicon nitride, silicon oxynitride, or a laminated film of two or more of them.

[0035] The barrier metal 99 is provided on the inner wall of the via BV with the spacer layer 40 interposed therebetween. In addition, the barrier metal 99 contacts the gate electrode 60 or the metal film 65 at the bottom of the via BV. The barrier metal 99 is formed of, for example, a conductive material such as titanium or titanium nitride.

[0036] Furthermore, the metal electrode 100 is filled in the via BV. That is, the metal electrode 100 is provided in the via BV that penetrates the semiconductor substrate 10 between the first surface F1 and the second surface F2. The metal electrode 100 is electrically connected to the gate electrode 60 via the barrier metal 99. On the other hand, as Figure 1 shown, the via BV may penetrate the gate electrode 60 up to the metal film 65, and in this case, the metal electrode 100 is electrically connected to the metal film 60 via the barrier metal 99. The metal electrode 100 is formed of, for example, a low-resistance metal such as copper, nickel, or aluminum. A bump 110 is provided under the metal electrode 100. The bump 110 is formed of, for example, a low-resistance metal such as solder or tin. In addition, the barrier metal 99 is so thin as to be negligible compared to the metal electrode 100 and can be regarded as integral with the metal electrode 100. Therefore, the barrier metal 99 and the metal electrode 100 are sometimes collectively referred to as the metal electrode 100.

[0037] At the bottom of the through-hole BV, the gate electrode 60 is disposed on the metal electrode 100 and the barrier metal 99. The structures of the metal film 65, the upper covering film 70, the termination film 77, the interlayer insulating film 80, and the via hole 90 disposed on the gate electrode 60 can be the same as those in the ultra-low voltage transistor VLV, the low voltage transistor LV, and the high voltage transistor HV. However, in a plan view observed from the Z direction, the planar layout of the gate electrode 60, the metal film 65, and the upper covering film 70 in the through electrode TSV can be different from their planar layouts in the ultra-low voltage transistor VLV, the low voltage transistor LV, and the high voltage transistor HV. For example, the area of the gate electrode 60 and the like in the through electrode TSV can be larger than the area of the gate electrode 60 and the like in the ultra-low voltage transistor VLV, the low voltage transistor LV, and the high voltage transistor HV. In this case, as Figure 1 shown, a plurality of via holes 90 can be disposed above the gate electrode 60. Thereby, a wiring (not shown) disposed above the via hole 90 can be electrically connected to the gate electrode 60 with low resistance. In addition, the gate electrode 60 and the metal film 65 function as a wiring or a plug for electrically connecting between the via hole 90 and the metal electrode 100, rather than functioning as a gate electrode in the through electrode TSV. In addition, the lower surface of the gate electrode 60 can include a first electrode surface U1 facing the first surface F1 side, and a second electrode surface U2 located closer to the center side of the through-hole than the first electrode surface U1 and closer to the first surface F1 side than the first electrode surface U1. The first electrode surface U1 can be in contact with the STI 20, and the second electrode surface U2 can be in contact with the gate insulating film 32.

[0038] Although not shown, in the through electrode TSV, sidewall films 75 and cushion layers 76 can be disposed on the side surfaces of the gate electrode 60, the metal film 65, and the upper covering film 70. The structures of the sidewall films 75 and the cushion layers 76 of the through electrode TSV can be the same as those in the ultra-low voltage transistor VLV, the low voltage transistor LV, and the high voltage transistor HV.

[0039] Furthermore, the interlayer insulating film 80 is disposed on the first surface F1 of the semiconductor substrate 10 so as to cover the structure on the first surface F1 side of the through electrode TSV. The termination film 77 is disposed on the upper covering film 70 within the interlayer insulating film 80.

[0040] As described above, a plurality of via holes 90 penetrate the interlayer insulating film 80 and the termination film 77 and are electrically connected to the gate electrode 60 of the through electrode TSV. The structures of the interlayer insulating film 80 and the via hole 90 can also be the same as those in the ultra-low voltage transistor VLV, the low voltage transistor LV, and the high voltage transistor HV.

[0041] Here, the shapes and positional relationships of the STI 20, the gate insulating film 32, the spacer layer 40, and the through-hole BV in the through electrode TSV will be described.

[0042] As Figure 1 and Figure 2 shown, for element isolation, the STI 20 is provided at a relatively deep position within the semiconductor substrate 10 from the first surface F1. The STI 20 of the through electrode TSV is provided so as to surround the through hole BV along the outer edge of the formation region of the through hole BV. Therefore, in a plan view observed from above the first surface F1, the outer edge of the through hole BV overlaps the STI 20. Accordingly, when forming the through hole BV, a part of the through hole BV is formed self-aligned with the outer edge of the STI 20. Thus, a part of the inner wall of the through hole BV is constituted by the STI 20, and another part of the inner wall of the through hole BV is constituted by the semiconductor substrate 10. Thus, in a plan view observed from above the first surface F1, the STI 20 protrudes in the radial direction ( Figure 2 the A direction) toward the center of the through hole BV from the outer edge or the inner wall of the through hole BV.

[0043] Within the region surrounded by the STI 20 of the through electrode TSV, the STI 20 is not provided, and the gate insulating film 32 is provided along the inner circumference of the STI 20. Therefore, in a plan view observed from above the first surface F1, the gate insulating film 32 protrudes or extends in the radial direction toward the center of the through hole BV from the inner circumference of the STI 20. Accordingly, the gate insulating film 32 is provided inside them along the inner circumferences of the through hole BV and the STI 20 (see Figure 3 and Figure 4 ). Further, compared with the gate insulating film 32, the STI 20 protrudes or extends more in the direction from the second surface F2 toward the first surface F1 (see Figure 1 and Figure 2 ).

[0044] The gate insulating film 32 has the same thickness as the gate insulating film 32 of the high-voltage transistor HV, and is thicker than the gate insulating films 30 and 31 of the ultra-low-voltage transistor VLV and the low-voltage transistor LV. However, the thickness of the gate insulating film 32 is much thinner than the thickness of the STI 20 for element isolation. For example, the thickness of the gate insulating film 30 is about 2 to 7 nm, the thickness of the gate insulating film 31 is about 5 to 15 nm. Further, the thickness of the gate insulating film 32 is about 20 nm to 60 nm, and the thickness of the STI 20 is about 300 nm or more.

[0045] As a result, since the thickness of the gate insulating film 32 is thicker than those of the gate insulating films 30 and 31, the gate insulating film 32 can function as an etch stop layer when forming the through hole BV. On the other hand, since the thickness of the gate insulating film 32 is thinner than that of the STI 20, it is not necessary to make the thickness of the spacer layer 40 used as a mask when forming the through hole BV very thick. The reason is that if the thickness of the gate insulating film 32 is thin, even if the thickness of the spacer layer 40 used as a mask is thinned, the gate insulating film 32 at the bottom of the through hole BV can be sufficiently removed by etch back. By thinning the spacer layer 40, the opening diameter of the through hole BV on the first surface F1 side can be enlarged, and as a result, the contact area between the metal electrode 100 or the barrier metal 99 and the gate electrode 60 is increased, and the contact resistance between the through electrode TSV and the gate electrode 60 is reduced. In addition, the method of forming the through hole BV will be described in more detail later.

[0046] The spacer layer 40 is provided between the inner wall of the through hole BV and the metal electrode 100, and electrically separates the semiconductor substrate 10 from the through electrode TSV. In addition, when forming the through hole BV, the spacer layer 40 functions as a mask during the removal of the gate insulating film 32 at the bottom of the through hole BV.

[0047] The boundary BD between the STI 20 and the gate insulating film 32 is located on the first surface F1 in a direction farther from the center of the through hole BV than the end (bottom surface end) E1 of the through hole BV. That is, the boundary BD is located more outside than the end E1 of the through hole BV. The spacer layer 40 covers the boundary BD and is provided on the gate insulating film 32 in the through hole BV. This means that when viewed from above in the Z direction, the gate insulating film 32 protrudes (extends) radially inward from the inner circumference of the STI 20 toward the through hole BV. The end E1 is the bottom surface end of the through hole BV on the first surface F1 side.

[0048] According to this configuration, the STI 20 and / or the spacer layer 40 are provided between the metal electrode 100 and the semiconductor substrate 10. The STI 20 and the gate insulating film 32 are provided between the gate electrode (electrode pad) 60 of the through electrode TSV and the semiconductor substrate 10. As a result, the withstand voltage between the through electrode TSV and the semiconductor substrate 10 and the withstand voltage between the gate electrode (electrode pad) 60 and the semiconductor substrate 10 can be maintained at a high level.

[0049] For example, in the case where STI 20 is not provided in the through electrode TSV, only the spacer layer 40 is interposed between the metal electrode 100 and the semiconductor substrate 10, and the breakdown voltage between the metal electrode 100 and the semiconductor substrate 10 will decrease. Or, when viewed from above the first surface F1 in a plan view, the opening diameter of the through hole BV is small, and if the end portion E2 of the through hole BV does not overlap with STI 20, the semiconductor substrate 10 will remain between the metal electrode 100 and STI 20. In this case, the breakdown voltage between the semiconductor substrate 10 and the gate electrode (electrode pad) 60 will also decrease. The end portion E2 is the opening end portion of the through hole BV on the second surface F2 side.

[0050] On the other hand, the breakdown voltage between the semiconductor substrate 10 and the metal electrode 100 and the breakdown voltage between the semiconductor substrate 10 and the gate electrode 60 will be high in the following case, that is, the gate insulating film 32 is not provided in the region of the through hole BV included in STI 20, and a thicker STI 20 is provided in the entire region of the through hole BV. However, as described above, the spacer layer 40 as a mask must be formed thickly on the second surface F2, and in this case, the overhang of the spacer layer 40 will cause the opening diameter of the through hole BV on the first surface F1 to become smaller. In this case, the contact resistance between the metal electrode 100 and the gate electrode 60 will increase.

[0051] In contrast, according to the present embodiment, when viewed from above the first surface F1 in a plan view, STI 20 protrudes radially from the inner wall of the through hole BV toward the center of the through hole BV. Therefore, the semiconductor substrate 10 is not interposed between STI 20 and the metal electrode 100, and the breakdown voltage between the through electrode TSV and the semiconductor substrate 10 can be maintained relatively high.

[0052] In addition, when viewed from above the first surface F1 in a plan view, the gate insulating film 32 protrudes radially from the boundary portion BD with STI 20 toward the center of the through hole BV. From this, it can be seen that the gate insulating film 32 is provided in the through hole BV when the through hole BV is formed. As described above, by providing the gate insulating film 32 in the region of the through hole BV, the opening diameter of the through hole BV can be formed larger. Thereby, the contact area between the metal electrode 100 and the gate electrode 60 can be increased, and thus their contact resistance can be reduced. In addition, the gate insulating film 32 is the gate insulating film 32 of the high-voltage transistor HV that is relatively thick among the gate insulating films 30 to 32. Therefore, the gate insulating film 32 can function as an etching stop layer for the through hole BV.

[0053] Next, the planar shape of the through electrode TSV will be described.

[0054] Figure 3 and Figure 4 is a plan view showing a configuration example of the through electrode TSV.Figure 3 and Figure 4 represent the planar layout of the through - electrode TSV on the first surface F1 along the 2 - 2 line Figure 1 or Figure 2 The end E2 of the through - hole BV shown represents the open end on the second surface F2, and the end E1 of the through - hole BV represents the open end of the through - hole BV on the first surface F1. That is to say, the shape of the end E2 of the through - hole BV on the second surface F2 (for example, approximately circular) is different from the shape of the end E1 on the first surface F1 (for example, approximately polygonal). The shape of the end E1 is determined by the shape of the STI20

[0055] Figure 3 and Figure 4 The end E2 of the through - hole BV shown represents the open end on the second surface F2, and the end E1 of the through - hole BV represents the open end of the through - hole BV on the first surface F1. That is to say, the shape of the end E2 of the through - hole BV on the second surface F2 (for example, approximately circular) is different from the shape of the end E1 on the first surface F1 (for example, approximately polygonal). The shape of the end E1 is determined by the shape of the STI20

[0056] The STI20 is provided along the end E2 of the through - hole BV. The semiconductor substrate 10 is provided outside the STI20. The STI20 protrudes (extends) into the inside of the end E2 of the through - hole BV. Thus, when viewed from above the first surface F1, the STI20 overlaps with the end E2 of the through - hole BV

[0057] Inside the STI20, the gate insulating film 32 protrudes (extends) toward the center of the through - hole BV. The gate insulating film 32 is provided along the inner end of the STI20 over the entire inner end. Inside the region surrounded by the gate insulating film 32, the metal electrode 100 contacts the gate electrode 60. That is to say, the area of the region surrounded by the gate insulating film 32 is the contact area between the through - electrode TSV and the gate electrode 60. The inner end of the gate insulating film 32 corresponds to the end E1 of the through - hole BV on the first surface F1

[0058] Figure 3 and Figure 4 The dashed line of represents the circumscribed circle C1 of the gate insulating film 32. The circumscribed circle C1 can be expanded to the through - hole BV. However, considering the misalignment in the photolithography step when forming the through - hole BV, the circumscribed circle C1 is preferably located inside the end E2 of the through - hole BV, for example, about 1 μm. Thus, even if there is misalignment, the end E2 of the through - hole BV will not overlap with the gate insulating film 32

[0059] If the end E2 of the through - hole BV overlaps with the gate insulating film 32, then as described above, the semiconductor substrate 10 will remain between the metal electrode 100 and the STI20, resulting in a decrease in the breakdown voltage between the metal electrode 100 and the semiconductor substrate 10. Thus, by leaving a margin between the circumscribed circle C1 and the end E2, it is possible to suppress the decrease in the breakdown voltage between the metal electrode 100 and the semiconductor substrate 10

[0060] Figure 3In [description], the shape of the contact area (the shape of the end portion E1) between the through electrode TSV on the first surface F1 and the gate electrode 60 is a stepped shape or a convex shape that is inscribed in a circle C1. Figure 4 In [description], the shape of the contact area (the shape of the end portion E1) between the through electrode TSV on the first surface F1 and the gate electrode 60 is a polygon inscribed in a circle C1. However, the shape of the contact area between the through electrode TSV and the gate electrode 60 is not limited to these. For example, the shape of the contact area may be a substantially circular shape, a substantially elliptical shape, or a substantially polygonal shape.

[0061] As Figure 2 and Figure 3 shown, in a plan view observed from the Z direction, the opening end portion E2 of the through hole BV overlaps with the STI 20. The end portion E2 of the through hole BV does not protrude to the outside or inside of the STI 20, and the STI 20 is exposed on the side wall of the through hole BV inside the STI 20. By the end portion E2 of the through hole BV not protruding to the outside of the STI 20, the material of the barrier metal 99 or the metal electrode 100 does not enter between the semiconductor substrate 10 and the STI 20. Thereby, a decrease in the withstand voltage between the metal electrode 100 and the semiconductor substrate 10 can be suppressed. In addition, by the end portion E2 of the through hole BV not protruding to the inside of the STI 20, the semiconductor substrate 10 does not remain between the metal electrode 100 and the STI 20. Thereby, a decrease in the withstand voltage between the metal electrode 100 and the semiconductor substrate 10 can be suppressed.

[0062] Next, a method for manufacturing the semiconductor device 1 will be described.

[0063] Figures 5 to 13 is a cross-sectional view showing an example of a method for manufacturing the semiconductor device 1. First, gate insulating films 30 to 32 are formed on the first surface F1 of the semiconductor substrate 10. The gate insulating film 30 is a gate insulating film of the ultra-low voltage transistor VLV, the gate insulating film 31 is a gate insulating film of the low voltage transistor LV, and the gate insulating film 32 is a gate insulating film of the high voltage transistor HV. The gate insulating films 30 to 32 may be, for example, silicon oxide films formed by thermally oxidizing the semiconductor substrate 10.

[0064] Next, the STI 20 is formed in the element isolation region on the first surface F1. By forming the STI 20, the working regions are defined between the STI 20s. A well diffusion layer 15 is formed in the working regions. The STI 20 is provided so as to surround the outer periphery of the formation region of the through electrode TSV and is not provided at its center portion. That is, in a plan view, the STI 20 has an annular shape. The STI 20 surrounds the gate oxide film 32. In addition, the so-called annular shape here includes not only a circular ring but also shapes such as a polygonal ring. The lower end portion of the STI 20 may be formed so as to be closer to the second surface side than the lower end portion of the gate insulating film 32.

[0065] Therefore, in the through electrode TSV, the gate insulating film 32 is formed at the central portion of the through electrode TSV surrounded by the STI 20. The thickness of the gate insulating film 32 is thinner than that of the STI 20. For example, the STI 20 is about 300 nm to 500 nm, while the gate insulating film 32 is about 20 nm to 60 nm. The gate insulating film 32 formed in the formation region of the through electrode TSV is thicker than the gate insulating films 30 and 31, so it functions as an etch stop layer when forming the via hole BV. At the same time, since the gate insulating film 32 is thinner than the STI 20, it can be easily removed when the bottom of the via hole BV is opened. Thus, the gate insulating film 32 is formed not only in the formation region of the high-voltage transistor HV in the working region but also in the formation region of the via hole BV on the first surface F1.

[0066] Next, a material of the gate electrode 60 (e.g., doped polysilicon) is deposited on the gate insulating films 30 to 32. A metal material (e.g., tungsten) is deposited on the gate electrode 60 to silicidize the upper part of the gate electrode 60. Thus, a metal film 65 (e.g., tungsten silicide) is formed on the gate electrode 60. A material of the upper covering film 70 (e.g., silicon nitride) is deposited on the metal film 65.

[0067] Next, by using photolithography technology and RIE (Reactive Ion Etching) method, etc., the material of the upper covering film 70 is processed into patterns of gate electrodes of the ultra-low voltage transistor VLV, low voltage transistor LV, and high voltage transistor HV. Further, using the upper covering film 70 as a mask, the metal film 65 and the material of the gate electrode 60 are processed into patterns of gate electrodes of the low voltage transistor VLV, low voltage transistor LV, and high voltage transistor HV. Thus, the gate electrode 60, the metal film 65, and the upper covering film 70 are formed.

[0068] At this time, the gate electrode 60, the metal film 65, and the upper covering film 70 can also be formed simultaneously in the formation region of the through electrode TSV. That is, the gate electrode 60, the metal film 65, and the upper covering film 70 are formed in the entire region surrounded by the STI 20 in contact with the STI 20 in the via hole BV. The gate electrode 60 and the metal film 65 of the through electrode TSV function as electrode pads. When observed from the semiconductor substrate, the gate oxide film 32 of the high voltage transistor HV and the gate oxide film 32 in the formation region of the through electrode TSV can be formed at the same height. When observed from the semiconductor substrate, the gate electrode 60 of the high voltage transistor HV and the gate electrode 60 in the formation region of the through electrode TSV can be formed at the same height.

[0069] Next, a sidewall film 75 is formed on the sidewalls of the gate electrode 60, the metal film 65, and the upper covering film 70. Using the upper covering film 70 and the sidewall film 75 as masks, the gate insulating films 30 to 32 are etched. Thus,Figure 5 The structure shown.

[0070] Next, the outer side of the sidewall film 75 is covered with the cushion layer 76. The cushion layer 76 uses, for example, a silicon nitride film. Next, the interlayer insulating film 80 is stacked, and the interlayer insulating film 80 is polished by a method such as CMP (Chemical Mechanical Polishing) until the upper covering film 70 is exposed. Next, a termination film 77 is formed on the upper covering film 70 and the interlayer insulating film 80, and further, the interlayer insulating film 80 is stacked on the termination film 77.

[0071] Next, contact holes are formed in the interlayer insulating film 80 using photolithography technology and etching technology. At this time, the termination film 77 and the upper covering film 70 function as an etching stop layer. Thus, a part of the contact hole is formed so as to reach the metal film 65 on the gate electrode 60, and another part of the contact hole is formed so as to reach the first surface F1 of the semiconductor substrate 10. Next, a metal material (such as tungsten or copper) is embedded in the contact hole to form a plug hole 90. Thus, the Figure 6 The structure shown.

[0072] Next, as Figure 7 shown, the semiconductor substrate 10 is inverted. Next, as Figure 8 shown, a through hole BV is formed in the formation region of the through electrode TSV using photolithography technology and etching technology. The through hole BV is formed so as to penetrate the semiconductor substrate 10 from the second surface F2 to the gate insulating film 32 in the formation region of the through hole BV. The through hole BV is formed on the gate insulating film 32 in its formation region and on the STI 20 around the gate insulating film 32. Therefore, in a plan view observed from the Z direction, the end portion E2 of the through hole BV is formed so as to overlap the STI 20 around the gate insulating film 32. Thus, at least a part of the STI 20 is exposed on a part of the inner wall of the through hole BV, and the inner wall of the through hole BV is composed of the semiconductor substrate 10 and the STI 20. In the plan view, the STI 20 protrudes radially toward the center of the through hole BV from the inner wall of the through hole BV. The STI 20 protrudes over the entire inner circumference of the through hole BV. At this time, the semiconductor substrate (such as silicon) 10 is selectively removed, and the gate insulating film 32 functions as an etching stop layer.

[0073] Next, as Figure 9As shown, the spacer layer 40 is stacked on the inner side surface, the bottom surface of the through hole BV, and the second surface F2 of the semiconductor substrate 10. The spacer layer 40 is, for example, a silicon oxide film (e.g., TEOS film), a silicon oxynitride film, a silicon nitride film, a silicon oxynitride film, or a laminated film of two or more of them. The spacer layer 40 covers the entire inner wall of the through hole BV, and covers the semiconductor substrate 10 and the STI 20 on the inner wall of the through hole BV. In addition, the spacer layer 40 covers both the gate insulating film 32 and the STI 20 at the bottom end of the through hole BV and is in contact with both of them.

[0074] By controlling the coverage of the CVD method, the spacer layer 40 is relatively thickly stacked on the second surface F2 of the semiconductor substrate 10 outside the through hole BV. On the other hand, the spacer layer 40 is only relatively thinly stacked on the bottom surface of the through hole BV. Therefore, without using lithography technology, by etching back the spacer layer 40 using the RIE method, the spacer layer 40 located on the bottom surface of the through hole BV can be removed self-alignedly. That is, by using the microloading effect of the RIE method, the spacer layer 40 located on the second surface F2 of the semiconductor substrate 10 and the inner side surface of the through hole BV is retained, while the spacer layer 40 located on the bottom surface of the through hole BV is removed. Thereby, the Figure 10 structure shown is obtained.

[0075] Furthermore, using the spacer layer 40 located on the second surface F2 of the semiconductor substrate 10 and the inner side surface of the through hole BV as a mask, the gate insulating film 32 and the gate electrode 60 located on the bottom surface of the through hole BV are removed. Thereby, the Figure 11 structure shown is obtained. Or instead of removing the gate electrode 60, it is only necessary to remove the gate insulating film 32. At this time, the gate insulating film 32 is thinner than the STI 20. Therefore, although the thickness of the spacer layer 40 is relatively thin, it can be easily removed at the bottom of the through hole BV. Therefore, it is not necessary to form the spacer layer 40 thick, and the overhang of the spacer layer 40 can be suppressed at the opening end E2 of the through hole BV. By suppressing the overhang of the spacer layer 40, the opening at the end E2 of the through hole BV can be maintained large. As a result, the opening diameter at the bottom of the through hole BV (the opening diameter of the end E1) can be enlarged, and thus the contact resistance between the through electrode TSV and the gate electrode (electrode pad) 60 can be reduced.

[0076] Here, when viewed from above in the Z direction, the boundary BD between the STI 20 and the gate insulating film 32 is located more inward than the end E2 of the through hole BV and more outward than the end E1. That is, the STI 20 protrudes from the inner wall of the through hole BV toward the center of the through hole BV. Thus, the STI 20 protrudes more toward the center of the through hole BV than the end E2. The gate insulating film 32 protrudes from the STI 20 toward the center of the through hole BV. Thus, the gate insulating film 32 protrudes more toward the center of the through hole BV than the boundary BD. The end E1 inside the gate insulating film 32 becomes the outer edge of the contact region between the through electrode TSV and the gate electrode (electrode pad) 60. From this configuration, it can be seen that the STI 20 is provided so as to surround the periphery of the formation region of the through hole BV, and the gate insulating film 32 is provided inside the formation region of the through hole BV surrounded by the STI 20.

[0077] Next, as Figure 12 shown, a material (e.g., Ti, TiN) for the barrier metal 99 is formed on the inner wall of the through hole BV. Further, a material (e.g., copper, tungsten) for the metal electrode 100 is filled on the barrier metal 99 in the through hole BV.

[0078] Next, using photolithography technology and etching technology, the materials of the metal electrode 100 and the barrier metal 99 located on the second surface F2 of the semiconductor substrate 10 are removed. Thus, the Figure 13 configuration shown is obtained.

[0079] After that, bumps 110 are formed on the metal electrode 100, thereby completing the Figure 1 and Figure 2 semiconductor device 1 shown.

[0080] According to the present embodiment, the STI 20 is provided on the outer periphery of the formation region of the through electrode TSV, and the gate insulating film 32 is provided at the center thereof. The gate insulating film 32 is the gate insulating film 32 of the high-voltage transistor HV, which is thicker than the gate insulating films 30 and 31 of other transistors VLV and LV, but thinner than the STI 20. Thus, the gate insulating film 32 functions as an etching stop layer for the through hole BV, and can suppress the thickness of the spacer layer 40 and increase the opening diameter of the through hole BV. Thereby, the contact resistance between the through electrode TSV and the gate electrode (electrode pad) 60 can be reduced.

[0081] In addition, by providing a gate insulating film 32 that is thinner than the STI 20 on the bottom surface of the through hole BV, even though the film thickness difference between the bottom of the through hole BV and the spacer layer 40 on the second surface F2 is small, the gate insulating film 32 at the bottom of the through hole BV can be easily removed. As a result, even though the aspect ratio of the through hole BV is small and the film thickness difference of the spacer layer 40 is small, the gate electrode 60 can be surely exposed at the bottom of the through hole BV. As a result, both the package thickness of the semiconductor device 1 can be made thinner and the through electrode TSV can be connected to the gate electrode (metal pad) with low resistance, thereby reducing the resistance between semiconductor chips.

[0082] In addition, in a plan view observed from the Z direction, the opening end E2 of the through hole BV overlaps with the STI 20, and the STI 20 is exposed on the side wall of the through hole BV. As a result, it is possible to prevent the material of the barrier metal 99 or the metal electrode 100 from entering between the through hole BV and the STI 20, or the semiconductor substrate 10 from remaining between the metal electrode 100 and the STI 20. As a result, it is possible to suppress a decrease in the withstand voltage between the through electrode TSV and the semiconductor substrate 10.

[0083] In addition, the STI 20 protrudes (extends) from the side wall of the through hole BV toward the center of the through hole BV. As a result, the distance between the gate electrode 60 and the semiconductor substrate 10 can be increased, and thus the withstand voltage between the gate electrode 60 and the semiconductor substrate 10 can be maintained at a high level.

[0084] (Modification example)

[0085] Figure 14 FIG. is a cross-sectional view taken in the middle of the manufacturing process of the semiconductor device 1 showing a modification example of the present embodiment. Figure 14 The steps of Figure 5 correspond to the steps of

[0086] In this modification example, the gate electrode 60 may be a stack of a first electrode layer 61 and a second electrode layer 62. At this time, the first electrode layer 61 may be formed before the STI 20 is formed. That is, after the gate insulating film 32 is formed, the first electrode layer 61 is formed, and then the STI 20 is formed. After that, the second electrode layer 62 is stacked, and then the metal film 65 is stacked. As a result, a part of the gate electrode 60 is formed before the STI 20 is formed. The gate electrodes 60 of the ultra-low voltage transistor VLV, the low voltage transistor LV, and the high voltage transistor HV can be formed in the same manner. The first electrode layer 61 and the second electrode layer 62 may be made of the same material or different materials. Figure 14 As shown in

[0087] The gate electrodes 60 of the ultra-low voltage transistors VLV, low voltage transistors LV, and high voltage transistors HV may similarly include a first electrode layer 61 and a second electrode layer 62. At this time, the gate oxide film 32 of the high voltage transistor HV may be formed simultaneously with the gate oxide film 32 in the TSV formation region. The gate electrode of the high voltage transistor HV may be formed simultaneously with the gate electrode in the TSV formation region.

[0088] The STI 20, the gate insulating film 32, and the spacer film 40 each include silicon oxide, and the film densities of the silicon oxides may be different from each other. The film density of the silicon oxide film included in the gate insulating film 32 may be greater than the film density of the silicon oxide film included in the STI 20. The film density of the silicon oxide film included in the STI 20 may be greater than the film density of the silicon oxide film included in the spacer film 40. Other configurations and manufacturing steps of this modification example may be the same as those of the above-described embodiment.

[0089] Some embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or their variations are included in the scope or gist of the invention, and are also included in the invention described in the claims and its equivalents.

Claims

1. A semiconductor device, characterized in that Comprising: A semiconductor substrate having a first surface provided with semiconductor elements and a second surface on the opposite side of the first surface; A metal electrode provided in a through-hole that penetrates the semiconductor substrate between the first surface and the second surface; A first insulating film provided on the first surface side of the semiconductor substrate and protruding radially toward the center of the through-hole from the outer edge or inner wall of the through-hole when viewed from above the first surface; A second insulating film protruding radially from the first insulating film when viewed from above the first surface, being thinner than the film thickness of the first insulating film, and in contact with the metal electrode; and A third insulating film, which is a continuous insulating film, provided between the inner wall of the through-hole and the metal electrode, including a first portion in contact with the first insulating film and the second insulating film, and a second portion in contact with the inner wall of the through-hole and closer to the second surface side than the first portion.

2. The semiconductor device according to claim 1, wherein An electrode pad provided on the first surface side and electrically connected to the metal electrode is further provided, and The first insulating film is provided between the electrode pad and the semiconductor substrate.

3. The semiconductor device according to claim 1 or 2, wherein The first insulating film, the second insulating film, and the third insulating film each contain silicon oxide, The film densities of the silicon oxide are different from each other.

4. The semiconductor device according to claim 1 or 2, wherein The first insulating film is a film formed by CVD method, The second insulating film is a film formed by oxidizing the semiconductor substrate, The third insulating film is a film formed using TEOS, a silicon hydride oxide film, silicon nitride, silicon oxynitride, or a laminated film of two or more of them.

5. The semiconductor device according to claim 1 or 2, wherein The semiconductor elements include a first transistor having a first gate insulating film and a second transistor having a second gate insulating film, and the film thickness of the second gate insulating film is thinner than the film thickness of the first gate insulating film.

6. The semiconductor device according to claim 5, wherein The semiconductor elements include a third transistor having a third gate insulating film, and the film thickness of the third gate insulating film is thinner than the film thickness of the second gate insulating film.

7. The semiconductor device according to claim 5, wherein The film thickness of the second insulating film is thicker than the film thickness of the second gate insulating film.

8. The semiconductor device according to claim 2, wherein The electrode pad contains tungsten.

9. A method for manufacturing a semiconductor device, characterized in that Including the following steps: Forming a first insulating film on the first surface side of a semiconductor substrate having a first surface and a second surface on the opposite side of the first surface; Forming a second insulating film on the first surface side; Forming an electrode pad on the second insulating film; Forming a through-hole that penetrates the semiconductor substrate from the second surface side of the semiconductor substrate in such a way as to expose at least a part of the first insulating film and the second insulating film; Forming a third insulating film on the second surface of the semiconductor substrate, the inner side surface of the through-hole, and the exposed second insulating film; Retaining the third insulating film on the second surface and the inner side surface of the through-hole, and removing the third insulating film on the bottom surface of the through-hole and the second insulating film; Forming a metal film in the through-hole; and The first surface side is the surface side where semiconductor elements are formed, When viewed from the first surface side, the first insulating film surrounds the second insulating film, The end portion of the second insulating film on the second surface side is closer to the first surface side than the end portion of the first insulating film on the second surface side.

10. The manufacturing method of the semiconductor device according to claim 9, characterized in that The first insulating film, the second insulating film, and the third insulating film each contain silicon oxide. The film densities of the silicon oxide are different from each other.

11. The manufacturing method of the semiconductor device according to claim 9, characterized in that The first insulating film is formed by a CVD method. The second insulating film is formed by oxidizing a semiconductor substrate. The third insulating film is formed using TEOS, a hydrogenated silicon oxide film, silicon nitride, silicon oxynitride, or a laminated film of two or more of them.

12. The manufacturing method of the semiconductor device according to claim 9, characterized in that The semiconductor element includes a first transistor having a first gate insulating film and a second transistor having a second gate insulating film, and the film thickness of the second gate insulating film is thinner than that of the first gate insulating film.

13. The manufacturing method of the semiconductor device according to claim 12, characterized in that The semiconductor element includes a third transistor having a third gate insulating film, and the film thickness of the third gate insulating film is thinner than that of the second gate insulating film.

14. The manufacturing method of the semiconductor device according to claim 12, characterized in that The film thickness of the first gate insulating film is the same as that of the second insulating film.

15. The manufacturing method of a semiconductor device according to any one of claims 12 to 14, characterized in that When forming the second insulating film, the first gate insulating film is formed simultaneously.

16. The manufacturing method of the semiconductor device according to any one of claims 9 to 14, characterized in that The second insulating film is formed prior to the first insulating film.

17. The manufacturing method of the semiconductor device according to any one of claims 9 to 14, characterized in that A part of the electrode pad is formed prior to the first insulating film.

18. The manufacturing method of the semiconductor device according to any one of claims 9 to 14, characterized in that The electrode pad contains tungsten.

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