TBC battery and preparation method thereof

Abstract

The invention relates to the technical field of solar cells, and discloses a TBC cell and a preparation method thereof.The preparation method comprises the steps that a tunneling layer and an intrinsic amorphous silicon layer are prepared on the back face of a silicon wafer; a first barrier layer is locally prepared on the back surface of the intrinsic amorphous silicon layer; boron diffusion enables the intrinsic amorphous silicon layer in a non-first barrier layer region to be converted into a boron-doped polycrystalline silicon layer; removing the local first barrier layer through laser patterning to expose the intrinsic amorphous silicon layer in a laser area; performing wet etching to form a Gap region, and exposing the boron-doped polycrystalline silicon layer and the intrinsic amorphous silicon layer in a non-laser region; locally preparing a second barrier layer on the back surfaces of the Gap region silicon wafer and the boron-doped polycrystalline silicon layer; phosphorus diffusion enables the exposed intrinsic amorphous silicon layer to be converted into a phosphorus-doped polycrystalline silicon layer; removing the second barrier layer and performing texturing; according to the method, the Gap region can be easily formed, the boron-doped polycrystalline silicon layer and the phosphorus-doped polycrystalline silicon layer have no height difference, the working procedures are few, the damage is little, the cost is low, and the battery efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a TBC cell and a preparation method thereof. Background Art

[0002] Topcon cells (tunneling oxide passivated contact cells) can achieve selective carrier transmission due to their unique structure, thus improving the cell's Voc (open circuit voltage) and FF (fill factor), thereby improving the cell's photoelectric conversion efficiency. The positive and negative electrodes of BC cells (back contact cells) are integrated in a forked-finger shape on the back of the cell. There is no metal electrode on the front of this type of cell, and the front of the BC cell will not suffer from shading losses due to electrode obstruction. Therefore, the BC cell has a higher short-circuit current and can effectively improve the cell's photoelectric conversion efficiency. The TBC cell is a solar cell that combines TOPCon and BC technologies. P+ polysilicon layers (P+polysi layers) and N+ polysilicon layers (N+polysi layers) are alternately prepared on the back of the cell, which can greatly improve the cell's photoelectric conversion efficiency.

[0003] The TBC cell manufacturing process typically requires the use of high-tech laser equipment such as femtosecond lasers for two to three processing steps (such as laser patterning and grooving). For example, the method for preparing a TBC solar cell, disclosed in publication number CN118782688B, requires three laser treatments to prepare the TBC solar cell. This requires multiple femtosecond laser devices, which are very expensive. Furthermore, these three laser treatments are mostly ultraviolet lasers, which are even more expensive. This undoubtedly increases the production cost of the TBC cell. These three laser treatments can also significantly damage the cell, hindering further improvements in the cell's electrical performance and photoelectric conversion efficiency.

[0004] Moreover, as shown in publication numbers CN118782672B and CN119653870B, there will be a height difference between the P+ polysilicon layer and the N+ polysilicon layer on the back of the TBC battery produced, which will increase the difficulty of screen printing the metal slurry, resulting in the subsequent metallization process of the P region and the N region being prone to short gate phenomenon, resulting in poor contact, resulting in a high contact resistivity of the electrode (or gate line), and causing problems such as poor welding on the back of the photovoltaic module.

[0005] Furthermore, as shown in CN116845140A and CN119653870B, in the TBC cell fabrication process, most of the first laser treatments are to locally process the BSG layer on the back of the P+ polysilicon layer to expose the local P+ polysilicon layer, and then clean and etch the local P+ polysilicon layer. However, the etching of the highly doped P+ polysilicon layer is very difficult, making it difficult to completely remove the local P+ polysilicon layer. This is also not conducive to further improving the electrical performance and photoelectric conversion efficiency of the TBC cell. Therefore, there is an urgent need to improve the existing TBC cell fabrication methods. Summary of the Invention

[0006] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a TBC battery and a method for preparing the same.

[0007] Based on this, the present invention discloses a method for preparing a TBC battery, comprising the following preparation steps:

[0008] Step 1: sequentially preparing a tunneling layer and an intrinsic amorphous silicon layer on the back side of the silicon wafer;

[0009] Step 2: locally forming a first barrier layer on the back side of the intrinsic amorphous silicon layer;

[0010] Step 3: Boron diffusion to transform the intrinsic amorphous silicon layer in the non-first barrier layer area into a boron-doped polysilicon layer, and to form a borosilicate glass layer on the back of the boron-doped polysilicon layer;

[0011] Step 4: Laser patterning is used to remove one end of the first barrier layer near the boron-doped polysilicon layer to expose the intrinsic amorphous silicon layer in the laser area; wet etching is performed to remove the intrinsic amorphous silicon layer and the tunneling layer in the laser area to form a gap region (isolation region) exposing the silicon wafer, and the borosilicate glass layer is removed to expose the boron-doped polysilicon layer. The first barrier layer in the non-laser area is removed to expose the intrinsic amorphous silicon layer;

[0012] Step 5: locally forming a second barrier layer on the back side of the silicon wafer and the boron-doped polysilicon layer in the Gap area;

[0013] Step 6: Phosphorus diffusion to transform the intrinsic amorphous silicon layer in the non-laser area into a phosphorus-doped polysilicon layer;

[0014] Step 7: removing the second barrier layer and performing texturing;

[0015] Step 8: Prepare a passivation anti-reflection film on the front and back sides of the textured silicon wafer, and then form a first metal electrode that ohmically contacts the boron-doped polysilicon layer and a second metal electrode that ohmically contacts the phosphorus-doped polysilicon layer through metallization.

[0016] Preferably, before step 1, the method further includes: performing double-side polishing on the silicon wafer to remove impurities on the surface of the silicon wafer and forming a polished surface on the back side of the silicon wafer.

[0017] Preferably, in step 1, the tunneling layer is a tunneling silicon oxide layer with a thickness of 2-4 nm; and the intrinsic amorphous silicon layer has a thickness of 200-380 nm.

[0018] Preferably, step 2 of preparing the first barrier layer comprises: locally printing the first barrier layer slurry on the back side of the intrinsic amorphous silicon layer by screen printing, and sintering to prepare the first barrier layer;

[0019] Step 5 of preparing the second barrier layer includes: locally printing the second barrier layer slurry on the back side of the silicon wafer and the boron-doped polysilicon layer in the Gap area using screen printing, and sintering to prepare the second barrier layer.

[0020] Further preferably, in step 2 and step 5, the screen printing screen opening is 400-620 μm, silicon oxide slurry is locally printed, and after printing, it is sintered at a high temperature of 860-900°C for 3-7 minutes; the first barrier layer and the second barrier layer are both silicon oxide barrier layers, and the width of the first barrier layer and the second barrier layer after sintering is 450-640 μm, the thickness is 0.2-2 μm, and the refractive index is 1.6-1.8.

[0021] Preferably, in step 3, the thickness of the borosilicate glass layer is 45-65 nm, and the doping concentration of the boron-doped polysilicon is 8e19-2e20 cm -3 .

[0022] Preferably, in step 4, the laser is a green laser with a laser wavelength of 500-550 nm, a laser power of 60-120 W, a laser scanning rate of 5000-50000 mm / s, and a laser frequency of 250-1000 KHz;

[0023] Alternatively, the laser is an infrared laser with a laser wavelength of 700-1200 nm, a laser power of 70-120 W, a laser scanning rate of 5000-20000 mm / s, and a laser frequency of 250-1000 KHz;

[0024] The width of the first barrier layer removed by the laser region is 70-120 μm, and the width of the remaining first barrier layer is 380-500 μm.

[0025] Further preferably, in step 4, the wet etching includes: first alkali etching to remove the intrinsic amorphous silicon layer in the laser area, and then acid etching to remove the tunneling layer in the laser area, the borosilicate glass layer in the non-first barrier layer area, and the first barrier layer in the non-laser area.

[0026] Preferably, in step 6, a 35-55 nm thick phosphorus-silicate glass layer is formed on the back of the phosphorus-doped polysilicon layer; the doping concentration of the phosphorus-doped polysilicon layer is 1e20-4e20 cm -3 .

[0027] Further preferably, the step 7 specifically includes: first acid wet etching to remove the phosphosilicate glass layer to expose the phosphorus-doped polysilicon layer, and remove the second barrier layer to expose the back side of the Gap area silicon wafer and the boron-doped polysilicon layer; then alkaline texturing to form a velvet surface on the front side of the silicon wafer and the back side of the Gap area silicon wafer.

[0028] The preparation method of the TBC battery of the present invention uses a screen printing plate twice to make a wider barrier layer; the first time, the screen plate is used to locally screen-print a wider first barrier layer on the back side of the i-polysi layer (intrinsic amorphous silicon layer) to facilitate the subsequent boron diffusion to realize the preparation of the P+polysi layer (boron-doped polysilicon layer), and then the local first barrier layer is removed by laser patterning, and the i-polysi layer and tunneling layer in the laser area are removed by wet etching to prepare the Gap area; and the second time, the screen plate is used to locally print a wider second barrier layer on the back side of the silicon wafer in the Gap area and the P+polysi layer, and then phosphorus is diffused to realize the preparation of the N+polysi layer (phosphorus-doped polysilicon layer). Therefore, by screen printing the barrier layer twice and combining it with laser patterning + wet etching, (1) the laser treatment of the first barrier layer exposes the i-polysi layer in the laser area, and the difficulty of wet etching the i-polysi layer (compared to wet etching the high-doping concentration P+polysi layer) is greatly reduced, and the Gap area can be easily formed; (2) the first barrier layer can protect the i-polysi layer on its front side from being doped with boron, and at the same time realize the preparation of a high-concentration P+polysi layer in the area other than the first barrier layer; and the second barrier layer can protect the P+polysi layer on its front side from being doped with phosphorus, and at the same time realize the preparation of a high-concentration N+polysi layer in the area other than the second barrier layer (corresponding to the non-laser area); (3) the N+polysi layer and the P+polysi layer can be doped and prepared in different areas of the same i-polysi layer to ensure that there is no height difference between the N+polysi layer and the P+polysi layer, which is beneficial to subsequent metallization.

[0029] The present invention also discloses a TBC battery, which is prepared by the preparation method of the TBC battery described above in the present invention.

[0030] Compared with the prior art, the present invention has at least the following beneficial effects:

[0031] The preparation method of the TBC battery of the present invention (1) reduces the laser process, which can reduce the equipment investment cost and the damage of the laser to the battery, and can form a high-doping concentration P+polysilicon layer and an N+polysilicon layer on the back; (2) it can also solve the problem of difficult etching of the high-doping concentration P+polysilicon layer faced by wet cleaning and etching of the high-doping concentration P+polysilicon layer to form a Gap as shown in CN119653870B (the present invention performs laser patterning on the first barrier layer, cooperates with wet etching to remove the i-polysilicon layer and the tunneling layer, and can easily form Gap area; compared with wet etching of a high-doping concentration P+ polysilicon layer, the difficulty of wet etching the i-polysi layer of the present invention is greatly reduced, and the Gap area can be easily formed); (3) At the same time, the N+polysi layer and the P+polysi layer can be prepared by doping in different areas of the same i-polysi layer, completely avoiding the height difference problem between the P+polysi layer and the N+polysi layer, reducing the difficulty of screen printing of the metal paste in the later stage, reducing the difficulty of metallization, and not causing short gates, poor contact of electrodes or gate lines, poor welding, etc. due to height differences. Therefore, the preparation method of the TBC battery of the present invention can not only reduce the production cost of the battery, but also further improve the FF, Jsc (short-circuit current density), Voc and photoelectric conversion efficiency of the battery.

[0032] In addition, the preparation method of the TBC battery of the present invention controls the thickness of the barrier layer by regulating the laser patterning process (to prevent the barrier layer from being too thick, resulting in uneven diffusion and doping, thereby reducing the passivation effect of the battery; at the same time, to prevent the barrier layer from being too thin, which will weaken the barrier ability and affect the contact resistance and passivation effect), and controls the sintering temperature and sintering time of the barrier layer slurry to control the refractive index and density of the sintered barrier layer (this can ensure that the barrier layer is not too thick in advance and still has a strong blocking ability and plays a better blocking role), which can further improve the FF, Jsc, Voc and photoelectric conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic diagram of the cross-sectional structure of a TBC battery prepared by the present invention after S1 treatment.

[0034] Figure 2 This is a schematic diagram of the cross-sectional structure of a TBC battery prepared by the present invention after S2 treatment.

[0035] Figure 3 This is a schematic diagram of the cross-sectional structure of a TBC battery prepared by the present invention after S3 treatment.

[0036] Figure 4This is a schematic diagram of the cross-sectional structure of a TBC battery prepared by the present invention after S4 treatment.

[0037] Figure 5 This is a schematic diagram of the cross-sectional structure of a TBC battery after S5 treatment according to the preparation method of the present invention.

[0038] Figure 6 This is a schematic diagram of the cross-sectional structure of a TBC battery prepared by the present invention after S6 treatment.

[0039] Figure 7 This is a schematic diagram of the cross-sectional structure of a TBC battery preparation method after S7 treatment according to the present invention.

[0040] Figure 8 This is a schematic diagram of the cross-sectional structure of a TBC battery prepared by the present invention after S8 treatment.

[0041] Figure 9 This is a schematic diagram of the cross-sectional structure of a TBC battery after S9 treatment according to the preparation method of the present invention.

[0042] Figure 10 This is a schematic diagram of the cross-sectional structure of a TBC battery preparation method of the present invention after S10 treatment.

[0043] Figure 11 This is a schematic diagram of the cross-sectional structure of a TBC battery preparation method of the present invention after S11 treatment.

[0044] Explanation of the accompanying drawings: silicon wafer 1; tunneling SiOx layer 2; i-polysi layer 3; first barrier layer 41; second barrier layer 42; P+polysi layer 5; BSG layer 6; N+polysi layer 7; PSG layer 8; AlOx film 9; SiNx film 10; first metal electrode 11; second metal electrode 12. DETAILED DESCRIPTION

[0045] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] A method for preparing a TBC battery of the present invention, see Figure 1-11 , comprising the following preparation steps:

[0047] S1: If Figure 1 As shown, the original silicon wafer 1 is double-sided polished to remove impurities on the surface of the original silicon wafer 1 and form a polished surface on the back of the original silicon wafer 1.

[0048] In step S1 , the resistivity of the original silicon wafer 1 is 4-10 Ω.cm and the thickness is 130-145 μm.

[0049] In step S1, the double-side polishing process is as follows: the original silicon wafer 1 is placed in an alkaline polishing tank containing a KOH solution and double-sided polished at 75-90° C. for 1-5 minutes.

[0050] S2: If Figure 2 As shown, a tunneling SiOx layer 2 (tunneling silicon oxide layer) and an i-polysi layer 3 (intrinsic amorphous silicon layer) are sequentially deposited on the back of a silicon wafer 1 .

[0051] In step S2, the deposition process conditions of the tunneling SiOx layer 2 are as follows: an O2 gas flow rate of 14000-28000 sccm, a reaction temperature of 510-690°C, a reaction time of 890-1800s, and a deposition thickness of the tunneling SiOx layer 2 of 2-4nm.

[0052] In step S2, the deposition process conditions of the i-polysi layer 3 are as follows: the i-polysi layer 3 is deposited on the tunneling SiOx layer 2, SiH4 is introduced at a gas flow rate of 500-1400 sccm, the reaction temperature is 610-745°C, the reaction time is 1.5-3.5h, the gas pressure is 160-430mTorr, and the deposition thickness of the i-polysi layer 3 is 200-380nm.

[0053] S3: If Figure 3 As shown, the first barrier layer slurry (such as SiO2 slurry, also known as silicon oxide slurry) is locally printed on the back side of the i-polysi layer 3 by screen printing, and the first barrier layer 41 (such as SiO2 barrier layer, also known as silicon oxide barrier layer) is prepared by sintering in a high-temperature furnace.

[0054] In step S3, the preparation process conditions of the first barrier layer 41 are as follows: according to P / N=1.5-1.8 (P / N is the line width ratio of the back P region to the N region), the screen printing screen opening is 450-600μm, SiO2 slurry is locally printed, and after printing, it passes through a high-temperature furnace, the sintering temperature is 860-900℃, the sintering time is 3-7min, the width of the SiO2 barrier layer is 460-620μm, the thickness is 0.2-2μm, and the refractive index is 1.6-1.8.

[0055] In step S3, a first barrier layer 41 is provided on the i-polysi layer 3, which not only protects the i-polysi layer 3 on the front side from subsequent boron diffusion doping, but also facilitates the subsequent wet etching to form a Gap region and prepare the N+polysi layer 7. At the same time, the subsequent boron diffusion can also transform the i-polysi layer 3 in the non-first barrier layer 41 area into a p+polysi layer 5 with a high doping concentration; therefore, the local preparation of the first barrier layer 41 on the back side can not only protect it from subsequent boron diffusion doping, but also facilitate the subsequent laser patterning combined with wet etching to form a Gap region and prepare the N+polysi layer 7.

[0056] S4: As Figure 4 As shown, boron diffusion is performed on the back side of the silicon wafer 1, so that the i-polysi layer 3 in the non-first barrier layer 41 area is transformed into a P+polysi layer 5 (boron-doped polysilicon layer), and a BSG layer 6 (borosilicate glass layer) is generated on the back side of the P+polysi layer 5; and the i-polysi layer 3 in the area of ​​the first barrier layer 41 can prevent boron atoms from entering the i-polysi layer 3 in the area of ​​the first barrier layer 41 due to the blocking of the boron doping source (such as boron atoms) by the first barrier layer 41, and the first barrier layer 41 contains boron atoms.

[0057] In step S4, the boron diffusion includes a deposition stage, a driving stage, and an oxidation stage performed sequentially. The process conditions of each stage are as follows:

[0058] In the deposition stage, the deposition temperature is 810-900°C, the deposition time is 1200-3200s, the BCl3 gas flow rate is 64-440sccm, and the O2 gas flow rate is 1000-3400sccm; in the N2 push stage, the push temperature is 910-930°C, the push time is 1200-2100s, and the N2 gas flow rate is 3200-6300sccm; in the O2 oxidation stage, the oxidation temperature is 945-1000°C, the oxidation time is 1200-3300s, and the O2 gas flow rate is 14000-35000sccm; the thickness of the BSG layer 6 is 45-65nm.

[0059] S5: If Figure 5As shown, a green laser is used to perform patterning on the left end region of the first barrier layer 41 (i.e., the end region close to the P+polysi layer 5) to remove the first barrier layer 41 in the left end region, exposing the left end region of the non-boron-doped i-polysi layer 3 (corresponding to the laser area); an alkaline wet bath is used to etch away the i-polysi layer 3 in the laser area, and then an acidic wet bath is used to remove the tunneling SiOx layer 2 in the laser area to expose the back surface of the silicon wafer 1 in the laser area to form a Gap area, and the BSG layer 6 in the area other than the first barrier layer 41 is removed to expose the P+polysi layer 5, and the first barrier layer 41 in the non-laser area is removed to expose the i-polysi layer 3 in the non-laser area (corresponding to the N area).

[0060] In step S5, the process conditions for the laser patterning process are as follows: a green laser or an infrared laser can be used, as long as the first barrier layer 41 localized on the left end can be removed. This facilitates alkaline wet trench etching, and a cheaper infrared laser can be used. When using an infrared laser, the infrared laser has a laser wavelength of 700-1200nm, a laser power of 70-120W, a laser scanning rate of 5000-20000mm / s, a laser frequency of 250-1000kHz, and a laser line spacing of 5-15um. When using a green laser, the laser wavelength is 500-550nm, the laser power is 60-120W, the laser scanning rate is 5000-50000mm / s, the laser frequency is 250-1000KHz, and the first barrier layer 41 with a local width of 70-120μm at the left end is removed to expose the i-polysi layer 3 in the laser area (compared to the highly doped P+polysi layer 5, it is very easy to etch the exposed i-polysi layer 3 using an alkaline wet bath, and the problem of difficulty and high cost in etching the highly doped P+polysi layer 5 will not occur). The width of the remaining first barrier layer 41 is 380-500μm.

[0061] In step S5 , the process conditions of alkaline wet trench etching are as follows: the etching temperature of the alkaline solution is 75-90° C., the etching time is 150-200 s, the etching depth is 1.2-2.3 μm, and a Gap region is formed.

[0062] In step S5, the process conditions for acidic wet tank removal are as follows: the volume ratio of HF solution to nitric acid solution is 1:3-1:5, the concentration of HF solution is 50-75wt%, the concentration of nitric acid solution is 55-65wt%, and the removal time is 100-140s.

[0063] S6: As Figure 6As shown, the second barrier layer slurry (such as SiO2 slurry) is locally printed on the back surface of the silicon wafer 1 and the P+polysi layer 5 in the Gap area by screen printing, and the second barrier layer 42 (such as SiO2 barrier layer) is prepared by sintering in a high-temperature furnace.

[0064] In step S6 , the second barrier layer 42 has a thickness of 0.9 μm and a width of 510 μm.

[0065] In step S6, the preparation process conditions of the second barrier layer 42 are as follows: according to P / N=1.5-1.8, the screen printing screen opening is 480-620μm, SiO2 slurry is locally printed, and after printing, it passes through a high-temperature furnace with a sintering temperature of 860-900℃ and a sintering time of 3-7min. The width of the SiO2 barrier layer is 500-640μm, the thickness is 0.2-2μm, and the refractive index is 1.6-1.8.

[0066] In step S6, a second barrier layer 42 is also formed on the Gap region and the side of the P+polySi layer 5 to prevent subsequent phosphorus from diffusing into the silicon wafer 1 and the P+polySi layer 5, thereby improving battery performance.

[0067] S7: As Figure 7 As shown, phosphorus diffusion is performed on the back of the silicon wafer 1, so that the i-polysi layer 3 in the non-laser area is transformed into the N+polysi layer 7 (phosphorus-doped polysilicon layer), and a PSG layer 8 (phosphorus silicon glass layer) is generated on the back of the N+polysi layer 7; and the P+polysi layer 5 in the second barrier layer 42 area and the back surface of the silicon wafer 1 in the Gap area are prevented from entering the P+polysi layer 5 in the second barrier layer 42 area and the silicon wafer 1 in the Gap area due to the blocking of the phosphorus doping source (such as phosphorus atoms) by the second barrier layer 42, and the second barrier layer 42 contains phosphorus atoms.

[0068] In step S7, the phosphorus diffusion includes a deposition stage, a diffusion stage and an oxidation stage performed in sequence. The process conditions of each stage are as follows: the N2 gas flow rate is 7-30L / min, so that the liquid doping source POCl3 enters the quartz tube, and then the O2 gas flow rate is 0.5-3.5L / min, the deposition temperature is 750-810°C, and the deposition time is 1000-3000s; in the diffusion stage, a sufficient amount of N2 is introduced, and its gas flow rate is 8-30L / min, the O2 gas flow rate is 0.5-3.5L / min, the diffusion temperature is 820-920°C, and the diffusion time is 500-2000s; in the oxidation stage, the N2 gas flow rate is 8-30L / min, and then the O2 gas flow rate is 0.2-3L / min, the oxidation temperature is 830-880°C, and the oxidation time is 600-2000s; the thickness of the PSG layer 8 is 35-55nm.

[0069] S8: Figure 8 As shown, the silicon wafer 1 after step S7 treatment enters an acidic wet process tank to remove the PSG layer 8 on the back to expose the N+polysi layer 7, and remove the phosphorus-containing second barrier layer 42 to expose the P+polysi layer 5 and the back surface of the silicon wafer 1 in the Gap area; then enters an alkaline wet process tank for texturing to prepare a pyramid-shaped texturing surface on both the back Gap area and the front of the silicon wafer 1.

[0070] In step S8, the process conditions for acidic wet tank removal are as follows: the volume ratio of HF solution to nitric acid solution is 1:3-1:5, the concentration of HF solution is 50-75wt%, the concentration of nitric acid solution is 55-65wt%, and the removal time is 100-140s.

[0071] In step S8, the process conditions of alkaline wet bath texturing are as follows: the concentration of KOH solution is 1.2-2.5wt%, at 75-90°C, texturing time is 150-600s, and a pyramid-shaped texturing surface is formed in the Gap area on the back side and the front side of the silicon wafer 1.

[0072] In the present invention, the doping concentration of the P+polysi layer 5 and the N+polysi layer 7 is high, and the thickness of the polysi layer is thick, which can effectively resist alkaline wet bath etching. At the same time, alkaline wet bath texturing can also regulate the thickness of the polysi layer.

[0073] S9: As Figure 9 As shown, AlOx films 9 (aluminum oxide films) are deposited on both the front and back sides of the silicon wafer 1 after the process in step S8 as passivation films.

[0074] In step S9, the deposition process conditions of the AlOx film 9 are as follows: using ALD (atomic layer deposition), through the reaction of Al(CH3)3 with water vapor, an AlOx film 9 with a thickness of 5-12 nm is deposited on the back side of the silicon wafer 1 (i.e., the back side of the Gap area, the P+polysi layer 5 and the N+polysi layer 7) and the front side of the silicon wafer 1. The process temperature is 200-380°C and the deposition time is 300-1000s.

[0075] S10: SiNx films 10 (silicon nitride films) are deposited on both the front surface of the front AlOx film 9 and the back surface of the back AlOx film 9 as passivation anti-reflection films.

[0076] In step S10, Figure 10As shown, the deposition process conditions of the SiNx film 10 are as follows: PECVD (plasma enhanced chemical vapor deposition) is used to prepare a front SiNx film 10 and a back SiNx film 10 on the front side of the front AlOx film 9 and on the back side of the back AlOx film 9, respectively, and the thickness of the front SiNx film 10 and the back SiNx film 10 are both 65-90 nm; during the preparation process, the gas in the tube is SiH4 and NH3, the working pressure is 1200-2200 mTorr, the power is 10000-15000 W, the temperature is 330-500 ° C, the gas flow rate of SiH4 is 800-12000 sccm, the flow rate of NH3 is 7000-12000 sccm, the silicon nitrogen ratio is 1:2-1:7, and the deposition time is 10-25 min.

[0077] S11: If Figure 11 As shown, the back side of the silicon wafer 1 processed in step S10 is metallized to obtain a first metal electrode 11 that ohmically contacts the P+polySi layer 5 and a second metal electrode 12 that ohmically contacts the N+polySi layer 7 .

[0078] In step S11, the metallization process conditions are as follows: screen printing metal paste (such as Ag paste), the opening of the printing screen is 10-60μm; after printing, sintering at 700-900℃ to form the first metal electrode 11 and the second metal electrode 12; after light injection, a TBC battery is obtained.

[0079] Specific examples and comparative examples are given below.

[0080] Example 1

[0081] A method for preparing a TBC battery in this embodiment is described in detail in Figure 1-11 , comprising the following preparation steps:

[0082] S1: If Figure 1 As shown, the original silicon wafer 1 is double-sided polished to remove impurities on the surface of the original silicon wafer 1 and form a polished surface on the back of the original silicon wafer 1.

[0083] In step S1 , the original silicon wafer 1 is an N-type silicon wafer with a resistivity of 4Ω.cm, a thickness of 145μm, and a size of 182.2mm*183.75mm.

[0084] In step S1 , the process conditions for double-side polishing include: the original silicon wafer 1 is placed in an alkaline polishing tank containing a KOH solution, double-sided polished at 75° C. for 5 minutes, with a polishing thickness of 3 μm and a thinning amount of 0.34 g.

[0085] S2: If Figure 2 As shown, a tunneling SiOx layer 2 (tunneling silicon oxide layer) and an i-polysi layer 3 (intrinsic amorphous silicon layer) are sequentially deposited on the back of a silicon wafer 1 .

[0086] In step S2, the deposition process conditions of the tunneling SiOx layer 2 are as follows: an O2 gas flow rate of 25000 sccm, a reaction temperature of 610°C, a reaction time of 1200s, and a deposition thickness of the tunneling SiOx layer 2 of 3.5nm.

[0087] In step S2, the deposition process conditions of the i-polysi layer 3 are as follows: the i-polysi layer 3 is deposited on the tunneling SiOx layer 2, SiH4 is introduced at a gas flow rate of 880 sccm, the reaction temperature is 738°C, the reaction time is 2.4h, the gas pressure is 320mTorr, and the deposition thickness of the i-polysi layer 3 is 280nm.

[0088] S3: If Figure 3 As shown, the first barrier layer slurry (such as SiO2 slurry, also known as silicon oxide slurry) is locally printed on the back side of the i-polysi layer 3 by screen printing, and the first barrier layer 41 (such as SiO2 barrier layer, also known as silicon oxide barrier layer) is prepared by sintering in a high-temperature furnace.

[0089] In step S3, the preparation process conditions of the first barrier layer 41 are as follows: according to P / N=1.6, the screen printing screen opening is 500μm, SiO2 slurry is locally printed, and after printing, it passes through a high-temperature furnace, the sintering temperature is 890℃, the sintering time is 4.5min, the width of the SiO2 barrier layer is 510μm, the thickness is 0.9μm, and the refractive index is 1.7.

[0090] S4: As Figure 4 As shown, boron diffusion is performed on the back side of the silicon wafer 1, so that the i-polysi layer 3 in the non-first barrier layer 41 area is transformed into a P+polysi layer 5 (boron-doped polysilicon layer), and a BSG layer 6 (borosilicate glass layer) is generated on the back side of the P+polysi layer 5; and the i-polysi layer 3 in the area of ​​the first barrier layer 41 can prevent boron atoms from entering the i-polysi layer 3 in the area of ​​the first barrier layer 41 due to the blocking of the boron doping source (such as boron atoms) by the first barrier layer 41, and the first barrier layer 41 contains boron atoms.

[0091] In step S4, the boron diffusion includes a deposition stage, a driving stage, and an oxidation stage performed sequentially. The process conditions of each stage are as follows:

[0092] In the deposition phase, the deposition temperature was 855°C, the deposition time was 2500s, the BCl3 gas flow rate was 350sccm, and the O2 gas flow rate was 3200sccm. In the N2 push phase, the push temperature was 928°C, the push time was 1800s, and the N2 gas flow rate was 4800sccm. In the O2 oxidation phase, the oxidation temperature was 956°C, the oxidation time was 2800s, and the O2 gas flow rate was 28000sccm. The boron doping concentration in the P+polySi layer 5 was 1.2e20cm -3 , the thickness of the BSG layer 6 is 55 nm.

[0093] S5: If Figure 5 As shown, a green laser is used to perform patterning on the left end region of the first barrier layer 41 (i.e., the end region close to the P+polysi layer 5) to remove the first barrier layer 41 in the left end region, exposing the left end region of the non-boron-doped i-polysi layer 3 (corresponding to the laser area); an alkaline wet bath is used to etch away the i-polysi layer 3 in the laser area, and then an acidic wet bath is used to remove the tunneling SiOx layer 2 in the laser area to expose the back surface of the silicon wafer 1 in the laser area to form a Gap area, and the BSG layer 6 in the area other than the first barrier layer 41 is removed to expose the P+polysi layer 5, and the first barrier layer 41 in the non-laser area is removed to expose the i-polysi layer 3 in the non-laser area (corresponding to the N area).

[0094] In step S5, the process conditions of the laser patterning treatment are as follows: the laser wavelength is 515nm, the laser power is 90W, the laser scanning rate is 34500mm / s, the laser frequency is 250KHz, the laser spot size is 50μm, and the first barrier layer 41 with a local width of 100μm at the left end is removed to expose the i-polysi layer 3 in the laser area. The remaining width of the first barrier layer 41 is 410μm.

[0095] In step S5 , the process conditions of alkaline wet trench etching are as follows: the concentration of the KOH solution is 3 wt %, the etching temperature is 75° C., the etching time is 180 s, the etching depth is 1.8 μm, and the width of the gap region is 100 μm.

[0096] In step S5 , the process conditions for acidic wet bath removal are as follows: the volume ratio of HF solution to nitric acid solution is 1:4, wherein the concentration of HF solution is 65 wt %, the concentration of nitric acid solution is 58 wt %, and the removal time is 130 s.

[0097] S6: As Figure 6As shown, the second barrier layer slurry (such as SiO2 slurry) is locally printed on the back surface of the P+polysi layer 5 and the Gap area silicon wafer 1 using screen printing, and the second barrier layer 42 (such as SiO2 barrier layer) is prepared by sintering in a high-temperature furnace.

[0098] In step S6, the second barrier layer 42 has a thickness of 0.9 μm and a width of 510 μm. The preparation process conditions of the second barrier layer 42 in step S6 refer to those in step S3 and are not described here.

[0099] S7: As Figure 7 As shown, phosphorus diffusion is performed on the back of the silicon wafer 1, so that the i-polysi layer 3 in the non-laser area is transformed into the N+polysi layer 7 (phosphorus-doped polysilicon layer), and a PSG layer 8 (phosphorus silicon glass layer) is generated on the back of the N+polysi layer 7; and the P+polysi layer 5 in the second barrier layer 42 area and the back surface of the silicon wafer 1 in the Gap area are prevented from entering the P+polysi layer 5 in the second barrier layer 42 area and the silicon wafer 1 in the Gap area due to the blocking of the phosphorus doping source (such as phosphorus atoms) by the second barrier layer 42, and the second barrier layer 42 contains phosphorus atoms.

[0100] In step S7, phosphorus diffusion includes a deposition stage, a diffusion stage, and an oxidation stage, which are performed in sequence. The process conditions of each stage are as follows: the N2 gas flow rate is 25 L / min, the liquid doping source POCl3 enters the quartz tube, and then the O2 gas flow rate is 2 L / min, the deposition temperature is 780 ° C, and the deposition time is 2600 s; in the diffusion stage, a sufficient amount of N2 is introduced, the gas flow rate is 10 L / min, the O2 gas flow rate is 1 L / min, the diffusion temperature is 835 ° C, and the diffusion time is 1700 s; in the oxidation stage, the N2 gas flow rate is 10 L / min, and then the O2 gas flow rate is 1 L / min, the oxidation temperature is 874 ° C, and the oxidation time is 1300 s; the thickness of the PSG layer 8 is 37 nm, and the phosphorus doping concentration in the N+polySi layer 7 is 2.1e20 cm -3 .

[0101] S8: Figure 8 As shown, the silicon wafer 1 after the step S7 treatment enters an acidic wet process tank to remove the PSG layer 8 on the back to expose the N+polysi layer 7, and remove the second phosphorus-containing barrier layer 42 to expose the P+polysi layer 5 and the back surface of the silicon wafer 1 in the Gap area; and then enters an alkaline wet process tank for texturing to prepare a pyramid-shaped texturing surface on both the front side of the silicon wafer 1 and the back side of the silicon wafer 1 in the Gap area.

[0102] In step S8, the process conditions for acidic wet bath removal are as follows: the volume ratio of HF solution to nitric acid solution is 1:4, wherein the concentration of HF solution is 65 wt %, the concentration of nitric acid solution is 58 wt %, and the removal time is 130 s.

[0103] In step S8, the process conditions of alkaline wet bath texturing are as follows: the concentration of KOH solution is 1.5wt%, and the texturing is performed at 82°C for 220s to form a pyramid-shaped texturing surface on the back and front sides of the silicon wafer 1 in the Gap area. The texturing surface has a height of 1.4μm and a width of 1.8μm.

[0104] S9: As Figure 9 As shown, AlOx films 9 (aluminum oxide films) are deposited on both the front and back sides of the silicon wafer 1 after the process in step S8 as passivation films.

[0105] In step S9, the deposition process conditions of the AlOx film 9 are as follows: using ALD (atomic layer deposition), through the reaction of Al(CH3)3 with water vapor, an AlOx film 9 with a thickness of 5 nm is deposited on the back side of the silicon wafer 1 (i.e., the back side of the Gap area, the P+polysi layer 5 and the N+polysi layer 7) and the front side of the silicon wafer 1. The process temperature is 250°C and the deposition time is 300s.

[0106] S10: SiNx films 10 (silicon nitride films) are deposited on both the front surface of the front AlOx film 9 and the back surface of the back AlOx film 9 as passivation anti-reflection films.

[0107] In step S10, Figure 10 As shown, the deposition process conditions of the SiNx film 10 are as follows: PECVD (plasma enhanced chemical vapor deposition) is used to prepare a front SiNx film 10 and a back SiNx film 10 on the front side of the front AlOx film 9 and on the back side of the back AlOx film 9, respectively, and the thickness of the front SiNx film 10 and the back SiNx film 10 are both 75 nm; during the preparation process, the gases in the tube are SiH4 and NH3, the working pressure is 1600 mTorr, the power is 13000 W, the temperature is 460°C, the gas flow rate of SiH4 is 950 sccm, the flow rate of NH3 is 7800 sccm, the silicon-nitrogen ratio is 1:5, and the deposition time is 10 min; the refractive index of the front SiNx film 10 is 1.7, and the refractive index of the back SiNx film 10 is 1.9.

[0108] S11: If Figure 11 As shown, the back side of the silicon wafer 1 processed in step S10 is metallized to obtain a first metal electrode 11 that ohmically contacts the P+polySi layer 5 and a second metal electrode 12 that ohmically contacts the N+polySi layer 7 .

[0109] In step S11, the metallization process conditions are as follows: screen printing metal paste (such as Ag paste), the opening of the printing screen is 40μm; after printing, sintering at 860°C to form the first metal electrode 11 and the second metal electrode 12; after light injection, a TBC battery is obtained.

[0110] Example 2

[0111] The method for preparing a TBC battery of this embodiment specifically refers to Example 1, and the difference between this method and Example 1 is that:

[0112] In step S5 of this embodiment, an infrared laser is used instead. The laser wavelength of the infrared laser is 1150 nm, the laser power is 70 W, the laser scanning rate is 20,000 mm / s, the laser frequency is 500 KHz, and the laser spot size is 60 μm. In addition, the etching time of the alkaline wet process tank is changed to 200 s.

[0113] Comparative Example 1

[0114] The preparation method of a TBC battery in this comparative example specifically refers to Example 1, and the difference between the comparative example and Example 1 is that:

[0115] In this comparative example, the thickness of the first barrier layer in step S3 and the second barrier layer in step S6 were both changed to 0.08 μm.

[0116] Comparative Example 2

[0117] The preparation method of a TBC battery in this comparative example specifically refers to Example 1, and the difference between the comparative example and Example 1 is that:

[0118] In this comparative example, the thickness of the first barrier layer in step S3 and the second barrier layer in step S6 were both changed to 3.5 μm.

[0119] Comparative Example 3

[0120] The preparation method of a TBC battery in this comparative example specifically refers to Example 1, and the difference between the comparative example and Example 1 is that:

[0121] In this comparative example, the sintering temperature of the first barrier layer slurry in step S3 and the second barrier layer slurry in step S6 were changed to 855° C. to change the density of the barrier layer, and the first barrier layer and the second barrier layer were sintered to obtain a refractive index of 1.5.

[0122] Comparative Example 4

[0123] The preparation method of a TBC battery in this comparative example specifically refers to Example 1, and the difference between the comparative example and Example 1 is that:

[0124] In this comparative example, the sintering time of the first barrier layer slurry in step S3 and the second barrier layer slurry in step S6 were changed to 2.4 min to change the density of the barrier layer, and the first barrier layer and the second barrier layer were sintered to have a refractive index of 1.5.

[0125] Performance Testing

[0126] The performance tests were conducted on the TBC batteries of Examples 1-2 and Comparative Examples 1-4. The test results are shown in Table 1 below:

[0127] Table 1

[0128] Serial number Photoelectric conversion efficiency (%) Voc(mV) <![CDATA[Jsc(mA / cm 2 )]]> FF(%) Example 1 26.55 743.81 42.39 84.21 Example 2 26.32 738.27 42.27 84.33 Comparative Example 1 26.22 737.64 42.37 83.89 Comparative Example 2 26.10 736.54 42.18 84.01 Comparative Example 3 26.27 733.44 42.13 85.02 Comparative Example 4 26.25 732.34 42.03 85.28

[0129] In Table 1, Voc is the open circuit voltage, Jsc is the short circuit current density, and FF is the fill factor.

[0130] Combined with Table 1, we can see that:

[0131] (1) The lasers and the corresponding alkaline wet etching times in step S5 of Example 1 and Example 2 are different, resulting in a 0.23% difference in the photoelectric conversion efficiency values ​​of the two. This is mainly because the green laser has a smaller thermal impact on the P+polysi layer than the infrared laser, and the heavy doping effect is not obvious; while the infrared laser has a larger thermal impact, affecting the doping concentration of the P+polysi layer and affecting the passivation effect of the battery. Secondly, the laser heat affects the crystallization degree of the i-polysi layer. The infrared laser will accelerate the crystallization state of the i-polysi layer, thereby affecting the phosphorus doping of the i-polysi layer in the later stage.

[0132] Therefore, in step S5, a green laser is preferably used to pattern the left end region of the first barrier layer, which can further improve the photoelectric conversion efficiency of the battery and shorten the alkaline wet etching time.

[0133] (2) Comparative Example 2 increases the thickness of the barrier layers (e.g., the first barrier layer and the second barrier layer). Although the barrier layer has a good effect in blocking boron doping and phosphorus doping, the excessively thick barrier layer has a significant impact on the airflow blocking between wafers (referring to adjacent silicon wafers during the diffusion process) during the boron and phosphorus diffusion processes, resulting in uneven diffusion within the wafer. This further leads to uneven doping concentrations in the P+polySi layer and the N+polySi layer, thereby reducing the passivation effect and other performance of the battery. As a result, the FF, Jsc, Voc, and photoelectric conversion efficiency of the battery in Comparative Example 2 are significantly lower than those in Example 1.

[0134] (3) Comparative Example 1 reduces the thickness of the barrier layers (e.g., the first barrier layer and the second barrier layer). A too thin barrier layer significantly weakens the barrier capability, causing boron and phosphorus to diffuse into the i-polysilicon layer, P+polysilicon layer, and gap region silicon wafers blocked by the barrier layer, thereby neutralizing some electrons or holes and adversely affecting the contact resistance and passivation effect of the battery. Therefore, the FF, Voc, and photoelectric conversion efficiency of the battery in Comparative Example 1 were significantly lower than those in Example 1.

[0135] (4) Comparative Examples 3 and 4 respectively control the sintering temperature and sintering time of the barrier layer slurry to obtain low-refractive-index barrier layers (such as the first barrier layer and the second barrier layer). The lower the refractive index, the worse the material density, and the worse the blocking effect on the doping source, causing boron and phosphorus to diffuse into the i-polysilicon layer, P+polysilicon layer, and Gap region silicon wafer blocked by the barrier layer, thereby neutralizing some electrons or holes, adversely affecting the contact resistance and passivation effect of the battery. Therefore, the Jsc, Voc, and photoelectric conversion efficiency of the batteries of Comparative Examples 3 and 4 are significantly lower than those of Example 1.

[0136] In summary, the preparation method of the TBC battery of the present invention can further improve the FF, Jsc, Voc and photoelectric conversion efficiency of the battery by regulating the laser patterning process (as shown in Examples 1 and 2), regulating the thickness of the barrier layer (as shown in Comparative Examples 1 and 2), and regulating the sintering temperature and sintering time of the barrier layer slurry to regulate the refractive index of the barrier layer after sintering.

[0137] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0138] The technical solution provided by the present invention is introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for preparing a TBC battery, characterized in that: The method comprises the following preparation steps: Step 1: sequentially preparing a tunneling layer and an intrinsic amorphous silicon layer on the back side of the silicon wafer; Step 2: locally forming a first barrier layer on the back side of the intrinsic amorphous silicon layer; Step 3: Boron diffusion to transform the intrinsic amorphous silicon layer in the non-first barrier layer area into a boron-doped polysilicon layer, and to form a borosilicate glass layer on the back of the boron-doped polysilicon layer; Step 4: Laser patterning is used to remove one end of the first barrier layer near the boron-doped polysilicon layer to expose the intrinsic amorphous silicon layer in the laser area; wet etching is performed to remove the intrinsic amorphous silicon layer and the tunneling layer in the laser area to form a gap region exposing the silicon wafer, and the borosilicate glass layer is removed to expose the boron-doped polysilicon layer. The first barrier layer in the non-laser area is also removed to expose the intrinsic amorphous silicon layer; Step 5: locally forming a second barrier layer on the back side of the silicon wafer and the boron-doped polysilicon layer in the Gap area; Step 6: Phosphorus diffusion to transform the intrinsic amorphous silicon layer in the non-laser area into a phosphorus-doped polysilicon layer; Step 7: removing the second barrier layer and performing texturing; Step 8: Prepare a passivation anti-reflection film on the front and back sides of the textured silicon wafer, and then form a first metal electrode that ohmically contacts the boron-doped polysilicon layer and a second metal electrode that ohmically contacts the phosphorus-doped polysilicon layer through metallization.

2. The method for preparing a TBC battery according to claim 1, wherein: Before step 1, the method further includes: performing double-side polishing on the silicon wafer to remove impurities on the surface of the silicon wafer and forming a polished surface on the back side of the silicon wafer; In step 1, the tunneling layer is a tunneling silicon oxide layer with a thickness of 2-4 nm; the thickness of the intrinsic amorphous silicon layer is 200-380 nm.

3. The method for preparing a TBC battery according to claim 1, wherein: Step 2 of preparing the first barrier layer includes: locally printing a first barrier layer slurry on the back side of the intrinsic amorphous silicon layer by screen printing, and sintering to prepare the first barrier layer; Step 5 of preparing the second barrier layer includes: locally printing the second barrier layer slurry on the back side of the silicon wafer and the boron-doped polysilicon layer in the Gap area using screen printing, and sintering to prepare the second barrier layer.

4. The method for preparing a TBC battery according to claim 3, wherein: In steps 2 and 5, the screen printing screen opening is 400-620 μm, silicon oxide slurry is locally printed, and after printing, it is sintered at a high temperature of 860-900°C for 3-7 minutes; the first barrier layer and the second barrier layer are both silicon oxide barrier layers, and the width of the first barrier layer and the second barrier layer after sintering is 450-640 μm, the thickness is 0.2-2 μm, and the refractive index is 1.6-1.

8.

5. The method for preparing a TBC battery according to claim 1, wherein: In step 3, the thickness of the borosilicate glass layer is 45-65 nm, and the doping concentration of the boron-doped polysilicon is 8e19-2e20 cm -3 .

6. The method for preparing a TBC battery according to claim 1, wherein: In step 4, the laser is a green laser with a laser wavelength of 500-550 nm, a laser power of 60-120 W, a laser scanning rate of 5000-50000 mm / s, and a laser frequency of 250-1000 KHz; Alternatively, the laser is an infrared laser with a laser wavelength of 700-1200 nm, a laser power of 70-120 W, a laser scanning rate of 5000-20000 mm / s, and a laser frequency of 250-1000 KHz; The width of the first barrier layer removed by the laser region is 70-120 μm, and the width of the remaining first barrier layer is 380-500 μm.

7. The method for preparing a TBC battery according to claim 1 or 6, characterized in that: In step 4, the wet etching includes: firstly performing alkaline etching to remove the intrinsic amorphous silicon layer in the laser area, and then performing acid etching to remove the tunneling layer in the laser area, the borosilicate glass layer in the non-first barrier layer area, and the first barrier layer in the non-laser area.

8. The method for preparing a TBC battery according to claim 1, wherein: In step 6, a 35-55 nm thick phosphorus-silicon glass layer is formed on the back of the phosphorus-doped polysilicon layer; the doping concentration of the phosphorus-doped polysilicon layer is 1e20-4e20 cm -3 .

9. The method for preparing a TBC battery according to claim 8, characterized in that: The step 7 specifically includes: first acid wet etching to remove the phosphosilicate glass layer to expose the phosphorus-doped polysilicon layer, and remove the second barrier layer to expose the back of the Gap area silicon wafer and the boron-doped polysilicon layer; then alkaline texturing to form a velvet surface on the front side of the silicon wafer and the back side of the Gap area silicon wafer.

10. A TBC battery, characterized in that: It is prepared by the preparation method of a TBC battery according to any one of claims 1 to 9.

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