A seamless splicing screen

Abstract

The present application discloses a seamless splicing screen, including a motherboard and a plurality of sub-boards spliced ​​on the motherboard; each of the sub-boards includes a plurality of pixel units distributed in a plurality of rows and columns and at least one first alignment mark spaced apart from the plurality of pixel units; wherein a gap area is formed between any two adjacent rows of pixel units or two adjacent columns of pixel units; the at least one first alignment mark is located in the gap area; the motherboard includes at least one second alignment mark arranged in one-to-one correspondence with the at least one first alignment mark of each sub-board; wherein the projection of the first alignment mark in a direction perpendicular to the motherboard overlaps or fits with the projection of the corresponding second alignment mark in a direction perpendicular to the motherboard. The present application can reduce the splicing seam and realize the seamless splicing screen technology, and the alignment method of the first alignment mark and the second alignment mark can effectively improve the alignment accuracy.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a seamless splicing screen. Background Art

[0002] With the development of display panel technology, large-size public and commercial displays are increasingly popular among the public. Since the direct production of large-size display panels is limited by the generation line, large-size display panels are currently usually produced by splicing. Taking OLED (Organic Light-Emitting Diode) display panels as an example, due to the characteristics of devices such as LTPS (Low Temperature Poly-silicon), it is difficult to produce display products larger than 20 inches under existing technology, so if you want to obtain a large-size OLED display, you need to achieve it by splicing.

[0003] In transparent splicing display technology, the splicing screen is formed by connecting the metal pad (pad) on the splicing sub-unit (sub-board) and the metal pad on the motherboard. In order to accurately align the sub-board and the motherboard, it is necessary to make alignment marks on the sub-board and the motherboard respectively. At present, the alignment marks of the sub-board are usually placed outside the display area and within the cutting line. Therefore, when the sub-board and the mother-board are aligned, due to the presence of the alignment marks, it will inevitably lead to a larger joint between the two adjacent sub-boards, and it is impossible to achieve seamless splicing screen technology. Summary of the invention

[0004] The present application provides a seamless splicing screen, which can reduce the seam between any two adjacent sub-panels, realize the seamless splicing screen technology, and the orthographic projection of the first alignment mark and the second alignment mark overlap or fit together, which can effectively improve the alignment accuracy.

[0005] The present application provides a seamless splicing screen, comprising a motherboard and a plurality of sub-boards spliced ​​and arranged on the motherboard;

[0006] Each of the sub-boards comprises a plurality of pixel units distributed in a plurality of rows and columns and at least one first alignment mark arranged at intervals from the plurality of pixel units; wherein a gap region is formed between any two adjacent rows of pixel units or two adjacent columns of pixel units; and the at least one first alignment mark is located in the gap region;

[0007] The motherboard includes at least one second alignment mark arranged in one-to-one correspondence with the at least one first alignment mark of each of the daughter boards; wherein the projection of the first alignment mark in a direction perpendicular to the motherboard overlaps or is embedded with the projection of the corresponding second alignment mark in a direction perpendicular to the motherboard.

[0008] Optionally, in any two adjacent rows of pixel units or two adjacent columns of pixel units, at least three adjacent pixel units enclose a sub-gap region, and the gap region is composed of a plurality of the sub-gap regions;

[0009] At least one of the sub-gap areas is a forbidden area, and the at least one first alignment mark is located in the forbidden area.

[0010] Optionally, the forbidden area is arranged close to a diagonal position of the sub-board.

[0011] Optionally, each of the sub-boards is rectangular, and each of the sub-boards has a forbidden area and the first alignment mark located in the forbidden area at four diagonal positions.

[0012] Optionally, the forbidden area of ​​the sub-board includes a substrate, and the first alignment mark and a transparent encapsulation layer sequentially arranged on the substrate.

[0013] Optionally, the transparent encapsulation layer includes a first inorganic encapsulation layer covering the substrate and the first alignment mark, a transparent ink material layer located on the first inorganic encapsulation layer, and a second inorganic encapsulation layer located on the transparent ink material layer.

[0014] Optionally, the material of the first inorganic encapsulation layer includes any one of silicon nitride and silicon oxide, and the material of the second inorganic encapsulation layer includes any one of silicon nitride and silicon oxide.

[0015] Optionally, the plurality of pixel units are arranged on the substrate, and each pixel unit includes a light shielding layer, a thin film transistor, and a light emitting device which are sequentially arranged on the substrate;

[0016] The first alignment mark is disposed on the same layer as the light shielding layer, and the second inorganic encapsulation layer extends to cover the plurality of pixel units.

[0017] Optionally, the projection shape of the first alignment mark in a direction perpendicular to the motherboard includes a "X" shape; the projection shape of the second alignment mark in a direction perpendicular to the motherboard includes any one of an "○" shape and a "╬" shape.

[0018] Optionally, the motherboard includes a plurality of pads which are arranged in a one-to-one correspondence with the plurality of pixel units and are electrically connected in a one-to-one correspondence with the plurality of pixel units.

[0019] The seamless splicing screen provided by the present application is conducive to narrowing the frame of the sub-board or even eliminating the frame of the sub-board by setting the first alignment mark on the sub-board in the gap area between the pixel units, that is, setting it in the display area, thereby reducing the joints between adjacent sub-boards and realizing large-size seamless splicing screen technology; and when the sub-board and the motherboard are aligned, the first alignment mark of the sub-board and the orthographic projection of the second alignment mark of the motherboard coincide or fit together, which can effectively improve the alignment accuracy. . BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0021] Figure 1 A schematic diagram of the structure of a seamless splicing screen provided in an embodiment of the present application.

[0022] Figure 2 A schematic diagram of the top view structure of a sub-board provided in an embodiment of the present application.

[0023] Figure 3 for Figure 2 Schematic diagram of the cross-sectional structure at AA in the middle.

[0024] Figure 4 A schematic diagram of the top view of the structure of a motherboard provided in an embodiment of the present application.

[0025] Figure 5 A schematic diagram of a first alignment mark and a second alignment mark provided in an embodiment of the present application.

[0026] Figure 6 A schematic diagram of the top view structure of another motherboard provided in an embodiment of the present application.

[0027] Figure 7 A schematic diagram of another mosaic of a first alignment mark and a second alignment mark provided in an embodiment of the present application.

[0028] Figure 8 A schematic diagram of the alignment of a daughter board and a mother board provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0030] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0031] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0032] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0033] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0034] like Figure 1 As shown, an embodiment of the present application provides a seamless splicing screen 1 , which includes a motherboard 2 and a plurality of sub-boards 3 spliced ​​and arranged on the motherboard 2 . Figure 1 Only nine sub-boards 3 are shown, but the present invention is not limited thereto.

[0035] like Figure 2 As shown, each sub-panel 3 includes a plurality of pixel units 4 distributed in a plurality of rows and columns and at least one first alignment mark 5 arranged at intervals from the plurality of pixel units 4. A gap area 6 is formed between any two adjacent rows of pixel units 4 or two adjacent columns of pixel units 4; at least one first alignment mark 5 is located in the gap area 6. It can be understood that the first alignment mark 5 is arranged in the display area of ​​the sub-panel 3, avoiding the need to reserve a space outside the display area to arrange the alignment mark, which is conducive to narrowing the frame of the sub-panel 3 or even eliminating the frame of the sub-panel 3, thereby reducing the joint seam between adjacent sub-panels 3, and is conducive to realizing seamless splicing technology.

[0036] Specifically, the number of the first alignment marks 5 may be one, two, three or four. The embodiment of the present application takes four as an example for description.

[0037] Specifically, in any two adjacent rows of pixel units 4 or two adjacent columns of pixel units 4, at least three adjacent pixel units 4 enclose a sub-gap region 7, and the gap region 6 is composed of a plurality of sub-gap regions 7. Figure 2 As shown, in any two adjacent rows of pixel units 4 or two adjacent columns of pixel units 4 , every four adjacent pixel units 4 enclose a sub-gap area 7 , and the gap area 6 is composed of a plurality of sub-gap areas 7 .

[0038] Specifically, at least one of the multiple sub-gap areas 7 is a forbidden area 8, and the first alignment mark 5 is set in the forbidden area 8. It can be understood that the sub-gap area 7 with the first alignment mark 5 is a forbidden area 8, the number of forbidden areas 8 is the same as the number of first alignment marks 5, and each first alignment mark 5 is correspondingly located in a sub-gap area 7. It should be noted that no other images except the alignment mark can be set in the forbidden area 8 to avoid interference with the alignment. It can be understood that the other areas in the forbidden area 8 except the alignment mark are transparent areas, which can be clearly used for the CCD (Charge-coupled Device) camera to capture the first alignment mark 5.

[0039] Specifically, in order to facilitate finding the position of the first alignment mark 5, the forbidden area 8 is arranged close to the diagonal position of the sub-board 3. It can be understood that the first alignment mark 5 is arranged close to the diagonal position of the sub-board 3.

[0040] In a specific embodiment, Figure 2 As shown, each sub-board 3 is rectangular, and each sub-board 3 is provided with a forbidden area 8 and a first alignment mark 5 located in the forbidden area 8 at four diagonal positions. In this embodiment, providing the first alignment mark 5 at the four diagonal positions of each sub-board 3 is conducive to improving the alignment accuracy.

[0041] like Figure 3 As shown, the forbidden area 8 of the sub-plate 3 includes a substrate 9, and a first alignment mark 5 and a transparent encapsulation layer 10 sequentially arranged on the substrate 9. The transparent encapsulation layer 10 includes a first inorganic encapsulation layer 11 covering the substrate 9 and the first alignment mark 5, a transparent ink material layer 12 located on the first inorganic encapsulation layer 11, and a second inorganic encapsulation layer 13 located on the transparent ink material layer 12.

[0042] Specifically, the material of the substrate 9 includes PI (Polyimide), and specifically can be any one of CPI (Colorless Polyimde, transparent polyimide) and YPI (Yellow Polyimide, yellow polyimide).

[0043] Specifically, the material of the first inorganic encapsulation layer 11 includes any one of silicon nitride and silicon oxide, and the material of the second inorganic encapsulation layer 13 includes any one of silicon nitride and silicon oxide.

[0044] like Figure 3As shown, a plurality of pixel units 4 are arranged on a substrate 9, and each pixel unit 4 includes a light shield (LS) layer 14, a barrier layer 15, a buffer layer 16, a thin film transistor 17, a flat layer 18, an anode layer 19, a pixel definition layer 20, and a light emitting device 21, which are sequentially arranged on the substrate 9. Among them, the first alignment mark 5 is arranged in the same layer as the light shield layer 14, and the second inorganic encapsulation layer 13 extends to cover the plurality of pixel units 4. In this embodiment, the first alignment mark 5 is arranged on the substrate 9, so that the first alignment mark 5 has a height difference with the adjacent pixel unit 4, which improves the focusing accuracy of the CCD camera during alignment, which is conducive to improving the alignment accuracy.

[0045] In a specific embodiment, the thin film transistor 17 is a dual-gate thin film transistor, specifically including a semiconductor layer 22 disposed on the buffer layer 16, a first gate 24 insulating layer 23 covering the semiconductor layer 22, a first gate 24 disposed on the first gate 24 insulating layer 23 and corresponding to the channel region 30 of the semiconductor layer 22, a second gate 26 insulating layer 25 covering the first gate 24, a second gate 26 disposed on the second gate 26 insulating layer 25 and corresponding to the second gate 26, an interlayer insulating layer 27 covering the second gate 26, and a source 28 and a drain 29 connected to doped portions 31 on both sides of the channel region 30 through a through hole penetrating the interlayer insulating layer 27, the second gate 26 insulating layer 25 and the first gate 24 insulating layer 23. The material of the semiconductor layer 22 includes polycrystalline silicon, and doped portions 31 (e.g., P+ doping) are disposed on both sides of the channel region 30 of the semiconductor layer 22, and the anode layer 19 is connected to the drain 29 through a through hole penetrating the planar layer 18.

[0046] It should be noted that the embodiment of the present application does not limit the specific structure of the thin film transistor 17 , and does not limit the specific structure of the light emitting device 21 .

[0047] In a specific embodiment, each pixel unit 4 further includes a support layer (not shown in the figure) disposed between the pixel definition layer 20 and the second inorganic encapsulation layer 13. Specifically, a pixel opening is disposed on the pixel definition layer 20 to expose the anode layer 19, and the light emitting device 21 is disposed in the pixel opening and electrically connected to the drain electrode 29 of the thin film transistor 17 through the anode layer 19.

[0048] It can be understood that the blocking layer 15, the buffer layer 16, the first gate 24 insulating layer 23, the second gate 26 insulating layer 25, the interlayer insulating layer 27, the flat layer 18 and the pixel definition layer 20 in the forbidden area 8 are all removed, and a transparent encapsulation layer 10 is formed, which is conducive to the CCD camera to accurately capture the first alignment mark 5.

[0049] like Figures 4 to 8As shown, the motherboard 2 includes at least one second alignment mark 32 arranged in one-to-one correspondence with at least one first alignment mark 5; wherein the projection of the first alignment mark 5 in a direction perpendicular to the motherboard 2 coincides or fits with the projection of the corresponding second alignment mark 32 in a direction perpendicular to the motherboard 2. Figure 8 As shown, in this embodiment, the sub-board 3 and the motherboard 2 are aligned by taking the first alignment mark 5 and the second alignment mark 32 as an example.

[0050] Specifically, the motherboard 2 is divided into a plurality of splicing areas 33 , each splicing area 33 is used to align a daughter board 3 , and each splicing area 33 is provided with the same number of second alignment marks 32 as the first alignment marks 5 on a single daughter board 3 .

[0051] It can be understood that the number of second alignment marks 32 of the motherboard 2 is the same as the total number of first alignment marks 5 of the multiple sub-boards 3, and when the multiple sub-boards 3 are spliced ​​on the motherboard 2, each first alignment mark 5 is overlapped with the projection of the corresponding second alignment mark 32 in the direction perpendicular to the motherboard 2.

[0052] Specifically, Figure 8 As shown, the motherboard 2 includes a plurality of pads 34 arranged one-to-one and electrically connected to the plurality of pixel units 4, and a driving circuit (not shown in the figure) electrically connected to the plurality of pads 34. The driving circuit is used to transmit electrical signals to the plurality of pixel units 4 in the daughterboard 3 through the plurality of pads 34 to control the light emitting device 21 to emit light.

[0053] Specifically, the number of pads 34 is equal to the total number of pixel units 4 of the plurality of sub-boards 3. It can be understood that the second alignment mark 32 is located between the pads 34 and the second alignment mark 32 is also located in the transparent forbidden area on the motherboard 2, so that the CCD camera can capture the second alignment mark 32.

[0054] In a specific embodiment, Figure 2 and Figure 4 As shown, the projection shape of the first alignment mark 5 in the direction perpendicular to the motherboard 2 is a "cross" shape, and the projection shape of the second alignment mark 32 in the direction perpendicular to the motherboard 2 is an "○" shape; when multiple sub-boards 3 are spliced ​​and arranged on the motherboard 2, the first alignment mark 5 and the second alignment mark 32 are aligned with each other, as shown in FIG. Figure 5 shown.

[0055] In another specific embodiment, Figure 2 and Figure 6As shown, the projection shape of the first alignment mark 5 in the direction perpendicular to the motherboard 2 includes a "cross" shape, and the projection shape of the second alignment mark 32 in the direction perpendicular to the motherboard 2 is a "╬" shape; when multiple sub-boards 3 are spliced ​​and arranged on the motherboard 2, the first alignment mark 5 and the second alignment mark 32 are aligned with each other, as shown in FIG. Figure 7 shown.

[0056] Of course, the specific shapes of the first alignment mark 5 and the second alignment mark 32 are not limited thereto.

[0057] In other embodiments, the projection shape of the second alignment mark 32 in the direction perpendicular to the motherboard 2 may also be the same as the projection shape of the first alignment mark 5 in the direction perpendicular to the motherboard 2. When multiple sub-boards 3 are spliced ​​and set on the motherboard 2, the first alignment mark 5 and the second alignment mark 32 overlap and align.

[0058] In this embodiment, by setting the first alignment mark 5 on the sub-board 3 in the gap area 6 between the pixel units 4 and the pixel units 4, that is, setting it in the display area, it is beneficial to narrow the border of the sub-board 3 or even eliminate the border of the sub-board 3, thereby reducing the joints between adjacent sub-boards 3, which is beneficial to realize large-size seamless splicing screen technology; and when the sub-board 3 and the motherboard 2 are aligned, the first alignment mark 5 of the sub-board 3 coincides or fits with the orthographic projection of the second alignment mark 32 of the motherboard 2, which can effectively improve the alignment accuracy.

[0059] The above is a detailed introduction to a seamless splicing screen provided in an embodiment of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A seamless splicing screen, characterized in that: It includes a motherboard and a plurality of sub-boards spliced ​​and arranged on the motherboard; Each of the sub-boards comprises a plurality of pixel units distributed in a plurality of rows and columns and at least one first alignment mark arranged at intervals from the plurality of pixel units; wherein a gap region is formed between any two adjacent rows of pixel units or two adjacent columns of pixel units; and the at least one first alignment mark is located in the gap region; The motherboard includes at least one second alignment mark arranged in one-to-one correspondence with the at least one first alignment mark of each of the daughter boards; wherein the projection of the first alignment mark in a direction perpendicular to the motherboard overlaps or interlocks with the projection of the corresponding second alignment mark in a direction perpendicular to the motherboard; in any two adjacent rows of pixel units or two adjacent columns of pixel units, at least three adjacently arranged pixel units enclose a sub-gap area, and the gap area is composed of a plurality of the sub-gap areas; At least one of the sub-gap areas is a forbidden area, and the at least one first alignment mark is located in the forbidden area; the forbidden area of ​​the sub-board includes a substrate and the first alignment mark and a transparent encapsulation layer sequentially arranged on the substrate; the transparent encapsulation layer includes a first inorganic encapsulation layer covering the substrate and the first alignment mark, a transparent ink material layer located on the first inorganic encapsulation layer, and a second inorganic encapsulation layer located on the transparent ink material layer; the multiple pixel units are arranged on the substrate, and each pixel unit includes a shading layer, a thin film transistor, and a light-emitting device sequentially arranged on the substrate; the first alignment mark is arranged on the same layer as the shading layer, and the second inorganic encapsulation layer extends to cover the multiple pixel units.

2. The seamless splicing screen according to claim 1, characterized in that: The forbidden area is arranged close to the diagonal position of the sub-board.

3. The seamless splicing screen according to claim 2, characterized in that: Each of the sub-plates is rectangular, and each of the sub-plates has a forbidden area and the first alignment mark located in the forbidden area at four diagonal positions.

4. The seamless splicing screen according to claim 1, characterized in that: The material of the first inorganic encapsulation layer includes any one of silicon nitride and silicon oxide, and the material of the second inorganic encapsulation layer includes any one of silicon nitride and silicon oxide.

5. The seamless splicing screen according to claim 1, characterized in that: The projection shape of the first alignment mark in a direction perpendicular to the motherboard includes a "X" shape; the projection shape of the second alignment mark in a direction perpendicular to the motherboard includes an "○" shape and a " ╬ "Any one of the following shapes.

6. The seamless splicing screen according to claim 1, characterized in that: The motherboard includes a plurality of pads which are arranged in a one-to-one correspondence with the plurality of pixel units and are electrically connected in a one-to-one correspondence.

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