Semiconductor structure and method for preparing three-dimensional memory

Abstract

The present application provides a method for preparing a semiconductor structure and a three-dimensional memory, which includes: alternately stacking sacrificial layers and dielectric layers on a substrate to form a stacked structure, wherein the stacked structure includes a cutting area; forming a plurality of first dummy channel openings that penetrate the portion of the stacked structure located in the cutting area and extend into the substrate; filling the first dummy channel openings with a channel filling material to form a first dummy channel structure; forming a cutting groove that penetrates the first dummy channel structure; and filling the cutting groove with a conductive material to form a cutting lane.

Description

Technical Field

[0001] The present application relates to the field of three-dimensional memory technology, and more specifically, to a semiconductor structure and a method for preparing a three-dimensional memory. Background Art

[0002] In 3D memory, scribe lines are used to separate different chips. Typically, a wafer contains multiple chips, with scribe lines between adjacent chips. Scribe lines are used to dice the wafer into small dies, which are then packaged to form chips. However, as the number of stacked layers in 3D memory increases, the etch depth-to-width ratio of the scribe lines also increases, making the manufacturing process more difficult. Summary of the Invention

[0003] An embodiment of the present application provides a method for preparing a three-dimensional memory, the method comprising: alternately stacking sacrificial layers and dielectric layers on a substrate to form a stacked structure, wherein the stacked structure includes a cutting area; forming a plurality of first dummy channel openings that penetrate a portion of the stacked structure located in the cutting area and extend into the substrate; filling the first dummy channel openings with a channel filling material to form a first dummy channel structure; forming a cutting groove that penetrates the first dummy channel structure; and filling the cutting groove with a conductive material to form a cutting lane.

[0004] In one embodiment, the first dummy channel opening, the cutting groove, and the cutting street have contour lines in a cross section parallel to the substrate in a direction parallel to the substrate.

[0005] In one embodiment, the stacking structure also includes a step area, and the method further includes: forming a second dummy channel opening that penetrates the portion of the stacking structure located in the step area and extends into the substrate, and filling the second dummy channel opening with a channel filling material to form a second dummy channel structure, wherein the second dummy channel opening and the first dummy channel opening are formed using the same mask plate, and the second dummy channel structure is formed when the first dummy channel structure is formed.

[0006] In one embodiment, the stacked structure further includes a core region and a step region, and the method further includes: forming a gate line slit that penetrates portions of the stacked structure located in the core region and the step region and extends into the substrate; and replacing the sacrificial layer in the core region and the step region with a gate layer through the gate line slit. In one embodiment, the method further includes: replacing the sacrificial layer with the gate layer.

[0007] In one embodiment, the step area includes a plurality of steps and an insulating layer covering the plurality of steps, and the method further includes: forming a plurality of conductive channel holes that penetrate the insulating layer and extend respectively to the portion of the gate layer located in the step area, and filling the conductive channel holes with conductive material to form a plurality of conductive pillars, wherein the plurality of conductive channel holes and the cutting grooves are formed using the same mask plate, and the plurality of conductive pillars are formed when the cutting path is formed.

[0008] In one embodiment, the insulating layer and the trench filling material are configured to have the same etching selectivity.

[0009] In a second aspect, an embodiment of the present application provides a semiconductor structure comprising a substrate; a stacked structure disposed on the substrate, the stacked structure comprising a cutting area; and a plurality of first dummy channel structures penetrating a portion of the stacked structure located in the cutting area and having a cutting path therethrough.

[0010] In one embodiment, a contour line of a cross section of the scribe line parallel to the substrate is in the shape of a U-shape.

[0011] In one embodiment, the portion of the stacked structure located in the cutting area includes alternately stacked sacrificial layers and dielectric layers.

[0012] In one embodiment, the stacked structure further includes a step region, wherein the semiconductor structure further includes a second dummy channel structure, and the second dummy channel structure penetrates the portion of the stacked structure located in the step region and extends into the substrate.

[0013] In one embodiment, the first dummy channel structure and the second dummy channel structure include the same channel filling material.

[0014] In one embodiment, the stack structure further includes a step region, and the portion of the stack structure located in the step region includes alternately stacked gate layers and dielectric layers.

[0015] In one embodiment, the step region includes a plurality of steps and an insulating layer covering the plurality of steps, wherein the semiconductor structure further includes a plurality of conductive pillars, which penetrate the insulating layer and extend respectively to portions of the gate layer located in the step region.

[0016] According to the semiconductor structure and three-dimensional memory fabrication method provided in this application, the dielectric layer and sacrificial layer of the stacked structure are retained in the dicing area, effectively reducing stress in the step region of the three-dimensional memory and lowering the processing difficulty in the step region. By forming a first dummy channel structure penetrating the stacked structure in the dicing area and then forming dicing streets through the first dummy channel structure, the dicing streets can be closer to the step region, thereby reducing the chip size of the three-dimensional memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0018] Figure 1 and Figure 2 It is a top view schematically showing the distribution of the cutting area, step area and core area of ​​the three-dimensional memory.

[0019] Figure 3 FIG. 1 is a schematic cross-sectional view of a semiconductor structure in an embodiment.

[0020] Figure 4 is a flow chart of a method for preparing a three-dimensional memory in another embodiment.

[0021] Figures 5 to 9 1 is a schematic diagram of a process for preparing a three-dimensional memory according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0022] For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not represent any limitation on the features. Therefore, without departing from the teachings of this application, the first dummy channel structure discussed below may also be referred to as the second dummy channel structure, and vice versa.

[0024] In the accompanying drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The drawings are for illustration purposes only and are not drawn strictly to scale. For example, the thickness of the substrate and stacked structure are not to scale as would be used in actual production. As used herein, the terms "substantially," "approximately," and similar terms are intended to indicate approximations, not degrees, and are intended to account for the inherent variations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art.

[0025] It should also be understood that the terms "comprises," "including," "having," "includes," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than modifying the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application." And, the term "exemplary" is intended to refer to an example or illustration.

[0026] Unless otherwise defined, all words used herein (including engineering terms and scientific and technological terms) have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that, unless otherwise specified in this application, words defined in commonly used dictionaries should be interpreted as having the same meaning as they do in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0027] As used herein, the term "layer" refers to a material portion comprising an area having a thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far away from the substrate. A layer can extend over the entire underlying structure or superstructure, or can have a range smaller than the underlying structure or superstructure. In addition, a layer can be an area of ​​a uniform or non-uniform continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer can be located at the top and bottom surfaces of a continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, such as a semiconductor layer. A substrate can include one or more layers therein, and / or can have one or more layers thereon, above and / or below. A substrate can be a layer having a thickness that is capable of supporting, or a layer having a thickness that is not capable of supporting.

[0028] It should be noted that, unless otherwise specified or inconsistent with the context, the embodiments and features of the embodiments in this application may be combined with each other. Furthermore, unless expressly limited or inconsistent with the context, the specific steps included in the methods described in this application are not necessarily limited to the order in which they are described, but may be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0029] Figure 1 and Figure 2 3D memory is a top view of the memory, which may include a core region (Core) 103 and a step region (SS) 102 surrounded by a cutting region 101, that is, the cutting region 101 is arranged around the core region 103 and the step region 102. In one embodiment of the present application, the core region 103 and the step region 102 are arranged as follows: Figure 1 As shown, the step area 102 is located between the two core areas 103. In another embodiment of the present application, the core area 103 and the step area 102 are arranged as follows Figure 2 As shown, the core area 103 is located between the two step areas 102. However, those skilled in the art will appreciate that Figure 1 and Figure 2 The configuration of the middle core area 103 and the step area 102 is an exemplary configuration, and the present application is not limited thereto.

[0030] Figure 1 and Figure 2 As schematically shown, the cutting area 101 may include two cutting streets 501 , wherein the contour line of the cross section of the cutting street 501 in a direction parallel to the substrate is in the shape of a U-shape.

[0031] Figure 3 FIG. 1 is a cross-sectional view of a semiconductor structure 10′ in an embodiment. Figure 3 As shown, a semiconductor structure 10' may include a substrate 10a and a stacked structure 20a formed on the substrate 10a, wherein the stacked structure 20a includes dielectric layers 201a and gate layers 203a alternately stacked on the substrate 10a. The semiconductor structure 10' may also include an insulating layer 30a. The insulating layer 30a primarily covers the step structure of the step region 102a and also serves as a support material for the dicing region 101a. For example, two dicing streets 501a are formed in the insulating layer 30a in the dicing region 101a. For example, the insulating layer 30a may include at least one insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The step region 102a may include a plurality of dummy channel structures 402a and conductive pillars 502a. The dummy channel structures 402a primarily provide support for the step region 102a.

[0032] The semiconductor structure 10' can be mechanically divided into a plurality of chips for subsequent formation of three-dimensional memory via the sawing lines 501a. The inventors have noticed in their research that Figure 3 In the semiconductor structure 10' of the illustrated embodiment, the insulating layer 30a located in the dicing region 101a is formed simultaneously with the formation of the insulating layer 30a in the step region 102a. The insulating layer 30a in the dicing region 102a is then etched to form a dicing groove (not shown), which is then filled with a conductive material to form a dicing street 501a. However, as the number of stacked structures 20a increases, the aspect ratio of the dicing street 501a increases, and the stress distribution imbalance between the insulating layer 30a and the stacked structure 20a becomes increasingly severe, resulting in an increasingly difficult process for preparing the dicing street 501a.

[0033] Some embodiments of the present application provide different Figure 3 The preparation method of the three-dimensional memory is shown. Figure 4 A flow chart of a method 1000 for preparing a three-dimensional memory in another embodiment is schematically shown. Figure 4 As shown, the method includes:

[0034] S110: alternately stacking sacrificial layers and dielectric layers on a substrate to form a stacked structure, wherein the stacked structure includes a cutting area;

[0035] S120: forming a plurality of first dummy channel openings penetrating the portion of the stacked structure located in the cutting region and extending into the substrate;

[0036] S130: filling a channel filling material in the first dummy channel opening to form a first dummy channel structure;

[0037] S140: forming a cutting groove penetrating the first dummy channel structure; and

[0038] S150: Filling the cutting groove with a conductive material to form a cutting street.

[0039] The process for preparing a 3D memory also includes numerous steps, such as preparing the core region and peripheral circuitry of the 3D memory. However, to highlight the key points of the invention, this application does not describe these steps. Those skilled in the art can, based on their knowledge, determine the preparation methods related to the dicing region disclosed in this application and other 3D memory structures. The embodiments and process flow in this application only illustrate the formation of an intermediate 3D memory having a dicing region and a step region.

[0040] It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. In addition, some of the steps may be performed simultaneously or in different steps. Figure 4Executed in the order shown.

[0041] Figures 5 to 9 1 is a cross-sectional diagram of a method 1000 for manufacturing a three-dimensional memory according to an embodiment of the present application. Figures 5 to 9 The above steps S110 to S150 are further described.

[0042] S110, alternately stacking sacrificial layers and dielectric layers on a substrate to form a stacked structure, wherein the stacked structure includes Cutting area.

[0043] In some implementations of step S110, Figure 5 As shown, in this step, dielectric layers 201 and sacrificial layers 202 are alternately stacked on the substrate 10 to form a stacked structure 20. Exemplarily, the method for forming the stacked structure 20 may include a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The number of stacks of dielectric layers 201 and sacrificial layers 202 in the stacked structure 20 may be, for example, 8 layers, 32 layers, 64 layers, 128 layers, etc. The more stacks of the stacked structure 20, the higher the integration, and the more memory cells formed thereby. The number of stacks and the stack height of the stacked structure 20 can be designed according to actual storage requirements, and this application does not specifically limit this.

[0044] For example, the material of the substrate 10 may include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, or any combination thereof. The material of the insulating layer 201 may include, for example, an oxide (e.g., silicon oxide). The material of the sacrificial layer 202 may include, for example, a nitride (e.g., silicon nitride).

[0045] In some examples, the function of the substrate 10 is to provide support for other structures prepared thereon, but in appropriate steps, a photolithography and etching process (e.g., a dry or wet etching process), a CMP process, or any combination thereof can be used to remove the substrate 10 from the side of the substrate 10 facing away from the stacked structure 20. In some cases, as an example, a semiconductor layer, such as polysilicon, can also be formed on the side of the stacked structure 20 exposed by removing the substrate 10. The substrate 10 also includes the above-mentioned semiconductor layer, and the substrate 10 may not have support capabilities. The present application does not limit the material and thickness of the substrate 10. The substrate 10 can be a layer with a thickness that has support capabilities, or a layer with a thickness that does not have support capabilities.

[0046] In exemplary embodiments, the stack structure 20 according to the present application may have a structure in which silicon oxide and silicon nitride are sequentially deposited as a stack.

[0047] In an exemplary embodiment, Figure 5 As shown, a cutting area 101 and a step area 102 can be defined in the stacking structure 20, or it can be considered that the stacking structure 20 can include portions located in the cutting area 101 and the step area 102. For example, the portion of the stacking structure 20 located in the step area 102 is patterned into multiple step structures.

[0048] In some embodiments, the step structure can be formed by performing multiple trim-etch cycles on a plurality of alternately stacked dielectric layers 201 and a plurality of sacrificial layers 202. For example, Figure 5 As shown, each step may include a dielectric layer 201 and a sacrificial layer 202. In a direction perpendicular to the substrate 10, the pair of dielectric layers 201 and sacrificial layers 202 farther from the substrate 10 partially cover the pair of dielectric layers 201 and sacrificial layers 202 adjacent and closer to the substrate 10, thereby leaving the sacrificial layer 202 in the pair of dielectric layers 201 and sacrificial layers 202 closer to the substrate 10 with an area exposed to the pair of dielectric layers 201 and sacrificial layers 202 adjacent and farther from the substrate 10. The exposed area of ​​the sacrificial layer 202 may serve as an electrical connection area for a wordline contact formed in a subsequent process.

[0049] In some embodiments, an insulating layer 30 is formed above the step structure. The insulating layer 30 includes at least one insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The insulating layer 30 is primarily used to cover the step structure and surrounding areas, such as the dicing area 101 and the core area (not shown). Chemical mechanical polishing (CMP) can be used to planarize the surface of the insulating layer 30 in the core area, the step area 102, and the dicing area 101.

[0050] S120, forming a plurality of first dummy channels penetrating the portion of the stacked structure located in the cutting area and extending into the substrate Speak.

[0051] In some implementations of step S120, Figure 6 As shown, in this step, a plurality of first dummy channel openings 41 are formed, wherein the first dummy channel openings 41 penetrate the portion of the stacked structure 20 located in the cutting area 101 and extend into the substrate 10 .

[0052] In some embodiments of step S120 , step S120 may further include forming a second dummy channel opening 42 , where the second dummy channel opening 42 penetrates the insulating layer 30 and a portion of the stacked structure 20 located in the step region 102 .

[0053] In some embodiments, the first dummy channel opening 41 and the second dummy channel opening 42 can be fabricated using the same process and method. That is, the first dummy channel opening 41 and the second dummy channel opening 42 can be formed simultaneously using the same mask. For example, a photolithography and etching process (e.g., a dry or wet etching process) can be used to form multiple dummy channel openings that penetrate the stacked structure 20 and extend into the substrate 10. In particular, for ease of distinction in the subsequent description, the dummy channel opening located in the cutting area 101 is defined as the first dummy channel opening 41, and the dummy channel opening located in the step area 102 is defined as the second dummy channel opening 42.

[0054] In some embodiments, a cross-sectional outline of the first dummy channel opening 41 in a direction parallel to the substrate 10 is closed, for example, a polygon.

[0055] In some embodiments, two first dummy channel openings 41 may be provided, and a cross-sectional profile of the first dummy channel opening 41 in a direction parallel to the substrate 10 is in a U-shaped shape.

[0056] S130 , filling the first dummy channel opening with a channel filling material to form a first dummy channel structure.

[0057] In some implementations of step S130, Figure 7 As shown, in this step, a trench filling material is filled in the first dummy trench opening 41 to form a first dummy trench structure 401 .

[0058] In some embodiments, a cross-sectional outline of the first dummy channel structure 401 in a direction parallel to the substrate 10 is closed, for example, a polygon.

[0059] In some embodiments, two first dummy channel structures 401 may be provided, and a cross-sectional profile of the first dummy channel structure 401 in a direction parallel to the substrate 10 is in a U-shape.

[0060] In some implementations of step S130 , step S130 may further include filling a trench filling material in the second dummy trench opening 42 to form a second dummy trench structure 402 .

[0061] In some embodiments, the filling material and filling process of the first dummy channel structure 401 and the second dummy channel structure 402 can be the same, that is, the first dummy channel opening 41 and the second dummy channel opening 42 can be filled with a channel filling material at the same time to simultaneously form the first dummy channel structure 401 and the second dummy channel structure 402. For example, after the first dummy channel opening 41 and the second dummy channel opening 42 are formed as described above, at least one channel filling material can be filled in the first dummy channel opening 41 and the second dummy channel opening 42 using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, wherein the channel filling material can be an insulating material, such as silicon oxide. Figure 7 The first dummy channel structure 401 and the second dummy channel structure 402 are simplified, or it is considered that Figure 7 The first dummy channel structure 401 and the second dummy channel structure 402 in the embodiment include only the channel filling material.

[0062] The functions of the first dummy channel structure 401 and the second dummy channel structure 402 include, but are not limited to, providing mechanical support or load balancing. In particular, the second dummy channel structure 402 is designed to alleviate stress imbalance between the insulating layer 30 and the step structure. It is understood that the multiple second dummy channel structures 402 can be closer together, thereby improving the support provided by the dummy channel structures 402 to the insulating layer 30. This is particularly true when the step structure has a large number of layers and a high height. The densely arranged second dummy channel structures 402 provide better support for the subsequent gate replacement process.

[0063] refer to Figure 7 and Figure 8A In an exemplary embodiment of the present application, the method 1000 for manufacturing a three-dimensional memory device may further include replacing the sacrificial layer 202 in the core region (not shown) and the step region 102 with a gate layer 203. The stacked structure 20 in the cut region 101 still retains the structure of alternately stacking dielectric layers 201 and sacrificial layers 202.

[0064] In some embodiments, a gate line slit (not shown) is formed that penetrates the portion of the stack structure 20 located in the core region (not shown) and the step region 102 and extends into the substrate 10, and the sacrificial layer 202 of the stack structure 20 located in the core region and the step region 102 is replaced with a gate layer 203 using the gate line slit. For example, a photolithography and etching process (such as a dry or wet etching process) can be used to form a gate line slit that penetrates the portion of the stack structure 20 located in the core region and the step region 102 and extends into the substrate 10. Further, the gate line slit can be used as a passage for providing an etchant and a chemical precursor, and a process such as wet etching can be used to remove the sacrificial layer 202 of the stack structure 20 located in the core region and the step region 102 to form a sacrificial gap (not shown). Subsequently, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to form a gate layer 203 ( Figure 8A ). Optionally, the material of the gate layer 203 may include, for example, a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof.

[0065] S140 , forming a cutting groove penetrating the first dummy channel structure.

[0066] In some implementations of step S140, Figure 8A As shown, in this step, a cutting groove 51 is formed through the first dummy channel structure 401. Exemplarily, the first dummy channel structure 401 is etched, and a photolithography and etching process (such as a dry or wet etching process) can be used to form the cutting groove 51 through the first dummy channel structure 401.

[0067] Figure 8B for Figure 8A In the cross-sectional schematic diagram at AA, for example, the contour line of the cross section of the cutting groove 51 in the direction parallel to the substrate 10 is in the shape of a U-shaped U.S. dollar.

[0068] In some embodiments, a cross-sectional contour line of the cutting groove 51 in a direction parallel to the substrate 10 is closed, for example, a polygon.

[0069] In some implementations of step S140, Figure 8A As shown, step S140 may further include forming conductive channel holes 52, which penetrate the insulating layer 30 and extend to the gate layer 203 at the corresponding steps. For example, etching the insulating layer 30 may be performed using photolithography and etching processes (eg, dry or wet etching processes).

[0070] In an exemplary embodiment, the trench filling material included in the first dummy trench structure 401 and the insulating layer 30 may be the same or have the same etching selectivity, and an etching process may be performed simultaneously using the same mask to form the cutting groove 51 and the conductive channel hole 52 simultaneously.

[0071] S150 , filling the cutting groove with a conductive material to form a cutting street.

[0072] In some implementations of step S150, Figure 9 As shown, in this step, a conductive material is filled in the cutting groove 51 to form a cutting street 501. For example, the conductive material can be filled in the cutting groove 51 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The conductive material can include, for example, tungsten, cobalt, copper, aluminum, or any combination thereof.

[0073] In some embodiments, a cross-sectional contour line of the scribe line 501 in a direction parallel to the substrate 10 is closed, for example, a polygon.

[0074] In some embodiments, two scribe lines 501 may be provided, and the outline of the cross section of the scribe line 501 in a direction parallel to the substrate 10 is in the shape of a U-shape.

[0075] In some implementations of step S150, Figure 9 As shown, step S150 may further include filling the conductive channel hole 52 with a conductive material to form a conductive pillar 502, which is the word line contact of the three-dimensional memory. For example, the conductive material may be filled in the conductive channel hole 52 using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. For example, the plurality of conductive pillars 502 may extend to the electrical connection region of the plurality of gate layers 203 in a direction intersecting the gate layer 203, such as a direction perpendicular or substantially perpendicular to the gate layer 203, so that one end of the conductive pillar 502 is electrically connected to the gate layer 203. The conductive material may, for example, include a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof.

[0076] In some embodiments, the materials and processes used for filling the cutting groove 51 with conductive material to form the cutting path 501 and filling the conductive channel hole 52 with conductive material to form the conductive pillar 502 may be the same, that is, the cutting path 501 and the conductive pillar 502 may be formed simultaneously.

[0077] Another aspect of the present application further provides a semiconductor structure 2000, such as Figure 9As shown, the semiconductor structure 2000 may include a cutting area 101 and a step area 102. According to some embodiments of the present application, the semiconductor structure includes: a substrate 10, a stacked structure 20, a first dummy channel structure 401 and a cutting street 501.

[0078] The substrate 10 is a semiconductor substrate. Suitable materials can be selected to form the substrate 10 based on actual needs, and no further details will be given here. In some examples, the substrate 10 serves to provide support for other structures fabricated thereon. However, in some cases, as an example, the substrate 10 may also be a semiconductor layer that does not have support capabilities, such as polycrystalline silicon. This application does not limit the material and thickness of the substrate 10. The substrate 10 may be a layer with a thickness that is supportive, or a layer with a thickness that is not supportive.

[0079] In an exemplary embodiment, the portion of the stacked structure 20 located in the cutting area 101 may include sacrificial layers 202 and dielectric layers 201 alternately stacked in a direction perpendicular or substantially perpendicular to the substrate 10. The material of the dielectric layer 201 may include, for example, an oxide (such as silicon oxide). The material of the sacrificial layer 202 may include, for example, a nitride (such as silicon nitride).

[0080] The first dummy channel structure 401 penetrates a portion of the stacked structure 20 located in the cutting region 101 . The first dummy channel structure 401 may include at least one channel filling material. The channel filling material may be an insulating material, such as silicon oxide.

[0081] The cutting street 501 is located in the cutting region 101 and passes through the first dummy trench structure 401. The cutting street 501 may include a conductive material, such as tungsten, cobalt, copper, aluminum, or any combination thereof.

[0082] In some embodiments, the cross-sectional contours of the first dummy channel structure 401 and the scribe line 501 in a direction parallel to the substrate 10 are closed, for example, polygonal.

[0083] In some embodiments, the cross-sectional profiles of the first dummy channel structure 401 and the scribe line 501 in a direction parallel to the substrate 10 are in the shape of a U-shape.

[0084] In an exemplary embodiment, the portion of the stacked structure 20 located in the step region 102 may include a plurality of steps, wherein each step includes at least one pair of gate layers 203 and dielectric layers 201. In a direction perpendicular to the substrate 10, the pair of dielectric layers 201 and gate layers 203 farther from the substrate 10 partially covers the pair of dielectric layers 201 and gate layers 203 adjacent and closer to the substrate 10, thereby leaving the gate layer 203 in the pair of dielectric layers 201 and gate layers 203 closer to the substrate 10 with an area exposed to the pair of dielectric layers 201 and gate layers 203 adjacent and farther from the substrate 10. The exposed area of ​​the gate layer 203 may serve as an electrical connection area for a wordline contact. The material of the gate layer 203 may include, for example, a conductive material such as tungsten, cobalt, copper, aluminum, or any combination thereof.

[0085] In an exemplary embodiment, the semiconductor structure 2000 further includes an insulating layer 30. The insulating layer 30 is mainly used to cover the step structure and the surrounding area. For example, the insulating layer 30 can cover the step area 102 and the cutting area 101. The material of the insulating layer 30 can be, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0086] In an exemplary embodiment, the semiconductor structure 2000 further includes a second dummy channel structure 402 located in the stepped region 102. The second dummy channel structure 402 may penetrate the insulating layer 30 and the portion of the stacked structure 20 located in the stepped region 102. The second dummy channel structure 402 may include at least one channel filling material, which may be an insulating material, such as silicon oxide.

[0087] In some embodiments, the trench filling material and filling process of the first dummy channel structure 401 and the second dummy channel structure 402 may be the same. Figure 9 The first dummy channel structure 401 and the second dummy channel structure 402 are simplified, or it is considered that Figure 9 The first dummy channel structure 401 and the second dummy channel structure 402 in the embodiment include only the channel filling material.

[0088] The functions of the first dummy channel structure 401 and the second dummy channel structure 402 include, but are not limited to, providing mechanical support or load balancing. In particular, the second dummy channel structure 402 is designed to alleviate stress imbalance between the insulating layer 30 and the step structure. It is understood that the multiple second dummy channel structures 402 can be closer to each other, thereby improving the support provided by the dummy channel structures 402 to the insulating layer 30. In particular, when the step structure has many layers and is therefore tall, the densely arranged second dummy channel structures 402 provide better support for processes such as gate replacement and chemical mechanical polishing.

[0089] In an exemplary embodiment, the trench filling material included in the first dummy trench structure 401 and the insulating layer 30 may be the same or have the same etching selectivity.

[0090] In an exemplary embodiment, the semiconductor structure 2000 further includes a conductive pillar 502 located in the step region 102. The conductive pillar 502 penetrates the insulating layer 30 and extends to the gate layer 203 of the corresponding step. The conductive pillar 502 may comprise a conductive material. For example, the plurality of conductive pillars 502 may extend in a direction intersecting the gate layer 203, for example, in a direction perpendicular or substantially perpendicular to the gate layer 203, to the electrical connection region of the plurality of gate layers 203, thereby electrically connecting one end of the conductive pillar 502 to the gate layer 203. The conductive pillar 502 serves as a wordline contact for a three-dimensional memory device. The conductive material may include, for example, tungsten, cobalt, copper, aluminum, or any combination thereof.

[0091] In some embodiments, the materials of the scribe lines 501 and the conductive pillars 502 may be the same.

[0092] Since the contents and structures involved in the above description of the preparation method 1000 are fully or partially applicable to the semiconductor structure described here, the relevant or similar contents are not repeated. The semiconductor structure 2000 can be mechanically divided into multiple chips for subsequent formation of a three-dimensional memory via saw streets 501.

[0093] Figure 3 The cutting area 101a in the semiconductor structure 10' in one embodiment shown does not retain the stacking structure 20a. The cutting area 101a is located in the insulating layer 30a near the step area 102a. When forming the cutting path 501a using the conductive contact (CT) process, a sufficient process width is required. Therefore, the cutting path 501a can only be set at a position far away from the step area 102a, so the size of the chip is larger. In addition, the step structure of the step area 102a and the insulating layer 30a covering the step structure and the cutting area 101a are made of different materials, which will cause the step area 102a to be subjected to greater stress. However, referring to Figure 9 The cutting area 101 of the semiconductor structure 2000 provided in the embodiment of the present application retains the dielectric layer 201 and the sacrificial layer 202 of the stacked structure 20, which can effectively relieve the stress of the step area 102. The cutting road 501 is formed by the first virtual channel structure 401, and the cutting road 501 can be closer to the step area 102, thereby reducing the chip size.

[0094] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also includes other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the technical concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions in this application.

Claims

1. A method for preparing a three-dimensional memory, characterized in that: The method comprises: Alternately stacking sacrificial layers and dielectric layers on a substrate to form a stacked structure, wherein the stacked structure includes a step region and a cutting region, and a portion of the stacked structure located in the step region has a step structure; forming an insulating layer covering the step structure; forming a plurality of first dummy channel openings penetrating the portion of the stacked structure located in the cutting region and extending into the substrate; Filling the first dummy channel opening with a channel filling material to form a first dummy channel structure, wherein the channel filling material is the same as the material of the insulating layer or has the same etching selectivity; forming a cutting groove penetrating the first dummy channel structure; and The cutting grooves are filled with a conductive material to form cutting streets.

2. The method according to claim 1, wherein The first dummy channel opening, the cutting groove, and the cutting street have contour lines in a cross section parallel to the substrate direction that are arranged in a U-shape.

3. The method according to claim 1, wherein The method further comprises: forming a second dummy channel opening penetrating the portion of the stacked structure located in the step region and extending into the substrate, and filling the second dummy channel opening with a channel filling material to form a second dummy channel structure; The second dummy channel opening and the first dummy channel opening are formed using the same mask plate, and the second dummy channel structure is formed when the first dummy channel structure is formed.

4. The method according to claim 1, wherein The stacked structure further includes a core area, and the method further includes: forming a gate line slit penetrating portions of the stacked structure located in the core region and the step region and extending into the substrate; and The sacrificial layer located in the core area and the step area is replaced with a gate layer through the gate line slits.

5. The method according to claim 4, wherein The method further comprises: forming a plurality of conductive channel holes penetrating the insulating layer and extending respectively to portions of the gate layer located in the step region, and filling the conductive channel holes with a conductive material to form a plurality of conductive pillars; The plurality of conductive channel holes and the cutting grooves are formed by using the same mask plate, and the plurality of conductive pillars are formed when the cutting streets are formed.

6. A semiconductor structure, wherein: include: substrate; A stacking structure is provided on the substrate, the stacking structure comprising a step area and a cutting area, and a portion of the stacking structure located in the step area has a step structure; an insulating layer covering the step structure; A plurality of first dummy channel structures penetrate the portion of the stacked structure located in the cutting area and have cutting streets therethrough. The material of the first dummy channel structure is the same as that of the insulating layer or has the same etching selectivity.

7. The semiconductor structure according to claim 6, wherein: The contour line of the cross section of the scribe line in a direction parallel to the substrate is in the shape of a U-shape.

8. The semiconductor structure according to claim 6, wherein The portion of the stacked structure located in the cutting area includes sacrificial layers and dielectric layers stacked alternately. 9 . The semiconductor structure according to claim 6 , further comprising a second dummy channel structure, wherein the second dummy channel structure penetrates a portion of the stack structure located in the step region and extends into the substrate.

10. The semiconductor structure according to claim 9, wherein The first dummy channel structure and the second dummy channel structure include the same channel filling material.

11. The semiconductor structure according to claim 6, wherein The portion of the stacked structure located in the step region includes alternately stacked gate layers and dielectric layers. 12 . The semiconductor structure according to claim 11 , further comprising a plurality of conductive pillars, each of which penetrates the insulating layer and extends to a portion of the gate layer located in the step region.

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