Display substrate, manufacturing method thereof, and display device

Abstract

The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes: a base substrate, a plurality of sub-pixels, a gate drive circuit, a plurality of input contact pads, a plurality of output contact pads, and a contact pad insulating layer, wherein surfaces of the plurality of input contact pads and the plurality of output contact pads facing away from the base substrate are exposed from the contact pad insulating layer, wherein the contact pad insulating layer includes a first portion having a first thickness and a second portion having a second thickness, the second thickness being less than the first thickness, edges of the plurality of input contact pads and the plurality of output contact pads are covered by the first portion of the contact pad insulating layer, and the second portion of the contact pad insulating layer is located in a region between the plurality of input contact pads and the plurality of output contact pads.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device. Background Art

[0002] Typically, the pins on display substrates that connect to driver chips are designed with a multilayer structure to elevate the pins and enhance adhesion to their corresponding pins on the driver chip. During the manufacturing process, an organic layer is applied to the pins, which is then removed to expose them. However, traditional display substrates can easily cause the driver chip IC to fall off during high-temperature and high-humidity reliability testing. Summary of the Invention

[0003] An embodiment of the present disclosure provides a display substrate, comprising:

[0004] The base substrate comprises a display area, a bonding area located on at least one side of the display area, and a side area located on at least the other side of the display area;

[0005] A plurality of sub-pixels are located in the display area;

[0006] a gate driving circuit, located in the side area, connected to the plurality of sub-pixels and configured to provide a gate driving signal to the plurality of sub-pixels;

[0007] a plurality of input contact pads located in the bonding area for electrically connecting to an external circuit;

[0008] a plurality of output contact pads located in the bonding area and between the plurality of input contact pads and the display area, the plurality of output contact pads being electrically connected to the plurality of sub-pixels and the gate driving circuit;

[0009] A contact pad insulating layer is located in the bonding area and is located in the gaps between adjacent input contact pads among the multiple input contact pads, the gaps between adjacent output contact pads among the multiple output contact pads, and the area between the multiple input contact pads and the multiple output contact pads, wherein surfaces of the multiple input contact pads and the multiple output contact pads facing away from the substrate are exposed from the contact pad insulating layer, wherein the contact pad insulating layer includes a first portion having a first thickness and a second portion having a second thickness, wherein the second thickness is less than the first thickness, edges of the multiple input contact pads and the multiple output contact pads are covered by the first portion of the contact pad insulating layer, and the second portion of the contact pad insulating layer is located in the area between the multiple input contact pads and the multiple output contact pads.

[0010] For example, the display substrate further includes: a plurality of first dummy contact pads located in the bonding region and in a region between the plurality of input contact pads and the plurality of output contact pads, wherein:

[0011] Edges of the plurality of first dummy contact pads are covered by a first portion of the contact pad insulating layer, and surfaces of the plurality of first dummy contact pads facing away from the substrate are exposed from the first portion of the contact pad insulating layer; and

[0012] The second portion of the contact pad insulating layer includes a first subportion located in a region between the first dummy contact pads and the input contact pads, and a second subportion located in a region between the first dummy contact pads and the output contact pads.

[0013] For example, the display substrate further includes: a plurality of array test contact pads located in the bonding area and in an area between the plurality of first dummy contact pads and the plurality of input contact pads, the plurality of array test contact pads being electrically connected to the plurality of sub-pixels and the gate drive circuit, wherein:

[0014] The first portion of the contact pad insulating layer includes a first sub-portion and a second sub-portion, edges of the plurality of input contact pads, edges of the plurality of output contact pads, and an edge of the first dummy contact pad are covered by the first sub-portion of the first portion of the contact pad insulating layer, edges of the plurality of array test contact pads are covered by the second sub-portion of the first portion of the contact pad insulating layer, and surfaces of the plurality of array test contact pads facing away from the substrate are exposed from the first portion of the contact pad insulating layer;

[0015] A projection of the second sub-portion of the first portion of the contact pad insulating layer on the base substrate is located within a projection of the first sub-portion of the second portion of the contact pad insulating layer on the base substrate.

[0016] For example, a distance between a projection of each of the plurality of input contact pads and the plurality of output contact pads on the base substrate and a projection of the second portion of the contact pad insulating layer on the base substrate is in a range of 3 μm to 100 μm.

[0017] For example, the second thickness is 0.

[0018] For example, the plurality of input contact pads are arranged in at least a first row along a first direction, where the first direction is an extension direction of a side of the display area facing the bonding area;

[0019] The plurality of output contact pads are arranged in at least a second row along the first direction;

[0020] The plurality of first virtual contact pads are arranged in at least a third row along the first direction;

[0021] The plurality of array test contact pads are arranged in at least a fourth row along the first direction.

[0022] For example, the display substrate further includes: a plurality of second virtual contact pads located in the bonding area, arranged in at least a first column and a second column along a second direction perpendicular to the first direction, wherein the first column and the second column are respectively located on both sides of the plurality of first virtual contact pads in the first direction, wherein,

[0023] Edges of the plurality of second dummy contact pads are covered by the first portion of the contact pad insulating layer, and surfaces of the plurality of second dummy contact pads facing away from the substrate are exposed from the first portion of the contact pad insulating layer; and

[0024] A distance between a projection of each of the plurality of second dummy contact pads on the base substrate and a projection of the second portion of the contact pad insulating layer on the base substrate is in a range of 3 micrometers to 100 micrometers.

[0025] For example, at least one of the plurality of input contact pads and the plurality of output contact pads includes:

[0026] a first lead connection portion located on the substrate, wherein the first lead connection portion of the input contact pad is electrically connected to a connection contact pad for connecting to an external circuit via a first lead provided in the bonding region, and the first lead connection portion of the output contact pad is electrically connected to the gate drive circuit or to at least one of the plurality of sub-pixels via a second lead provided in the bonding region;

[0027] a first conductor portion, located on a side of the first lead connection portion facing away from the base substrate and electrically connected to the first lead connection portion;

[0028] The second conductor portion is located on a side of the first conductor portion away from the base substrate and is electrically connected to the first conductor portion. An edge of the second conductor portion is covered by the first portion of the contact pad insulating layer.

[0029] For example, the display substrate further includes:

[0030] A first gate insulating layer in the bonding region is located in the bonding region and covers the base substrate, and the first lead connection portion is located on a side of the first gate insulating layer in the bonding region away from the base substrate;

[0031] a second gate insulating layer in the bonding region, located in the bonding region, located on a side of the first gate insulating layer in the bonding region away from the base substrate and covering the first lead connection portion;

[0032] a bonding region interlayer insulating layer located in the bonding region and located on a side of the second gate insulating layer in the bonding region facing away from the base substrate, wherein the first conductor portion is electrically connected to the first lead connection portion through a via hole provided in the second gate insulating layer in the bonding region and a via hole provided in the bonding region interlayer insulating layer;

[0033] The bonding area passivation layer is located in the bonding area, on a side of the bonding area interlayer insulating layer away from the base substrate and covers the first conductor portion. The second conductor portion is electrically connected to the first conductor portion through a via hole provided in the bonding area passivation layer.

[0034] For example, the thickness of a portion of the bonding region passivation layer located between the second portion of the contact pad insulating layer and the second gate insulating layer in the bonding region is greater than or equal to 0.

[0035] For example, the display substrate also includes:

[0036] A first gate insulating layer in the bonding region is located in the bonding region and covers the base substrate, and the first lead connection portion is located on a side of the first gate insulating layer in the bonding region away from the base substrate;

[0037] a second gate insulating layer in the bonding region, located in the bonding region, located on a side of the first gate insulating layer in the bonding region away from the base substrate and covering the first lead connection portion;

[0038] The bonding area interlayer insulating layer is located in the bonding area and is located on the side of the second gate insulating layer in the bonding area away from the base substrate. The first conductor portion is electrically connected to the first lead connection portion through a via hole provided in the second gate insulating layer in the bonding area and a via hole provided in the interlayer insulating layer in the bonding area. The second conductor portion is located on the side of the first conductor portion away from the base substrate and covers the first conductor portion.

[0039] For example, the at least one of the plurality of input contact pads and the plurality of output contact pads further comprises:

[0040] The third conductor portion is located on a side of the second conductor portion away from the base substrate and is electrically connected to the second conductor portion.

[0041] For example, the display substrate further includes:

[0042] a bonding area barrier layer, located in the bonding area, covering the second conductor layer and the first portion of the contact pad insulating layer;

[0043] The bonding area inorganic layer is located in the bonding area and covers the bonding area barrier layer. The third conductor part is electrically connected to the second conductor part through a via hole provided in the bonding area barrier layer and a via hole provided in the bonding area inorganic layer.

[0044] For example, at least one of the plurality of first dummy contact pads includes a fourth conductor portion, the fourth conductor portion is located on a side of the substrate facing the plurality of input contact pads and the plurality of output contact pads, and an edge of the fourth conductor portion is covered by the first portion of the contact pad insulating layer.

[0045] At least one of the plurality of input contact pads and the plurality of output contact pads includes a first lead connection portion, a first conductor portion, and a second conductor portion, and the fourth conductor portion is provided in the same layer as the second conductor portion.

[0046] For example, at least one of the plurality of first virtual contact pads further includes a fifth conductor portion, the fifth conductor portion is located between the fourth conductor portion and the base substrate and is electrically connected to the fourth conductor portion, and the fifth conductor portion is provided in the same layer as the first conductor portion.

[0047] For example, at least one of the plurality of array test contact pads comprises:

[0048] a second lead connection portion, located on a side of the substrate facing the plurality of input contact pads and the plurality of output contact pads;

[0049] a sixth conductor portion, located on a side of the second lead connection portion facing away from the base substrate, and electrically connected to the second lead connection portion;

[0050] a seventh conductor portion, located on a side of the sixth conductor portion facing away from the substrate, electrically connected to the sixth conductor portion, and an edge of the seventh conductor portion being covered by the first portion of the contact pad insulating layer;

[0051] At least one of the multiple input contact pads and the multiple output contact pads includes a first lead connection portion, a first conductor portion, and a second conductor portion, and the second lead connection portion, the sixth conductor portion, and the seventh conductor portion are respectively arranged on the same layer as the first lead connection portion, the first conductor portion, and the second conductor portion.

[0052] For example, at least one of the plurality of second dummy contact pads includes an eighth conductor portion, the eighth conductor portion is located on a side of the substrate facing the plurality of input contact pads and the plurality of output contact pads, and an edge of the eighth conductor portion is covered by the first portion of the contact pad insulating layer.

[0053] At least one of the plurality of input contact pads and the plurality of output contact pads includes a first lead connection portion, a first conductor portion, and a second conductor portion, and the eighth conductor portion is provided in the same layer as the second conductor portion.

[0054] For example, at least one of the plurality of second virtual contact pads further includes a ninth conductor portion, the ninth conductor portion is located between the eighth conductor portion and the base substrate and is electrically connected to the eighth conductor portion, and the ninth conductor portion is provided in the same layer as the first conductor portion.

[0055] For example, at least one of the plurality of sub-pixels includes a pixel driving circuit, a first planarization layer, a first transfer electrode, a second planarization layer, and a light-emitting element.

[0056] The first planarization layer is provided on a side of the pixel driving circuit away from the substrate to provide a first planarized surface;

[0057] The first switching electrode is on the first planarized surface and is electrically connected to the pixel driving circuit through a via hole provided in the first planarized layer;

[0058] The second planarization layer is provided on a side of the first transfer electrode away from the base substrate to provide a second planarized surface;

[0059] The light emitting element is on the second planarized surface and is electrically connected to the first switching electrode through a via hole provided in the second planarized layer;

[0060] Wherein, the contact pad insulating layer and the second planarization layer are provided in the same layer.

[0061] For example, the pixel driving circuit includes a thin film transistor, the thin film transistor includes a gate, a source and a drain, and at least one of the plurality of input contact pads and the plurality of output contact pads includes a first lead connection portion, a first conductor portion and a second conductor portion, wherein,

[0062] The first lead connection portion is provided on the same layer as the gate;

[0063] The first conductor portion is provided in the same layer as the source and drain,

[0064] The second conductor portion and the first switching electrode are arranged in the same layer.

[0065] For example, the display substrate further includes a display area passivation layer, the display area passivation layer is located between the pixel driving circuit and the first planarization layer, and the pixel driving circuit and the first switching electrode are further electrically connected through a via hole provided in the display area passivation layer;

[0066] The display substrate further includes a bonding area passivation layer, and the bonding area passivation layer and the display area passivation layer are arranged on the same layer.

[0067] For example, the display substrate further includes an encapsulation layer located in the display area, a display area barrier layer, a first touch electrode layer, a second touch electrode layer, and a touch insulation layer. The encapsulation layer is located on a side of the light-emitting element away from the base substrate. The display area barrier layer is located on a side of the encapsulation layer away from the base substrate. The first touch electrode layer is located on a side of the display area barrier layer away from the base substrate. The touch insulation layer is located on a side of the first touch electrode layer away from the base substrate and covers the first touch electrode layer. The second touch electrode layer is located on a side of the touch insulation layer away from the base substrate.

[0068] The display substrate also includes a bonding area barrier layer and a bonding area inorganic layer located in the bonding area, and at least one of the multiple input contact pads and the multiple output contact pads also includes a third conductor portion. The bonding area barrier layer, the bonding area inorganic layer and the third conductor portion are respectively located on the same layer as the display area barrier layer, the touch insulation layer and the second touch electrode layer.

[0069] For example, at least one of the plurality of sub-pixels further includes a display area interlayer insulating layer, a display area first gate insulating layer, and a display area second gate insulating layer, wherein the display area interlayer insulating layer is located between the gate electrode and the source electrode and the drain electrode, the display area first gate insulating layer is located on a side of the display area interlayer insulating layer facing the base substrate, and the display area second gate insulating layer is located between the display area interlayer insulating layer and the display area first gate insulating layer;

[0070] The display substrate further includes a bonding area interlayer insulating layer, a bonding area first gate insulating layer and the bonding area second gate insulating layer. The bonding area interlayer insulating layer, the bonding area first gate insulating layer and the bonding area second gate insulating layer are respectively arranged on the same layer as the display area interlayer insulating layer, the display area first gate insulating layer and the display area second gate insulating layer.

[0071] For example, at least one of the multiple sub-pixels further includes a storage capacitor, a first electrode of the storage capacitor is arranged in the same layer as the gate, and a second electrode of the storage capacitor is arranged between the display area interlayer insulating layer and the display area second gate insulating layer.

[0072] For example, the substrate includes:

[0073] First flexible layer,

[0074] a second flexible layer located on a side of the first flexible layer facing the plurality of input contact pads and the plurality of output contact pads;

[0075] a first substrate barrier layer located between the first flexible layer and the second flexible layer;

[0076] a second substrate barrier layer, located on a side of the second flexible layer facing away from the first flexible layer;

[0077] The buffer layer is located on a side of the second substrate barrier layer facing away from the first flexible layer.

[0078] An embodiment of the present disclosure further provides a display device including the above-mentioned display substrate.

[0079] An embodiment of the present disclosure further provides a method for manufacturing the above-mentioned display substrate, comprising:

[0080] Providing a base substrate, the base substrate comprising a display area, a bonding area located on at least one side of the display area, and a side area located on at least another side of the display area;

[0081] forming a plurality of sub-pixels in the display area;

[0082] forming a gate driving circuit in the side area, the gate driving circuit being connected to the plurality of sub-pixels and configured to provide a gate driving signal to the plurality of sub-pixels;

[0083] forming a plurality of input contact pads in the bonding region for electrical connection with an external circuit;

[0084] forming a plurality of output contact pads in the bonding area, the plurality of output contact pads being located between the plurality of input contact pads and the display area, the plurality of output contact pads being electrically connected to the plurality of sub-pixels and the gate driving circuit;

[0085] A contact pad insulating layer is formed in the bonding area, wherein the contact pad insulating layer is located in gaps between adjacent input contact pads among the multiple input contact pads, gaps between adjacent output contact pads among the multiple output contact pads, and an area between the multiple input contact pads and the multiple output contact pads, surfaces of the multiple input contact pads and the multiple output contact pads facing away from the substrate are exposed from the contact pad insulating layer, wherein the contact pad insulating layer includes a first portion having a first thickness and a second portion having a second thickness, wherein the second thickness is less than the first thickness, edges of the multiple input contact pads and the multiple output contact pads are covered by the first portion of the contact pad insulating layer, and the second portion of the contact pad insulating layer is located in an area between the multiple input contact pads and the multiple output contact pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0086] Figure 1A A schematic diagram of a display substrate according to an embodiment of the present disclosure is shown.

[0087] Figure 1B Shown Figure 1A Schematic diagram of a display area of ​​a display substrate.

[0088] Figure 2 A partial plan view of a bonding area of ​​a display substrate according to an embodiment of the present disclosure is shown.

[0089] Figure 3 Shown Figure 2 Schematic diagram of a cross section of a display substrate along A1-B1.

[0090] Figure 4A Shown Figure 2 A cross-sectional view of an example of a display substrate along A2-B2.

[0091] Figure 4B Shown Figure 2 A cross-sectional view of an example of a display substrate along A3-B3.

[0092] Figure 4C Shown Figure 2 A cross-sectional view of an example of a display substrate along A4-B4.

[0093] Figure 5 A cross-sectional view of a display area of ​​a display substrate according to an embodiment of the present disclosure is shown.

[0094] Figure 6A and Figure 6B Shown respectively Figure 2 Another example of a display substrate is a cross-sectional view taken along A2 - B2 and along A3 - B3 .

[0095] Figure 7A and Figure 7B Shown respectively Figure 2 sectional views of yet another example of a display substrate at the bonding area along lines A2 - B2 and A3 - B3 .

[0096] Figure 8A and Figure 8B Shown respectively Figure 2 A cross-sectional view of yet another example of a display substrate at the bonding area along lines A2 - B2 and A3 - B3 is shown.

[0097] Figure 9 A cross-sectional view of a display area of ​​a display substrate according to another embodiment of the present disclosure is shown.

[0098] Figure 10 A partial plan view of a bonding area of ​​a display substrate according to another embodiment of the present disclosure is shown.

[0099] Figure 11 Shown Figure 10 Schematic diagram of a cross section of a display substrate along C1-D1.

[0100] Figure 12A Shown Figure 11A cross-sectional view of an example of a display substrate along C2-D2.

[0101] Figure 12B Shown Figure 11 A cross-sectional view of another example of a display substrate taken along C2-D2.

[0102] Figure 12C Shown Figure 11 A cross-sectional view of yet another example of a display substrate along C2-D2.

[0103] Figure 13 A partial plan view of a bonding area of ​​a display substrate according to yet another embodiment of the present disclosure is shown.

[0104] Figure 14 Shown Figure 13 Schematic diagram of a cross section of a display substrate along E1-F1.

[0105] Figure 15A Shown Figure 13 A cross-sectional view of an example of a display substrate along E2-F2.

[0106] Figure 15B Shown Figure 13 A cross-sectional view of an example of a display substrate along E3-F3.

[0107] Figure 15C Shown Figure 13 A cross-sectional view of another example of a display substrate taken along E3-F3.

[0108] Figure 15D Shown Figure 13 A cross-sectional view of yet another example of a display substrate taken along E3-F3.

[0109] Figure 16A A cross-sectional view of a display area of ​​a display substrate according to another embodiment of the present disclosure is shown.

[0110] Figure 16B Shown Figure 16A A cross-sectional view of the bonding area of ​​the display substrate.

[0111] Figures 17A to 17G A schematic diagram illustrating a manufacturing process of a display substrate according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0112] While the present disclosure will be fully described with reference to the accompanying drawings that contain preferred embodiments of the present disclosure, it should be understood before this description that one of ordinary skill in the art may modify the disclosure described herein while still achieving the technical benefits of the present disclosure. Therefore, it should be understood that the above description is intended to be a broad disclosure for one of ordinary skill in the art and is not intended to limit the exemplary embodiments described herein.

[0113] In addition, in the following detailed description, for ease of explanation, numerous specific details are set forth to provide a comprehensive understanding of the disclosed embodiments. However, it is apparent that one or more embodiments can be practiced without these specific details. In other cases, well-known structures and devices are shown in diagrammatic form to simplify the accompanying drawings.

[0114] Figure 1A A schematic diagram of a display substrate according to an embodiment of the present disclosure is shown. Figure 1B Shown Figure 1A Schematic diagram of a display area of ​​a display substrate.

[0115] like Figure 1A and Figure 1B As shown, the display substrate includes a base substrate 10, which includes a display area 11, a bonding area 12 located on at least one side of the display area 11, and a side area 13 located on at least the other side of the display area. Figure 1A In the embodiment, the bonding area 12 is located on one side of the display area 11 along the y direction, and the side area 13 is located on both sides of the display area 11 along the x direction. A plurality of sub-pixels Pix are provided in the display area 11. The plurality of sub-pixels Pix can be arranged in an array. Figure 1B In the figure, x represents the row direction of the sub-pixel array, and y represents the column direction of the sub-pixel array. The display area 11 is also provided with a plurality of gate lines G1 to GN and a plurality of data lines D1 to DM. Each gate line G1 to GN is connected to at least one row of sub-pixels Pix to provide a gate drive signal to the sub-pixels Pix in that row, and each data line D1 to DM is connected to at least one column of sub-pixels Pix to provide a data signal to the sub-pixels Pix in that column. Each sub-pixel Pix can be turned on under the control of the gate drive signal on the gate line connected to it, and the turned-on sub-pixel Pix can emit light under the drive of the data signal on the data line connected to it.

[0116] The gate driving circuit 130 is located in the side area 13. Figure 1A There are two gate drive circuits 130, which are respectively located in the side areas 13 on both sides of the display area 11. The gate drive circuits 130 are connected to the plurality of sub-pixels Pix. Figure 1A and Figure 1B In the embodiment, the gate driving circuit 130 is connected to a plurality of rows of sub-pixels Pix through a plurality of gate lines G1 to GN to provide gate driving signals to the sub-pixels Pix in each row. Figure 1AAs shown, the gate drive circuit 130 is also connected to various drive control signal lines, such as a first clock signal line CK1 for providing a first clock signal, a second clock signal line CK2 for providing a second clock signal, and a start signal line STV for providing a start signal. The gate drive circuit 130 may include multiple cascaded shift registers GOA0 to GOAN. Each stage of the shift registers GOA0 to GOAN is connected to a corresponding drive control signal line to generate a gate drive signal under the control of the drive control signal and provide the gate drive signal to the sub-pixel Pix of the display area 11.

[0117] A plurality of input contact pads P1 and a plurality of output contact pads P2 are located in the bonding area 12, and the plurality of output contact pads P2 are located between the plurality of input contact pads P1 and the display area 11. Figure 1A In the embodiment, the plurality of input contact pads P1 are arranged in at least a first row along a first direction, which is an extension direction of a side of the display area 11 facing the bonding area 12, i.e., an x-direction. The plurality of output contact pads P2 are arranged in at least a second row along the first direction.

[0118] The plurality of input contact pads P1 are used to electrically connect to an external circuit, and the plurality of output contact pads P2 are electrically connected to the sub-pixels Pix in the display area 11 and the gate drive circuit 130. For example, the plurality of input contact pads P1 can be connected to the plurality of connection contact pads in the area 1220 for connecting to the flexible circuit board through a plurality of first leads W1. The plurality of output contact pads P2 can be connected to the sub-pixels Pix in the display area 11 and the gate drive circuit 13 through a plurality of second leads W2. Figure 1A The plurality of output contact pads P2 on the left and right sides are respectively connected to the first clock signal line CK1, the second clock signal line CK2 and the start signal line STV through a plurality of second lead lines W2, thereby being connected to the gate drive circuit 13; Figure 1AThe multiple output contact pads P2 located in the middle are respectively connected to the data lines D1 to DM in the display area 11 through multiple second leads W2, and thus connected to the sub-pixels Pix in the display area 11. In some embodiments, structures such as a cell test (CT) circuit, an electrostatic discharge (ESD) circuit, and a multiplexing circuit can be set in the bonding area 12. For example, the unit test circuit can be set in the area between the multiple output contact pads P2 and the display area 11, and the unit test circuit can be connected to multiple test signal lines and multiple sub-pixels in the display area. For example, the multiplexing circuit can be set in the area between the unit test circuit and the multiple output contact pads P2, and the multiplexing circuit can be linked to at least one output contact pad P2 and the data line of the display area to multiplex the data signal provided by the output contact pad P2 and provide it to the data line of the display area. Of course, the embodiments of the present disclosure are not limited to this. In some embodiments, at least one of the unit test circuit, electrostatic protection circuit, multiplexing circuit and other auxiliary circuits can be set in the area between the input contact pad P1 and the output contact pad P2, and in other embodiments can be located in the area between the output contact pad P2 and the first virtual contact pad P3 described below.

[0119] When the control chip is connected to the display substrate, the input contact pad P1 is connected to the input pin of the control chip, and the output contact pad P2 is connected to the output pin of the control chip. The signal provided by the flexible circuit board (such as but not limited to the power signal, control signal, etc.) is provided to the control chip through the input contact pad P1, so that the control chip generates a driving signal (such as but not limited to a clock signal, a start signal, a data signal, etc.). The driving signal generated by the control chip is provided to the sub-pixels Pix and / or the gate driving circuit of the display area 11 through the output contact pad P2. For example, the data signal generated by the control chip is provided to the data lines D1 to DM through the output contact pad P2 located in the middle part, and thus provided to the sub-pixels in the display area 11; the first clock signal, the second clock signal, and the start signal STV generated by the control chip are respectively provided to the first clock signal line CK1, the second clock signal line CK2, and the start signal line STV through the output contact pads P2 located on both sides, and thus provided to the gate driving circuit 130.

[0120] In the bonding area 12, the contact pad insulating layer in the region 1210 between the plurality of input contact pads P1 and the plurality of output contact pads P2 is at least partially removed, thereby alleviating the poor contact with the control chip caused by the contact pad insulating layer in the region 1210. Figures 2 to 15C Let's explain this in detail.

[0121] Figure 2FIG. 1 shows a partial plan view of a bonding area of ​​a display substrate according to an embodiment of the present disclosure, Figure 3 Shown Figure 2 Schematic diagram of the bonding area along the cross section A1-B1. It should be noted that Figure 2 For ease of description, only Figure 1A One side of the bond area ( Figure 2 The other side of the bonding area may have a similar structure, for example, a symmetrical structure relative to the left side. Figure 3 The cross-sectional view is only for illustrating the positional relationship and thickness difference between the first portion and the second portion of the contact pad insulating layer. More details of the layer structure of the bonding area will be further described in detail below.

[0122] like Figure 2 and Figure 3 As shown, in the bonding area 12, the contact pad insulating layer 1230 is located in the gaps between adjacent input contact pads P1 among the multiple input contact pads P1, the gaps between adjacent output contact pads P2 among the multiple output contact pads P2, and the area between the multiple input contact pads P1 and the multiple output contact pads P2. The surfaces of the input contact pads P1 and the output contact pads P2 facing away from the base substrate 10 are exposed from the contact pad insulating layer 1230. According to an embodiment of the present disclosure, the contact pad insulating layer 1230 includes a first portion 1230A having a first thickness and a second portion 1230B having a second thickness, and the second thickness is less than the first thickness. The edges of the input contact pads P1 and the output contact pads P2 are covered by the first portion 1230A of the contact pad insulating layer 1230, and the second portion 1230B of the contact pad insulating layer 1230 is located in the area between the multiple input contact pads P1 and the multiple output contact pads P1. As shown Figure 2 As shown, a distance d1 exists between the projection of the input contact pad P1 on the substrate 10 and the projection of the second portion 1230B of the contact pad insulating layer 1230 on the substrate 10. A distance d2 exists between the projection of the output contact pad P2 on the substrate 10 and the projection of the second portion 1230B of the contact pad insulating layer 1230 on the substrate 10. d1 and d2 may be in the range of 3 microns to 100 microns. In some embodiments, d1 may be equal to d2.

[0123] Figure 4A Shown Figure 2 A cross-sectional view of an example of a display substrate along the A2 - B2 bonding area.

[0124] like Figure 4A As shown, the output contact pad P2 includes a first lead connection portion 1241, a first conductor portion 1242 and a second conductor portion 1243. The first lead connection portion 1241 is located on the base substrate 10. Figure 1A The first lead connection portion 1241 of the output contact pad P2 can be connected to the second lead W2 of the bonding region, thereby being electrically connected to the gate driving circuit 130 or to at least one of the plurality of sub-pixels in the display region 11 .

[0125] The first conductor portion 1242 is located on a side of the first lead connection portion 1241 away from the substrate 10 and is electrically connected to the first lead connection portion 1241. The second conductor portion 1243 is located on a side of the first conductor portion 1242 away from the substrate 10 and is electrically connected to the first conductor portion 1242.

[0126] The bonding area of ​​the display substrate is further provided with a first gate insulating layer 1251, a second gate insulating layer 1252, an interlayer insulating layer 1253, and a passivation layer 1254. The first gate insulating layer 1251 covers the base substrate 10, and the first lead connection portion 1241 is located on the side of the first gate insulating layer 1251 facing away from the base substrate 10. The second gate insulating layer 1252 is located on the side of the first gate insulating layer 1251 facing away from the base substrate 10 and covers the first lead connection portion 1241. The interlayer insulating layer 1253 is located on the side of the second gate insulating layer 1252 facing away from the base substrate 10. The passivation layer 1254 is located on the side of the interlayer insulating layer 1253 facing away from the base substrate 10 and covers the first conductor portion 1242.

[0127] like Figure 4A As shown in the dotted box in FIG, the first conductor portion 1242 is electrically connected to the first lead connection portion 1241 through a via provided in the second gate insulating layer 1252 in the bonding area and a via provided in the interlayer insulating layer 1253 in the bonding area, and the second conductor portion 1243 is electrically connected to the first conductor portion 1242 through a via provided in the passivation layer 1254 in the bonding area. Figure 4A In the embodiment, multiple vias, for example, three, are provided in the second gate insulating layer 1252 in the bonding region, the interlayer insulating layer 1253 in the bonding region, and the passivation layer 1254 in the bonding region. However, the embodiments of the present disclosure are not limited thereto. In other examples of the present disclosure, the number of vias can also be set as needed, for example, two or four.

[0128] like Figure 4AAs shown, the edge of the second conductor portion 1243 of the output contact pad P2 is covered by a first portion 1230A of the contact pad insulation layer 1230 having a thickness of H1. A second portion 1230B of the contact pad insulation layer 1230 having a thickness of H2 is located between the input contact pad P1 and the output contact pad P1, where H2 is less than H1. The thickness herein refers to the distance from the surface of the contact pad insulation layer 1230 facing the substrate 10 to the surface facing away from the substrate 10. By making the thickness H2 less than the thickness H1, the surface of the second portion 1230B of the contact pad insulation layer 1230 facing away from the substrate 10 is lower than the surface of the first portion 1230A of the contact pad insulation layer 1230 facing away from the substrate 10, thereby mitigating the impact of the contact pad insulation layer 1230 on the connection reliability between the output contact pad P2 and the pins of the control chip. At the same time, the thicker first portion 1230A can encapsulate the edge of the output contact pad P2, thereby providing protection.

[0129] Figure 4B Shown Figure 2 A cross-sectional view of an example of a display substrate along the A3-B3 bonding area.

[0130] like Figure 4B As shown, the structure of the input contact pad P1 can be substantially the same as that of the output contact pad P2. The output contact pad P2 also includes a first lead connection portion 1241, a first conductor portion 1242, and a second conductor portion 1243. The first conductor portion 1242 is electrically connected to the first lead connection portion 1241 through a via in the second gate insulation layer 1252 in the bonding area and a via in the interlayer insulation layer 1253 in the bonding area. The second conductor portion 1243 is electrically connected to the first conductor portion 1242 through a via in the passivation layer 1254 in the bonding area. Figure 1A The first lead connection portion 1241 of the input contact pad P1 can be connected to the first lead W1 in the bonding region 12, thereby being electrically connected to the connection contact pad in the region 1220 for connecting to an external circuit.

[0131] In some embodiments, the material of the contact pad insulating layer 1230 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, or may include an organic insulating material such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin. The embodiments of the present disclosure do not specifically limit the material of the contact pad insulating layer. The materials of the first conductor portion 1242 and the second conductor portion 1243 may include a metal material or an alloy material, such as a single or multilayer metal structure formed of molybdenum, aluminum, or titanium.

[0132] Figure 4C Shown Figure 2 A cross-sectional view of an example of a display substrate along the A4-B4 bonding area.

[0133] The base substrate 10 of the embodiment of the present disclosure may include organic materials, such as one or more resin materials such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate. The base substrate 10 may be a flexible substrate or a non-flexible substrate. Figure 4C The base substrate 10 is a flexible substrate and may include a first flexible layer 1010, a second flexible layer 1020, a first substrate barrier layer 1030, a second substrate barrier layer 1040, and a buffer layer 1050. The second flexible layer 1020 is located on the side of the first flexible layer 1010 facing the multiple input contact pads P1 and the multiple output contact pads P2. The first substrate barrier layer 1030 is located between the first and second flexible layers 1020. The second substrate barrier layer 1040 is located on the side of the second flexible layer 1020 facing away from the first flexible layer 1010. The buffer layer 1050 is located on the side of the second substrate barrier layer 1040 facing away from the first flexible layer 1010. For example, the material of the buffer layer 1050 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The buffer layer 1050 can prevent harmful substances in the base substrate 10 from invading the interior of the display substrate and enhance the adhesion of the film layers in the display substrate to the base substrate 10.

[0134] On the surface of buffer layer 1050 facing away from first flexible layer 1010, a first gate insulating layer 1251 in the bonding region, a second gate insulating layer 1252 in the bonding region, an interlayer insulating layer 1253 in the bonding region, a passivation layer 1254 in the bonding region, and a contact pad insulating layer 1230 are stacked in this order. Contact pad insulating layer 1230 includes a first portion 1230A having a first thickness and a second portion 1230B having a second thickness, the second thickness being less than the first thickness. The edges of input contact pads P1 and output contact pads P2 are covered by first portion 1230A of contact pad insulating layer 1230, while second portion 1230B of contact pad insulating layer 1230 is located in the region between the plurality of input contact pads P1 and the plurality of output contact pads P2.

[0135] Figure 5 A cross-sectional view of a display area of ​​a display substrate according to an embodiment of the present disclosure is shown.

[0136] like Figure 5 As shown, the sub-pixel in the display area may include a pixel driving circuit 1120 , a first planarization layer 1130 , a first transfer electrode 1180 , a second planarization layer 1190 and a light-emitting element 1140 .

[0137] The pixel driving circuit 1120 includes an active layer 1122 located on the base substrate 10, a first gate insulating layer 1128 in the display region located on the side of the active layer 1122 facing away from the base substrate 1000, a gate electrode 11211 located on the first gate insulating layer 1128 in the display region, a second gate insulating layer 1129 in the display region located on the side of the gate electrode 11211 facing away from the base substrate 10, a display region interlayer insulating layer 11210 located on the second gate insulating layer 1129 in the display region, and a source electrode 1125 and a drain electrode 1126 located on the display region interlayer insulating layer 11210. The gate electrode 11211 can be provided on the same layer as the first lead connection portion 1241 in the bonding region 12. The source electrode 1125 and the drain electrode 1126 can be provided on the same layer as the first conductor portion 1242 in the bonding region 12. Therefore, the gate electrode 11211 and the first lead connection portion 1241 can be formed on the same layer during the manufacturing process, for example, by patterning the same material layer. The source electrode 1125 and the drain electrode 1126 can be formed in the same layer as the first conductor portion 1242 in the bonding region 12 during the fabrication process, for example, by patterning the same material layer. The display region first gate insulating layer 1128 in the display region is provided in the same layer as the bonding region first gate insulating layer 1251 in the bonding region. The display region second gate insulating layer 1129 in the display region is provided in the same layer as the bonding region second gate insulating layer 1252 in the bonding region. The display region interlayer insulating layer 11211 in the display region is provided in the same layer as the bonding region interlayer insulating layer 1253.

[0138] In some examples of the above-described embodiments of the present disclosure, the active layer 1122 may include a source region 1123 and a drain region 1124, as well as a channel region located between the source region 1123 and the drain region 1124. The display region interlayer insulating layer 11210, the display region second gate insulating layer 1129, and the display region first gate insulating layer 1128 have vias to expose the source region 1123 and the drain region 1124. The source electrode 1125 and the drain electrode 1126 are electrically connected to the source region 1123 and the drain region 1124, respectively, through the vias. The gate electrode 11211 overlaps with the channel region located between the source region 1123 and the drain region 1124 in the active layer 1122 in a direction perpendicular to the base substrate 1000. The first planarization layer 1130 is located above the source electrode 1125 and the drain electrode 1126 and is used to planarize the surface of the pixel driving circuit 1120 away from the base substrate. A via 1131 is formed in the first planarization layer 1130 to expose the source electrode 1125 or the drain electrode 1126 (as shown in the figure). A display area passivation layer 11110 is formed between the pixel driving circuit 1120 and the first planarization layer 1130, and the display area passivation layer 11110 includes a via 11111. The display area passivation layer 11110 can protect the source and drain electrodes of the pixel driving circuit from corrosion by water vapor. The bonding area passivation layer 1254 of the display area can be provided in the same layer as the display area passivation layer 11110. Therefore, the bonding area passivation layer 1254 of the display area and the display area passivation layer 11110 can be formed in the same layer during the manufacturing process, for example, by using the same material layer through a patterning process.

[0139] A first transfer electrode 1180 is formed on the first planarization layer 1130. The first transfer electrode 1180 is electrically connected to the drain electrode 1126 through the via 1131 and the via 11111. This first transfer electrode 1180 avoids forming a direct via with an excessively large aperture in the first planarization layer 1130 and the second planarization layer 1190, thereby improving the quality of the via electrical connection. Furthermore, the first transfer electrode 1180 can be formed on the same layer as other signal lines (e.g., power lines), thereby avoiding an increase in process steps. The first transfer electrode 1180 is disposed on the same layer as the second conductor portion 1243 of the contact pad 1210. Therefore, the first transfer electrode 1180 and the second conductor portion 1243 can be formed on the same layer during the manufacturing process, for example, by patterning the same material layer, thereby simplifying the manufacturing process.

[0140] For example, the material of the first connecting electrode 1180 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium.

[0141] For example, the material of the active layer 1122 may include polysilicon or an oxide semiconductor (for example, indium gallium zinc oxide). The material of the gate 11211 may include a metal material or an alloy material, for example, a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, for example, the multilayer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum and titanium (Ti / Al / Ti). The material of the source 1125 and the drain 1126 may include a metal material or an alloy material, for example, a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, for example, the multilayer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum and titanium (Ti / Al / Ti). The embodiments of the present disclosure do not specifically limit the materials of the functional layers.

[0142] For example, the material of the display area passivation layer 11110 may include an organic insulating material or an inorganic insulating material, such as silicon nitride material. Since it has a high dielectric constant and good hydrophobicity, it can well protect the pixel driving circuit from being corroded by water vapor.

[0143] In some examples of the present disclosure, Figure 5 As shown, the pixel driving circuit 1120 may further include a first display metal layer 1127, which is provided on the same layer as the first conductor portion 1242. The first display metal layer 1127 includes a source electrode 1125 and a drain electrode 1126 of the thin film transistor in the pixel driving circuit. The source electrode 1125 and the drain electrode 1126 are provided on the same layer as the first conductor portion 1242.

[0144] In some examples of the present disclosure, Figure 5 As shown, a second planarization layer 1190 is disposed on a side of the first transfer electrode 1180 away from the base substrate 10 to provide a planarized surface on the side of the first transfer electrode 1180 away from the base substrate 10. Vias 1191 are formed in the second planarization layer 1190. The second planarization layer 1190 is formed on the same layer as the contact pad insulation layer 1230 in the bonding area 1200. Therefore, the second planarization layer 1190 and the contact pad insulation layer 1230 can be formed on the same layer during the fabrication process, for example, by patterning the same material layer, thereby simplifying the fabrication process.

[0145] For example, a light-emitting element 1140 is formed on the second planarization layer, that is, the light-emitting element 1140 is disposed on the side of the second planarization layer 1190 away from the base substrate. The light-emitting element 1140 includes a first electrode 1141, a light-emitting layer 1142, and a second electrode 1143. The first electrode 1141 of the light-emitting element is electrically connected to the first transfer electrode 1180 through a second via 1191 in the second planarization layer 1140. A pixel-defining layer 1144 is formed on the first electrode 1141. The pixel-defining layer 1144 includes a plurality of openings to define a plurality of pixel units. Each of the plurality of openings exposes a corresponding first electrode 1141. Subsequently, the light-emitting layer 1142 is disposed in the plurality of openings of the pixel-defining layer 1144, and the second electrode 1143 is disposed on the pixel-defining layer 1144 and the light-emitting layer 1142. For example, the second electrode 1143 can be disposed in part or the entire display area, so that it can be formed over the entire surface during the manufacturing process.

[0146] For example, the material of the second planarization layer 1190 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, and the embodiments of the present disclosure are not limited to this.

[0147] For example, the first electrode 1141 may include a reflective layer, and the second electrode 1143 may include a transparent layer or a semi-transparent layer. Thus, the first electrode 1141 can reflect light emitted from the light-emitting layer 1142, with some of the light being emitted into the external environment through the second electrode 1143, thereby improving light extraction efficiency. When the second electrode 1143 includes a semi-transmissive layer, some of the light reflected by the first electrode 1141 is reflected again by the second electrode 1143, thereby forming a resonant structure with the first electrode 1141 and the second electrode 1143, thereby improving light extraction efficiency.

[0148] For example, the material of the first electrode 1141 may include at least one transparent conductive oxide material including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In addition, the first electrode 1141 may include a metal with high reflectivity as a reflective layer, such as silver (Ag).

[0149] For example, for OLEDs, the light-emitting layer 1142 can include small molecule organic materials or polymer molecule organic materials, and can be fluorescent or phosphorescent, emitting red, green, blue, or white light. Furthermore, the light-emitting layer can further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer, as needed. For QLEDs, the light-emitting layer can include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, and indium arsenide quantum dots, with a particle size of 2-20 nm.

[0150] For example, the second electrode 1143 may include various conductive materials, such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), and the like.

[0151] For example, the material of the pixel defining layer 1144 may include an organic insulating material such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin, or an inorganic insulating material such as silicon oxide or silicon nitride, which is not limited in the embodiments of the present disclosure.

[0152] In addition, the display substrate also includes a storage capacitor 1160, which may include a first electrode 1161 and a second electrode 1162. The first electrode 1161 of the storage capacitor 1160 is disposed between the first gate insulating layer 1128 and the second gate insulating layer 1129 in the display area, while the second electrode 1162 of the storage capacitor 1160 is disposed between the second gate insulating layer 1129 and the interlayer insulating layer 11210 in the display area. The first electrode 1161 and the second electrode 1162 are stacked, at least partially overlapping in a direction perpendicular to the base substrate 10. The first electrode 1161 and the second electrode 1162 utilize the second gate insulating layer 1129 in the display area as a dielectric material to form the storage capacitor. The first electrode 1161 is disposed in the same layer as the gate electrode 11211 in the pixel driving circuit 1120 and the lead 1220 in the bonding area 1200. Similarly, as described above, in variations of the above example, the first and second electrodes of the storage capacitor 1160 may also be located in other layers, thereby resulting in sub-pixels with different structures.

[0153] In another example, as Figure 5 In a variation of the example shown, the first electrode of the storage capacitor is still arranged in the same layer as the gate 11211, while the second electrode of the storage capacitor is arranged in the same layer as the source 1125 and the drain 1126 in the thin film transistor (that is, also located in the first display metal layer 1127), thereby the first electrode and the second electrode of the storage capacitor use the stack of the second gate insulating layer 1129 of the display area and the interlayer insulating layer 11210 of the display area as dielectric materials to form a storage capacitor.

[0154] In yet another example, as Figure 5 In a variation of the example shown, the first electrode of the storage capacitor is no longer arranged in the same layer as the gate electrode 11211, but is located between the second gate insulation layer 1129 of the display area and the interlayer insulation layer 11210 of the display area, while the second electrode of the storage capacitor is arranged in the same layer as the source electrode 1125 and the drain electrode 1126 in the thin film transistor (that is, also located in the first display metal layer 1127), thereby the first electrode and the second electrode of the storage capacitor use the display area interlayer insulation layer 11210 as a dielectric material to form a storage capacitor.

[0155] In some examples of the present disclosure, Figure 5 As shown, the display substrate may further include an encapsulation layer 1150 disposed on the light-emitting element 1140. The encapsulation layer 1150 seals the light-emitting element 1140, thereby reducing or preventing degradation of the light-emitting element 1140 caused by moisture and / or oxygen in the environment. The encapsulation layer 1150 may have a single-layer structure or a composite layer structure including a stack of inorganic and organic layers. For example, the encapsulation layer 1150 may include a first inorganic encapsulation layer 1151, a first organic encapsulation layer 1152, and a second inorganic encapsulation layer 1153 disposed in sequence. The encapsulation layer 1150 may extend to the bonding area. In the above example, the encapsulation layer does not cover the contact pads.

[0156] For example, the encapsulation layer may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resins. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, and the like. The organic encapsulation layer may be made of a polymer material containing a desiccant or a polymer material that can block moisture, such as a polymer resin, to planarize the surface of the display substrate and relieve stress on the first and second inorganic encapsulation layers. It may also include a desiccant or other absorbent material to absorb intrusive water, oxygen, and other substances.

[0157] Figure 6A and Figure 6B Shown respectively Figure 2 Another example of a display substrate is a cross-sectional view taken along A2 - B2 and along A3 - B3 . Figure 6A and Figure 6B Bonding area Figure 4A and Figure 4B The difference is at least that the input contact pad P1 and the output contact pad P2 further include a third conductor portion. For the sake of simplicity, the following will mainly describe in detail the difference.

[0158] like Figure 6AAs shown, the output contact pad P2 includes, in addition to the above-mentioned first lead connection portion 1241, the first conductor portion 1242, and the second conductor portion 1243, a third conductor portion 1244. The display substrate also includes a bonding area barrier layer 1255 and a bonding area inorganic layer 1256. The third conductor portion 1244 is located on the side of the second conductor portion 1243 facing away from the base substrate 10, and the bonding area barrier layer 1255 and the bonding area inorganic layer 1256 are located between the third conductor portion 1244 and the second conductor portion 1243. The bonding area barrier layer 1255 covers the second conductor layer 1243 and the first portion 1230A of the contact pad insulating layer 1230, and the bonding area inorganic layer 1256 covers the bonding area barrier layer 1255. The third conductor portion 1244 is connected to the substrate 120 through a via provided in the bonding area barrier layer 1255 and a via provided in the bonding area inorganic layer 1256 (as shown in FIG. Figure 6A , as shown in the dotted box in FIG. 1 , and electrically connected to the second conductor portion 1243 .

[0159] like Figure 6B As shown, the input contact pad P1 has substantially the same structure as the output contact pad P2, which will not be described in detail here.

[0160] Figure 7A and Figure 7B Shown respectively Figure 2 Cross-sectional views of yet another example of a display substrate along A2 - B2 and along A3 - B3 . Figure 7A and Figure 7B Bonding area Figure 6A and Figure 6B The difference is that at least the second portion of the contact pad insulating layer is removed, that is, the second thickness is 0. Figure 7A and 7B As shown, the thickness of second portion 1230B of contact pad insulating layer 1230' is 0, i.e., second portion 1230B of contact pad insulating layer 1230' is removed, while first portion 1230A remains. The portion of bonding region passivation layer 1254 between second portion 1230B and bonding region second gate insulating layer 1254 has a thickness greater than 0, i.e., is at least partially retained.

[0161] Figure 8A and Figure 8B Shown respectively Figure 2 Cross-sectional views of yet another example of a display substrate along lines A2 - B2 and A3 - B3 . Figure 8A and Figure 8B Bonding area Figure 7A and Figure 7B The difference is that at least the passivation layer is also partially removed. Figure 8A and 8BAs shown, the second portion 1230B of the contact pad insulating layer 1230' and the portion of the bonding area passivation layer 1254 thereunder are removed, so that the thickness of the second portion 1230B is 0, and the thickness of the portion of the bonding area passivation layer 1254 located between the second portion 1230B of the contact pad insulating layer 1230' and the bonding area second gate insulating layer 1254 is also 0.

[0162] Figure 9 A cross-sectional view of a display area of ​​a display substrate according to another embodiment of the present disclosure is shown. Figure 9 The display area structure and Figure 5 The difference is at least that the display substrate further includes a display area barrier layer, a first touch electrode layer, a second touch electrode layer and a touch insulation layer. For the sake of simplicity, the following will mainly describe the differences in detail.

[0163] like Figure 9 As shown, the encapsulation layer 1150 is located on the side of the light-emitting element 1140 away from the base substrate 10, the display area barrier layer 1171 is located on the side of the encapsulation layer 1150 away from the base substrate 10, the first touch electrode layer 1172 is located on the side of the display area barrier layer 1171 away from the base substrate 10, the touch insulation layer 1174 is located on the side of the first touch electrode layer 1172 away from the base substrate 10 and covers the first touch electrode layer 1172, and the second touch electrode layer 1173 is located on the side of the touch insulation layer 1174 away from the base substrate 10. Figure 9 In the embodiment, the second touch electrode layer 1173 is electrically connected to the first touch electrode layer 1172 through vias in the touch insulating layer 1174. Of course, the embodiments of the present disclosure are not limited thereto. The first touch electrode layer 1172 and the second touch electrode layer 1173 can be arranged in other patterns as needed. The first touch electrode layer 1172 and the second touch electrode layer 1173 can be used to implement a capacitive touch structure, which can be a self-capacitive touch structure or a mutual-capacitive touch structure.

[0164] The third conductor portion 1244 located in the bonding area can be arranged in the same layer as the second touch electrode layer 1173 in the display area, the bonding area barrier layer 1255 located in the bonding area can be arranged in the same layer as the display area barrier layer 1171 in the display area, and the bonding area inorganic layer 1256 located in the bonding area can be arranged in the same layer as the touch insulation layer 1174 in the display area.

[0165] Figure 10 A partial plan view of a bonding area of ​​a display substrate according to another embodiment of the present disclosure is shown. Figure 11 Shown Figure 10 Schematic diagram of the bonding area along the cross section C1-D1. Figure 10 and Figure 11 Display substrate and Figure 2 and Figure 3The difference between the bonding area 12 and the display substrate is at least that a plurality of first virtual contact pads P3 are further provided in the bonding area 12. For the sake of simplicity, the following will mainly describe the difference in detail.

[0166] like Figure 10 and Figure 11 As shown, the display substrate further includes a plurality of first dummy contact pads P3 located in the bonding region 12, between the plurality of input contact pads P1 and the plurality of output contact pads P2. The first dummy contact pads P3 may not be connected to leads. When the control chip is bonded to the bonding region of the display substrate, the first dummy contact pads P3 mate with corresponding pins on the control chip, thereby providing support. The edges of the first dummy contact pads P3 are covered by the first portion 1230A of the contact pad insulating layer 1230, while the surface of the first dummy contact pads P3 facing away from the base substrate 10 is exposed through the first portion 1230A of the contact pad insulating layer 1230. The second portion 1230B of the contact pad insulating layer 1230 includes a first sub-portion 1230B1 and a second sub-portion 1230B2, wherein the first sub-portion 1230B1 is located in the area between the multiple first virtual contact pads P3 and the multiple input contact pads P1, and the second sub-portion 1230B2 is located in the area between the multiple first virtual contact pads P3 and the multiple output contact pads P2.

[0167] Figure 12A Shown Figure 10 A cross-sectional view of an example of a display substrate along C2-D2.

[0168] like Figure 12A As shown, the first virtual contact pad P3 includes a fourth conductor portion 1245. A first gate insulation layer 1251 in the bonding region, a second gate insulation layer 1252 in the bonding region, an interlayer insulation layer 1253 in the bonding region, and a passivation layer 1254 in the bonding region are stacked sequentially on the substrate 10. Fourth conductor portion 1245 is located on the side of the passivation layer 1254 in the bonding region facing away from the substrate 10, that is, on the side of the substrate 10 facing the multiple input contact pads P1 and the multiple output contact pads P2. A first portion 1230A of the contact pad insulation layer 1230 covers the edge of the fourth conductor portion 1245. A second portion 1230B of the contact pad insulation layer 1230 includes a first sub-portion 1230B1 and a second sub-portion 1230B2, and its thickness is less than that of the first portion 1230A. The fourth conductor portion 1245 may be disposed in the same layer as the second conductor portion 1243 . For example, the fourth conductor portion 1245 and the second conductor portion 1243 may both be disposed in the same layer as the first switching electrode 1180 in the display area.

[0169] Figure 12B Shown Figure 11 A cross-sectional view of another example of a display substrate taken along C2-D2. Figure 12B Display substrate and Figure 12A The difference compared to the display substrate is that at least the second portion of the contact pad insulating layer and a portion of the bonding area passivation layer are removed. Figure 12B As shown, the second portion 1230B of the contact pad insulating layer 1230 ′ and a portion of the first gate insulating layer 1251 in the bonding region thereunder are removed, ie, the thickness of both portions is 0.

[0170] Figure 12C Shown Figure 11 Yet another example of a bonding area is a cross-sectional view of the bonding area along C2-D2. Figure 12C Display substrate and Figure 12A The difference compared with the display substrate is that the first virtual contact pad P3 includes a fifth conductor portion 1246 in addition to the fourth conductor portion 1245 ′, and the fifth conductor portion 1246 is located between the fourth conductor portion 1245 and the base substrate 10.

[0171] exist Figure 12C In the embodiment, a first gate insulating layer 1251 in the bonding region, a second gate insulating layer 1252 in the bonding region, and an interlayer insulating layer 1253 in the bonding region are stacked sequentially on the base substrate 10. A fifth conductor portion 1246 is located on the side of the interlayer insulating layer 1253 in the bonding region facing away from the base substrate 10. A passivation layer 1254 in the bonding region is located on the side of the interlayer insulating layer 1253 in the bonding region facing away from the base substrate 10 and covers the edge of the fifth conductor portion 1246. A fourth conductor portion 1245' is located on the side of the fifth conductor portion 1246 facing away from the base substrate 10, with the edge of the fourth conductor portion covered by the first portion of the contact pad insulating layer. Fifth conductor portion 1246 is electrically connected to fourth conductor portion 1245 through a via in the passivation layer 1254 in the bonding region. Fourth conductor portion 1245' can be provided on the same layer as the second conductor portion 1243, and fifth conductor portion 1246 can be provided on the same layer as the first conductor portion 1242. For example, the fourth conductor portion 1245 ′ may be provided on the same layer as the second conductor portion 1243 and the first switching electrode 1180 in the display area, and the fifth conductor portion 1246 may be provided on the same layer as the first conductor portion 1242 and the first display metal layer 1127 in the display area.

[0172] Figure 13 FIG. 1 shows a partial plan view of a bonding area of ​​a display substrate according to another embodiment of the present disclosure. Figure 14 Shown Figure 13 Schematic diagram of the cross section of the display substrate along E1-F1. Figure 2 and Figure 10 The unilateral indication is different. Figure 13 The plan view shows the left and right parts of the bonding area of ​​the display substrate along the x-direction. Figure 13 and Figure 14 Display substrate and Figure 10 and Figure 11 The difference compared with the display substrate is at least that the bonding area 12 is further provided with multiple array test contact pads P4 and multiple second virtual contact pads P5. For the sake of simplicity, the following will mainly describe the differences in detail.

[0173] like Figure 13 and Figure 14 As shown, the bonding region of the display substrate is further provided with a plurality of array test contact pads P4, which are located in the region between the plurality of first dummy contact pads P1 and the plurality of input contact pads P2. The plurality of array test contact pads P4 are used for array testing during the display substrate manufacturing process. The array test contact pads P4 can be electrically connected to the plurality of sub-pixels. For example, at least one of the array test contact pads P4 can be connected to a sub-pixel in the display region via a lead in the bonding region, such as via a lead connected to a multiplexing circuit, and then connected to a plurality of data signal lines in the display region via the multiplexing circuit, thereby achieving electrical connection with the sub-pixel.

[0174] like Figure 13 and Figure 14 As shown, the first portion 1230A of the contact pad insulating layer 1230 includes a first sub-portion 1230A1 and a second sub-portion 1230A2. The edges of the plurality of input contact pads P1, the edges of the plurality of output contact pads P2, and the edge of the first dummy contact pad P3 are covered by the first sub-portion 1230A1 of the first portion 1230A of the contact pad insulating layer 1230. The edges of the plurality of array test contact pads P4 are covered by the second sub-portion 1230A2 of the first portion 1230A of the contact pad insulating layer 1230, and the surfaces of the plurality of array test contact pads P4 facing away from the base substrate 10 are exposed from the second sub-portion 1230A1 of the first portion 1230A of the contact pad insulating layer 1230. In some embodiments, as Figure 13 As shown, the projection of the second subportion 1230A2 of the first portion 1230A of the contact pad insulating layer 1230 on the base substrate 10 is located within the projection of the first subportion 1230B1 of the second portion 1230B of the contact pad insulating layer 1230 on the base substrate 10. This arrangement of the contact pad insulating layer 1230 improves the stability of the contact pad connection while protecting the edges of the input contact pad P1, output contact pad P2, first dummy contact pad P3, and array test contact pad P4. This prevents etching of the exposed contact pad edges by etching solution in subsequent patterning processes, thereby improving the product yield and reliability of the display substrate.

[0175] In the above embodiment, multiple input contact pads P1 are arranged in a first row along a first direction, which is the direction extending from the side of the display area facing the bonding area (the x-direction); multiple output contact pads P2 are arranged in a second row along the first direction; multiple first dummy contact pads are arranged in a third row along the first direction; and multiple array test contact pads are arranged in a fourth row along the first direction. Of course, the embodiments of the present disclosure are not limited to this; any of the input contact pads P1, output contact pads P2, first dummy contact pads P3, and array test contact pads P4 may be arranged in multiple rows or in other arrangements as needed.

[0176] In some embodiments, as Figure 13 As shown, the bonding area of ​​the display substrate may also be provided with a plurality of second virtual contact pads P5. The second virtual contact pads P5 may have a structure similar to that of the first virtual contact pads P4 and may also play a supporting role. The plurality of second virtual contact pads P5 are arranged into a first column and a second column along a second direction (y direction) perpendicular to the first direction, wherein the first column and the second column are respectively located on both sides of the plurality of first virtual contact pads P1 in the first direction. Of course, the embodiments of the present disclosure are not limited thereto, and the plurality of second virtual contact pads P5 may be arranged in multiple columns or in other forms as needed, or may be located on one side (e.g., the left or right side) of the plurality of first virtual contact pads P1.

[0177] exist Figure 13 In the embodiment, the edges of the plurality of second virtual contact pads P5 are covered by the first portion 1230A of the contact pad insulating layer 1230, and the surfaces of the plurality of second virtual contact pads P5 facing away from the base substrate 10 are exposed from the first portion 1230A of the contact pad insulating layer 1230. Figure 13 As shown, the projections of the input contact pad P1, output contact pad P2, first dummy contact pad P3, array test contact pad P4, and second dummy contact pad P5 on the base substrate 10 are spaced apart from the projections of the second portion 1230B of the contact pad insulating layer 1230 on the base substrate 10. This spacing can range from 3 microns to 100 microns. The spacings between the input contact pad P1, output contact pad P2, first dummy contact pad P3, array test contact pad P4, and second dummy contact pad P5 and the second portion 1230B of the contact pad insulating layer 1230 can be the same or different. For example, the spacings between the input contact pad P1, output contact pad P2, and second dummy contact pad P5 and the second portion 1230B of the contact pad insulating layer 1230 can be equal, but greater than the spacings between the first dummy contact pad P3 and the array test contact pad P4 and the second portion 1230B of the contact pad insulating layer 1230.

[0178] In the above embodiment, the projections of the input contact pad P1, the output contact pad P2, the first virtual contact pad P3, the array test contact pad P4, and the second virtual contact pad P5 on the base substrate 10 are shown to have specific shapes. For example, the projections of the input contact pad P1 and the output contact pad P2 on the base substrate 10 are parallelograms, the projections of the array test contact pad P4 and the second virtual contact pad P5 on the base substrate 10 are rectangles, and the projection of the first virtual contact pad P3 on the base substrate 10 is substantially square. Figure 13 In the embodiment, the input contact pad P1, the output contact pad P2, the first dummy contact pad P3, the array test contact pad P4, and the second dummy contact pad P5 are each symmetrically arranged along the symmetry axis Y of the display substrate in the y-direction. However, the embodiments of the present disclosure are not limited thereto, and the shape and arrangement of the contact pads can be configured as needed.

[0179] Figure 15A Shown Figure 13 A cross-sectional view of an example of a display substrate along E2-F2.

[0180] like Figure 15A As shown, the array test contact pad P5 has a similar Figure 4A The output contact pads and Figure 4B Array test contact pad P5 includes a second lead connection portion 1247, a sixth conductor portion 1248, and a seventh conductor portion 1249. Second lead connection portion 1247, sixth conductor portion 1248, and seventh conductor portion 1249 can be provided on the same layer as first lead connection portion 1241, first conductor portion 1242, and second conductor portion 1243, respectively.

[0181] The second lead connection portion 1247 is located on a side of the base substrate 10 facing the multiple input contact pads P1 and the multiple output contact pads P2, and is configured to connect to a lead connected to a data line, thereby electrically connecting the second lead connection portion 1247 to the sub-pixels in the display area. A sixth conductor portion 1248 is located on a side of the second lead connection portion 1247 facing away from the base substrate 10 and is electrically connected to the second lead connection portion 1247. A seventh conductor portion 1249 is located on a side of the sixth conductor portion 1247 facing away from the base substrate 10 and is electrically connected to the sixth conductor portion 1248.

[0182] The second virtual contact pad P5 may have a structure similar to that of the first virtual contact pad P4 described above. Figures 15B to 15D To explain.

[0183] Figure 15B Shown Figure 13 An example of a cross-sectional view of a display substrate along E3-F3. Figure 15BAs shown, the second virtual contact pad P5 has Figure 12A The second virtual contact pad P5 has a similar structure to the first virtual contact pad P4. The second virtual contact pad P5 includes an eighth conductor portion 12410. The eighth conductor portion 12410 is located on the side of the substrate surface 10 facing the multiple input contact pads P1 and the multiple output contact pads P2. The eighth conductor portion 12410 can be provided on the same layer as the second conductor portion 1243. The edge of the eighth conductor portion 12410' is covered by the first portion 1230A of the contact pad insulation layer 1230. Figure 15D The first sub-portion 1230A1 of the first portion 1230A of the middle contact pad insulating layer 1230 is covered.

[0184] Figure 15C Shown Figure 13 A cross-sectional view of another example of a display substrate taken along E3-F3. Figure 15C Display substrate and Figure 15B The difference compared to the display substrate is that at least the second portion 1230B of the contact pad insulating layer 1230 and a portion of the bonding area passivation layer 1241 are removed. Figure 15C As shown, the thickness of the second portion 1230B of the contact pad insulating layer 1230 ′ and the first gate insulating layer 1251 in the bonding region thereunder are both 0.

[0185] Figure 15D Shown Figure 13 Another example of a cross-sectional view of a display substrate along E3-F3. Figure 15D As shown, the second virtual contact pad P5 has a Figure 12C The structure of the first virtual contact pad P4 is as follows. The second virtual contact pad P5 includes, in addition to the eighth conductor portion 12410', a ninth conductor portion 12411. The ninth conductor portion 12411 is located between the eighth conductor portion 12410' and the base substrate 10 and is electrically connected to the eighth conductor portion 12410'. The eighth conductor portion 12410' can be provided on the same layer as the second conductor portion 1243, and the ninth conductor portion can be provided on the same layer as the first conductor portion 1242. The edge of the eighth conductor portion 12410' is covered by the first portion 1230A of the contact pad insulating layer 1230. Figure 15D The first sub-portion 1230A1 of the first portion 1230A of the middle contact pad insulating layer 1230 is covered.

[0186] Although the embodiment in which the second portion of the contact pad insulating layer and the passivation layer in the bonding area thereunder are thinned or removed is described above in conjunction with a specific contact pad structure, the embodiments of the present disclosure are not limited thereto. The thinning or removal of the second portion of the contact pad insulating layer and the passivation layer in the bonding area thereunder is applicable to other contact pad structures. For example, in some embodiments, Figures 4A to 4C 、 Figure 12C as well as Figure 15Aand Figure 15D The second portion of the at least one contact pad insulating layer and / or the bonding region passivation layer thereunder may be thinned or removed as needed.

[0187] Figure 16A A cross-sectional view showing a display area of ​​a display substrate according to another embodiment of the present disclosure Figure 16B Shown Figure 16A A cross-sectional view of the bonding area of ​​the display substrate. Figure 16A and Figure 16B The display substrate of the embodiment differs from the display substrate of the aforementioned embodiment in that at least it does not have a passivation layer.

[0188] like Figure 16A As shown, the display area of ​​the display substrate has a structure similar to Figure 9 The structure of the display area is different from that of the display area passivation layer 11110. Figure 16B As shown, the bonding area of ​​the display substrate has a similar Figure 7A and 8A The structure of the bonding area is different in that it does not have the bonding area passivation layer 1245, 1245', the second conductor portion 1243 is located on the side of the first conductor portion 1242 away from the base substrate 10 and covers the first conductor portion 1242, and the contact pad insulation layer 1230' is arranged on the side of the bonding area interlayer insulation layer 1253 away from the base substrate 10 and covers the edge of the second conductor portion 1243.

[0189] For the sake of simplicity Figure 16B Only the bonding area structure of the output contact pad P2 and its surrounding area is shown in FIG. The other parts of the bonding area can be connected with Figures 4A to 4C 、 Figures 6A to 8B 、 12A to 12C as well as 15A to 15D The structures described are similar except that the bond area passivation layer is removed from these structures.

[0190] At least one embodiment of the present disclosure provides a display device, which may include the display substrate of any of the above embodiments.

[0191] For example, in some examples, the display device may further include a flexible circuit board and a control chip. For example, the flexible circuit board may be bonded to a bonding region of the display substrate, while the control chip may be mounted on the flexible circuit board, thereby electrically connecting to the display region. Alternatively, the control chip may be directly bonded to the bonding region, thereby electrically connecting to the display region.

[0192] For example, the control chip may be a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and realize power supply and signal input and output functions through separately provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer executable codes, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0193] For example, the display device provided in at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0194] At least one embodiment of the present disclosure further provides a method for preparing a display substrate, the method comprising: providing a base substrate, the base substrate comprising a display area, a bonding area located on at least one side of the display area, and a side area located on at least another side of the display area; forming a plurality of sub-pixels in the display area; forming a gate drive circuit in the side area, the gate drive circuit being connected to the plurality of sub-pixels and being configured to provide gate drive signals to the plurality of sub-pixels; forming a plurality of input contact pads for electrically connecting to an external circuit in the bonding area; forming a plurality of output contact pads in the bonding area, the plurality of output contact pads being located between the plurality of input contact pads and the display area, the plurality of output contact pads being electrically connected to the plurality of sub-pixels and the gate drive circuit; forming a plurality of gate drive circuits in the bonding area; A contact pad insulating layer is formed, the contact pad insulating layer is located in the gaps between adjacent input contact pads among the multiple input contact pads, the gaps between adjacent output contact pads among the multiple output contact pads, and the area between the multiple input contact pads and the multiple output contact pads, the surfaces of the multiple input contact pads and the multiple output contact pads facing away from the substrate are exposed from the contact pad insulating layer, wherein the contact pad insulating layer includes a first portion with a first thickness and a second portion with a second thickness, the second thickness is less than the first thickness, the edges of the multiple input contact pads and the multiple output contact pads are covered by the first portion of the contact pad insulating layer, and the second portion of the contact pad insulating layer is located in the area between the multiple input contact pads and the multiple output contact pads.

[0195] The following combination Figure 8A and Figure 9 Display substrate, reference Figures 17A to 17G To illustrate the manufacturing process of the display substrate of the embodiment of the present disclosure.

[0196] like Figure 17A As shown, a substrate 10 is provided. The substrate 10 includes a display area and a peripheral area located around the display area. The peripheral area includes at least one bonding area located on at least one side of the display area and a side area located on at least another side of the display area. A pixel driving circuit 1120, a storage capacitor 1160, a first planarization layer 1130, and a first transfer electrode 1180 are formed in the display area of ​​the substrate 10. In the bonding area of ​​the display substrate 10, a bonding area first gate insulation layer 1251, a first lead connection portion 1231, a second gate insulation layer 1252, a bonding area interlayer insulation layer 1253, a first conductor portion 1242, a bonding area passivation layer 1254', and a second conductor portion 1243 are formed. The second conductor portion 1243 covers the edge of the first conductor portion 1242 to prevent corrosion of the first conductor portion 1242. In this embodiment, the first conductor portion 1242 and the second conductor portion 1243 are stacked.

[0197] like Figure 17B As shown, an insulating material layer 1710 is deposited on the substrate, and a photoresist 1720 is deposited on the insulating material layer 1710. The insulating material layer 1710 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0198] like Figure 17C As shown, a mask 1610 is provided for exposing a photoresist 1720. Mask 1610 includes a fully transparent region, a partially transparent region, and a non-transparent region. Mask 1610 includes a first transparent pattern 1611 in the bonding region, which overlaps with the region where the second portion 1230B of the contact pad insulating layer 1230 is to be formed, and a second transparent pattern 1612, which overlaps with the output contact pad P2. Mask 1610 includes the second transparent pattern 1612 and a non-transparent pattern 1613 in the display region. First transparent pattern 1611 is located in the partially transparent region, second transparent pattern 1612 is located in the fully transparent region, and non-transparent pattern 1613 is located in the non-transparent region. That is, mask 1610 is a gray mask or a halftone mask. The photoresist is a positive-tone photoresist. Accordingly, the transmittance of first transparent pattern 1611 is lower than that of second transparent pattern 1612. During the exposure process, the portion of the photoresist 1720 corresponding to the second light-transmitting pattern 1612 may be fully exposed while the portion of the photoresist 1720 corresponding to the first light-transmitting pattern 1611 may be partially exposed. The portion of the photoresist 1720 corresponding to the non-light-transmitting pattern 1613 in the display area is not exposed.

[0199] For another example, in the above-mentioned patterning process, a negative photoresist may also be used. Then the mask used is, for example, a mask complementary to the above-mentioned mask 1610 , thereby obtaining the above-mentioned photoresist pattern 1721 and photoresist pattern 1722 after exposure and development.

[0200] like Figure 17DAs shown, photoresist 1720 is developed, and the fully exposed portions of photoresist 1720 are removed. Specifically, in the bonding area, the photoresist 1720 overlapping the output contact pad P2 and the area where the second portion 1230B of the contact pad insulating layer is to be disposed is removed. The partially exposed portions of photoresist 1720 are thinned, while the thickness of the unexposed portions of photoresist 1720 remains substantially unchanged. After development, photoresist 1720 forms a photoresist pattern 1721 in the bonding area. Similarly, in the display area, the photoresist 1720 overlapping the drain electrode 1126 is removed. After development, photoresist 1720 forms a photoresist pattern 1722 in the display area.

[0201] like Figure 17E As shown, the insulating material layer 1710 in the bonding area and the display area is etched to remove the insulating material layer overlapping with the output contact pad P2 and the second portion 1230B of the contact pad insulating layer in the bonding area, and to form a second via hole 1191 in the display area.

[0202] like Figure 17F As shown, an ashing process is performed to remove the photoresist pattern 1721 in the bonding area and to thin the photoresist pattern 1722 in the display area. Here, the photoresist pattern 1722 in the display area is retained. Then, using the current photoresist pattern, the remaining insulating material layer 1710 in the bonding area is etched and the etching thickness is controlled to form a contact pad insulating layer 1230. The contact pad insulating layer 1230 formed after etching has a first portion 1230A and a second portion 1230B having a thickness smaller than the first portion 1230A. Figure 17F The thickness of the second portion 1230B is 0, i.e., the insulating material in this portion is removed. This makes the height of the second portion 1230B of the contact pad insulating layer relative to the surface of the substrate 10 lower than the height of the first portion 1230B relative to the surface of the substrate 1000. The photoresist pattern 1722 in the display area is removed. A second planarization layer 1190 is formed in the display area to provide a planarized surface. A light-emitting element 1140 is formed on the second planarization layer 1190 in the display area. An encapsulation layer 1150 is formed on the light-emitting element 1140 in the display area. Encapsulation layer 1150 seals the light-emitting element 1140, thereby reducing or preventing degradation of the light-emitting element 1140 caused by moisture and / or oxygen in the environment.

[0203] like Figure 17GAs shown, a display area barrier layer 1171 is formed on the encapsulation layer 1150 in the display area, and a bonding area barrier layer 1255 is formed in the bonding area. Then, a first touch electrode layer 1172 is formed on the display area barrier layer 1171 in the display area. A touch insulation layer 1174 is formed on the first touch electrode layer 1172 in the display area, and a bonding area inorganic layer 1256 is formed on the bonding area barrier layer 1255 in the bonding area. Then, a second touch electrode layer 1173 is formed on the touch insulation layer 1174 in the display area, and a third conductor portion 1244 is formed on the bonding area inorganic layer 1256 in the bonding area.

[0204] Those skilled in the art will appreciate that the embodiments described above are exemplary and that they may be improved upon. The structures described in the various embodiments may be freely combined without causing any conflict in structure or principle.

[0205] After describing the preferred embodiments of the present disclosure in detail, those skilled in the art will clearly understand that various changes and modifications may be made without departing from the scope and spirit of the appended claims, and that the present disclosure is not limited to the exemplary embodiments described in the specification.

Claims

1. A display substrate, comprising: The base substrate comprises a display area, a bonding area located on at least one side of the display area, and a side area located on at least the other side of the display area; A plurality of sub-pixels are located in the display area; a gate driving circuit, located in the side area, connected to the plurality of sub-pixels and configured to provide a gate driving signal to the plurality of sub-pixels; a plurality of input contact pads located in the bonding area for electrically connecting to an external circuit; a plurality of output contact pads located in the bonding area and between the plurality of input contact pads and the display area, the plurality of output contact pads being electrically connected to the plurality of sub-pixels and the gate driving circuit; a contact pad insulating layer located in the bonding region and located in gaps between adjacent input contact pads among the plurality of input contact pads, gaps between adjacent output contact pads among the plurality of output contact pads, and regions between the plurality of input contact pads and the plurality of output contact pads, wherein surfaces of the plurality of input contact pads and the plurality of output contact pads facing away from the substrate are exposed from the contact pad insulating layer, wherein the contact pad insulating layer includes a first portion having a first thickness and a second portion having a second thickness, the second thickness being smaller than the first thickness, edges of the plurality of input contact pads and the plurality of output contact pads are covered by the first portion of the contact pad insulating layer, and the second portion of the contact pad insulating layer is located in the region between the plurality of input contact pads and the plurality of output contact pads; The display substrate further includes: a plurality of array test contact pads, at least one of the plurality of array test contact pads being connected to a multiplexing circuit via a lead in a bonding region and connected to a plurality of sub-pixels in the display region via the multiplexing circuit; A plurality of first virtual contact pads are located in the bonding area, in an area between the plurality of input contact pads and the plurality of output contact pads, wherein edges of the plurality of first virtual contact pads are covered by the first portion, and surfaces of the plurality of first virtual contact pads facing away from the substrate are exposed from the first portion.

2. The display substrate according to claim 1, wherein The second portion of the contact pad insulating layer includes a first subportion located in a region between the first dummy contact pads and the input contact pads, and a second subportion located in a region between the first dummy contact pads and the output contact pads.

3. The display substrate according to claim 2, further comprising: A plurality of array test contact pads are located in the bonding area and in a region between the plurality of first dummy contact pads and the plurality of input contact pads, the plurality of array test contact pads being electrically connected to the plurality of sub-pixels, wherein: The first portion of the contact pad insulating layer includes a first sub-portion and a second sub-portion, edges of the plurality of input contact pads, edges of the plurality of output contact pads, and an edge of the first dummy contact pad are covered by the first sub-portion of the first portion of the contact pad insulating layer, edges of the plurality of array test contact pads are covered by the second sub-portion of the first portion of the contact pad insulating layer, and surfaces of the plurality of array test contact pads facing away from the substrate are exposed from the first portion of the contact pad insulating layer; A projection of the second sub-portion of the first portion of the contact pad insulating layer on the base substrate is located within a projection of the first sub-portion of the second portion of the contact pad insulating layer on the base substrate.

4. The display substrate according to claim 1, wherein: A distance between a projection of each of the plurality of input contact pads and the plurality of output contact pads on the base substrate and a projection of the second portion of the contact pad insulating layer on the base substrate is in a range of 3 micrometers to 100 micrometers.

5. The display substrate according to claim 1, wherein The second thickness is 0. The display substrate according to claim 3 , wherein: The plurality of input contact pads are arranged in at least a first row along a first direction, wherein the first direction is an extension direction of a side of the display area facing the bonding area; The plurality of output contact pads are arranged in at least a second row along the first direction; The plurality of first virtual contact pads are arranged in at least a third row along the first direction; The plurality of array test contact pads are arranged in at least a fourth row along the first direction.

7. The display substrate according to claim 6, further comprising: A plurality of second virtual contact pads are located in the bonding area and arranged in at least a first column and a second column along a second direction perpendicular to the first direction, wherein the first column and the second column are respectively located on both sides of the plurality of first virtual contact pads in the first direction, wherein: Edges of the plurality of second dummy contact pads are covered by the first portion of the contact pad insulating layer, and surfaces of the plurality of second dummy contact pads facing away from the substrate are exposed from the first portion of the contact pad insulating layer; and A distance between a projection of each of the plurality of second dummy contact pads on the base substrate and a projection of the second portion of the contact pad insulating layer on the base substrate is in a range of 3 micrometers to 100 micrometers.

8. The display substrate according to claim 1, wherein: At least one of the plurality of input contact pads and the plurality of output contact pads comprises: a first lead connection portion located on the substrate, wherein the first lead connection portion of the input contact pad is electrically connected to a connection contact pad for connecting to an external circuit via a first lead provided in the bonding region, and the first lead connection portion of the output contact pad is electrically connected to the gate drive circuit or to at least one of the plurality of sub-pixels via a second lead provided in the bonding region; a first conductor portion, located on a side of the first lead connection portion facing away from the base substrate and electrically connected to the first lead connection portion; The second conductor portion is located on a side of the first conductor portion away from the base substrate and is electrically connected to the first conductor portion. An edge of the second conductor portion is covered by the first portion of the contact pad insulating layer.

9. The display substrate according to claim 8, further comprising: A first gate insulating layer in the bonding region is located in the bonding region and covers the base substrate, and the first lead connection portion is located on a side of the first gate insulating layer in the bonding region away from the base substrate; a second gate insulating layer in the bonding region, located in the bonding region, located on a side of the first gate insulating layer in the bonding region away from the base substrate and covering the first lead connection portion; a bonding region interlayer insulating layer located in the bonding region and located on a side of the second gate insulating layer in the bonding region facing away from the base substrate, wherein the first conductor portion is electrically connected to the first lead connection portion through a via hole provided in the second gate insulating layer in the bonding region and a via hole provided in the bonding region interlayer insulating layer; The bonding area passivation layer is located in the bonding area, on a side of the bonding area interlayer insulating layer away from the base substrate and covers the first conductor portion. The second conductor portion is electrically connected to the first conductor portion through a via hole provided in the bonding area passivation layer.

10. The display substrate according to claim 9, wherein: The thickness of a portion of the bonding region passivation layer located between the second portion of the contact pad insulating layer and the second gate insulating layer in the bonding region is greater than or equal to 0.

11. The display substrate according to claim 8, further comprising: A first gate insulating layer in the bonding region is located in the bonding region and covers the base substrate, and the first lead connection portion is located on a side of the first gate insulating layer in the bonding region away from the base substrate; a second gate insulating layer in the bonding region, located in the bonding region, located on a side of the first gate insulating layer in the bonding region away from the base substrate and covering the first lead connection portion; The bonding area interlayer insulating layer is located in the bonding area and is located on the side of the second gate insulating layer in the bonding area away from the base substrate. The first conductor portion is electrically connected to the first lead connection portion through a via hole provided in the second gate insulating layer in the bonding area and a via hole provided in the interlayer insulating layer in the bonding area. The second conductor portion is located on the side of the first conductor portion away from the base substrate and covers the first conductor portion.

12. The display substrate according to claim 8, wherein: The at least one of the plurality of input contact pads and the plurality of output contact pads further comprises: The third conductor portion is located on a side of the second conductor portion away from the base substrate and is electrically connected to the second conductor portion.

13. The display substrate according to claim 12, further comprising: a bonding region barrier layer, located in the bonding region and covering the second conductor portion and the first portion of the contact pad insulating layer; The bonding area inorganic layer is located in the bonding area and covers the bonding area barrier layer. The third conductor part is electrically connected to the second conductor part through a via hole provided in the bonding area barrier layer and a via hole provided in the bonding area inorganic layer.

14. The display substrate according to claim 2, wherein: At least one of the plurality of first dummy contact pads includes a fourth conductor portion, the fourth conductor portion is located on a side of the substrate facing the plurality of input contact pads and the plurality of output contact pads, and an edge of the fourth conductor portion is covered by the first portion of the contact pad insulating layer. At least one of the plurality of input contact pads and the plurality of output contact pads includes a first lead connection portion, a first conductor portion, and a second conductor portion, and the fourth conductor portion is provided in the same layer as the second conductor portion.

15. The display substrate according to claim 14, wherein: At least one of the plurality of first dummy contact pads further includes a fifth conductor portion, the fifth conductor portion is located between the fourth conductor portion and the base substrate and is electrically connected to the fourth conductor portion, and the fifth conductor portion is provided in the same layer as the first conductor portion.

16. The display substrate according to claim 3, wherein: At least one of the plurality of array test contact pads comprises: a second lead connection portion, located on a side of the substrate facing the plurality of input contact pads and the plurality of output contact pads; a sixth conductor portion, located on a side of the second lead connection portion facing away from the base substrate, and electrically connected to the second lead connection portion; a seventh conductor portion, located on a side of the sixth conductor portion facing away from the substrate, electrically connected to the sixth conductor portion, and an edge of the seventh conductor portion being covered by the first portion of the contact pad insulating layer; At least one of the multiple input contact pads and the multiple output contact pads includes a first lead connection portion, a first conductor portion, and a second conductor portion, and the second lead connection portion, the sixth conductor portion, and the seventh conductor portion are respectively arranged on the same layer as the first lead connection portion, the first conductor portion, and the second conductor portion.

17. The display substrate according to claim 7, wherein: At least one of the plurality of second dummy contact pads includes an eighth conductor portion, the eighth conductor portion is located on a side of the substrate facing the plurality of input contact pads and the plurality of output contact pads, and an edge of the eighth conductor portion is covered by the first portion of the contact pad insulating layer. At least one of the plurality of input contact pads and the plurality of output contact pads includes a first lead connection portion, a first conductor portion, and a second conductor portion, and the eighth conductor portion is provided in the same layer as the second conductor portion.

18. The display substrate according to claim 17, wherein: At least one of the plurality of second dummy contact pads further includes a ninth conductor portion, the ninth conductor portion is located between the eighth conductor portion and the base substrate and is electrically connected to the eighth conductor portion, and the ninth conductor portion is provided in the same layer as the first conductor portion.

19. The display substrate according to any one of claims 1 to 18, wherein: At least one of the plurality of sub-pixels includes a pixel driving circuit, a first planarization layer, a first transfer electrode, a second planarization layer, and a light-emitting element. The first planarization layer is provided on a side of the pixel driving circuit away from the substrate to provide a first planarized surface; The first switching electrode is on the first planarized surface and is electrically connected to the pixel driving circuit through a via hole provided in the first planarized layer; The second planarization layer is provided on a side of the first transfer electrode away from the base substrate to provide a second planarized surface; The light emitting element is on the second planarized surface and is electrically connected to the first switching electrode through a via hole provided in the second planarized layer; Wherein, the contact pad insulating layer and the second planarization layer are provided in the same layer.

20. The display substrate according to claim 19, wherein The pixel driving circuit includes a thin film transistor, the thin film transistor includes a gate, a source and a drain, and at least one of the plurality of input contact pads and the plurality of output contact pads includes a first lead connection portion, a first conductor portion and a second conductor portion, wherein, The first lead connection portion is provided on the same layer as the gate; The first conductor portion is provided in the same layer as the source and drain, The second conductor portion and the first switching electrode are arranged in the same layer.

21. The display substrate according to claim 19, further comprising a display area passivation layer, wherein the display area passivation layer is located between the pixel driving circuit and the first planarization layer, and the pixel driving circuit and the first transfer electrode are further electrically connected through a via hole provided in the display area passivation layer; The display substrate further includes a bonding area passivation layer, and the bonding area passivation layer and the display area passivation layer are arranged on the same layer.

22. The display substrate according to claim 19, further comprising an encapsulation layer, a display area barrier layer, a first touch electrode layer, a second touch electrode layer, and a touch insulation layer located in the display area, wherein the encapsulation layer is located on a side of the light-emitting element away from the base substrate, the display area barrier layer is located on a side of the encapsulation layer away from the base substrate, the first touch electrode layer is located on a side of the display area barrier layer away from the base substrate, the touch insulation layer is located on a side of the first touch electrode layer away from the base substrate and covers the first touch electrode layer, and the second touch electrode layer is located on a side of the touch insulation layer away from the base substrate; The display substrate also includes a bonding area barrier layer and a bonding area inorganic layer located in the bonding area, and at least one of the multiple input contact pads and the multiple output contact pads also includes a third conductor portion. The bonding area barrier layer, the bonding area inorganic layer and the third conductor portion are respectively located on the same layer as the display area barrier layer, the touch insulation layer and the second touch electrode layer.

23. The display substrate according to claim 20, wherein: At least one of the plurality of sub-pixels further includes a display area interlayer insulating layer, a display area first gate insulating layer, and a display area second gate insulating layer, wherein the display area interlayer insulating layer is located between the gate electrode and the source electrode and the drain electrode, the display area first gate insulating layer is located on a side of the display area interlayer insulating layer facing the base substrate, and the display area second gate insulating layer is located between the display area interlayer insulating layer and the display area first gate insulating layer; The display substrate further includes a bonding area interlayer insulating layer, a bonding area first gate insulating layer and a bonding area second gate insulating layer. The bonding area interlayer insulating layer, the bonding area first gate insulating layer and the bonding area second gate insulating layer are respectively arranged on the same layer as the display area interlayer insulating layer, the display area first gate insulating layer and the display area second gate insulating layer.

24. The display substrate according to claim 20, wherein: At least one of the multiple sub-pixels further includes a storage capacitor, a first electrode of the storage capacitor is arranged in the same layer as the gate, and a second electrode of the storage capacitor is arranged between the display area interlayer insulating layer and the display area second gate insulating layer.

25. The display substrate according to any one of claims 1 to 18, wherein: The substrate comprises: First flexible layer, a second flexible layer located on a side of the first flexible layer facing the plurality of input contact pads and the plurality of output contact pads; a first substrate barrier layer located between the first flexible layer and the second flexible layer; a second substrate barrier layer, located on a side of the second flexible layer facing away from the first flexible layer; The buffer layer is located on a side of the second substrate barrier layer facing away from the first flexible layer.

26. A display device comprising the display substrate according to any one of claims 1 to 25.

27. A method for manufacturing the display substrate according to any one of claims 1 to 25, comprising: Providing a base substrate, the base substrate comprising a display area, a bonding area located on at least one side of the display area, and a side area located on at least another side of the display area; forming a plurality of sub-pixels in the display area; forming a gate driving circuit in the side area, the gate driving circuit being connected to the plurality of sub-pixels and configured to provide a gate driving signal to the plurality of sub-pixels; forming a plurality of input contact pads in the bonding region for electrical connection with an external circuit; forming a plurality of output contact pads in the bonding area, the plurality of output contact pads being located between the plurality of input contact pads and the display area, the plurality of output contact pads being electrically connected to the plurality of sub-pixels and the gate driving circuit; A contact pad insulating layer is formed in the bonding area, wherein the contact pad insulating layer is located in gaps between adjacent input contact pads among the multiple input contact pads, gaps between adjacent output contact pads among the multiple output contact pads, and an area between the multiple input contact pads and the multiple output contact pads, surfaces of the multiple input contact pads and the multiple output contact pads facing away from the substrate are exposed from the contact pad insulating layer, wherein the contact pad insulating layer includes a first portion having a first thickness and a second portion having a second thickness, wherein the second thickness is less than the first thickness, edges of the multiple input contact pads and the multiple output contact pads are covered by the first portion of the contact pad insulating layer, and the second portion of the contact pad insulating layer is located in an area between the multiple input contact pads and the multiple output contact pads.

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